MM912F634DV2APR2_技术文档

Document Number: MM912F634

Rev. 7.0, 5/2013

Freescale Semiconductor

Advanced Information

Integrated S12 Based Relay

Driver with LIN

MM912F634

48-PIN LQFP-EP, 7.0 mm x 7.0 mm

AE SUFFIX: Exposed Pad Option

The MM912F634 is an integrated single package solution that

integrates an HCS12 microcontroller with a SMARTMOS

analog control IC. The Die to Die Interface (D2D) controlled

analog die combines system base chip and application specific

functions, including a LIN transceiver.

48-PIN LQFP, 7.0 mm x 7.0 mm

AP SUFFIX: Non-exposed Pad Option

ORDERING INFORMATION

See Page 2.

Features

• 16-Bit S12 CPU, 32 kByte FLASH, 2.0 kByte RAM

• Background Debug (BDM) & Debug Module (DBG)

• Die to Die bus interface for transparent memory mapping

• On-chip oscillator & two independent watchdogs

• LIN 2.1 Physical Layer Interface with integrated SCI

• Six digital MCU GPIOs shared with SPI (PA5…0)

• 10-Bit, 15 Channel - Analog to Digital Converter (ADC)

• 16-Bit, 4 Channel - Timer Module (TIM16B4C)

• 8-Bit, 2 Channel - Pulse width modulation module (PWM)

• Six high voltage / Wake-up inputs (L5.0)

• Low Power Modes with cyclic sense & forced wake-up

• Current Sense Module with selectable gain

• Reverse Battery protected Voltage Sense Module

• Two protected low side outputs to drive inductive loads

• Two protected high side outputs

• Chip temperature sensor

• Hall sensor supply

• Integrated voltage regulator(s)

• Three low voltage GPIOs (PB2.0)

MM912F634

Battery Sense

Power Supply

VSENSE¹

LS1

VS1

VS2

PGND

M

Low-Side Drivers

LS2

LIN interface

ADC Supply

LIN

ISENSEH¹

LGND

ADC2p5

AGND

Current Sense Module

Hall Sensor supply

ISENSEL¹

HSUP

VDD

2.5V Supply

5V Supply

EVDD

Hall Sensor

VDDX

EVDDX

PTB0/AD0/RX/TIM0CH0

PTB1/AD1/TX/TIM0CH1

PTB2/AD2/PWM/TIM0CH2

5V GPI/O with optional

pull-up (shared with

ADC, PWM, Timer, SCI)

DGND

EVSS

Digital Ground

Reset

EVSSX

HS1

12V Light/LED

and switch supply

RESET

RESET_A

PA0/MISO

PA1/MOSI

PA2/SCK

PA3/SS

PA4

HS2¹

L0

L1

L2¹

L3¹

L4¹

L5¹

5V digital I/O

Analog/Digital Inputs

(High Voltage- and Wake

Up capable)

PA5

BKGD/MODC

EXTAL

Debug and

external

Oscillator

XTAL

TCLK

Analog Test

MCU Test

TEST

TEST_A

¹⁾Feature not available in all Analog Options

Figure 1. Simplified Application Diagram

* This document contains certain information on a new product.

Specifications and information herein are subject to change without notice.

Ordering Information

1

Ordering Information

‘

Table 1. Ordering Information

Device

(Add an R2 for Tape

and Reel orders)

Max. Bus

Stop

mode

wake-up

Temperature

Range (T_A)

Analog

Package

Frequency (MHz) Flash (kB) RAM (kB)

Option⁽¹⁾

(f_BUSMAX

)

(2)

MM912F634CV1AE

MM912F634DV1AE

MM912F634CV2AE

MM912F634DV2AE

MM912F634CV2AP

MM912F634DV2AP

1

2

Enhanced

98ASA00173D

48-PIN LQFP-EP

20

32

(2)

-40 to 105 °C

2

Enhanced

(2)

98ASH00962A

48-PIN LQFP

16

Enhanced

Note:

1. See Table 2.

2. Refer to MM912F634, Silicon Analog Mask (M91W) / Digital Mask (M33G) Errata

Table 2. Analog Options⁽³⁾

Feature

Option 1

Option 2

Current Sense Module

Wake-up Inputs (Lx)

YES

NO

L0…L5

L0…L3

Note:

3. This table only highlights the analog die differences between the derivatives. See

Section 4.2.3, “Analog Die Options" for detailed information.

The device part number is following the standard scheme below:

MM

9

12

f

xxx

r

t

a

PP

RR

Memory Size

A – 1k

B – 2k

C – 4k

D – 8k

E – 16k

F – 32k

G – 48k

H – 64k

I – 96k

Product Category

MM – Qualified Standard 9 – FLASH, OTP

SM – Custom Device

PM – Prototype Device

Memory Type

MCU Core

08 – HC08

12 – HC12

Analog Core/

Target

Revision

(default A)

T

_ATemperature

Range

Analog Die

Option

(default 1)

Package Designator

AE – LQFP48-EP

AP – LQFP48

Tape & Reel

Indicator

Blank - ROM

I = 0°C to 85°C

C = -40°C to 85°C

V = -40°C to 105°C

M = -40°C to 125°C

J – 128k

Figure 2. Part Number Scheme

MM912F634

Freescale Semiconductor

2

Ordering Information

Table of Contents

1

2

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1

2.2

MM912F634 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

MCU Die Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Static Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Dynamic Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Thermal Protection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

ESD Protection and Latch-up Immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Additional Test Information ISO7637-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4

Functional Description and Application Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

MM912F634 - Analog Die Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Die to Die Interface - Target. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Wake-up / Cyclic Sense. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Window Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

4.10 Hall Sensor Supply Output - HSUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

4.11 High Side Drivers - HS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

4.12 Low Side Drivers - LSx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

4.13 PWM Control Module (PWM8B2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

4.14 LIN Physical Layer Interface - LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

4.15 Serial Communication Interface (S08SCIV4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

4.16 High Voltage Inputs - Lx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

4.17 General Purpose I/O - PTB[0…2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

4.18 Basic Timer Module - TIM (TIM16B4C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

4.19 Analog Digital Converter - ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

4.20 Current Sense Module - ISENSE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

4.21 Temperature Sensor - TSENSE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

4.22 Supply Voltage Sense - VSENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

4.23 Internal Supply Voltage Sense - VS1SENSE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

4.24 Internal Bandgap Reference Voltage Sense - BANDGAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

4.25 MM912F634 - Analog Die Trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

4.26 MM912F634 - MCU Die Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

4.27 Port Integration Module (9S12I32PIMV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

4.28 Memory Mapping Control (S12SMMCV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

4.29 Interrupt Module (S12SINTV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

4.30 Background Debug Module (S12SBDMV1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

4.31 S12S Debug (S12SDBGV1) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

4.32 S12S Clocks and Reset Generator (S12SCRGV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

4.33 External Oscillator (S12SS12SCRGV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

4.34 Real Time Interrupt (S12SRTIV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

4.35 Computer Operating Properly (S12SCOPV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

4.36 32 kbyte Flash Module (S12SFTSR32KV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

4.37 Die-to-Die Initiator (D2DIV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

4.38 Serial Peripheral Interface (S12SPIV4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333

5

6

5.1

Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338

MM912F634

Freescale Semiconductor

3

Ordering Information

PTA

BKGD/MODC

RESET

DDRA

EVSS

EVDD

Internal Bus

VDD

VDDX

DGND

RESET_A

VSENSE

TCLK

VS1

VS2

TEST_A

Internal Bus

ISENSEH

ISENSEL

HS1

HS2

LS2

HSUP

LIN

PGND

LS1

Figure 3. Device Block Diagram

MM912F634

Freescale Semiconductor

4

Pin Assignment

2

Pin Assignment

NC

EXTAL

XTAL

TEST

PA5

L5

1

2

36

35

34

33

32

31

30

29

28

27

26

25

L4

L3

3

L2

4

L1

5

PA4

L0

6

PA3

AGND

ADC2p5

PTB2

PTB1

PTB0

LGND

7

PA2

8

PA1

9

PA0

10

11

12

EVSSX

EVDDX

Figure 4. MM912F634 Pin Out

NOTE

The device exposed pad (package option AE only) is recommended to be connected to

GND.

Not all pins are available for analog die option 2. See Section 4.2.3, “Analog Die Options"

for details.

MM912F634

Freescale Semiconductor

5

Pin Assignment

MM912F634 Pin Description

2.1

MM912F634 Pin Description

The following table gives a brief description of all available pins on the MM912F634 package. Refer to the highlighted chapter for

detailed information.

Table 3. MM912F634 Pin Description

Pin #

Pin Name

Formal Name

Description

1

NC

Not connected Pin

This pin is reserved for alternative function and should be left floating or connected

to GND.

2

3

EXTAL

XTAL

MCU Oscillator Pin

EXTAL is one of the optional crystal/resonator driver and external clock pins. On

reset, all the device clocks are derived from the Internal Reference Clock. See

Section 4.33, “External Oscillator (S12SS12SCRGV1)".

XTAL is one of the optional crystal/resonator driver and external clock pins. On

reset, all the device clocks are derived from the Internal Reference Clock. See

Section 4.33, “External Oscillator (S12SS12SCRGV1)".

4

5

6

7

TEST

PA5

MCU Test Pin

MCU PA5 Pin

MCU PA4 Pin

MCU PA3 / SS Pin

This input only pin is reserved for test. This pin has a pull-down device. The TEST

pin must be tied to EVSS in user mode.

General purpose port A input or output pin 5. See Section 4.27, “Port Integration

Module (9S12I32PIMV1)"

PA4

General purpose port A input or output pin 4. See Section 4.27, “Port Integration

Module (9S12I32PIMV1)".

PA3

General purpose port A input or output pin 3, shared with the SS signal of the

integrated SPI Interface. See Section 4.27, “Port Integration Module

(9S12I32PIMV1)".

8

9

PA2

PA1

PA0

MCU PA2 / SCK Pin

MCU PA1 / MOSI Pin

MCU PA0 / MISO Pin

General purpose port A input or output pin 2, shared with the SCLK signal of the

integrated SPI Interface. See Section 4.27, “Port Integration Module

(9S12I32PIMV1)".

General purpose port A input or output pin 1, shared with the MOSI signal of the

integrated SPI Interface. See Section 4.27, “Port Integration Module

(9S12I32PIMV1)".

10

General-purpose port A input or output pin 0, shared with the MISO signal of the

integrated SPI Interface. See Section 4.27, “Port Integration Module

(9S12I32PIMV1)".

11

12

EVSSX

EVDDX

MCU 5.0 V Ground Pin

MCU 5.0 V Supply Pin

Ground for the MCU 5.0 V power supply.

MCU 5.0 V - I/O buffer supply. See Section 4.26, “MM912F634 - MCU Die

Overview".

13

14

EVSS

EVDD

MCU 2.5 V Ground Pin

MCU 2.5 V Supply Pin

Ground for the MCU 2.5 V power supply.

MCU 2.5 V - MCU Core- and Flash power supply. See Section 4.26, “MM912F634

- MCU Die Overview".

15

16

17

18

VDD

VDDX

Voltage Regulator

Output 2.5 V

+2.5 V main voltage regulator output pin. External capacitor (C_VDD) needed. See

Section 4.4, “Power Supply".

Voltage Regulator Output +5.0 V main voltage regulator output pin. External capacitor (C_VDDX) needed. See

5.0 V

Section 4.4, “Power Supply".

DGND

VSENSE

Digital Ground Pin

This pin is the device digital ground connection for the 5.0 V and 2.5 V logic. DGND,

LGND, and AGND are internally connected to PGND via a back to back diode.

Voltage Sense Pin

Battery voltage sense input. This pin can be connected directly to the battery line for

voltage measurements. The voltage present at this input is scaled down by an

internal voltage divider, and can be routed to the internal ADC via the analog

multiplexer.The pin is self-protected against reverse battery connections. An

external resistor (R_VSENSE) is needed for protection⁽⁴⁾. See Section 4.22, “Supply

Voltage Sense - VSENSE".

MM912F634

Freescale Semiconductor

6

Pin Assignment

MM912F634 Pin Description

Table 3. MM912F634 Pin Description (continued)

Pin #

Pin Name

Formal Name

Description

19

VS1

Power Supply Pin 1

This pin is the device power supply pin 1. VS1 is primarily supplying the VDDX

Voltage regulator and the Hall Sensor Supply Regulator (HSUP). VS1 can be

sensed via a voltage divider through the AD converter. Reverse battery protection

diode is required. See Section 4.4, “Power Supply"

20

21

VS2

HS1

Power Supply Pin 2

High Side Output 1

This pin is the device power supply pin 2. VS2 supplies the High Side Drivers (HSx).

Reverse battery protection diode required. See Section 4.4, “Power Supply"

This pin is the first High Side output. It is supplied through the VS2 pin. It is designed

to drive small resistive loads with optional PWM. In cyclic sense mode, this output

will activate periodically during low power mode. See Section 4.11, “High Side

Drivers - HS".

22

23

HS2

High Side Output 2

This pin is the second High Side output. It is supplied through the VS2 pin. It is

designed to drive small resistive loads with optional PWM. In cyclic sense mode, this

output will activate periodically during low power mode. See Section 4.11, “High

Side Drivers - HS".

HSUP

Hall Sensor Supply Output This pin is designed as an 18 V Regulator to drive Hall Sensor Elements. It is

supplied through the VS1 pin. An external capacitor (C_HSUP) is needed. See

Section 4.10, “Hall Sensor Supply Output - HSUP".

24

25

26

LIN

LIN Bus I/O

This pin represents the single-wire bus transmitter and receiver. See Section 4.14,

“LIN Physical Layer Interface - LIN".

LGND

PTB0

LIN Ground Pin

General Purpose I/O 0

This pin is the device LIN Ground connection. DGND, LGND, and AGND are

internally connected to PGND via a back to back diode.

This is the General Purpose I/O pin 0 based on VDDX with the following shared

functions:

• PTB0 - Bidirectional 5.0 V (VDDX) digital port I/O with selectable internal pull-up

resistor.

• AD0 - Analog Input Channel 0, 0…2.5 V (ADC2p5) analog input

• TIM0CH0 - Timer Channel 0 Input/Output

• Rx - Selectable connection to LIN / SCI

See Section 4.17, “General Purpose I/O - PTB[0…2]".

27

PTB1

General Purpose I/O 1

This is the General Purpose I/O pin 1 based on VDDX with the following shared

functions:

• PTB1 - Bidirectional 5.0 V (VDDX) digital port I/O with selectable internal pull-up

resistor.

• AD1 - Analog Input Channel 1, 0…2.5 V (ADC2p5) analog input

• TIM0CH1 - Timer Channel 1 Input/Output

• Tx - Selectable connection to LIN / SCI

See Section 4.17, “General Purpose I/O - PTB[0…2]".

28

PTB2

General Purpose I/O 2

This is the General Purpose I/O pin 2 based on VDDX with the following shared

functions:

• PTB2 - Bidirectional 5.0 V (VDDX) digital port I/O with selectable internal pull-up

resistor.

• AD2 - Analog Input Channel 2, 0…2.5 V (ADC2p5) analog input

• TIM0CH2 - Timer Channel 2 Input/Output

• PWM - Selectable connection to PWM Channel 0 or 1

See Section 4.17, “General Purpose I/O - PTB[0…2]".

29

30

ADC2p5

AGND

ADC Reference Voltage

Analog Ground Pin

This pin represents the ADC reference voltage and has to be connected to a filter

capacitor. See Section 4.19, “Analog Digital Converter - ADC"

This pin is the device Analog to Digital Converter ground connection. DGND, LGND

and AGND are internally connected to PGND via a back to back diode.

MM912F634

Freescale Semiconductor

7

Pin Assignment

MM912F634 Pin Description

Table 3. MM912F634 Pin Description (continued)

Pin #

Pin Name

Formal Name

Description

31

L0

High Voltage Input 0

This pins is the High Voltage Input 0 with the following shared functions:

• L0 - Digital High Voltage Input 0. When used as digital input, a series resistor

(R_Lx) must be used to protect against automotive transients.⁽⁵⁾

• AD3 - Analog Input 3 with selectable divider for 0…5.0 V and 0…18 V

measurement range.

• WU0 - Selectable Wake-up input 0 for wake up and cyclic sense during low

power mode.

See Section 4.16, “High Voltage Inputs - Lx"

32

33

34

35

L1

L2

L3

L4

High Voltage Input 1

High Voltage Input 2

High Voltage Input 3

High Voltage Input 4

This pins is the High Voltage Input 1 with the following shared functions:

• L1 - Digital High Voltage Input 1. When used as digital input, a series resistor

(R_Lx) must be used to protect against automotive transients.⁽⁵⁾

• AD4 - Analog Input 4 with selectable divider for 0…5.0 V and 0…18 V

measurement range.

• WU1 - Selectable Wake-up input 1 for wake-up and cyclic sense during low

power mode.

See Section 4.16, “High Voltage Inputs - Lx"

This pins is the High Voltage Input 2 with the following shared functions:

• L2 - Digital High Voltage Input 2. When used as digital input, a series resistor

(R_Lx) must be used to protect against automotive transients.⁽⁵⁾

• AD5 - Analog Input 5 with selectable divider for 0…5.0 V and 0…18 V

measurement range.

• WU2 - Selectable Wake-up input 2 for wake-up and cyclic sense during low

power mode.

See Section 4.16, “High Voltage Inputs - Lx".

This pins is the High Voltage Input 3 with the following shared functions:

• L3 - Digital High Voltage Input 3. When used as digital input, a series resistor

(R_Lx) must be used to protect against automotive transients.⁽⁵⁾

• AD6 - Analog Input 6 with selectable divider for 0…5.0 V and 0…18 V

measurement range.

• WU3 - Selectable Wake-up input 3 for wake-up and cyclic sense during low

power mode.

See Section 4.16, “High Voltage Inputs - Lx".

This pins is the High Voltage Input 4 with the following shared functions:

• L4 - Digital High Voltage Input 4. When used as digital input, a series resistor

(R_Lx) must be used to protect against automotive transients.⁽⁵⁾

• AD7 - Analog Input 7 with selectable divider for 0…5.0 V and 0…18 V

measurement range.

• WU4 - Selectable Wake-up input 4 for wake-up and cyclic sense during low

power mode.

See Section 4.16, “High Voltage Inputs - Lx". Note: This pin function is not available

on all device configurations.

36

L5

High Voltage Input 5

This pins is the High Voltage Input 5 with the following shared functions:

• L5 - Digital High Voltage Input 5. When used as digital input, a series resistor

(R_Lx) must be used to protect against automotive transients.⁽⁵⁾

• AD8 - Analog Input 8 with selectable divider for 0…5.0 V and 0…18 V

measurement range.

• WU5 - Selectable Wake-up input 5 for wake-up and cyclic sense during low

power mode.

See Section 4.16, “High Voltage Inputs - Lx". Note: This pin function is not available

on all device configurations.

37

38

LS1

Low Side Output 1

Power Ground Pin

Low Side output 1 used to drive small inductive loads like relays. The output is

short-circuit protected, includes active clamp circuitry and can be also controlled by

the PWM module.

See Section 4.12, “Low Side Drivers - LSx"

PGND

This pin is the device Low Side Ground connection. DGND, LGND and AGND are

internally connected to PGND via a back to back diode.

MM912F634

Freescale Semiconductor

8

Pin Assignment

MM912F634 Pin Description

Table 3. MM912F634 Pin Description (continued)

Pin #

Pin Name

Formal Name

Description

39

LS2

Low Side Output 2

Low Side output 2 used to drive small inductive loads like relays. The output is

short-circuit protected, includes active clamp circuitry and can be also controlled by

the PWM module.

See Section 4.12, “Low Side Drivers - LSx"

40

41

ISENSEL

ISENSEH

Current Sense Pins L

Current Sense Pins H

Current Sense differential input “Low”. This pin is used in combination with

ISENSEH to measure the voltage drop across a shunt resistor. See Section 4.20,

“Current Sense Module - ISENSE". Note: This pin function is not available on all

device configurations.

Current Sense differential input “High”. This pin is used in combination with

ISENSEL to measure the voltage drop across a shunt resistor. Section 4.20,

“Current Sense Module - ISENSE". Note: This pin function is not available on all

device configurations.

42

43

NC

Not connected Pin

Test Mode Pin

This pin is reserved for alternative function and should be left floating.

TEST_A

Analog die Test Mode pin for Test Mode only. This pin must be grounded in user

mode.

44

TCLK

Test Clock Input

Test Mode Clock Input pin for Test Mode only. The pin can be used to disable the

internal watchdog for development purpose in user mode. See Section 4.9,

“Window Watchdog". The pin is recommended to be grounded in user mode.

45

46

RESET_A

RESET

Reset I/O

Bidirectional Reset I/O pin of the analog die. Active low signal. Internal pull-up. V_DDX

based. See Section 4.7, “Resets". To be externally connected to the RESET pin.

MCU Reset Pin

The RESET pin is an active low bidirectional control signal. It acts as an input to

initialize the MCU to a known start-up state, and an output when an internal MCU

function causes a reset. The RESET pin has an internal pull-up device to EVDDX.

47

48

BKGD

NC

MCU Background Debug

and Mode Pin

The BKGD/MODC pin is used as a pseudo-open-drain pin for the background

debug communication. It is used as MCU operating mode select pin during reset.

The state of this pin is latched to the MODC bit at the rising edge of RESET. The

BKGD pin has a pull-up device.

Not connected Pin

This pin is reserved for alternative function and should be left floating or connected

to GND.

Note:

4. An optional filter capacitor C_VSENSEis recommended to be placed between the board connector and R_VSENSEto GND for increased ESD

performance.

5. An optional filter capacitor C_Lxis recommended to be placed between the board connector and R_Lxto GND for increased ESD

performance.

MM912F634

Freescale Semiconductor

9

Pin Assignment

MCU Die Signal Properties

2.2

MCU Die Signal Properties

This section describes the external MCU signals. It includes a table of signal properties.

Table 4. Signal Properties Summary

Internal Pull

Name

Function 1

Name

Function 2

Resistor

Power

Supply

Description

Reset

State

CTRL

EXTAL

XTAL

RESET

TEST

BKGD

PA5

—

V_DD

NA

Oscillator pins

—

V_DDX

N.A.

Pull-up

External reset

Test input

—

RESET pin

Down

UP

MODC

—

V_DDX

Always on

NA

Background debug

Port A I/O

NA

PA4

—

NA

Port A I/O

PA3

SS

NA

Port A I/O, SPI

PA2

SCK

MOSI

MISO

NA

PA1

NA

PA0

NA

MM912F634

Freescale Semiconductor

10

Electrical Characteristics

General

3

Electrical Characteristics

General

3.1

This supplement contains electrical information for the embedded MC9S12I32 microcontroller die, as well as the MM912F634

analog die.

3.2

Absolute Maximum Ratings

Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed.

Stress beyond those limits may affect the reliability or cause permanent damage of the device.

This device contains circuitry protecting against damage due to high static voltage or electrical fields. However, it is advised that

normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance

circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. All voltages are with respect

to ground unless otherwise noted.

Table 5. Absolute Maximum Electrical Ratings - Analog Die

Ratings

Symbol

Value

Unit

Supply Voltage at VS1 and VS2

Normal Operation (DC)

Transient Conditions (load dump)

Transient input voltage with external component (according to LIN

Conformance Test Specification / ISO7637-2)

-0.3 to 27

-0.3 to 40

see Section 3.9,

“Additional Test

Information

V

V_SUP(SS)

V_SUP(PK)

V_SUP(TR)

ISO7637-2"

L0…L5 - Pin Voltage

-27 to 40

see Section 3.9,

“Additional Test

Information

V

Normal Operation with a series R_LXresistor (DC)

Transient input voltage with external component (according to LIN

Conformance Test Specification / ISO7637-2)

V_LxDC

V_LxTR

ISO7637-2"

LIN Pin Voltage

Normal Operation (DC)

Transient input voltage with external component (according to LIN

Conformance Test Specification / ISO7637-2)

-33 to 40

see Section 3.9,

“Additional Test

Information

V_BUSDC

V_BUSTR

ISO7637-2"

Supply Voltage at VDDX

Supply Voltage at VDD ⁽⁶⁾

VDD output current

V_DDX

V_DD

-0.3 to 5.5

-0.3 to 2.75

V

A

V

I_VDD

Internally Limited

-0.3 to 10

VDDX output current

I_VDDX

V_TCLK

V_IN

TCLK Pin Voltage

RESET_A Pin Voltage

-0.3 to V_DDx+0.3

-0.3 to VS2+0.3

-0.3 to 45

Input / Output Pins PTB[0:2] Voltage

HS1 and HS2 Pin Voltage (DC)

LS1 and LS2 Pin Voltage (DC)

ISENSEH and ISENSEL Pin Voltage (DC)

HSUP Pin Voltage (DC)

VSENSE Pin Voltage (DC)

Note:

V_IN

V_HS

V_LS

V_ISENSE

V_HSUP

V_VSENSE

-0.3 to 40

-0.3 to VS1+0.3

-27 to 40

6. Caution: As this pin is adjacent to the VDDX pin, care should be taken to avoid a short between VDD and VDDX, for example, during

the soldering process. A short-circuit between these pins might lead to permanent damage.

MM912F634

Freescale Semiconductor

11

Electrical Characteristics

Absolute Maximum Ratings

Table 6. Maximum Electrical Ratings - MCU Die

Ratings

Symbol

Value

Unit

5.0 V Supply Voltage

2.5 V Supply Voltage

Digital I/O input voltage (PA0...PA7, PE0, PE1)

EXTAL, XTAL

V_EDDX

V_EDD

V_IN

-0.3 to 6.0

-0.3 to 2.75

-0.3 to 6.0

-0.3 to 2.16

-0.3 to 10.0

-25 to 25

V

V_ILV

V

TEST input

V_TEST

I_D

V

Instantaneous maximum current

mA

Single pin limit for all digital I/O pins

Instantaneous maximum current

Single pin limit for EXTAL, XTAL

I_DL

-25 to 25

mA

Table 7. Maximum Thermal Ratings

Ratings

Symbol

Value

Unit

Storage Temperature

T_STG

-55 to 150

C

Package Thermal Resistance - LQFP48-EP

Four layer board (JEDEC 2s2p)

C/W

Junction to Ambient Natural Convection ⁽⁷⁾

Junction to Board ⁽⁹⁾

R_JA

R_JB

39

16

Two layer board (JEDEC 1s)

Junction to Ambient Natural Convection ^{(7), (8)}

R_JA

91

Package Thermal Resistance - LQFP48

Four layer board (JEDEC 2s2p)

Junction to Ambient Natural Convection ⁽⁷⁾

Junction to Board ⁽⁹⁾

C/W

R_JA

R_JB

59

31

Two layer board (JEDEC 1s)

Junction to Ambient Natural Convection ^{(7), (8)}

R_JA

96

Peak Package Reflow Temperature During Reflow ^(10),(11)

T_PPRT

300

°C

Notes

7. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature,

ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

8. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.

9. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top

surface of the board near the package.

10. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

11. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow

Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes

and enter the core ID to view all orderable parts. (i.e. MC34xxxD enter 34xxx), and review parametrics.

MM912F634

Freescale Semiconductor

12

Electrical Characteristics

OperatingConditions

3.3

Operating Conditions

This section describes the operating conditions of the device. Unless otherwise noted those conditions apply to all the following

data.

Table 8. Operating Conditions

Ratings

Analog Die Nominal Operating Voltage

Symbol

Value

Unit

V_SUP

5.5 to 18

5.5 to 27

V

Analog Die Functional Operating Voltage - Device is fully functional. All

features are operating.

V_SUPOP

MCU I/O and supply voltage⁽¹²⁾

MCU Digital logic supply voltage⁽¹²⁾

MCU External Oscillator

V_EDDX

V_EDD

f_OSC

f_BUS

T_A

4.5 to 5.5

2.25 to 2.75

4.0 to 16

V

MHz

C

(13)

MCU Bus frequency

f_BUSMAX

Operating Ambient Temperature

MM912x634xVxxx

-40 to 105

-40 to 150

-40 to 140

Operating Junction Temperature - Analog Die

Operating Junction Temperature - MCU Die

T_{J_A}

T_{J_M}

C

Note:

12. During power up and power down sequence always V_DD< V_DDX

13. f_BUSMAXfrequency ratings differ by device and is specified in Table 1

3.4

Supply Currents

This section describes the current consumption characteristics of the device as well as the conditions for the measurements.

3.4.1 Measurement Conditions

All measurements are without output loads. Unless otherwise noted, the currents are measured in MCU special single chip mode

and the CPU code is executed from RAM.

Table 9. Supply Currents

Ratings

Symbol

Min

Typ⁽¹⁴⁾

Max

Unit

Normal Mode analog die only, excluding external loads, LIN Recessive State

(5.5 V  V_SUP 18 V, 2.25 V  E_VDD 2.75 V, 4.5 V  E_VDDX 5.5 V, -40 °C

 T_{J_A} 150 °C).

I_{RUN_A}

-

5.0

8.0

mA

Normal Mode MCU die only (T_{J_}₍_M₁₈=_{) (}1₁₅4₎0 °C; V_DD= 2.75 V, V_DDX= 5.5 V,

I_{RUN_M}

I_{STOP_A}

-

12.5

15

mA

µA

f

_OSC= 4.0 MHz, f_BUS= f_BUSMAX

)

Stop Mode internal analog die only, excluding external loads, LIN Recessive

State, Lx enabled, measured at VS1+VS2 (5.5 V  V_SUP 18 V, 2.25 V 

E_VDD 2.75 V, 4.5 V  E_VDDX 5.5 V)

-40 °C  T_{J_A} 125 °C

125 °C  T_{J_A} 140 °C

-

20

-

40

50

Stop Mode MCU die only (V_DD= 2.75 V, V_DDX= 5.5 V, f_OSC= 4.0 MHz,

f

T_{J_M}= 140 °C

T_{J_M}= 105 °C

T_{J_M}= 25 °C

I_{STOP_M}

mA

_BUS= f_BUSMAX⁽¹⁸⁾; MCU in STOP; RTI and COP off)⁽¹⁶⁾

-

0.135

0.035

0.010

0.400

0.200

0.030

Stop Mode MCU die only (V_DD= 2.75 V, V_DDX= 5.5 V, f_OSC= 4.0 MHz,

I_{STOP_M}

f

_BUS= f_BUSMAX⁽¹⁸⁾; MCU in STOP; RTI and COP on)⁽¹⁶⁾

T_{J_M}= 140 °C

-

0.205

0.104

0.079

0.500

0.300

0.110

T

_{J_M}= 105 °C

_{J_M}= 25 °C

MM912F634

Freescale Semiconductor

13

Electrical Characteristics

Static Electrical Characteristics

Table 9. Supply Currents (continued)

Ratings

Symbol

Min

Typ⁽¹⁴⁾

Max

Unit

Wait Mode MCU die only (T_{J_M}= 140 °C; V_DD= 2.75 V, V_DDX= 5.5 V,

f

I_{WAIT_M}

-

7.0

12

mA

_OSC= 4.0 MHz, f_BUS= f_BUSMAX⁽¹⁸⁾; All modules except RTI disabled)⁽¹⁷⁾

Sleep Mode (VDD = VDDX = OFF; 5.5 V  V_SUP 18 V; -40 °C  T_{J_A}

150 °C; 3.0 V  L_X 1.0 V).



I_SLEEP

I_CS

-

15

28

20

µA

Cyclic Sense Supply Current Adder (5.0 ms Cycle)

Note:

14. Typical values noted reflect the approximate parameter mean at T_A= 25 °C

15.

16.

17.

18.

I

f

_{RUN_M}denotes the sum of the currents flowing into VDD and VDDX.

_{STOP_M}denotes the sum of the currents flowing into VDD and VDDX.

_{WAIT_M}denotes the sum of the currents flowing into VDD and VDDX.

_BUSMAXfrequency ratings differ by device and is specified in Table 1.

3.5

Static Electrical Characteristics

Static electrical characteristics noted under conditions 5.5V  VSUP  18 V, -40 °C  T_A 105 °C, unless otherwise noted. Typical

values noted reflect the approximate parameter mean at T_A= 25 °C under nominal conditions unless otherwise noted.

3.5.1

Static Electrical Characteristics Analog Die

Table 10. Static Electrical Characteristics - Power Supply

Ratings

Symbol

Min

Typ

Max

Unit

Power-On Reset (POR) Threshold (measured on VS1)

V_POR

1.5

-

3.5

V

Low Voltage Warning (LVI)

Threshold (measured on VS1, falling edge)

Hysteresis (measured on VS1)

V_LVI

V_{LVI_H}

5.55

-

6.0

1.0

6.6

-

High Voltage Warning (HVI)

Threshold (measured on VS2, rising edge)

Hysteresis (measured on VS2)

V

V_HVI

V_{HVI_H}

18

-

19.25

1.0

20.5

-

Low Battery Warning (LBI)

Threshold (measured on VSENSE, falling edge)

Hysteresis (measured on VSENSE)

V_LBI

V_{LBI_H}

5.55

-

6.0

1.0

6.6

-

J2602 Under-voltage threshold

V_J2602UV

V_LVRX

5.5

2.7

5.7

3.0

6.2

3.3

2.4

2.1

3.0

6.1

V

Low VDDX Voltage (LVRX) Threshold

Low VDD Voltage Reset (LVR) Threshold Normal Mode

Low VDD Voltage Reset (LVR) Threshold Stop Mode ⁽¹⁹⁾

VDD Over-voltage Threshold (VROV)

VDDX Over-voltage Threshold (VROVX)

Note:

V_LVR

2.30

1.6

2.35

V_LVRS

1.85

V_VDDOV

V_VDDXOV

2.575

5.25

2.7875

5.675

19. See MM912F634ER, MM912F634, Silicon Analog Mask (M91W) / Digital Mask (M33G) Errata

Table 11. Static Electrical Characteristics - Resets

Ratings

Low-state Output Voltage I_OUT= 2.0 mA

Symbol

Min

Typ

Max

Unit

V_OL

R_RPU

V_IL

-

0.8

V

kOhm

V

Pull-up Resistor

25

50

Low-state Input Voltage

High-state Input Voltage

Reset Release Voltage (VDDX)

RESET_A pin Current Limitation

-

0.3V_DDX

V_IH

0.7V_DDX

-

V

V_RSTRV

-

1.5

7.5

V

5.0

10

mA

MM912F634

Freescale Semiconductor

14

Electrical Characteristics

Static Electrical Characteristics

Table 12. Static Electrical Characteristics - Window Watchdog

Ratings

Symbol

Min

Typ

Max

Unit

Watchdog Disable Voltage (fixed voltage)

Watchdog Enable Voltage (fixed voltage)

V_TST

7.0

-

10

V

V_TSTEN

5.5

Table 13. Static Electrical Characteristics - Voltage Regulator 5V (VDDX)

Ratings

Symbol

Min

Typ

Max

Unit

Normal Mode Output Voltage

1.0 mA < I_VDDX+ I_VDDXINTERNAL< 80 mA; 5.5 V < V_SUP< 27 V ⁽²⁰⁾

V_DDXRUN

V

4.75

80

-

5.00

130

5.0

5.25

200

5.5

Normal Mode Output Current Limitation (I_VDDX

)

I_VDDXLIMRUN

V_DDXSTOP

mA

V

Stop Mode Output Voltage

(I_VDDX+ I_VDDXINTERNAL< 500 µA for T_J 25 °C; I_VDDX+ I_VDDXINTERNAL

<

400 µA for T_J< 25 °C) ⁽²⁰⁾

Stop Mode Output Current Limitation (I_VDDX

)

I_VDDXLIMSTOP

-

20

mA

mV

Line Regulation

Normal Mode, I_VDDX= 80 mA

Stop Mode, I_VDDX= 500 µA

LR_XRUN

LR_XSTOP

-

20

-

25

200

Load Regulation

mV

Normal Mode, 1.0 mA < I_VDDX< 80 mA

Normal Mode, V_SUP= 3.6 V, 1.0 mA < I_VDDX< 40 mA

Stop Mode, 100 µA < I_VDDX< 500 µA

LD_XRUN

LD_XCRK

LD_XSTOP

-

15

-

80

200

250

External Capacitor

External Capacitor ESR

Note:

C_VDDX

1.0

-

10

µF

C_{VDDX_R}

Ohm

20.

I_VDDXINTERNALincludes internal consumption from both analog and MCU die.

Table 14. Static Electrical Characteristics - Voltage Regulator 2.5 V (VDD)

Ratings

Symbol

Min

Typ

Max

Unit

Normal Mode Output Voltage

1.0 mA < I_VDD+ I_VDDINTERNAL 45 mA; 5.5 V < V_SUP< 27 V ⁽²¹⁾

V_DDRUN

V

2,425

2.5

2,575

Normal Mode Output Current Limitation (I_VDD

T_J< 25 °C

^T_J 25 °C

Stop Mode Output Voltage´

)

I_VDDLIMRUN

mA

V

-

80

120

143

V_DDSTOP

2.25

2.5

2.75

(I_VDD+ I_VDDINTERNAL< 500 µA for T_J 25 °C; I_VDD+ I_VDDINTERNAL

<

400 µA for T_J< 25 °C) ⁽²¹⁾

Stop Mode Output Current Limitation (I_VDD

)

I_VDDLIMSTOP

-

10

mA

mV

Line Regulation

Normal Mode, I_VDD= 45 mA

Stop Mode, I_VDD= 1.0 mA

LR_RUN

LR_STOP

-

10

-

12.5

200

Load Regulation

mV

Normal Mode, 1.0 mA < I_VDD< 45 mA

Normal Mode, V_{SUP =}3.6 V, 1.0 mA < I_VDD< 30 mA

Stop Mode, 100 µA < I_VDD< 500 µA

LD_RUN

LD_CRK

LD_STOP

-

7.5

-

40

200

External Capacitor

External Capacitor ESR

Note:

C_VDD

1.0

-

10

µF

C_{VDD_R}

Ohm

21.

I_VDDINTERNALincludes internal consumption from both analog and MCU die.

MM912F634

Freescale Semiconductor

15

Electrical Characteristics

Static Electrical Characteristics

Table 15. Static Electrical Characteristics - Hall Sensor Supply Output - HSUP

Ratings

Symbol

Min

Typ

Max

Unit

^{Current Limitation (3.7 V} V_SUP 18 V)

I_HSUP

40

70

90

mA

Output Drain-to-Source On resistance

R_DS(ON)

Ohm

T_{J =}150 °C, I_LOAD= 30 mA; 5.5 V  V_SUP 16 V

-

10

12

T

_{J =}150 °C, I_LOAD= 30 mA; 3.7 V  V_SUP< 5.5 V

^{Output Voltage: (18 V} V_SUP 27 V)

Load Regulation (1.0 mA < I_HSUP< 30 mA; V_SUP> 18 V)

Hall Supply Capacitor Range

VHSUP_max

LD_HSUP

C_HSUP

16

17.5

18

500

10

V

-

0.22

-

mV

µF

External Capacitor ESR

C_{HSUP_R}

10

Ohm

(continued)

Table 16. Static Electrical Characteristics - High Side Drivers - HS

Ratings

Symbol

Min

Typ

Max

Unit

Output Drain-to-Source On resistance

T_J= 25 °C, I_LOAD= 50 mA; V_SUP> 9.0 V

R_DS(ON)

Ohm

-

7.0

10

14

T

_{J =}150 °C, I_LOAD= 50 mA; V_SUP> 9.0 V

T_J= 150 °C, I_LOAD= 30 mA; 5.5V < V_SUP< 9.0 V

Output Current Limitation (0 V < V_OUT< V_SUP- 2.0 V)

Open Load Current Detection

I_LIMHSX

I_OLHSX

I_LEAK

60

110

5.0

-

250

7.5

10

-

mA

µA

V

-

Leakage Current (-0.2 V < V_HSx< V_S2+ 0.2 V)

Current Limitation Flag Threshold (5.5 V < V_SUP< 27 V)

-

V_THSC

V_SUP-2

-

Table 17. Static Electrical Characteristics - Low Side Drivers - LS

Ratings

Symbol

Min

Typ

Max

Unit

Output Drain-to-Source On resistance

R_DS(ON)

Ohm

T_J= 25 °C, I_LOAD= 150 mA, V_SUP> 9.0 V

T_J= 150 °C, I_LOAD= 150 mA, V_SUP> 9.0 V

T_J= 150 °C, I_LOAD= 120 mA, 5.5 V < V_SUP< 9.0 V

–

2.5

4.5

10

Output Current Limitation (2.0 V < V_OUT< V_SUP

Open Load Current Detection

)

I_LIMLSX

I_OLLSX

I_LEAK

180

-

275

380

12

mA

µA

8.0

Leakage Current (-0.2 V < V_OUT< VS1)

Active Output Energy Clamp (I_OUT= 150 mA)

Coil Series Resistance (I_OUT= 150 mA)

Coil Inductance (I_OUT= 150 mA)

-

10

V_CLAMP

R_COIL

V_THSC

40

120

-

45

V

Ohm

m

V

400

-

Current Limitation Flag Threshold (5.5 V < V_SUP< 27 V)

2.0

Table 18. Static Electrical Characteristics - LIN Physical Layer Interface - LIN

Ratings

Symbol

Min

Typ

Max

Unit

Current Limitation for Driver dominant state. V_BUS= 18 V

I_BUSLIM

40

120

-

200

-

mA

Input Leakage Current at the Receiver incl. Pull-up Resistor

RSLAVE; Driver OFF; VBUS = 0 V; VBAT = 12 V

IBUS_PAS_DOM

-1.0

Input Leakage Current at the Receiver incl. Pull-up Resistor

RSLAVE; Driver OFF;

8.0 V < VBAT < 18 V; 8.0 V < VBUS < 18 V; VBUS  VBAT

IBUS_PAS_REC

IBUS_NO_GND

-

20

µA

Input Leakage Current; GND Disconnected; GNDDEVICE = VSUP;

0 < VBUS < 18 V; VBAT = 12 V

-1.0

1.0

mA

MM912F634

Freescale Semiconductor

16

Electrical Characteristics

Static Electrical Characteristics

Table 18. Static Electrical Characteristics - LIN Physical Layer Interface - LIN (continued)

Ratings

Symbol

Min

Typ

Max

Unit

Input Leakage Current; VBAT disconnected;

VSUP_DEVICE = GND; 0 < VBUS < 18 V

IBUS_NO_BAT

-

100

µA

Receiver Input Voltage; Receiver Dominant State

Receiver Input Voltage; Receiver Recessive State

Receiver Threshold Center (V_{TH_DOM}+ V_{TH_REC})/2

Receiver Threshold Hysteresis (V_{TH_REC}- V_{TH_DOM}

Voltage Drop at the serial Diode

V_BUSDOM

V_BUSREC

V_{BUS_CNT}

V_{BUS_HYS}

D_{SER_INT}

R_SLAVE

-

0.6

0.475

-

0.4

-

V_SUP

V

0.5

-

0.525

0.175

1.0

)

0.4

20

0.7

30

5.0

-

LIN Pull-up Resistor

Bus Wake-up Threshold from Stop or Sleep⁽²²⁾

60

kOhm

V

V_WUP

4.5

-

6.0

Bus Dominant Voltage

V_DOM

2.5

V

Note:

22. Considering drop from VBAT to LIN, at very low VBAT level, the internal logic will detect a dominant as the threshold will not decrease

with VSUP.

MM912F634

Freescale Semiconductor

17

Electrical Characteristics

Static Electrical Characteristics

Table 19. Static Electrical Characteristics - High Voltage Inputs - Lx

Ratings

Symbol

Min

Typ

Max

Unit

Low Detection Threshold

7.0 V  V_SUP 27 V

5.5 V  V_SUP 7 V

V_THL

V_THH

V_HYS

V

2.2

1.5

2.5

3.4

4.0

High Detection Threshold

7.0 V  V_SUP 27 V

5.5 V  V_SUP 7 V

V

2.6

2.0

3.0

3.7

4.5

Hysteresis

5.5 V  V_SUP 27 V

0.25

-10

-

0.45

-

1.0

10

Input Current Lx (-0.2 V < V_IN< VS1)

Analog Input Impedance Lx

Lx Series Resistor

I_IN

R_LxIN

R_Lx

µA

MOhm

kOhm

nF

-

1.2

10.5

-

9.5

-

10

100

Lx Capacitor (optional)⁽²³⁾

C_Lx

Analog Input Divider Ratio (RATIO_Lx= V_Lx/ V_ADOUT0

LXDS (Lx Divider Select) = 0

LXDS (Lx Divider Select) = 1

)

RATIO_Lx

-

2.0

7.2

-

Analog Input Divider Ratio Accuracy

RATIO_LX

Lx_MATCH

-5.5

-

5.5

%

Analog Inputs Channel Ratio - Mismatch

LXDS (Lx Divider Select) = 0

LXDS (Lx Divider Select) = 1

-

5.0

Note:

23. The ESD behavior specified in Section 3.8, “ESD Protection and Latch-up Immunity" are guaranteed without the optional capacitor.

Table 20. Static Electrical Characteristics - General Purpose I/O - PTB[0…2]

Ratings

Symbol

Min

Typ

Max

Unit

Input high voltage

V_IH

V_IL

0.7V_DDX

V_SS-0.3

-

V_DDX+0.3

0.35V_DDX

-

V

Input low voltage

-

Input hysteresis

V_HYS

V_IH3.7

V_IL3.7

V_HYS3.7

I_IN

140

mV

V

Input high voltage (VS1 = 3.7 V)

Input low voltage (VS1 = 3.7 V)

Input hysteresis (VS1 = 3.7 V)

2.1

-

V_DDX+0.3

1.4

V_SS-0.3

100

-

200

-

V

300

mV

µA

Input leakage current (pins in high-impedance input mode)

(V_IN= V_DDXor V_SSX

-1.0

1.0

)

Output high voltage (pins in output mode) Full drive I_OH= –10 mA

Output low voltage (pins in output mode) Full drive I_OL= +10 mA

Internal pull-up resistance (V_IHmin > Input voltage > V_ILmax)

Input capacitance

V_OH

V_OL

V_DDX-0.8

-

0.8

48.75

-

V

-

R_PUL

C_IN

26.25

37.5

kOhm

pF

-

6.0

Clamp Voltage when selected as analog input

Analog Input impedance = 10 kOhm max, Capacitance = 12 pF

Analog Input Capacitance = 12 pF

V_{CL_AIN}

R_AIN

VDD

-

V

-

10

-

kOhm

pF

C_AIN

12

-

Maximum current all PTB combined (VDDX capability)

Output Drive strength at 10 MHz

I_BMAX

C_OUT

-15

-

15

100

mA

pF

-

MM912F634

Freescale Semiconductor

18

Electrical Characteristics

Static Electrical Characteristics

Table 21. Static Electrical Characteristics - Analog Digital Converter - ADC⁽²⁴⁾

Ratings

Symbol

Min

Typ

Max

Unit

ADC2p5 Reference Voltage

5.5 V < V_SUP< 27 V

V_ADC2p5RUN

V

2,45

-

2.5

-

2,55

100

ADC2p5 Reference Stop Mode Output Voltage

V_ADC2p5STO

mV

P

Line Regulation, Normal Mode

External Capacitor

LR_RUNA

-

10

12.5

1.0

10

mV

µF

C_ADC2p5

C_{VDD_R}

E_SCALE

E_DNL

0.1

-

External Capacitor ESR

-

Ohm

LSB

V

Scale Factor Error

-1

-

1

Differential Linearity Error

Integral Linearity Error

-1.5

-2.0

-0.5

-5.0

1.1

-

1.5

2.0

0.5

5.0

1.4

E_INL

-

Zero Offset Error

E_OFF

-

Quantization Error

E_Q

-

Total Error with offset compensation

TE

Bandgap measurement Channel (CH14) Valid Result Range

AD_CH14

1.25

(including 7.0% bg1p25 sleep accuracy + high-impedance measurement

(25)

error of 5.0% at f_ADC

)

Note:

24. No external load allowed on the ADC2p5 pin.

25. Reduced ADC frequency will lower measurement error.

Table 22. Static Electrical Characteristics - Current Sense Module - ISENSE

Ratings

Symbol

Min

Typ

Max

Unit

Gain

G

CSGS (Current Sense Gain Select) = 000

CSGS (Current Sense Gain Select) = 001

CSGS (Current Sense Gain Select) = 010

CSGS (Current Sense Gain Select) = 011

CSGS (Current Sense Gain Select) = 100

CSGS (Current Sense Gain Select) = 101

CSGS (Current Sense Gain Select) = 110

CSGS (Current Sense Gain Select) = 111

-

7.0

9.0

10

12

14

18

24

36

-

Gain Accuracy

-3.0

-1.5

-

3.0

1.5

-

%

Offset

Resolution⁽²⁶⁾

RES

V_IN

51

-

mA/LSB

V

ISENSEH, ISENSEL Input Common Mode Voltage Range

Current Sense Module - Normal Mode Current Consumption Adder (CSE = 1)

Note:

-0.2

-

3.0

-

I_ISENSE

600

µA

26. RES = 2.44 mV/(GAIN*R_SHUNT

)

MM912F634

Freescale Semiconductor

19

Electrical Characteristics

Static Electrical Characteristics

Table 23. Static Electrical Characteristics - Temperature Sensor - TSENSE

Ratings

Symbol

Min

Typ

Max

Unit

Internal Chip Temperature Sense Gain⁽²⁷⁾

TS_G

TS_Err

-

9.17

-

mV/k

°C

Internal Chip Temperature Sense Error at the end of conversion⁽²⁷⁾

Temperature represented by a ADC_INVoltage of 0.150 V⁽²⁷⁾

Temperature represented by a ADC_INVoltage of 1.984 V⁽²⁷⁾

–5.0

-55

145

5.0

-45

155

T_0.15V

T_1.984V

-50

150

°C

Note:

27. Guaranteed by design and characterization.

Table 24. Static Electrical Characteristics - Supply Voltage Sense - VSENSE and VS1SENSE

Ratings

Symbol

Min

Typ

Max

Unit

VSENSE Input Divider Ratio (RATIO_VSENSE= V_VSENSE/ ADCIN)

5.5 V < V_SUP< 27 V

RATIO_VSENS

E

10.8

-

VSENSE error - whole path (VSENSE pin to Digital value)

ER_VSENSE

-

5.0

%

VS1SENSE Input Divider Ratio (RATIO_VS1SENSE= V_VS1SENSE/ ADCIN)

5.5 V < V_SUP< 27 V

RATIO_VS1SE

NSE

10.8

-

VS1SENSE error - whole path (VS1 pin to Digital value)

ER_VS1SENSE

-

9.5

-

5.0

10.5

-

%

kOhm

nF

VSENSE Series Resistor

R_VSENSE

C_VSENSE

10

VSENSE Capacitor (optional)⁽²⁸⁾

Note:

100

28. The ESD behavior specified in Section 3.8, “ESD Protection and Latch-up Immunity" is guaranteed without the optional capacitor.

MM912F634

20

Freescale Semiconductor

Electrical Characteristics

Static Electrical Characteristics

3.5.2

Static Electrical Characteristics MCU Die

I/O Characteristics

3.5.2.1

This section describes the characteristics of all I/O pins except EXTAL, XTAL, TEST and supply pins.

Table 25. 5.0 V I/O Characteristics for PTA, RESET and BKGD Pins

Ratings

Symbol

Min

Typ

Max

Unit

Input high voltage

Input low voltage

Input hysteresis

V_IH

V_IL

0.65*V_DD

-

V

-

V_DD+ 0.3

-

V_SS- 0.3

-

0.35*V_DD

V

V_IL

-

250

-

V

V_HYS

I_IN

mV

A

Input leakage current (pins in high-impedance input mode)

or V

-1.0

1.0

V

in = DDX

SSX

Output high voltage (pins in output mode)

Partial Drive I -2.0 mA

V_OH

V_OL

V_DD– 0.8

-

V

OH =

Output high voltage (pins in output mode)

Full Drive I -10 mA

V_DD– 0.8

-

OH =

Output low voltage (pins in output mode)

Partial drive I_{OL =}+2.0 mA

-

0.8

50

-

V

Output low voltage (pins in output mode)

Full Drive I_{OL =}+10 mA

V_OL

-

V

Internal pull-up resistance

(V_IHmin > input voltage > V_ILmax)

R_PUL

R_PDH

C_in

25

-

k

Internal pull-down resistance

(V_IHmin > input voltage > V_ILmax)

-

Input capacitance

6.0

pF

Injection current⁽²⁹⁾

mA

Single pin limit

Total device Limit, sum of all injected currents

I_ICS

I_ICP

-2.5

-25

-

2.5

25

Note:

29. Refer to Section 3.8, “ESD Protection and Latch-up Immunity"” for more details.

MM912F634

Freescale Semiconductor

21

Electrical Characteristics

Dynamic Electrical Characteristics

3.6

Dynamic Electrical Characteristics

Dynamic electrical characteristics noted under conditions 5.5V  VSUP  18 V, -40 °C  T_A 105 °C, unless otherwise noted.

Typical values noted reflect the approximate parameter mean at T_A= 25 °C under nominal conditions unless otherwise noted.

3.6.1

Dynamic Electrical Characteristics Analog Die

Table 26. Dynamic Electrical Characteristics - Modes of Operation

Ratings

Symbol

Min

Typ

Max

Unit

VDD Short Timeout

Analog Base Clock

Reset Delay

t_VTO

f_BASE

t_RST

110

-

150

100

200

205

-

ms

kHz

µs

140

280

Table 27. Dynamic Electrical Characteristics - Power Supply

Ratings

Symbol

Min

Typ

Max

Unit

Glitch Filter Low Battery Warning (LBI)⁽³⁰⁾

Glitch Filter Low Voltage Warning (LVI)⁽³⁰⁾

Glitch Filter High Voltage Warning (HVI)⁽³⁰⁾

t_LB

t_LV

t_HV

-

2.0

-

µs

Note:

30. Guaranteed by design.

Table 28. Dynamic Electrical Characteristics - Die to Die Interface - D2D

Ratings

Symbol

Min

Typ

Max

Unit

(31)

Operating Frequency (D2DCLK, D2D[0:3])

f_D2D

f_ADC(MIN)

-

f_BUSMAX

MHz

Note:

31. f_BUSMAXfrequency ratings differ by device and is specified in Table 1

Table 29. Dynamic Electrical Characteristics - Resets

Ratings

Symbol

Min

Typ

Max

Unit

Reset Deglitch Filter Time

Reset Low Level Duration

t_RSTDF

1.2

2.0

3.0

µs

t_RSTLOW

140

200

280

Table 30. Dynamic Electrical Characteristics - Wake-up / Cyclic Sense

Ratings

Symbol

Min

Typ

Max

Unit

Lx Wake-up Filter Time

t_WUF

CS_AC

CS_ACT

t_S

-

20

-

s

%

-

Cyclic Sense / Forced Wake-up Timing Accuracy - not trimmed

Cyclic Sense / Forced Wake-up Timing Accuracy - trimmed⁽³²⁾

Time between HSx on and Lx sense during cyclic sense

HSx ON duration during Cyclic Sense

-35

-5.0

35

-

5.0

same as t_HSON/ t_HSONT

t_HSON

t_HSONT

140

180

200

280

220

s

HSx ON duration during Cyclic Sense - trimmed⁽³²⁾

Note:

32. Trimming parameters are not available in Sleep mode.

MM912F634

Freescale Semiconductor

22

Electrical Characteristics

Dynamic Electrical Characteristics

Table 31. Dynamic Electrical Characteristics - Window Watchdog

Ratings

Symbol

Min

Typ

Max

Unit

Initial Non-window Watchdog Timeout

Watchdog Timeout Accuracy - not trimmed

Watchdog Timeout Accuracy - trimmed

t_IWDTO

WD_AC

WD_ACT

110

-35

150

190

35

ms

%

-

-5.0

5.0

%

Table 32. Dynamic Electrical Characteristics - High Side Drivers - HS

Ratings

High Side Operating Frequency⁽³³⁾

Symbol

f_HS

Min

Typ

Max

Unit

-

50

kHz

Load Condition: C_LOAD2.2 nF; R_LOAD500 

Note:

33. Guaranteed by design.

Table 33. Dynamic Electrical Characteristics - Low Side Drivers - LS

Ratings

Symbol

Min

Typ

Max

Unit

Low Side Operating Frequency

f_LS

-

10

kHz

Table 34. Dynamic Electrical Characteristics - LIN Physical Layer Interface - LIN

Ratings

Symbol

Min

Typ

Max

Unit

Bus Wake-up Deglitcher (Sleep and Stop Mode)

t_PROPWL

BR_FAST

t_{REC_PD}

t_{REC_SYM}

60

80

-

100

6.0

µs

kBit/s

µs

Fast Bit Rate (Programming Mode)

-

(34)

Propagation Delay of Receiver, t_{REC_PD =}MAX (t_{REC_PDR}, t_{REC_PDF}

Symmetry of Receiver Propagation Delay, t_{REC_PDF}- t_{REC_PDR}

)

-

-2.0

-

2.0

µs

LIN Driver - 20.0 kBit/s; Bus load conditions (C_BUS; R_BUS): 1.0 nF; 1.0 k / 6,8 nF;660  / 10 nF;500 . Measurement thresholds: 50% of TXD

signal to LIN signal threshold defined at each parameter. See Figure 5 and Figure 6.

Duty Cycle 1:

D1

0.396

-

TH_REC(MAX)= 0.744 x V_SUP

TH_DOM(MAX)= 0.581 x V_SUP

7.0 V V_SUP18 V; t_{Bit =}50 µs;

D1 = t_{BUS_REC(MIN)}/(2 x t_Bit

)

Duty Cycle 2:

D2

-

0.581

TH_REC(MIN)= 0.422 x V_SUP

TH_DOM(MIN)= 0.284 x V_SUP

7.6 V V_SUP18 V; t_{BIT =}50 µs

D2 = t_{BUS_REC(MAX)}/(2 x t_BIT

)

LIN Driver - 10.0 kBit/s; Bus load conditions (C_BUS; R_BUS): 1.0 nF; 1.0 k / 6,8 nF;660  / 10 nF;500  Measurement thresholds: 50% of TXD

signal to LIN signal threshold defined at each parameter. See Figure 5 and Figure 7.

Duty Cycle 3:

D3

0.417

-

TH_REC(MAX)= 0.778 x V_SUP

TH_DOM(MAX)= 0.616 x V_SUP

7.0 V V_SUP18 V; t_{BIT =}96 µs

D3 = T_{BUS_REC(MIN)}/(2 x t_BIT

)

Duty Cycle 4:

D4

-

0.590

TH_REC(MIN)= 0.389 x V_SUP

TH_DOM(MIN)= 0.251 x V_SUP

7.6 V V_SUP18 V; t_{BIT =}96 µs

D4 = t_{BUS_REC(MAX)}/(2 x t_BIT

)

MM912F634

Freescale Semiconductor

23

Electrical Characteristics

Dynamic Electrical Characteristics

Table 34. Dynamic Electrical Characteristics - LIN Physical Layer Interface - LIN (continued)

Ratings

Symbol

Min

Typ

Max

Unit

Transmitter Symmetry

_{TRAN_SYM}< MAX(t_{TRAN_SYM}60%, t_{TRAN_SYM}40%)

t_{TRAN_SYM}

-7.25

0

7.25

µs

t

tran_sym60% = ttran_pdf60% - ttran_pdr60%

tran_sym40% = ttran_pdf40% - ttran_pdr40%

Note:

34. V_SUPfrom 7.0 to 18 V, bus load R_BUSand C_BUS1.0 nF / 1.0 k, 6.8 nF / 660 , 10 nF / 500 . Measurement thresholds: 50% of TXD

signal to LIN signal threshold defined at each parameter. See Figure 5 and Figure 8.

35. LIN Transmitter Timing, (V_SUPfrom 7.0 to 18 V) - See Figure 9

V_SU

VSU

R_O

C_O

TXD

LIN

RXD

GND

Note: Rn and Cn: 1.0k/1.0nF, 660/6.8

Figure 5. Test Circuit for Timing Measurements

Figure 6. LIN Timing Measurements for Normal Baud Rate

MM912F634

Freescale Semiconductor

24

Electrical Characteristics

Dynamic Electrical Characteristics

Figure 7. LIN Timing Measurements for Slow Baud Rate

Figure 8. LIN Receiver Timing

TX

BUS

60%

40%

ttran_pdf60%

ttran_pdf40%

Figure 9. LIN Transmitter Timing

ttran_pdr40%

ttran_pdr60%

MM912F634

Freescale Semiconductor

25

Electrical Characteristics

Dynamic Electrical Characteristics

Table 35. Dynamic Electrical Characteristics - General Purpose I/O - PTB[0…2]

Ratings

Symbol

Min

Typ

Max

Unit

GPIO Digital Frequency⁽³⁶⁾

Propagation Delay - Rising Edge^{(36), (37)}

Rise Time - Rising Edge⁽³⁶⁾

Propagation Delay - Falling Edge⁽³⁶⁾

Rise Time - Falling Edge⁽³⁶⁾

f_PTB

t_PDR

t_RISE

t_PDF

t_FALL

-

10

20

MHz

ns

17.5

20

ns

17.5

ns

Note:

36. Guaranteed by design.

37. Load PTBx = 100 pF.

Table 36. Dynamic Electrical Characteristics - Analog Digital Converter - ADC

Ratings

Symbol

Min

Typ

Max

Unit

ADC Operating Frequency⁽³⁸⁾

Conversion Time (from ACCR write to CC Flag)⁽³⁸⁾

Sample Frequency Channel 14 (Bandgap)⁽³⁸⁾

f_ADC

t_CONV

f_CH14

1.6

2.0

26

-

2.4

MHz

clk

-

2.5

kHz

Note:

38. Guaranteed by design.

3.6.2

Dynamic Electrical Characteristics MCU Die

NVM Timing

3.6.2.1

The time base for all NVM program or erase operations is derived from the bus block. A minimum bus frequency f_NVMBUSis

required for performing program or erase operations. The NVM module do not has any means to monitor the frequency and will

not prevent a program or erase operation at frequencies above or below the specified minimum. Attempting to program or erase

the NVM modules at a lower frequency, a full program, or erase transition is not assured.

The Flash program and erase operations are timed using a clock derived from the bus clock using the FCLKDIV and register.

The frequency of this clock must be set within the limits specified as f_NVMOP

.

The minimum program and erase times shown in Table 37 are calculated for maximum f_NVMOPand maximum f_BUS. The

maximum times are calculated for minimum f_NVMOPand a f_BUSof 2.0 MHz.

3.6.2.1.1

Single Word Programming

The programming time for single word programming is dependant on the bus frequency as a well as on the frequency f_NVMOP

,

and can be calculated according to the following formula.

1

------------------------

----------

t

= 9 

+ 25 

swpgm

f

NVMOP

bus

MM912F634

Freescale Semiconductor

26

Electrical Characteristics

3.6.2.1.2 Burst Programming

Dynamic Electrical Characteristics

This applies only to the Flash, where up to 64 words in a row can be programmed consecutively, using burst programming by

keeping the command pipeline filled. The time to program a consecutive word can be calculated as:

1

------------------------

----------

t

= 4 

+ 9 

bwpgm

f

NVMOP

bus

The time to program a whole row is:

t

= t

+ 63  t

brpgm

swpgm

bwpgm

Burst programming is more than 2 times faster than single word programming.

3.6.2.1.3 Sector Erase

NOTE

The sector erase cycle is divided into 16 individual erase pulses to achieve faster system

response during the erase flow. The given erase time (t_ERA) specifies the time considering

consecutive pulses.

Erasing a 512-byte Flash sector takes:

1

------------------------

t

 4000 

era

f

NVMOP

The setup time can be ignored for this operation.

3.6.2.1.4

Mass Erase

Erasing a NVM block takes:

1

t

 20000 Þ ------------------------

mass

f

NVMOP

The setup time can be ignored for this operation.

MM912F634

Freescale Semiconductor

27

Electrical Characteristics

3.6.2.1.5 Blank Check

Dynamic Electrical Characteristics

The time it takes to perform a blank check on the Flash is dependant on the location of the first non-blank word, starting at relative

address zero. It takes one bus cycle per word to verify plus a setup of the command.

t

ª location Þ t

+ 10 Þ t

check

cyc

Table 37. NVM Timing Characteristics

Rating

Symbol

Min

Typ

Max

Unit

Bus frequency for programming or erase operations

Operating frequency

f_NVMBUS

f_NVMOP

t_SWPGM

t_BWPGM

t_BRPGM

t_ERA

1.0

-

MHz

kHz

s

150

200

Single word programming time

Flash burst programming consecutive word

Flash burst programming time for 64 words⁽⁴²⁾

Sector erase time⁽⁴⁰⁾

46⁽³⁹⁾

20.4⁽³⁹⁾

1331.2⁽³⁹⁾

20⁽⁴¹⁾

74.5⁽³⁹⁾

31⁽⁴⁰⁾

s

2027.5⁽⁴⁰⁾

26.7⁽⁴⁰⁾

133⁽⁴⁰⁾

65546⁽⁴³⁾

s

ms

t_CYC

Mass erase time

t_MASS

100⁽⁴³⁾

11⁽⁴²⁾

Blank check time Flash per block

Note:

t_CHECK

39. Minimum programming times are achieved under maximum NVM operating frequency f_NVMOPand maximum bus frequency f_BUS

.

40. The sector erase cycle is divided into 16 individual erase pulses to achieve faster system response during the erase flow. The given

erase time (t_ERA) specifies the time considering consecutive pulses.

41. Minimum erase times are achieved under maximum NVM operating frequency, f_NVMOP

.

42. Minimum time, if first word in the array is not blank.

43. Maximum time to complete check on an erased block.

MM912F634

Freescale Semiconductor

28

Electrical Characteristics

3.6.2.2 NVM Reliability

Dynamic Electrical Characteristics

The reliability of the NVM blocks is guaranteed by stress tests during qualification, constant process monitors, and burn-in to

screen early life failures. The program/erase cycle count on the sector is incremented every time a sector or mass erase event

is executed.

Table 38. NVM Reliability Characteristics

Rating

Symbol

Min

Typ

Max

Unit

,

(45)

Data retention after 10,000 program/erase cycles for T_JAVG85 C⁽⁴⁴⁾

t_FLRET

15

20

100⁽⁴⁶⁾

-

Years

,

(45)

Data retention with <100 program/erase cycles for T_JAVG 85 C⁽⁴⁴⁾

Number of program/erase cycles⁽⁴⁵⁾

n_FL

10,000

Cycles

(-40 C  T_J 0 C)

Number of program/erase cycles⁽⁴⁵⁾

10,000

100,000⁽⁴⁷⁾

-

(0 C  T_J 140 C)

Note:

44.

45.

T

_JAVGis the Average Junction Temperature

_JAVGwill not exceed 85 °C considering a typical temperature profile over the lifetime of a consumer, industrial, or automotive application.

46. Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25 °C, using

the Arrhenius equation. For additional information on how Freescale defines Typical Data Retention, refer to Engineering Bulletin EB618.

47. Spec table quotes typical endurance evaluated at 25 °C for this product family, typical endurance at various temperature can be estimated

using the graph in Figure 10. For additional information on how Freescale defines Typical Endurance, refer to Engineering Bulletin EB619.

300

250

200

150

100

50

0

120

60

80

-40

-20

0

20

40

100

140

Operating Temperature T_J[C]

Figure 10. Typical Flash Cycling Endurance vs. Temperature

MM912F634

Freescale Semiconductor

29

Electrical Characteristics

Dynamic Electrical Characteristics

3.6.2.3

Reset, Oscillator and Internal Clock Generation

Startup & FLL Characteristics

3.6.2.3.1

Table 39 summarizes several startup characteristics explained in this section. Detailed description of the startup behavior can be

found in the Clock and Reset Generator (CRG) block description.

Table 39. Startup & FLL Characteristics

Rating

Symbol

Min

Typ

Max

Unit

Internal Reference Frequency⁽⁴⁸⁾(-40 C  T_J 105 C)

Internal Reference Frequency⁽⁴⁸⁾(-40 C  T_J 140 C)

Allowed frequency range for FLL Reference Clock

DCO Frequency locking range

f_{IREF_TRIM}

f_FLLREF

f_DCO

31.36

32

-

32.64

33.60

40

kHz

MHz

ms

30.40

25.52

32

18

-

40

DCO minimum frequency

f_{DCO_MIN}

t_STAB

| _LOCK

-

29

DCO stabilization delay in frequency locked loop

Lock Detection

0.3

-

(49)

|

0

1.5

2.5

0.2

-

%

(49)

Un-lock Detection

| _UNLOCCK

|

0.5

-

%

(50)

DCO quantization error

t_DCO

-

%t_DCO

STOP recovery time

t_{STP_REC}

-

20

s

(Internal Reference Clock trimmed to 32 kHz)

Oscillator Monitor Failure Assert Frequency

Reset input pulse width, minimum input time

Startup from Reset

f_OMFA

PW_RSTL

n_RST

50

2.0

772

-

200

-

kHz

t_{DCO_MIN}

773

Note:

48. Reference Frequency is factory trimmed

49. % deviation from target frequency, target frequency is f_{IREF_TRIM}* (1000 + 2*MULT[6:0])

50. _{DCO =}40 MHz, f_{IREF_TRIM =}32 kHz, MULT = $7D

f

MM912F634

Freescale Semiconductor

30

Electrical Characteristics

3.6.2.3.2 Power On Reset

Dynamic Electrical Characteristics

The release level V_PORDand the assert level V_PORAare derived from the VDD supply. After releasing the POR reset, the oscillator

is started.

V

V_DD

V_PORD

V_PORA

t

POR

Figure 11. Power on Reset

Symbol

Table 40. Power On Reset Characteristics

Rating

Min

Typ

Max

Unit

Power On Reset assert level

V_PORA

V_PORD

0.84

-

1.51

-

V

Power On Reset de-assert level

2.01

MM912F634

Freescale Semiconductor

31

Electrical Characteristics

3.6.2.3.3 Oscillator

Dynamic Electrical Characteristics

The device features an internal full-swing Pierce oscillator configuration. The device features an oscillator monitor. An oscillator

monitor failure is asserted if the frequency is below the assert frequency f_CMFA.

Table 41. Oscillator Characteristics

Rating

Symbol

Min

4.0

-

Typ

-

Max

16

Unit

MHz

ms

f_OSC

Crystal oscillator range

Oscillator start-up time⁽⁵¹⁾

t_UPOSC

f_CMFA

C_IN

2.0

100

7.0

5.0

200

-

Clock Monitor Failure Assert Frequency

Input Capacitance (EXTAL, XTAL pins)

50

-

KHz

pF

Note:

51. f_OSC= 4.0 MHz, C = 22 pF.

3.6.2.4

SPI Timing

This section provides electrical parameters and ratings for the SPI. Table 42 lists the measurement conditions.

Table 42. Measurement Conditions

Description

Value

Unit

Drive mode

Full drive mode

50

-

(52)

Load capacitance C_{LOAD ,}on all outputs

Thresholds for delay measurement points

pF

V

(20% / 80%) VDDX

Note:

52. Timing specified for equal load on all SPI output pins. Avoid asymmetric load.

MM912F634

Freescale Semiconductor

32

Electrical Characteristics

Dynamic Electrical Characteristics

3.6.2.4.1

Master Mode

Figure 12 depicts the timing diagram for master mode with transmission format CPHA = 0.

SS1

(Output)

2

1

12

13

3

SCK

(CPOL = 0)

4

(Output)

4

SCK

(CPOL = 1)

(Output)

5

6

MISO

(Input)

Bit MSB-1… 1

9

MSB IN2

10

MSB OUT2

LSB IN

11

MOSI

(Output)

Bit MSB-1…1

LSB OUT

1. If configured as an output.

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, bit 2... MSB.

Figure 12. SPI Master Timing (CPHA = 0)

In Figure 13 depicts the timing diagram for master mode with transmission format CPHA=1.

SS1

(Output)

1

12

13

3

2

SCK

(CPOL = 0)

(Output)

4

SCK

(CPOL = 1)

(Output)

5

6

MISO

(Input)

Bit MSB-1… 1

MSB IN2

LSB IN

11

9

MOSI

(Output)

Port Data

Bit MSB-1… 1

Master LSB OUT

Port Data

Master MSB OUT2

1.If configured as output

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1,bit 2... MSB.

Figure 13. SPI Master Timing (CPHA = 1)

MM912F634

Freescale Semiconductor

33

Electrical Characteristics

Dynamic Electrical Characteristics

Table 43 lists the timing characteristics for master mode.

Table 43. SPI Master Mode Timing Characteristics

Characteristic

Symbol

Min

Typ

Max

Unit

SCK frequency

f_SCK

t_SCK

t_LEAD

t_LAG

t_WSCK

t_SU

1/2048

-

12

f_BUS

t_BUS

t_SCK

ns

SCK period

2.0

-

2048

Enable lead time

-

1/2

-

Enable lag time

-

1/2

Clock (SCK) high or low time

Data setup time (inputs)

Data hold time (inputs)

Data valid after SCK edge

Data valid after SS fall (CPHA = 0)

Data hold time (outputs)

Rise and fall time inputs

Rise and fall time outputs

1/2

-

8.0

-

t_HI

-

ns

t_VSCK

t_VSS

t_HO

29

15

-

ns

-

ns

20

-

ns

t_RFI

8.0

ns

t_RFO

-

ns

MM912F634

Freescale Semiconductor

34

Electrical Characteristics

Dynamic Electrical Characteristics

3.6.2.4.2

Slave Mode

Figure 14 depicts the timing diagram for slave mode with transmission format CPHA = 0.

SS

(Input)

1

12

13

3

SCK

(CPOL = 0)

(Input)

4

2

SCK

(CPOL = 1)

10

7

(Input)

8

9

11

MISO

(Output)

See

Note

Bit MSB-1…1

Slave LSB OUT

Slave MSB

6

Note

5

MOSI

(Input)

Bit MSB-1…1

MSB IN

LSB IN

NOTE: Not defined

Figure 14. SPI Slave Timing (CPHA = 0)

Figure 15 depicts the timing diagram for slave mode with transmission format CPHA = 1.

SS

(Input)

3

1

12

13

2

SCK

(CPOL = 0)

(Input)

4

12

11

SCK

(CPOL = 1)

(Input)

8

9

MISO

See

Bit MSB-1…1

Slave MSB OUT

Slave LSB OUT

LSB IN

Note

(Output)

7

5

6

MOSI

(Input)

MSB IN

Bit MSB-1…1

NOTE: Not defined

Figure 15. SPI Slave Timing (CPHA = 1)

MM912F634

Freescale Semiconductor

35

Electrical Characteristics

Dynamic Electrical Characteristics

Table 44 lists the timing characteristics for slave mode.

Table 44. SPI Slave Mode Timing Characteristics

Characteristic

Symbol

Min

Typ

Max

Unit

SCK frequency

SCK period

f_SCK

t_SCK

t_LEAD

t_LAG

t_WSCK

t_SU

DC

4.0

8.0

-

14

f_BUS

t_BUS

ns



Enable lead time

Enable lag time

-

Clock (SCK) high or low time

Data setup time (inputs)

Data hold time (inputs)

Slave access time (time to data active)

Slave MISO disable time

Data valid after SCK edge

Data valid after SS fall

Data hold time (outputs)

Rise and fall time inputs

Rise and fall time outputs

Note:

-

t_HI

-

ns

t_A

20

ns

t_DIS

-

22

ns

(52)

t_VSCK

t_VSS

t_HO

-

29 + 0.5  t_BUS

ns

-

29 + 0.5  t_BUS

ns

20

-

ns

t_RFI

8.0

ns

t_RFO

-

ns

53. 0.5 t_BUSadded due to internal synchronization delay

MM912F634

Freescale Semiconductor

36

Electrical Characteristics

Thermal Protection Characteristics

3.7

Thermal Protection Characteristics

Characteristics noted under conditions 5.5V  VSUP  18 V, -40 °C  T_A 105 °C, unless otherwise noted. Typical values noted

reflect the approximate parameter mean at T_A= 25 °C under nominal conditions unless otherwise noted.

Table 45. Thermal Characteristics - Voltage Regulators VDD (2.5 V) & VDDX (5.0 V)

Ratings

Symbol

Min

Typ

Max

Unit

VDD/VDDX High-temperature Warning (HTI)⁽⁵⁴⁾

°C

Threshold

Hysteresis

T_HTI

T_{HTI_H}

110

-

125

10

140

-

VDD/VDDX Over-temperature Shutdown⁽⁵⁴⁾

°C

Threshold

Hysteresis

T_SD

T_{SD_H}

155

-

170

10

185

-

HSUP Over-temperature Shutdown⁽⁵⁴⁾

HSUP Over-temperature Shutdown Hysteresis⁽⁵⁴⁾

HS Over-temperature Shutdown⁽⁵⁴⁾

HS Over-temperature Shutdown Hysteresis⁽⁵⁴⁾

LS Over-temperature Shutdown⁽⁵⁴⁾

LS Over-temperature Shutdown Hysteresis⁽⁵⁴⁾

LIN Over-temperature Shutdown⁽⁵⁴⁾

LIN Over-temperature Shutdown Hysteresis⁽⁵⁴⁾

T_HSUPSD

T_{HSUPSD_HYS}

T_HSSD

150

165

10

180

°C

-

150

-

180

-

165

10

T_{HSSD_HYS}

T_LSSD

T_{LSSD_HYS}

T_LINSD

150

-

165

10

180

-

150

-

165

20

200

-

T_{LINSD_HYS}

Note:

54. Guaranteed by characterization. Functionality tested.

MM912F634

Freescale Semiconductor

37

Electrical Characteristics

ESD Protection and Latch-up Immunity

3.8

ESD Protection and Latch-up Immunity

All ESD testing is in conformity with CDF-AEC-Q100 stress test qualification for automotive grade integrated circuits. During the

device qualification, ESD stresses were performed for the Human Body Model (HBM), Machine Model (MM), Charge Device

Model (CDM), as well as LIN transceiver specific specifications.

A device will be defined as a failure if after exposure to ESD pulses, the device no longer meets the device specification.

Complete DC parametric and functional testing is performed per the applicable device specification at room temperature,

followed by hot temperature, unless specified otherwise in the device specification.

Table 46. ESD and Latch-up Protection Characteristics

Ratings

Symbol

Value

Unit

ESD - Human Body Model (HBM) following AEC-Q100 / JESD22-A114

V_HBM

V

(C_ZAP= 100 pF, R_ZAP= 1500 )

- LIN (DGND, PGND, AGND, and LGND shorted)

- VS1, VS2, VSENSE, Lx

- HSx

±8000

±4000

±3000

±2000

- All other Pins

ESD - Charged Device Model (CDM) following AEC-Q100,

Corner Pins (1, 12, 13, 24, 25, 36, 37, and 48)

All other Pins

V_CDM

V

±750

±500

ESD - Machine Model (MM) following AEC-Q100

(C_ZAP= 200 pF, R_ZAP= 0 ), All Pins

Latch-up current at T_A= 125 C⁽⁵⁵⁾

ESD GUN - LIN Conformance Test Specification⁽⁵⁷⁾, unpowered, contact

discharge, C_ZAP= 150 pF, R_ZAP= 330 .

- LIN (with or without bus filter C_BUS=220 pF)

- VS1, VS2 with C_VS

V_MM

I_LAT

±200

±100

mA

V

±15000

±20000

±6000

- Lx with serial R_LX

ESD GUN - IEC 61000-4-2 Test Specification⁽⁵⁸⁾, unpowered, contact

discharge, C_ZAP= 150 pF, R_ZAP= 330 

V

- LIN (with or without bus filter C_BUS=220 pF)

±8000

(56)

- VSENSE with serial R_VSENSE

- VS1, VS2 with C_VS

- Lx with serial R_LX

ESD GUN - ISO10605 Test Specification⁽⁵⁸⁾, unpowered, contact discharge,

C_ZAP= 150 pF, R_ZAP= 2.0 k

- LIN (with or without bus filter C_BUS=220pF)

±6000

(56)

- VSENSE with serial R_VSENSE

- VS1, VS2 with C_VS

- Lx with serial R_LX

ESD GUN - ISO10605 Test Specification⁽⁵⁸⁾, powered, contact discharge,

C_ZAP= 330 pF, R_ZAP= 2.0 k

- LIN (with or without bus filter C_BUS=220 pF)

- VSENSE with serial R_VSENSE

- VS1, VS2 with C_VS

- Lx with serial R_LX

±8000

(56)

Note:

55. Input Voltage Limit = -2.5 to 7.5 V.

56. With C_VBAT(10…100 nF) as part of the battery path.

57. Certification available on request

58. Tested internally only; certification pending

MM912F634

Freescale Semiconductor

38

Electrical Characteristics

Additional Test Information ISO7637-2

3.9

Additional Test Information ISO7637-2

For immunity against transients for the LIN, Lx, and VBAT is specified according to the LIN Conformance Test Specification -

Section LIN EMC Test Specification refer to the LIN Conformance Test Certification Report - available as a separate document

from ISO.

MM912F634

Freescale Semiconductor

39

Functional Description and Application Information

Introduction

4

Functional Description and Application Information

Introduction

4.1

This chapter describes the MM912F634 dual die device functions on a block by block base. To distinguish between the module

location being the MCU die or the analog die, the following symbols are shown on all module cover pages:

The documented module is physically located on the Analog die. This applies to Section 4.2, “MM912F634 - Analog

Die Overview" through Section 4.25, “MM912F634 - Analog Die Trimming".

MCU

ANALOG

The documented module is physically located on the Microcontroller die. This applies to Section 4.26, “MM912F634

- MCU Die Overview" through Section 4.38, “Serial Peripheral Interface (S12SPIV4)".

MCU

ANALOG

Sections concerning both dies or the complete device will not have a specific indication.

4.1.1 Device Register Maps

Table 47 shows the device register memory map overview for the 32 kByte MCU die (MC9S12I32).

NOTE

Reserved register space shown in Table 47 is not allocated to any module. This register

space is reserved for future use, and will show as grayed areas in tables throughout this

document. Writing to these locations has no effect. Read access to these locations returns

zero.

Table 47. Device Register Memory Map Overview

Address

Module

PIM (port integration module)

Size (Bytes)

0x0000–0x0007

0x0008–0x0019

0x001A–0x001B

0x001C–0x001E

0x001F

8

18

2

Reserved

Part ID register

Reserved

3

INT (interrupt module)

DBG (debug module)

MMC (memory map control)

CRG (clock and reset generator)

RTI (real time interrupt)

COP (computer operating properly)

Reserved

1

0x0020–0x002F

0x0030-0x0033

0x0034–0x003B

0x003C–0x003D

0x003E–0x003F

0x0040–0x00D7

0x00D8–0x00DF

0x00E0–0x00E7

0x00E8-0x00EF

0x00F0–0x00FF

0x0100–0x0113

0x0114–0x011F

0x0120–0x0123

0x0124–0x01FF

0x0200-0x02FF

0x0300–0x03FF

16

4

8

2

152

8

D2DI (die 2 die initiator)

Reserved

8

SPI (serial peripheral interface)

Reserved

8

16

20

12

4

FTSR control registers

Reserved

PIM (port integration module)

Reserved

220

256

D2DI (die 2 die initiator, blocking access window)

D2DI (die 2 die initiator, non-blocking access window)

MM912F634

Freescale Semiconductor

40

Functional Description and Application Information

4.1.2 Detailed Module Register Maps

Introduction

Table 48 to Table 65 show the detailed module maps of the MM912F634 MCU die.

Table 48. 0x0000–0x0017 Port Integration Module (PIM) 1of 2

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

R

W

R

0

0x0000

PTA

PTA5

0

PTA4

0

PTA3

0

PTA2

0

PTA1

0

PTA 0

0

0x0001

0x0002

0x0003

0x0004

0x0005

0x0006

0x0007

Reserved

DDRA

W

R

DDRA5

0

DDRA4

0

DDRA3

0

DDRA2

0

DDRA1

0

DDRA0

0

W

R

Reserved

PTC

W

R

0

PTC1

PTD1

PTC0

PTD0

W

R

W

R

PTD

PTD7

0

PTD6

0

PTD5

0

PTD4

0

PTD3

0

PTD2

0

DDRC

DDRC1

DDRC0

W

R

W

R

DDRD

DDRD7

0

DDRD6

0

DDRD5

0

DDRD4

0

DDRD3

0

DDRD2

0

DDRD1

0

DDRD0

0

0x0008-

0x0017

Reserved

W

Table 49. 0x0018–0x001E Miscellaneous Peripheral

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

R

W

R

0

0x0018-0

x0019

Reserved

PARTIDH

0x001A

0x001B

PARTIDH

PARTIDL

Reserved

W

R

PARTIDL

W

R

0

0x001C-

0x001E

W

Table 50. 0x001F Interrupt Module (S12SINT)

R

0x001F

IVBR

IVB_ADDR[7:0]

W

MM912F634

Freescale Semiconductor

41

Functional Description and Application Information

Table 51. 0x0020–0x002F Debug Module (S12XDBG)

Introduction

Bit 0

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

R

W

R

0

TRIG

0

0x0020

DBGC1

ARM

BDM

0

DBGBRK

0

COMRV

TBF⁽⁵⁹⁾

0

SSF2

SSF1

0

SSF0

0x0021

0x0022

DBGSR

DBGTCR

DBGC2

W

R

0

TSOURCE

0

TRCMOD

TALIGN

W

R

0

Bit 15

Bit 7

TBF⁽⁵⁹⁾

0

0x0023

ABCM

W

R

Bit 14

Bit 13

Bit 5

Bit 12

Bit 4

Bit 11

Bit 3

Bit 10

Bit 2

Bit 9

Bit 1

Bit 8

Bit 0

0x0024

DBGTBH

DBGTBL

DBGCNT

DBGSCRX

DBGMFR

DBGACTL

DBGBCTL

DBGCCTL

DBGXAH

DBGXAM

DBGXAL

DBGADH

DBGADL

DBGADHM

DBGADLM

W

R

Bit 6

0x0025

W

R

0

CNT

0x0026

W

R

0

0x0027

SC2

MC2

SC1

MC1

SC0

MC0

W

R

0

0x0027

W

R

0

0x0028⁽⁶⁰⁾

0x0028⁽⁶¹⁾

0x0028⁽⁶²⁾

0x0029

NDB

TAG

BRK

RW

RWE

COMPE

Bit 16

Bit 8

W

R

SZE

0

SZ

0

W

R

TAG

0

BRK

0

RW

0

RWE

0

W

R

0

Bit 17

W

R

0x002A

0x002B

0x002C

0x002D

0x002E

Bit 15

Bit 7

14

6

13

5

12

4

11

3

10

2

9

1

9

1

9

1

W

R

Bit 0

W

R

Bit 15

Bit 7

14

6

13

5

12

4

11

3

10

2

Bit 8

W

R

Bit 0

W

R

Bit 15

Bit 7

14

6

13

5

12

4

11

3

10

2

Bit 8

W

R

0x002F

Note:

Bit 0

W

59. This bit is visible at DBGCNT[7] and DBGSR[7]

60. This represents the contents if the Comparator A control register is blended into this address.

61. This represents the contents if the Comparator B control register is blended into this address.

62. This represents the contents if the Comparator C control register is blended into this address.

MM912F634

Freescale Semiconductor

42

Functional Description and Application Information

Introduction

Table 52. 0x0030–0x0033 Module Mapping Control (S12SMMC)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

R

W

R

0

0x0030

PPAGE

PIX3

PIX2

PIX1

PIX0

0x0031

0x0032

0x0033

DIRECT

MODE

DP15

DP14

0

DP13

0

DP12

0

DP11

0

DP10

0

DP9

0

DP8

0

W

R

MODC

0

W

R

0

MMCCTL1

IFRON

W

Table 53. 0x0034–0x003B Clock and Reset Generator (CRG)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

R

W

R

0

0x0034

CRGCTL0

OSCEN

RDIV[2:0]

BCLKS

0

REFS

0

OSC4MHZ

0x0035

0x0036

0x0037

0x0038

0x0039

0x003A

CRGCTL1

CRGMULT

CRGFLG

BDIV[3:0]

LOCKIE

W

R

MULT[6:0]

LOCKST

W

R

0

UPOSC

0

PORF

0

LOCKIF

0

ILAF

0

W

R

0

CRGTRIMH

CRGTRIML

Reserved

TRIM[8]

W

R

TRIM[7:0]

W

R

0

W

Table 54. 0x003C–0x003D Real Time Interrupt (RTI)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

R

W

R

0

0x003C

RTICTL

RTIF

RTIFRZ

RTISWAI

RTIRSTP

RTIE

RTIRT1

RTIRT0

WRTMSK

0x003D

RTICNT

RTICNT7

RTICNT6

RTICNT5

RTICNT4

RTICNT3

RTICNT2

RTICNT1

RTICNT0

W

Table 55. 0x003E–0x003F Computer Operating Properly (COP)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

R

W

R

0

WRTMASK

0

0x003E

COPCTL

WCOP

RSBCK

COPWAI

COPSTP

CR2

CR1

CR0

0

0x003F

ARMCOP

W

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MM912F634

Freescale Semiconductor

43

Functional Description and Application Information

Table 56. 0x0040–0x00D7 Reserved Register Space

Introduction

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

R

0

0x0040-

0x00D7

Reserved

W

Table 57. 0x00D8–0x00DF Die 2 Die Initiator (D2DI) 1 of 3

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

R

W

R

0

0x00D8

D2DCTL0

D2DEN

D2DCW

0

D2DSWAI

0

D2DCLKDIV[1:0]

0

0x00D9

0x00DA

0x00DB

0x00DC

0x000D

0x00DE

0x00DF

D2DCTL1

D2DSTAT0

D2DSTAT1

D2DADRHI

D2DADRLO

D2DDATAHI

D2DDATALO

D2DIE

TIMOUT[3:0]

W

R

ACKERF

D2DBSY

SZ8

CNCLF

TIMEF

0

TERRF

PARF

PAR1

PAR0

ERRIF

D2DIF

W

R

0

W

R

RWB

NBLK

W

R

ADR[7:0]

W

R

DATA[15:8]

DATA[7:0]

W

R

W

Table 58. 0x00E0–0x00E7 Reserved Register Space

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

R

0

0x00E0-

0x00E7

Reserved

W

Table 59. 0x00E8–0x00EF Serial Peripheral Interface (SPI)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

R

W

R

0x00E8

SPI0CR1

SPIE

0

SPE

0

SPTIE

0

MSTR

CPOL

CPHA

0

SSOE

LSBFE

0x00E9

0x00EA

0x00EB

0x00EC

SPI0CR2

SPI0BR

SPI0SR

Reserved

MODFEN

BIDIROE

0

SPISWAI

SPC0

W

R

0

SPIF

0

SPPR2

0

SPPR1

SPTEF

SPPR0

MODF

SPR2

0

SPR1

0

SPR0

0

W

R

0

W

R

0

W

MM912F634

Freescale Semiconductor

44

Functional Description and Application Information

Introduction

Bit 0

Table 59. 0x00E8–0x00EF Serial Peripheral Interface (SPI) (continued)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

R

W

R

0x00ED

SPI0DR

Bit 7

0

Bit 6

0

Bit 5

0

Bit 4

0

Bit 3

0

Bit 2

0

Bit 1

0

Bit 0

0

0x00EE

0x00EF

Reserved

W

R

0

W

Table 60. 0x00F0–0x00FF Reserved Register Space

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

R

0

0x00F0-

0x00FF

Reserved

W

Table 61. 0x0100–0x0113 Flash Control & Status Register FTSR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

R

W

R

0x0100

FCLKDIV

FDIVLD

PRDIV8

KEYEN0

FDIV5

0

FDIV4

0

FDIV3

0

FDIV2

0

FDIV1

SEC1

FDIV0

SEC0

KEYEN1

0x0101

0x0102

0x0103

0x0104

0x0105

0x0106

0x0107

0x0108

0x0109

0x010A

0x010B

0x010C

0x010D

FSEC

FRSV0

W

R

0

W

R

FCNFG

FPROT

FSTAT

CBEIE

FPHS4

CCIE

KEYACC

FPHS2

PVIOL

W

R

FPHS3

CCIF

FPHS1

FPHS0

0

FPLS2

BLANK

FPLS1

0

FPLS0

0

W

R

CBEIF

0

ACCERR

W

R

FCMD

CMDB6

0

CMDB5

0

CMDB4

0

CMDB3

0

CMDB2

0

CMDB1

0

CMDB0

0

W

R

0

FRSV1

W

R

0

FAB13

0

FAB12

0

FAB10

0

FADDRHI

FADDRLO

FDATAHI

FDATALO

FRSV2

W

R

FAB11

0

FAB9

0

FAB8

0

W

R

FAB7

FAB6

FAB5

FAB4

FAB3

FAB2

FAB1

FAB0

FD15

FD14

FD13

FD12

FD11

FD10

FD9

FD8

W

R

FD7

0

FD6

0

FD5

0

FD4

0

FD3

0

FD2

0

FD1

0

FD0

0

W

R

W

R

0

FRSV3

W

MM912F634

Freescale Semiconductor

45

Functional Description and Application Information

Introduction

Table 61. 0x0100–0x0113 Flash Control & Status Register FTSR (continued)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

R

W

R

0

0x010E

FRSV4

0

0x010F

FRSV5

W

R

0x0110-

0x0113

Reserved

W

Table 62. 0x0114–0x011F Reserved Register Space

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

R

0

0x0114-

0x011F

Reserved

W

Table 63. 0x0120–0x0123 Port Integration Module (PIM) 2 of 2

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

R

W

R

0

0x0120

PTIA

PTIA5

0

PTIA4

0

PTIA3

0

PTIA2

0

PTIA1

0

PTIA0

0

0x0121

0x0122

0x0123

Reserved

RDRA

W

R

RDRA5

0

RDRA4

0

RDRA3

0

RDRA2

0

RDRA1

0

RDRA0

0

W

R

Reserved

W

Table 64. 0x0124–0x01FF Reserved Register Space

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

R

0

0x0124-

0x01FF

Reserved

W

Table 65 shows the detailed module maps of the MM912F634 analog die.

Table 65. Analog die Registers⁽⁶³⁾- 0x0200–0x02FF D2D Blocking Access (D2DI) 2 of 3/

0x0300–0x03FF D2D Non Blocking Access (D2DI) 3 of 3

Offset

Name

7

6

5

4

3

2

1

0

ISR (hi)

Interrupt Source Register

ISR (lo)

R

W

R

0

HOT

LSOT

HSOT

LINOT

SCI

RX

0x00

TX

0

ERR

TOV

CH3

CH2

CH1

CH0

LVIE

VSI

0x01

0x02

0x04

Interrupt Source Register

IVR

W

R

0

IRQ

Interrupt Vector Register

VCR

W

R

0

VROVIE

HTIE

HVIE

LBIE

Voltage Control Register

W

MM912F634

Freescale Semiconductor

46

Functional Description and Application Information

Introduction

Table 65. Analog die Registers⁽⁶³⁾- 0x0200–0x02FF D2D Blocking Access (D2DI) 2 of 3/

0x0300–0x03FF D2D Non Blocking Access (D2DI) 3 of 3 (continued)

Offset

Name

7

6

5

4

3

2

1

0

VSR

Voltage Status Register

LXR

R

W

R

0

VROVC

HTC

HVC

LVC

LBC

0x05

0

L5

L4

L3

L2

L1

L0

0x08

0x09

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x18

0x20

0x21

0x22

0x28

0x29

0x30

0x31

Lx Status Register

LXCR

W

R

L5DS

0

L4DS

0

L3DS

0

L2DS

L1DS

L0DS

Lx Control Register

WDR

W

R

WDOFF

WDWO

WDTO

Watchdog Register

WDSR

W

R

WDSR

Watchdog Service Register

WCR

W

R

CSSEL

L5WE

L4WE

L3WE

L2WE

L1WE

L0WE

Wake Up Control Register

TCR

W

R

FWM

CST

Timing Control Register

WSR

W

R

FWU

LINWU

L5WU

WDR

0

L4WU

EXR

0

L3WU

WUR

0

L2WU

LVRX

0

L1WU

LVR

L0WU

POR

Wake Up Source Register

RSR

W

R

0

Reset Status Register

MCR

W

R

MODE

LINSR

Mode Control Register

LINR

W

R

LINOTC

RX

LINOTIE

0

TX

LVSD

0

LINEN

LIN Register

W

R

PTBC1

PUEB2

0

PUEB1

0

PUEB0

0

DDRB2

DDRB1

DDRB0

Port B Configuration Register 1

PTBC2

W

R

0

PWMCS PWMEN

SERMOD

Port B Config Register 2

PTB

W

R

0

PTB2

PTB1

PTB0

Port B Data Register

HSCR

W

R

HSHVSD

E

HSOTIE

HSOTC

PWMCS2 PWMCS1 PWMHS2 PWMHS1

HS2CL HS1CL

HS2

HS1

High Side Control Register

HSSR

W

R

0

HS2OL

HS1OL

High Side Status Register

LSCR

W

R

LSOTIE

LSOTC

PWMCS2 PWMCS1 PWMLS2 PWMLS1

LS2

LS1

Low Side Control Register

LSSR

W

R

0

LS2CL

LS1CL

LS2OL

LS1OL

Low Side Status Register

LSCEN

W

R

0

0x32

0x38

LSCEN

Low-Side Control Enable

Register

W

HSR

R

HOTC

0

HOTIE

HSUPON

Hall Supply Register

W

MM912F634

Freescale Semiconductor

47

Functional Description and Application Information

Introduction

Table 65. Analog die Registers⁽⁶³⁾- 0x0200–0x02FF D2D Blocking Access (D2DI) 2 of 3/

0x0300–0x03FF D2D Non Blocking Access (D2DI) 3 of 3 (continued)

Offset

Name

7

6

5

4

3

2

1

0

CSR

Current Sense Register

SCIBD (hi)

R

W

R

0

0x3C

CSE

CCD

CSGS

0

0x40

0x41

0x42

0x43

0x44

0x45

0x46

0x47

0x60

0x61

0x62

0x63

0x64

0x65

0x66

0x67

0x68

0x69

0x80

0x81

LBKDIE RXEDGIE

SBR12

SBR4

M

SBR11

SBR10

SBR2

ILT

SBR9

SBR1

PE

SBR8

SBR0

PT

SCI Baud Rate Register

SCIBD (lo)

W

R

SBR7

SBR6

0

SBR5

RSRC

SBR3

0

SCI Baud Rate Register

SCIC1

W

R

LOOPS

SCI Control Register 1

SCIC2

W

R

TIE

TCIE

TC

RIE

ILIE

TE

RE

NF

RWU

FE

SBK

PF

SCI Control Register 2

SCIS1

W

R

TDRE

RDRF

IDLE

OR

SCI Status Register 1

SCIS2

W

R

0

RAF

LBKDIF RXEDGIF

RXINV

TXINV

RWUID

ORIE

BRK13

NEIE

LBKDE

FEIE

SCI Status Register 2

SCIC3

W

R

R8

T8

TXDIR

PEIE

SCI Control Register 3

SCID

W

R

R7

T7

R6

T6

R5

T5

R4

T4

R3

T3

R2

T2

R1

T1

R0

T0

SCI Data Register

PWMCTL

W

R

CAE1

0

CAE0

PCLK1

PCLK0

PPOL1

0

PPOL0

PWME1

PWME0

PCKA0

Bit 0

PWM Control Register

PWMPRCLK

W

R

PCKB2

PCKB1

PCKB0

PCKA2

PCKA1

PWM Presc. Clk Select Reg

PWMSCLA

W

R

Bit 7

6

5

4

3

2

1

PWM Scale A Register

PWMSCLB

W

R

Bit 0

PWM Scale B Register

PWMCNT0

W

R

Bit 7

0

6

0

6

0

5

0

5

0

4

0

4

0

3

0

3

0

2

0

2

0

1

0

1

0

Bit 0

0

PWM Ch Counter Reg 0

PWMCNT1

W

R

Bit 7

0

Bit 0

0

PWM Ch Counter Reg 1

PWMPER0

W

R

Bit 7

6

5

4

3

2

1

Bit 0

PWM Ch Period Register 0

PWMPER1

W

R

PWM Ch Period Register 1

PWMDTY0

W

R

PWM Ch Duty Register 0

PWMDTY1

W

R

3

0

PWM Ch Duty Register 1

ACR

W

R

SCIE

SCF

CCE

OCE

0

ADCRST

0

PS2

PS1

PS0

ADC Config Register

ASR

W

R

2p5CLF

CCNT3

CCNT2

CCNT1

CCNT0

ADC Status Register

W

MM912F634

Freescale Semiconductor

48

Functional Description and Application Information

Introduction

Table 65. Analog die Registers⁽⁶³⁾- 0x0200–0x02FF D2D Blocking Access (D2DI) 2 of 3/

0x0300–0x03FF D2D Non Blocking Access (D2DI) 3 of 3 (continued)

Offset

Name

7

6

5

4

3

2

1

0

ACCR (hi)

ADC Conversion Ctrl Reg

ACCR (lo)

R

W

R

0

0x82

CH15

CH14

CH12

CH11

CH10

CH9

CH8

0x83

0x84

0x85

0x86

0x87

0x88

0x89

0x8A

0x8B

0x8C

0x8D

0x8E

0x8F

0x90

0x91

0x92

0x93

0x94

0x95

0x96

CH7

CH6

CH5

0

CH4

CH3

CH2

CH1

CC9

CH0

CC8

ADC Conversion Ctrl Reg

ACCSR (hi)

W

R

CC15

CC14

CC12

CC11

CC10

ADC Conv Complete Reg

ACCSR (lo)

W

R

CC7

CC6

CC5

adr0 7

0

CC4

adr0 6

0

CC3

adr0 5

0

CC2

adr0 4

0

CC1

adr0 3

0

CC0

adr0 2

0

ADC Conv Complete Reg

ADR0 (hi)

W

R

adr0 9

adr0 1

adr1 9

adr1 1

adr2 9

adr2 1

adr3 9

adr3 1

adr4 9

adr4 1

adr5 9

adr5 1

adr6 9

adr6 1

adr7 9

adr7 1

adr8 9

adr0 8

adr0 0

adr1 8

adr1 0

adr2 8

adr2 0

adr3 8

adr3 0

adr4 8

adr4 0

adr5 8

adr5 0

adr6 8

adr6 0

adr7 8

adr7 0

adr8 8

ADC Data Result Register 0

ADR0 (lo)

W

R

ADC Data Result Register 0

ADR1 (hi)

W

R

adr1 7

0

adr1 6

0

adr1 5

0

adr1 4

0

adr1 3

0

adr1 2

0

ADC Data Result Register 1

ADR1 (lo)

W

R

ADC Data Result Register 1

ADR2 (hi)

W

R

adr2 7

0

adr2 6

0

adr2 5

0

adr2 4

0

adr2 3

0

adr2 2

0

ADC Data Result Register 2

ADR2 (lo)

W

R

ADC Data Result Register 2

ADR3 (hi)

W

R

adr3 7

0

adr3 6

0

adr3 5

0

adr3 4

0

adr3 3

0

adr3 2

0

ADC Data Result Register 3

ADR3 (lo)

W

R

ADC Data Result Register 3

ADR4 (hi)

W

R

adr4 7

0

adr4 6

0

adr4 5

0

adr4 4

0

adr4 3

0

adr4 2

0

ADC Data Result Register 4

ADR4 (lo)

W

R

ADC Data Result Register 4

ADR5 (hi)

W

R

adr5 7

0

adr5 6

0

adr5 5

0

adr5 4

0

adr5 3

0

adr5 2

0

ADC Data Result Register 5

ADR5 (lo)

W

R

ADC Data Result Register 5

ADR6 (hi)

W

R

adr6 7

0

adr6 6

0

adr6 5

0

adr6 4

0

adr6 3

0

adr6 2

0

ADC Data Result Register 6

ADR6 (lo)

W

R

ADC Data Result Register 6

ADR7 (hi)

W

R

adr7 7

0

adr7 6

0

adr7 5

0

adr7 4

0

adr7 3

0

adr7 2

0

ADC Data Result Register 7

ADR7 (lo)

W

R

ADC Data Result Register 7

ADR8 (hi)

W

R

adr8 7

adr8 6

adr8 5

adr8 4

adr8 3

adr8 2

ADC Data Result Register 8

W

MM912F634

Freescale Semiconductor

49

Functional Description and Application Information

Introduction

Table 65. Analog die Registers⁽⁶³⁾- 0x0200–0x02FF D2D Blocking Access (D2DI) 2 of 3/

0x0300–0x03FF D2D Non Blocking Access (D2DI) 3 of 3 (continued)

Offset

Name

7

6

5

4

3

2

1

0

ADR8 (lo)

ADC Data Result Register 8

ADR9 (hi)

R

W

R

adr8 1

adr8 0

0

0x97

adr9 9

adr9 1

adr10 9

adr10 1

adr11 9

adr11 1

adr12 9

adr12 1

adr14 9

adr14 1

adr15 9

adr15 1

0

adr9 8

adr9 0

adr10 8

adr10 0

adr11 8

adr11 0

adr12 8

adr12 0

adr14 8

adr14 0

adr15 8

adr15 0

0

adr9 7

adr9 6

adr9 5

adr9 4

adr9 3

0

adr9 2

0

0x98

0x99

0x9A

0x9B

0x9C

0x9D

0x9E

0x9F

0xA2

0xA3

0xA4

0xA5

0xC0

0xC1

0xC2

0xC3

0xC4

0xC5

0xC6

0xC7

ADC Data Result Register 9

ADR9 (lo)

W

R

0

ADC Data Result Register 9

ADR10 (hi)

W

R

adr10 7

adr10 6

adr10 5

adr10 4

adr10 3

adr10 2

ADC Data Result Reg 10

ADR10 (lo)

W

R

0

ADC Data Result Reg 10

ADR11 (hi)

W

R

adr11 7

adr11 6

adr11 5

adr11 4

adr11 3

adr11 2

ADC Data Result Reg 11

ADR11 (lo)

W

R

0

ADC Data Result Reg 11

ADR12 (hi)

W

R

adr12 7

adr12 6

adr12 5

adr12 4

adr12 3

adr12 2

ADC Data Result Reg 12

ADR12 (lo)

W

R

0

adr14 5

0

adr14 4

0

adr14 3

0

adr14 2

0

ADC Data Result Reg 12

ADR14 (hi)

W

R

adr14 7

adr14 6

ADC Data Result Reg 14

ADR14 (lo)

W

R

0

ADC Data Result Reg 14

ADR15 (hi)

W

R

adr15 7

adr15 6

adr15 5

0

adr15 4

0

adr15 3

0

adr15 2

0

ADC Data Result Reg 15

ADR15 (lo)

W

R

0

ADC Data Result Reg 15

TIOS

W

R

IOS3

IOS2

IOS1

IOS0

TIM InCap/OutComp Select

CFORC

W

R

0

Timer Compare Force Reg

OC3M

W

R

FOC3

FOC2

FOC1

FOC0

0

OC3M3

OC3D3

tcnt 11

OC3M2

OC3D2

tcnt 10

OC3M1

OC3D1

tcnt 9

OC3M0

OC3D0

tcnt 8

Output Comp 3 Mask Reg

OC3D

W

R

0

Output Comp 3 Data Reg

TCNT (hi)

W

R

tcnt 15

tcnt 7

tcnt 14

tcnt 13

tcnt 12

tcnt 4

Timer Count Register

TCNT (lo)

W

R

tcnt 6

0

tcnt 5

0

tcnt 3

0

tcnt 2

0

tcnt 1

0

tcnt 0

0

Timer Count Register

TSCR1

W

R

TEN

0

TFFCA

0

Timer System Control Reg 1

TTOV

W

R

0

TOV3

TOV2

TOV1

TOV0

Timer Toggle Overflow Reg

W

MM912F634

Freescale Semiconductor

50

Functional Description and Application Information

Introduction

Table 65. Analog die Registers⁽⁶³⁾- 0x0200–0x02FF D2D Blocking Access (D2DI) 2 of 3/

0x0300–0x03FF D2D Non Blocking Access (D2DI) 3 of 3 (continued)

Offset

Name

7

6

5

4

3

2

1

0

TCTL1

Timer Control Register 1

TCTL2

R

W

R

0xC8

OM3

OL3

OM2

OL2

OM1

OL1

OM0

OL0

0xC9

0xCA

0xCB

0xCC

0xCD

0xCE

0xCF

0xD0

0xD1

0xD2

0xD3

0xD4

0xD5

0xF0

0xF1

0xF2

0xF3

EDG3B

0

EDG3A

0

EDG2B

0

EDG2A

0

EDG1B

C3I

EDG1A

C2I

EDG0B

C1I

EDG0A

C0I

Timer Control Register 2

TIE

W

R

Timer Interrupt Enable Reg

TSCR2

W

R

0

TOI

0

TCRE

PR2

PR1

PR0

Timer System Control Reg 2

TFLG1

W

R

C3F

0

C2F

0

C1F

0

C0F

0

Main Timer Interrupt Flag 1

TFLG2

W

R

TOF

tc0 15

tc0 7

Main Timer Interrupt Flag 2

TC0 (hi)

W

R

tc0 14

tc0 6

tc0 13

tc0 5

tc0 12

tc0 4

tc0 11

tc0 3

tc0 10

tc0 2

tc0 9

tc0 1

tc1 9

tc1 1

tc2 9

tc2 1

tc3 9

tc3 1

tc0 8

tc0 0

tc1 8

tc1 0

tc2 8

tc2 0

tc3 8

tc3 0

TIM InCap/OutComp Reg 0

TC0 (lo)

W

R

TIM InCap/OutComp Reg 0

TC1 (hi)

W

R

tc1 15

tc1 7

tc1 14

tc1 6

tc1 13

tc1 5

tc1 12

tc1 4

tc1 11

tc1 3

tc1 10

tc1 2

TIM InCap/OutComp Reg 1

TC1 (lo)

W

R

TIM InCap/OutComp Reg 1

TC2 (hi)

W

R

tc2 15

tc2 7

tc2 14

tc2 6

tc2 13

tc2 5

tc2 12

tc2 4

tc2 11

tc2 3

tc2 10

tc2 2

TIM InCap/OutComp Reg 2

TC2 (lo)

W

R

TIM InCap/OutComp Reg 2

TC3 (hi)

W

R

tc3 15

tc3 7

tc3 14

tc3 6

tc3 13

tc3 5

tc3 12

tc3 4

tc3 11

tc3 3

tc3 10

tc3 2

TIM InCap/OutComp Reg 3

TC3 (lo)

W

R

TIM InCap/OutComp Reg 3

CTR0

W

R

LINTRE

LINTR

WDCTRE CTR0_4

BGTRIMU BGTRIMD

CTR0_3 WDCTR2 WDCTR1 WDCTR0

IREFTRE IREFTR2 IREFTR1 IREFTR0

Trimming Reg 0

CTR1

W

R

BGTRE

0

CTR1_6

0

P

N

Trimming Reg 1

CTR2

W

R

0

SLPBGTR SLPBG_L SLPBGTR SLPBGTR SLPBGTR

E

OCK

2

1

0

Trimming Reg 2

CTR3

W

R

OFFCTRE OFFCTR2 OFFCTR1 OFFCTR0 CTR3_E CTR3_2

CTR3_1

CTR3_0

Trimming Reg 3

SRR

W

R

0

FMREV

MMREV

0xF4

Note:

Silicon Revision Register

W

63. Registers not shown are reserved and must not be accessed.

MM912F634

Freescale Semiconductor

51

Functional Description and Application Information

MM912F634 - Analog Die Overview

4.2

MM912F634 - Analog Die Overview

MCU

ANALOG

4.2.1

Introduction

The MM912F634 analog die implements all system base functionality to operate the integrated microcontroller, and

delivers application specific actuator control as well as input capturing.

4.2.2

System Registers

4.2.2.1

Silicon Revision Register (SRR)

NOTE

Please refer to the MM912F634ER - Mask set errata document for details on the analog die

mask revisions.

Table 66. Silicon Revision Register (SRR)

Offset⁽⁶⁴⁾0xF4

Access: User read

7

6

5

4

3

2

1

0

R

0

FMREV

MMREV

W

Note:

64. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 67. SRR - Register Field Descriptions

Field

Description

3-2

MM912F634 analog die Silicon Revision Register - These bits represent the revision of Silicon of the analog

die. They are incremented for every full mask or metal mask issued of the device.

One number is set for one revision of the silicon of the analog die.

FMREV

1-0

MMREV

4.2.3

Analog Die Options

NOTE

This document describes the features and functions of option 1 (all modules available and

tested). Beyond this chapter, there will be no additional note or differentiation between the

different implementations.

The following section describes the differences between analog die options 1 and 2.

Table 68. Analog Die Options (continued)

Feature

Option 1

Option 2

Current Sense Module

Wake Up Inputs (Lx)

YES

NO

L0…L5

L0.L3

MM912F634

Freescale Semiconductor

52

Functional Description and Application Information

4.2.3.1 Current Sense Module

For device options with the current sense module not available, the following considerations are to be made.

MM912F634 - Analog Die Overview

4.2.3.1.1

Pinout considerations

Table 69. ISENSE - Pin Considerations

PIN name for option 1

New PIN name

Comment

40

41

ISENSEL

ISENSEH

NC

ISENSE feature not bonded and/or not tested. Connect PINs 40 and

41 (NC) to GND.

4.2.3.1.2

Register Considerations

The Current Sense Register must remain in default (0x00) state.

Offset

Name

7

6

5

4

3

2

1

0

CSR

R

0

0x3C

CSE

CCD

CSGS

Current Sense Register

W

The Conversion Control Register - Bit 9 must always be written 0.

ACCR (hi)

R

0

0x82

CH15

CH14

CH12

CC12

CH11

CC11

CH10

CC10

CH9

CC9

CH8

CC8

ADC Conversion Ctrl Reg

W

The Conversion Complete Register - Bit 9 must be ignored.

ACCSR (hi)

R

CC15

CC14

0x84

ADC Conv Complete Reg

W

The ADC Data Result Reg 9 must be ignored.

ADR9 (hi)

R

W

R

adr9 9

adr9 1

adr9 8

adr9 0

adr9 7

0

adr9 6

0

adr9 5

0

adr9 4

0

adr9 3

0

adr9 2

0

0x98

0x99

ADC Data Result Register 9

ADR9 (lo)

ADC Data Result Register 9

W

MM912F634

Freescale Semiconductor

53

Functional Description and Application Information

4.2.3.1.3 Functional Considerations

MM912F634 - Analog Die Overview

•

The complete Current Sense Module is not available.

The ADC Channel 9 is not available.

4.2.3.2

Wake-up Inputs (Lx)

For device options with reduced number of wake up inputs (Lx), the following considerations are to be made.

4.2.3.2.1 Pinout Considerations

Table 70. Lx - Pin Considerations

PIN Name for New PIN

Comment

Option 1

name

31…36

Lx

NC

One or more Lx wake up inputs are not available based on the analog die option. Not available Lx

inputs are not bonded and/or not tested. Connect not available Lx pins (NC) to GND. R_Lxis not

required on those pins.

4.2.3.2.2

Register Considerations

The Lx - Bit for the not available Lx input in the Lx Status Register must be ignored.

Offset

Name

7

6

5

4

3

2

1

0

LXR

R

0

L5

L4

L3

L2

L1

L0

0x08

Lx Status Register

W

The Lx Control register for the not available Lx input must be written 0.

LXCR

R

0

0x09

L5DS

L4DS

L3DS

L2DS

L1DS

L0DS

Lx Control Register

W

A not available Lx input can not be selected as Wake-up Source and must have its LxWE bit set to 0.

WCR

R

0x12

CSSEL

L5WE

L4WE

L3WE

L2WE

L1WE

L1WU

L0WE

L0WU

Wake Up Control Register

W

The Wake-up Source Register for not available Lx inputs must be ignored.

WSR

R

FWU

LINWU

L5WU

L4WU

L3WU

L2WU

0x14

Wake Up Source Register

W

The Conversion Control Register for the not available Lx analog input (3…8) must always be written 0.

ACCR (hi)

R

W

R

0

0x82

0x83

CH15

CH7

CH14

CH6

CH12

CH4

CH11

CH3

CH10

CH2

CH9

CH1

CH8

CH0

ADC Conversion Ctrl Reg

ACCR (lo)

CH5

ADC Conversion Ctrl Reg

W

MM912F634

Freescale Semiconductor

54

Functional Description and Application Information

MM912F634 - Analog Die Overview

The Conversion Complete Register for the not available Lx analog input (3.8) must be ignored.

ACCSR (hi)

ADC Conv Complete Reg

ACCSR (lo)

R

W

R

CC15

CC7

CC14

CC6

0

CC12

CC4

CC11

CC3

CC10

CC2

CC9

CC1

CC8

CC0

0x84

0x85

CC5

ADC Conv Complete Reg

W

The ADC Data Result Register for the not available Lx analog input (3.8) must be ignored.

ADRx (hi)

R

W

R

adrx 9

adrx 1

adrx 8

adrx 0

adrx 7

0

adrx 6

0

adrx 5

0

adrx 4

0

adrx 3

0

adrx 2

0

ADC Data Result Register x

ADRx (lo)

0x8C-0

x97

ADC Data Result Register x

W

4.2.3.2.3

Functional Considerations

For the not available Lx inputs, the following functions are limited:

•

No Wake-up feature / Cyclic Sense

No Digital Input

No Analog Input and conversion via ADC

MM912F634

Freescale Semiconductor

55

Functional Description and Application Information

Modes of Operation

4.3

Modes of Operation

The MM912F634 analog die offers three main operating modes: Normal (Run), Stop, and Sleep. In Normal mode, the device is

active and is operating under normal application conditions. In Stop mode, the voltage regulator operates with limited current

capability, the external load is expected to be reduced while in Stop mode. In Sleep mode both voltage regulators are turned off

(V_DD= V_DDX= 0 V).

Wake-up from Stop mode is indicated by an interrupt signal. Wake-up from Sleep mode will change the MM912F634 analog die

into reset mode while the voltage regulator is turned back on.

The selection of the different modes is controlled by the Mode Control Register (MCR).

Figure 16 describes how transitions are done between the different operating modes.

Power

Down

Power Up

(POR = 1)

Power Down

(V_SUP<V_POR

)

Reset

Power Down

(V_SUP<V_POR

)

WatchDog Time-Out¹,

External or Internal Reset

Wake Up

V_DDHigh and Reset

Delay (t_RST) expired

External or

V_DDLow and VSUV = 0

and Delay (t_VTO) expired

Internal Reset

Normal

Mode

Wake Up

Stop

Sleep

Command

Stop

Mode

Sleep

Mode

¹⁾Initial WD to be served within t_WDTOto enable Window WD

Figure 16. Modes of Operation and Transitions

4.3.1

Power Down Mode

For the device power (VS1) below V_POR, the MM912F634 analog die is virtually in Power Down mode. Once VS1>V_POR, the

MM912F634 analog die will enter Reset mode with the condition “Power On Reset - POR”.

4.3.2

Reset Mode

The MM912F634 analog die enters Reset mode if a reset condition occurs (POR - Power On Reset, LVR- Low Voltage Reset,

Low Voltage VDDX Reset - LVRX, WDR - Watchdog Reset, EXR - External Reset, and WUR - Wake-up Sleep Reset).

MM912F634

Freescale Semiconductor

56

Functional Description and Application Information

Modes of Operation

For internal reset sources, the RESET_A pin is driven low for t_RSTafter the reset condition is gone. After this delay, the RESET_A

pin is released. With a high detected on the RESET_A pin, VDD>V_LVRand VDDX>V_LVRXthe MM912F634 analog die enters in

Normal mode.

To avoid short-circuit conditions being present for a long time, a t_VTOtimeout is implemented. Once VDD < V_LVRor VDDX < V_LVRX

with VS1 > (V_LVRI+ V_{LVR _H}) for more than t_VTO, the MM912F634 analog die will transit directly to Sleep mode.

The Reset Status Register (RSR) will indicate the source of the reset by individual flags.

•

POR - Power On Reset

LVR - Low Voltage Reset VDD

LVRX - Low Voltage Reset VDDX

WDR - Watchdog Reset

EXR - External Reset

WUR - Wake-up Sleep Reset


型号：	MM912F634DV2APR2
厂家：	NXP
描述：	SPECIALTY MICROPROCESSOR CIRCUIT, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, LQFP-48 外围集成电路
文件：	总339页 (文件大小：2337K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MM912F634DV2APR2 [NXP]

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