MKM33Z64ACLL5 [NXP]
Security and integrity modules;型号: | MKM33Z64ACLL5 |
厂家: | NXP |
描述: | Security and integrity modules |
文件: | 总53页 (文件大小:1751K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Document Number: MKMxxZxxACxx5
Rev. 1, 09/2014
Freescale Semiconductor
Data Sheet: Advance Information
MKMxxZxxACxx5
KM Family
Supports the following:
MKM14Z64ACHH5,
MKM14Z128ACHH5,
MKM33Z64ACLH5,
MKM33Z128ACLH5,
MKM33Z64ACLL5, MKM33Z128ACLL5,
MKM34Z128ACLL5
Features
Security and integrity modules
– Hardware programmable CRC module to support
fast cyclic redundancy checks
– Hardware random-number generator
– 128-bit unique identification (ID) number per chip
•
•
Operating Characteristics
•
– Voltage range: 1.71 V to 3.6 V (when Analog Front
End (AFE) is not used)
– Voltage range: 2.7 V to 3.6 V (when Analog Front
End (AFE) is used)
– iRTC battery supply voltage range: 1.71 to 3.6 V
– Flash write voltage range: 1.71 to 3.6 V
– Temperature range (ambient): -40°C to 85°C
Human-machine interface
– Segment LCD controller supporting up to 36
frontplanes and 8 backplanes or 40 frontplanes and 4
backplanes
Performance
– General-purpose input/output which can acts as
Rapid GPIO (single cycle access)
•
•
– Up to 50 MHz ARM Cortex-M0+ core delivering
0.95 Dhrystone MIPS per MHz
Analog modules
– 16-bit SAR ADC
– 24-bit Analog Front End comprising of 24-bit Sigma
Delta ADCs (after averaging)
•
Memories and memory interfaces
– 128/64 KB program flash memory. There is no
FlexMemory on these devices
– 16 KB of single access RAM
– Programmable Gain Amplifier (PGA with gains
upto 32)
– Two analog comparators (CMP) containing a 6-bit
DAC and programmable reference input
– 1.2V Voltage reference
Clocks
•
•
– 1 to 32 MHz crystal oscillator
– 32 kHz crystal oscillator
– Multi-purpose clock generator
Timers
•
System peripherals
– 4 channel Quad Timer with 16-bit counters
– Periodic interrupt timers
– 16-bit low-power timer
– Independent Real Time Clock with calendaring and
compensation
– Multiple low-power modes to provide power
optimization based on application requirements
– Memory protection unit with multi-master
protection
– 4-channel DMA controller, supporting up to 64
request sources
– External watchdog monitor
– Robust watchdog monitor
– Low-leakage wakeup unit
– Asynchronous wakeup unit
– Peripheral Crossbar (allows internal signals to be
connected to other on-chip modules)
This document contains information on a new product. Specifications and
information herein are subject to change without notice.
© 2011–2014 Freescale Semiconductor, Inc.
Communication interfaces
•
– One SPI module with FIFO support (supports 5V AMR operation)
– One SPI module without FIFO (no AMR operation)
– Two I2C modules with SMBus support
– Two UART modules with ISO7816 support and Two UART without ISO 7816 support
– Any one SCI can be used for IrDA operation. 5V AMR support on one SCI.
KM Family Data Sheet, Rev. 1, 09/2014.
2
Freescale Semiconductor, Inc.
Table of Contents
1 Ordering parts...........................................................................4
5.3 Switching specifications.....................................................18
5.3.1 Device clock specifications...................................18
5.3.2 General switching specifications...........................18
5.4 Thermal specifications.......................................................19
5.4.1 Thermal operating requirements...........................19
5.4.2 Thermal attributes.................................................19
6 Peripheral operating requirements and behaviors....................20
6.1 Core modules....................................................................21
6.1.1 Single Wire Debug (SWD)....................................21
6.1.2 Analog Front End (AFE)........................................21
6.2 Clock modules...................................................................22
6.2.1 MCG specifications...............................................22
6.2.2 Oscillator electrical specifications.........................24
6.2.3 32 kHz oscillator electrical characteristics.............27
6.3 Memories and memory interfaces.....................................28
6.3.1 Flash electrical specifications................................28
6.4 Analog...............................................................................29
6.4.1 ADC electrical specifications.................................29
6.4.2 CMP and 6-bit DAC electrical specifications.........33
6.4.3 Voltage reference electrical specifications............35
6.4.4 AFE electrical specifications.................................37
6.5 Timers................................................................................41
6.6 Communication interfaces.................................................41
6.6.1 I2C switching specifications..................................41
6.6.2 UART switching specifications..............................41
6.6.3 SPI switching specifications..................................41
6.7 Human-Machine Interfaces (HMI).....................................44
6.7.1 LCD electrical characteristics................................44
7 Dimensions...............................................................................45
7.1 Obtaining package dimensions.........................................46
8 Pinout........................................................................................46
8.1 Package Types..................................................................46
8.2 KM Signal Multiplexing and Pin Assignments...................47
8.3 KM Family Pinouts.............................................................49
1.1 Determining valid order-able parts....................................4
2 Part identification......................................................................4
2.1 Description.........................................................................4
2.2 Format...............................................................................4
2.3 Fields.................................................................................4
2.4 Example............................................................................5
3 Terminology and guidelines......................................................5
3.1 Definition: Operating requirement......................................5
3.2 Definition: Operating behavior...........................................6
3.3 Definition: Attribute............................................................6
3.4 Definition: Rating...............................................................6
3.5 Result of exceeding a rating..............................................7
3.6 Relationship between ratings and operating
requirements......................................................................7
3.7 Guidelines for ratings and operating requirements............8
3.8 Definition: Typical value.....................................................8
3.9 Typical value conditions....................................................9
4 Ratings......................................................................................10
4.1 Thermal handling ratings...................................................10
4.2 Moisture handling ratings..................................................10
4.3 ESD handling ratings.........................................................10
4.4 Voltage and current operating ratings...............................11
5 General.....................................................................................11
5.1 AC electrical characteristics..............................................11
5.2 Nonswitching electrical specifications...............................11
5.2.1 Voltage and current operating requirements.........11
5.2.2 LVD and POR operating requirements.................12
5.2.3 Voltage and current operating behaviors..............13
5.2.4 Power mode transition operating behaviors..........14
5.2.5 Power consumption operating behaviors..............15
5.2.6 EMC radiated emissions operating behaviors.......17
5.2.7 Designing with radiated emissions in mind...........17
5.2.8 Capacitance attributes..........................................18
KM Family Data Sheet, Rev. 1, 09/2014.
Freescale Semiconductor, Inc.
3
Ordering parts
1 Ordering parts
1.1 Determining valid order-able parts
Valid order-able part numbers are provided on the web. To determine the order-able part
numbers for this device, go to freescale.com and perform a part number search for the
following device numbers:
• MKM14Z64ACHH5
• MKM14Z128ACHH5
• MKM33Z64ACLH5
• MKM33Z128ACLH5
• MKM33Z64ACLL5
• MKM33Z128ACLL5
• MKM34Z128ACLL5
NOTE
It is recommended to order the RevA part numbers for the KM
parts.
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format:
Q K M S A FFF R T PP CC N
2.3 Fields
Following table lists the possible values for each field in the part number (not all
combinations are valid):
KM Family Data Sheet, Rev. 1, 09/2014.
4
Freescale Semiconductor, Inc.
Terminology and guidelines
Values
Field
Description
Q
Qualification status
• M = Fully qualified, general market flow
• P = Pre-qualification (Proto)
K
Main family
Sub family
• K = Kinetis
M
• M1 = Metering only (No LCD support)
• M3 = Metering with LCD support
S
Number of Sigma Delta (SD) ADC
• 3 = 2 SD ADC with PGA and 1 SD ADC
• 4 = 2 SD ADC with PGA and 2 SD ADC
A
Key attribute
• Z = Cortex-M0+
FFF
Program flash memory size
• 64 = 64 KB
• 128 = 128 KB
R
Silicon revision
• Z = Initial
• (Blank) = Main
• A = Second revision
T
Temperature range (°C)
Package identifier
• C = –40 to 85
PP
• HH = 44 LGA (5 mm x 5 mm)
• LH = 64 LQFP (10 mm x 10 mm)
• LL = 100 LQFP (14 mm x 14 mm)
CC
N
Maximum CPU frequency (MHz)
Packaging type
• 5 = 50 MHz
• R = Tape and reel
• (Blank) = Trays
2.4 Example
This is an example part number:
• MKM34Z128CLL5
3 Terminology and guidelines
3.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
3.1.1 Example
This is an example of an operating requirement:
KM Family Data Sheet, Rev. 1, 09/2014.
Freescale Semiconductor, Inc.
5
Terminology and guidelines
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
0.9
1.1
V
3.2 Definition: Operating behavior
Unless otherwise specified, an operating behavior is a specified value or range of values
for a technical characteristic that are guaranteed during operation if you meet the
operating requirements and any other specified conditions.
3.2.1 Example
This is an example of an operating behavior:
Symbol
Description
Min.
Max.
Unit
IWP
Digital I/O weak pullup/ 10
pulldown current
130
µA
3.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.
3.3.1 Example
This is an example of an attribute:
Symbol
Description
Min.
Max.
Unit
CIN_D
Input capacitance:
digital pins
—
7
pF
3.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
KM Family Data Sheet, Rev. 1, 09/2014.
6
Freescale Semiconductor, Inc.
Terminology and guidelines
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
3.4.1 Example
This is an example of an operating rating:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
–0.3
1.2
V
3.5 Result of exceeding a rating
40
30
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
20
10
0
Operating rating
Measured characteristic
KM Family Data Sheet, Rev. 1, 09/2014.
Freescale Semiconductor, Inc.
7
Terminology and guidelines
3.6 Relationship between ratings and operating requirements
Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- No permanent failure
- Correct operation
- No permanent failure
Expected permanent failure
- Possible decreased life
- Possible incorrect operation
- Possible decreased life
- Possible incorrect operation
–∞
∞
Operating (power on)
Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
–∞
∞
Handling (power off)
3.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
3.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
KM Family Data Sheet, Rev. 1, 09/2014.
8
Freescale Semiconductor, Inc.
Terminology and guidelines
3.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol
Description
Min.
Typ.
Max.
Unit
IWP
Digital I/O weak
pullup/pulldown
current
10
70
130
µA
3.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
5000
4500
4000
TJ
3500
150 °C
3000
105 °C
2500
25 °C
2000
–40 °C
1500
1000
500
0
0.90
0.95
1.00
1.05
1.10
VDD (V)
3.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Ambient temperature
3.3 V supply voltage
Value
Unit
TA
25
°C
V
VDD
3.3
KM Family Data Sheet, Rev. 1, 09/2014.
Freescale Semiconductor, Inc.
9
Ratings
4 Ratings
4.1 Thermal handling ratings
Symbol
TSTG
Description
Min.
–55
—
Max.
150
Unit
°C
Notes
Storage temperature
Solder temperature, lead-free
1
2
TSDR
260
°C
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.2 Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
VHBM
Electrostatic discharge voltage, human body model (All
pins except RESET pin)
-4000
+4000
V
1
Electrostatic discharge voltage, human body model
(RESET pin only)
-2500
-750
+2500
+750
V
V
1
2
3
VCDM
Electrostatic discharge voltage, charged-device model
(for corner pins)
VCDM
VPESD
ILAT
Electrostatic discharge voltage, charged-device model
Powered ESD voltage
-500
-6000
-100
+500
+6000
+100
V
V
Latch-up current at ambient temperature of 105°C
mA
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
KM Family Data Sheet, Rev. 1, 09/2014.
10
Freescale Semiconductor, Inc.
General
4.4 Voltage and current operating ratings
Symbol
VDD
Description
Min.
–0.3
–0.3
–0.3
–0.3
–25
Max.
3.6
Unit
Digital supply voltage
V
V
VDIO
Digital input voltage (except RESET, EXTAL, and XTAL)
VDD + 0.3
VBAT + 0.3
VDD + 0.3
25
VDTamper
VAIO
Tamper input voltage
Analog1, RESET, EXTAL, and XTAL input voltage
V
V
ID
Instantaneous maximum current single pin limit (applies to all
port pins)
mA
VDDA
VBAT
Analog supply voltage
VDD – 0.3
–0.3
VDD + 0.3
3.6
V
V
RTC battery supply voltage
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
5 General
5.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
Figure 1. Input signal measurement reference
5.2 Nonswitching electrical specifications
KM Family Data Sheet, Rev. 1, 09/2014.
Freescale Semiconductor, Inc.
11
General
5.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol
Description
Min.
2.7
Max.
3.6
3.6
3.6
0.1
0.1
3.6
Unit
V
Notes
VDD
Supply voltage when AFE is operational
Supply voltage when AFE is NOT operational
Analog supply voltage
1.71
2.7
V
VDDA
V
VDD – VDDA VDD-to-VDDA differential voltage
VSS – VSSA VSS-to-VSSA differential voltage
–0.1
–0.1
1.71
V
V
VBAT
VIH
RTC battery supply voltage
Input high voltage
V
1
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
0.7 × VDD
—
—
V
V
0.75 × VDD
VIL
Input low voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
—
—
0.35 × VDD
0.3 × VDD
V
V
VHYS
IICDIO
Input hysteresis
0.06 × VDD
-5
—
—
V
Digital pin negative DC injection current — single pin
• VIN < VSS-0.3V
mA
IICAIO
Analog2, EXTAL, and XTAL pin DC injection current —
single pin
mA
-3
—
• VIN < VSS-0.3V (Negative current injection)
• VIN > VDD+0.3V (Positive current injection)
—
+3
IICcont
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
-25
—
—
mA
V
• Negative current injection
• Positive current injection
+25
VRFVBAT
VBAT voltage required to retain the VBAT register file
VPOR_VBAT
—
1. VBAT always needs to be there for the chip to be operational.
2. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
5.2.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol Description
Min.
0.8
Typ.
1.1
Max.
1.5
Unit
V
Notes
VPOR
Falling VDD POR detect voltage
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
Table continues on the next page...
KM Family Data Sheet, Rev. 1, 09/2014.
12
Freescale Semiconductor, Inc.
General
Table 2. VDD supply LVD and POR operating requirements (continued)
Symbol Description
Low-voltage warning thresholds — high range
Min.
Typ.
Max.
Unit
Notes
1
VLVW1H
VLVW2H
VLVW3H
VLVW4H
• Level 1 falling (LVWV=00)
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
2.62
2.72
2.82
2.92
2.70
2.80
2.90
3.00
2.78
2.88
2.98
3.08
V
V
V
V
VHYSH
VLVDL
Low-voltage inhibit reset/recover hysteresis —
high range
—
80
—
mV
V
Falling low-voltage detect threshold — low range
(LVDV=00)
1.54
1.60
1.66
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00)
1
VLVW1L
VLVW2L
VLVW3L
VLVW4L
1.74
1.84
1.94
2.04
1.80
1.90
2.00
2.10
1.86
1.96
2.06
2.16
V
V
V
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
—
60
—
mV
VBG
tLPO
Bandgap voltage reference
0.97
900
1.00
1.03
V
Internal low power oscillator period — factory
trimmed
1000
1100
μs
1. Rising threshold is the sum of falling threshold and hysteresis voltage
Table 3. VBAT power operating requirements
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VPOR_VBAT Falling VBAT supply POR detect voltage
0.8
1.1
1.5
V
5.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
VOH
Output high voltage — high-drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = 20 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = 10 mA
VDD – 0.5
VDD – 0.5
—
—
V
V
Output high voltage — low-drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = 5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = 2.5 mA
VDD – 0.5
VDD – 0.5
—
—
V
V
IOHT
Output high current total for all ports
—
100
mA
Table continues on the next page...
KM Family Data Sheet, Rev. 1, 09/2014.
Freescale Semiconductor, Inc.
13
General
Table 4. Voltage and current operating behaviors (continued)
Symbol
Description
Min.
Max.
Unit
Notes
VOL
Output low voltage — high-drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 20 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 10 mA
—
—
0.5
0.5
V
V
Output low voltage — low-drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 2.5 mA
—
—
0.5
0.5
V
V
IOLT
IOZ
Output low current total for all ports
Hi-Z (off-state) leakage current (per pin)
Internal pullup resistors
—
—
30
30
100
1
mA
μA
kΩ
kΩ
RPU
RPD
60
60
1,
2
Internal pulldown resistors
1. Measured at Vinput = VSS
2. Measured at Vinput = VDD
5.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx→RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = 50 MHz
• Bus clock = 25 MHz
• Flash clock = 25 MHz
• Temp: -40 °C, 25 °C, and 85 °C
• VDD: 1.71 V, 3.3 V, and 3.6 V
Table 5. Power mode transition operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
tPOR
After a POR event, amount of time from the point VDD
reaches 1.71 V to execute the first instruction across
the operating temperature range of the chip.
563
659
μs
1
—
—
—
—
—
372
372
273
273
5.0
μs
μs
μs
μs
μs
• VLLS0 → RUN
• VLLS1 → RUN
• VLLS2 → RUN
• VLLS3 → RUN
• VLPS → RUN
Table continues on the next page...
KM Family Data Sheet, Rev. 1, 09/2014.
14
Freescale Semiconductor, Inc.
General
Notes
Table 5. Power mode transition operating behaviors (continued)
Symbol
Description
Min.
Max.
Unit
—
5.0
μs
• STOP → RUN
1. Normal boot (FTFA_OPT[LPBOOT]=1)
5.2.5 Power consumption operating behaviors
Table 6. Power consumption operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA
Analog supply current
—
—
See note
mA
1
2
IDD_RUN Run mode current — all peripheral clocks
disabled, code executing from flash
• @ 3.0 V
—
—
—
6.17
6.39
6.93
7.1
6.7
8.3
mA
mA
mA
• 25 °C
• -40 °C
• 105 °C
IDD_RUN Run mode current — all peripheral clocks
enabled, code executing from flash
2
• @ 3.0 V
—
—
—
8.24
8.26
9.00
10.4
9.8
mA
mA
mA
• 25 °C
• -40 °C
• 105 °C
11.5
IDD_WAIT Wait mode high frequency current at 3.0 V— all
2
peripheral clocks disabled and Flash is not in
low-power
• 25 °C
—
—
—
3.95
4.65
4.4
6
mA
mA
mA
• -40 °C
• 105 °C
IDD_WAIT Wait mode high frequency current at 3.0 V— all
2, 3
peripheral clocks disabled and Flash disabled
(put in low-power)
• 25 °C
—
—
—
3.81
4.4
4.2
5.8
mA
mA
mA
• -40 °C
• 105 °C
IDD_VLPR Very-low-power run mode current at 3.0 V — all
4
5
peripheral clocks disabled
• 25 °C
—
—
—
248.8
245.30
535.40
500
470
μA
μA
μA
• -40 °C
• 105 °C
1800
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
• 25 °C
—
—
—
343.4
336.62
626.18
530
500
μA
μA
μA
• -40 °C
• 105 °C
2000
Table continues on the next page...
KM Family Data Sheet, Rev. 1, 09/2014.
Freescale Semiconductor, Inc.
15
General
Table 6. Power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDD_VLPW Very-low-power wait mode current at 3.0 V — all
6
peripheral clocks disabled
• 25 °C
—
—
—
162
350
330
μA
μA
μA
158.50
446.94
• -40 °C
• 105 °C
1700
IDD_STOP Stop mode current at 3.0 V
• 25 °C
• -40 °C
• 105 °C
—
—
—
311.90
364
730
700
μA
μA
μA
645.13
2250
IDD_VLPS Very-low-power stop mode current at 3.0 V
• 25 °C
• -40 °C
• 105 °C
—
—
—
8.56
1.98
1.24
0.89
0.35
0.472
0.3
46
44
μA
μA
μA
1500
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
• 25 °C
• -40 °C
• 105 °C
—
—
—
3.5
3.3
85
μA
μA
μA
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
• 25 °C
• -40 °C
• 105 °C
—
—
—
2.6
2.5
μA
μA
μA
59.5
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
• 25 °C
• -40 °C
• 105 °C
—
—
—
1.7
1.6
μA
μA
μA
38.8
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit disabled
—
—
—
0.67
0.64
38
μA
μA
μA
• 25 °C
• -40 °C
• 105 °C
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit enabled
—
—
—
0.76
0.72
38.4
μA
μA
μA
• 25 °C
• -40 °C
• 105 °C
IDD_VBAT Average current with RTC and 32 kHz disabled
at 3.0 V and VDD is OFF
• 25 °C
—
—
—
1
μA
μA
μA
0.95
15
• -40 °C
• 105 °C
Table continues on the next page...
KM Family Data Sheet, Rev. 1, 09/2014.
16
Freescale Semiconductor, Inc.
General
Table 6. Power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDD_VBAT Average current when VDD is OFF and LFSR
and Tamper clocks set to 2 Hz.
8, 9
• @ 3.0 V
• 25 °C
—
1.3 7
3
μA
μA
μA
2.5
16
• -40 °C
• 105 °C
1. See AFE specification for IDDA.
2. 50 MHz core and system clock, 25 MHz bus clock, and 25 MHz flash clock. MCG configured for FBE mode. All peripheral
clocks disabled.
3. Should be reduced by 500 μA.
4. 2 MHz core, system, bus clock, and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled.
Code executing while (1) loop from flash.
5. 2 MHz core, system and bus clock, and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks enabled
but peripherals are not in active operation. Code executing while (1) loop from flash.
6. 2 MHz core, system and bus clock, and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled.
No flash accesses; some activity on DMA & RAM assumed.
7. Current consumption will vary with number of CPU accesses done and is dependent on the frequency of the accesses and
frequency of bus clock. Number of CPU accesses should be optimized to get optimal current value.
8. Includes 32 kHz oscillator current and RTC operation.
9. An external power switch for VBAT should be present on board to have better battery life and keep VBAT pin powered in
all conditions. There is no internal power switch in RTC.
5.2.6 EMC radiated emissions operating behaviors
Table 7. EMC radiated emissions operating behaviors
Symbol
Description
Frequency
band (MHz)
Typ.
Unit
Notes
VRE1
VRE2
Radiated emissions voltage, band 1
Radiated emissions voltage, band 2
Radiated emissions voltage, band 3
Radiated emissions voltage, band 4
IEC level
0.15–50
50–150
14
16
12
5
dBμV
dBμV
dBμV
dBμV
—
1, 2
VRE3
150–500
500–1000
0.15–1000
VRE4
VRE_IEC
M
2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of
Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported
emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the
measured orientations in each frequency range.
2. VDD = 3.3 V, TA = 25 °C, fOSC = 10 MHz (crystal), fSYS = 50 MHz, fBUS = 25 MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method
KM Family Data Sheet, Rev. 1, 09/2014.
Freescale Semiconductor, Inc.
17
General
5.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.freescale.com.
2. Perform a keyword search for “EMC design.”
5.2.8 Capacitance attributes
Table 8. Capacitance attributes
Symbol
CIN_A
Description
Min.
—
Max.
Unit
pF
Input capacitance: analog pins
Input capacitance: digital pins
Input capacitance: fast digital pins
7
7
9
CIN_D
—
pF
CIN_D_io60
—
pF
5.3 Switching specifications
5.3.1 Device clock specifications
Table 9. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Notes
Normal run mode
fSYS
fBUS
fFLASH
fAFE
System and core clock
Bus clock
50
25
25
6.5
MHz
MHz
MHz
MHz
Flash clock
AFE Modulator clock
VLPR mode1
fSYS
fBUS
fFLASH
fAFE
System and core clock
Bus clock
2
1
MHz
MHz
MHz
MHz
Flash clock
AFE Modulator clock2
1
1.6
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any
other module.
2. AFE working in low-power mode.
KM Family Data Sheet, Rev. 1, 09/2014.
18
Freescale Semiconductor, Inc.
General
5.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
and I2C signals.
Table 10. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Asynchronous path
16
—
—
ns
2
External reset pulse width (digital glitch filter disabled)
100
ns
2
3
Port rise and fall time—Low (All pins) and high drive
(only PTC2) strength
• Slew disabled
—
—
8
5
ns
ns
• 1.71 ≤ VDD ≤ 2.7 V
• 2.7 ≤ VDD ≤ 3.6 V
• Slew enabled
—
—
27
16
ns
ns
• 1.71 ≤ VDD ≤ 2.7 V
• 2.7 ≤ VDD ≤ 3.6 V
1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. Only PTC2 has high drive capability and load is 75 pF, other pins load (low drive) is 25 pF.
5.4 Thermal specifications
5.4.1 Thermal operating requirements
Table 11. Thermal operating requirements
Symbol
TJ
Description
Min.
–40
–40
Max.
105
85
Unit
°C
Notes
Die junction temperature
Ambient temperature
TA
°C
1
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to
determine TJ is: TJ = TA + θJA × chip power dissipation
KM Family Data Sheet, Rev. 1, 09/2014.
Freescale Semiconductor, Inc.
19
Peripheral operating requirements and behaviors
5.4.2 Thermal attributes
Board type
Symbol
Description
100 LQFP
44 LGA
Unit
Notes
Single-layer
(1s)
RθJA
Thermal
resistance,
junction to
63
95
°C/W
1
ambient (natural
convection)
Four-layer
(2s2p)
RθJA
Thermal
resistance,
junction to
ambient (natural
convection)
50
53
44
36
50
79
45
35
°C/W
°C/W
°C/W
°C/W
1
1
1
2
Single-layer
(1s)
RθJMA
RθJMA
RθJB
Thermal
resistance,
junction to
ambient (200 ft./
min. air speed)
Four-layer
(2s2p)
Thermal
resistance,
junction to
ambient (200 ft./
min. air speed)
—
Thermal
resistance,
junction to
board
—
—
RθJC
Thermal
resistance,
junction to case
18
3
28
4
°C/W
°C/W
3
4
ΨJT
Thermal
characterization
parameter,
junction to
package top
outside center
(natural
convection)
1.
Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental Conditions—Forced Convection (Moving Air).
2.
3.
Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material
between the top of the package and the cold plate.
4.
Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
6 Peripheral operating requirements and behaviors
KM Family Data Sheet, Rev. 1, 09/2014.
20
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.1 Core modules
6.1.1 Single Wire Debug (SWD)
Table 12. SWD switching characteristics at 2.7 V (2.7-3.6 V)
Symbol
SWD CLK
Description
Value
Unit
Notes
Frequency of SWD
operation
20
MHz
1
Inputs, tSUI
inputs,tHI
Data setup time
Data hold time
5
ns
ns
ns
ns
1
1
1
1
0
after clock edge, tDVO Data valid Time
tHO Data Valid Hold
32
0
1. Input transition assumed =1 ns. Output transition assumed = 50 pf.
Table 13. Switching characteristics at 1.7 V (1.7-3.6 V)
Symbol
SWD CLK
Description
Value
Unit
Notes
Frequency of SWD
operation
18
MHz
Inputs, tSUI
inputs,tHI
Data setup time
Data hold time
4.7
0
ns
ns
ns
ns
after clock edge, tDVO Data valid Time
tHO Data Valid Hold
49.4
0
2
1. Frequency of SWD clock (18 Mhz) is applicable only in case the input setup time of the device outside is not more than
6.15 ns, else the frequency of SWD clock would need to be lowered.
6.1.2 Analog Front End (AFE)
AFE switching characteristics at (2.7 V-3.6 V)
Case1: Clock is coming In and Data is also coming In (XBAR ports timed with respect to
the XBAR ports timed with respect to AFE clock defined at pad ptb[7] and pte[3])
Table 14. AFE switching characteristics (2.7 V-3.6 V)
Symbol
AFE CLK
Description
Value
Unit
Notes
Frequency of operation 10
MHz
ns
1
1
1
Inputs, tSUI
inputs,tHI
Data setup time
Data hold time
5
0
ns
1. Input Transition: 1ns. Output Load: 50 pf.
KM Family Data Sheet, Rev. 1, 09/2014.
Freescale Semiconductor, Inc.
21
Peripheral operating requirements and behaviors
Case 2: Clock is going Out and Data is coming In (XBAR ports timed with respect to
generated clock defined at the XBAR out ports)
Table 15. AFE switching characteristics (2.7V-3.6V)
Symbol
AFE CLK
Description
Value
Unit
Notes
Frequency of operation 6.2
MHz
ns
Inputs, tSUI
inputs,tHI
Data setup time
Data hold time
36
0
ns
AFE switching characteristics at (1.7 V-3.6 V)
Case1: Clock is coming In and Data is also coming In ( XBAR ports timed with respect
to AFE clock defined at pad ptb[7] and pte[3])
Table 16. AFE switching characteristics (1.7 V-3.6 V)
Symbol
AFE CLK
Description
Value
Unit
Notes
Frequency of operation 10
MHz
ns
Inputs, tSUI
inputs,tHI
Data setup time
Data hold time
5.1
0
ns
Case 2: Clock is going Out and Data is coming In ( XBAR ports timed with respect to
generated clock defined at XBAR out ports)
Table 17. AFE switching characteristics (1.7 V-3.6 V)
Symbol
AFE CLK
Description
Value
Unit
Notes
Frequency of operation 6.2
MHz
ns
Inputs, tSUI
inputs,tHI
Data setup time
Data hold time
54
0
ns
6.2 Clock modules
6.2.1 MCG specifications
Table 18. MCG specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
fints_ft
Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
—
32.768
—
kHz
Table continues on the next page...
KM Family Data Sheet, Rev. 1, 09/2014.
22
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 18. MCG specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
Δfints_t
Total deviation of internal reference
frequency (slow clock) over voltage and
temperature
—
+0.5/-0.7
—
%
Δfints_t
Total deviation of internal reference
frequency (slow clock) over fixed voltage and
full operating temperature range
-2
—
+2
%
fints_t
Internal reference frequency (slow clock) —
user trimmed
31.25
—
—
39.0625
0.6
kHz
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
0.3
%fdco
1
1
1
Δfdco_t
Total deviation of trimmed average DCO
output frequency over voltage and
temperature
—
—
+0.5/-0.7
0.4
%fdco
%fdco
Δfdco_t
Total deviation of trimmed average DCO
output frequency over fixed voltage and
temperature range of 0–70°C
—
fintf_ft
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
—
—
4
—
—
MHz
%
Δfintf_t
Total deviation of internal reference
frequency (fast clock) over voltage and
temperature — factory trimmed at nominal
VDD and 25°C
+1/-2
fintf_t
Internal reference frequency (fast clock) —
user trimmed at nominal VDD and 25 °C
3
—
—
—
5
MHz
kHz
kHz
floc_low
floc_high
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
—
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
FLL
fdco
DCO output
frequency range
Low-range (DRS=00)
640 × fints_t
20
40
60
80
20.97
41.94
62.91
83.89
22
45
67
90
MHz
MHz
MHz
MHz
2, 3
Mid-range (DRS=01)
1280 × fints_t
Mid-high range (DRS=10)
1920 × fints_t
High-range (DRS=11)
2560 × fints_t
Table continues on the next page...
KM Family Data Sheet, Rev. 1, 09/2014.
Freescale Semiconductor, Inc.
23
Peripheral operating requirements and behaviors
Table 18. MCG specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
fdco_t_DMX32 DCO output
frequency
Low-range (DRS=00)
732 × fints_t
—
23.99
—
MHz
4, 5, 6
Mid-range (DRS=01)
1464 × fints_t
—
—
—
47.97
71.99
95.98
—
—
—
MHz
MHz
MHz
Mid-high range (DRS=10)
2197 × fints_t
High-range (DRS=11)
2929 × fints_t
Jcyc_fll
FLL period jitter
—
—
70
—
140
1
ps
7
8
tfll_acquire FLL target frequency acquisition time
ms
PLL
fvco
Ipll
VCO operating frequency
11.71875
12.288 14.6484375
MHz
µA
PLL operating current
• IO 3.3 V current
9
—
300
100
—
39.0625
700
• Max core voltage current
fpll_ref
PLL reference frequency range
PLL period jitter (RMS)
• fvco = 12 MHz
31.25
32.768
kHz
ps
Jcyc_pll
10
Dlock
Dunl
Lock entry frequency tolerance
Lock exit frequency tolerance
Lock detector detection time
1.49
4.47
—
—
—
—
2.98
5.97
150 × 10-6
1075(1/
%
%
s
11
12
tpll_lock
+
fpll_ref
)
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
3. Chip max freq is 5075 MHz, so Mid-range with DRS = 10 and High-range of DCO cannot be used and should not be
configured.
4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
6. Chip max freq is 5075 MHz, so Mid-range with DRS = 10 and High-range of DCO cannot be used and should not be
configured.
7. This specification is based on standard deviation (RMS) of period or frequency.
8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
9. Excludes any oscillator currents that are also consuming power while PLL is in operation.
10. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
11. Will be updated later
12. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
KM Family Data Sheet, Rev. 1, 09/2014.
24
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.2.2 Oscillator electrical specifications
6.2.2.1 Oscillator DC electrical specifications
Table 19. Oscillator DC electrical specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
Supply current — low-power mode (HGO=0)
1
• 32 kHz
—
—
—
—
—
—
—
500
200
200
300
950
1.2
—
—
—
—
—
—
—
nA
μA
μA
μA
μA
mA
mA
• 1 MHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz
1.5
IDDOSC
Supply current — high-gain mode (HGO=1)
1
• 32 kHz
—
—
—
—
—
—
—
25
300
400
500
2.5
3
—
—
—
—
—
—
—
μA
μA
• 1 MHz
• 4 MHz
μA
• 8 MHz (RANGE=01)
• 16 MHz
μA
mA
mA
mA
• 24 MHz
• 32 MHz
4
Cx
Cy
EXTAL load capacitance
XTAL load capacitance
—
—
—
—
—
—
—
—
2, 3
2, 3
Capacitanc
e of
247
ff
0.495
pF
EXTAL
•
Die
level
(100
LQF
P)
• Pack
age
level
(100
LQF
P)
Capacitance of XTAL
—
—
265
ff
• Die level (100 LQFP)
• Package level (100 LQFP)
0.495
pF
Table continues on the next page...
KM Family Data Sheet, Rev. 1, 09/2014.
Freescale Semiconductor, Inc.
25
Peripheral operating requirements and behaviors
Table 19. Oscillator DC electrical specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
RF Feedback resistor — low-frequency, low-power
—
—
—
MΩ
2, 4
mode (HGO=0)
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
—
—
—
—
—
10
—
—
—
—
—
—
—
MΩ
MΩ
MΩ
kΩ
Feedback resistor — high-frequency, low-power
mode (HGO=0)
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
1
RS
Series resistor — low-frequency, low-power
mode (HGO=0)
—
Series resistor — low-frequency, high-gain mode
(HGO=1)
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
kΩ
Series resistor — high-frequency, high-gain
mode (HGO=1)
• 1 MHz resonator
• 2 MHz resonator
• 4 MHz resonator
• 8 MHz resonator
• 16 MHz resonator
• 20 MHz resonator
• 32 MHz resonator
—
—
—
—
—
—
—
—
6.6
3.3
0
—
—
—
—
—
—
—
—
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
V
0
0
0
0
5
Vpp
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
0.6
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
—
—
VDD
0.6
—
—
—
V
V
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
VDD
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx and Cy can be provided by using either integrated capacitors or external components.
4. When low-power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any
other device.
KM Family Data Sheet, Rev. 1, 09/2014.
26
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.2.2.2 Oscillator frequency specifications
Table 20. Oscillator frequency specifications
Symbol Description
fosc_lo Oscillator crystal or resonator frequency — low-
frequency mode (MCG_C2[RANGE]=00)
Min.
32
Typ.
Max.
40
Unit
Notes
—
kHz
fosc_hi_1 Oscillator crystal or resonator frequency — high-
frequency mode (low range)
1
8
—
—
8
MHz
MHz
(MCG_C2[RANGE]=01)
fosc_hi_2 Oscillator crystal or resonator frequency — high
frequency mode (high range)
32
(MCG_C2[RANGE]=1x)
fec_extal
tdc_extal
tcst
Input clock frequency (external clock mode)
Input clock duty cycle (external clock mode)
—
40
—
—
48
60
—
MHz
%
1, 2
3, 4
50
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
ms
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
—
—
—
ms
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
0.6
1
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
—
ms
1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register
being set.
6.2.3 32 kHz oscillator electrical characteristics
6.2.3.1 32 kHz oscillator DC electrical specifications
Table 21. 32kHz oscillator DC electrical specifications
Symbol
VBAT
RF
Description
Min.
1.71
—
Typ.
—
Max.
3.6
—
Unit
V
Supply voltage
Internal feedback resistor
Parasitical capacitance of EXTAL32 and XTAL32
Peak-to-peak amplitude of oscillation
100
5
MΩ
pF
V
Cpara
—
7
1
Vpp
—
0.6
—
1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to
required oscillator components and must not be connected to any other devices.
KM Family Data Sheet, Rev. 1, 09/2014.
Freescale Semiconductor, Inc.
27
Peripheral operating requirements and behaviors
6.2.3.2 32 kHz oscillator frequency specifications
Table 22. 32 kHz oscillator frequency specifications
Symbol Description
Min.
—
Typ.
32.768
1000
—
Max.
—
Unit
kHz
ms
Notes
fosc_lo
tstart
Oscillator crystal
Crystal start-up time
—
—
1
vec_extal32 Externally provided input clock amplitude
700
VBAT
mV
2 , 3
1. Proper PC board layout procedures must be followed to achieve specifications.
2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The
oscillator remains enabled and XTAL32 must be left unconnected.
3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied
clock must be within the range of VSS to VBAT
.
NOTE
The 32 kHz oscillator works in low power mode by default and
cannot be moved into high power/gain mode.
6.3 Memories and memory interfaces
6.3.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
6.3.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 23. NVM program/erase timing specifications
Symbol Description
Min.
—
Typ.
7.5
13
Max.
18
Unit
μs
Notes
thvpgm4
Longword Program high-voltage time
—
1
thversscr Sector Erase high-voltage time
—
113
452
ms
ms
thversall
Erase All high-voltage time
—
52
1
1. Maximum time based on expectations at cycling end-of-life.
6.3.1.2 Flash timing specifications — commands
Table 24. Flash command timing specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
trd1sec1k Read 1s Section execution time (flash sector)
—
—
60
μs
1
Table continues on the next page...
KM Family Data Sheet, Rev. 1, 09/2014.
28
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 24. Flash command timing specifications (continued)
Symbol Description
Min.
—
—
—
—
—
—
—
—
—
Typ.
—
Max.
45
Unit
μs
Notes
tpgmchk
trdrsrc
tpgm4
Program Check execution time
1
1
Read Resource execution time
Program Longword execution time
Erase Flash Sector execution time
Read 1s All Blocks execution time
Read Once execution time
—
30
μs
65
14
—
145
114
1.8
25
μs
—
2
tersscr
trd1all
ms
ms
μs
—
1
trdonce
—
tpgmonce Program Once execution time
65
88
—
—
μs
—
2
tersall
Erase All Blocks execution time
650
30
ms
μs
tvfykey
Verify Backdoor Access Key execution time
1
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
6.3.1.3 Flash high voltage current behaviors
Table 25. Flash high voltage current behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
IDD_PGM
Average current adder during high voltage
flash programming operation
—
2.5
6.0
mA
IDD_ERS
Average current adder during high voltage
flash erase operation
—
1.5
4.0
mA
6.3.1.4 Reliability specifications
Table 26. NVM reliability specifications
Symbol Description
Min.
Program Flash
Typ.1
Max.
Unit
Notes
tnvmretp10k Data retention after up to 10 K cycles
tnvmretp1k Data retention after up to 1 K cycles
nnvmcycp Cycling endurance
5
50
—
—
—
years
years
cycles
—
—
2
20
100
50 K
10 K
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant
25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering
Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.
6.4 Analog
KM Family Data Sheet, Rev. 1, 09/2014.
Freescale Semiconductor, Inc.
29
Peripheral operating requirements and behaviors
6.4.1 ADC electrical specifications
All ADC channels meet the 12-bit single-ended accuracy specifications.
6.4.1.1 16-bit ADC operating conditions
Table 27. 16-bit ADC operating conditions
Symbol Description
Conditions
Min.
1.71
-100
-100
1.13
Typ.1
Max.
3.6
Unit
V
Notes
VDDA
ΔVDDA
ΔVSSA
VREFH
Supply voltage
Supply voltage
Ground voltage
Absolute
—
—
2
Delta to VDD (VDD – VDDA
)
0
+100
+100
VDDA
mV
mV
V
Delta to VSS (VSS – VSSA
)
0
2
ADC reference
voltage high
VDDA
VREFL
ADC reference
voltage low
VSSA
VSSA
VSSA
V
VADIN
CADIN
Input voltage
VREFL
—
—
8
VREFH
10
V
—
—
Input capacitance
• 16-bit mode
pF
• 8-bit / 10-bit / 12-bit
modes
—
4
5
RADIN
RAS
Input series
resistance
—
—
2
5
5
kΩ
kΩ
—
3
Analog source
resistance
(external)
12-bit modes
fADCK < 4 MHz
—
fADCK
fADCK
Crate
ADC conversion ≤ 12-bit mode
clock frequency
1.0
2.0
—
—
18.0
12.0
MHz
MHz
4
4
5
ADC conversion 16-bit mode
clock frequency
ADC conversion ≤ 12-bit modes
rate
No ADC hardware averaging
20.000
37.037
—
—
818.330
461.467
Ksps
Ksps
Continuous conversions
enabled, subsequent
conversion time
Crate
ADC conversion 16-bit mode
5
rate
No ADC hardware averaging
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The RAS/CAS
time constant should be kept to < 1 ns.
4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
KM Family Data Sheet, Rev. 1, 09/2014.
30
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
Pad
ZAS
CHANNEL SELECT
leakage
due to
input
CIRCUIT
ADC SAR
ENGINE
RADIN
RAS
protection
VADIN
CAS
VAS
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
RADIN
CADIN
Figure 2. ADC input impedance equivalency diagram
6.4.1.2 16-bit ADC electrical characteristics
Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA
)
Symbol Description
Conditions1
Min.
0.215
1.2
Typ.2
Max.
1.7
3.9
6.1
7.3
9.5
Unit
Notes
IDDA_ADC Supply current
—
mA
3
ADC
asynchronous
• ADLPC = 1, ADHSC = 0
• ADLPC = 1, ADHSC = 1
• ADLPC = 0, ADHSC = 0
• ADLPC = 0, ADHSC = 1
2.4
4.0
5.2
6.2
MHz
MHz
MHz
MHz
tADACK = 1/
fADACK
2.4
clock source
fADACK
3.0
4.4
Sample Time
See Reference Manual chapter for sample times
TUE
DNL
Total unadjusted
error
• 12-bit modes
• <12-bit modes
—
—
4
6.8
2.1
LSB4
LSB4
5
5
1.4
Differential non-
linearity
• 12-bit modes
• <12-bit modes
• 12-bit modes
• <12-bit modes
—
—
—
—
0.7
0.2
1.0
0.5
–1.1 to
+1.9
–0.3 to 0.5
INL
Integral non-
linearity
–2.7 to
+1.9
LSB4
5
–0.7 to
+0.5
Table continues on the next page...
KM Family Data Sheet, Rev. 1, 09/2014.
Freescale Semiconductor, Inc.
31
Peripheral operating requirements and behaviors
Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
Conditions1
Min.
—
Typ.2
Max.
–5.4
–1.8
—
Unit
Notes
EFS
EQ
Full-scale error
• 12-bit modes
• <12-bit modes
• 16-bit modes
• 12-bit modes
–4
LSB4
VADIN
VDDA
=
5
—
–1.4
–1 to 0
—
Quantization
error
—
LSB4
—
0.5
ENOB
Effective number 16-bit single-ended mode
6
12.8
11.9
14.5
13.8
—
—
bits
bits
of bits
• Avg = 32
• Avg = 4
12.2
11.4
13.9
13.1
—
—
bits
bits
Signal-to-noise
plus distortion
See ENOB
SINAD
THD
6.02 × ENOB + 1.76
dB
Total harmonic
distortion
16-bit single-ended mode
• Avg = 32
7
7
—
—
82
78
-94
-85
95
—
—
—
—
dB
dB
dB
SFDR
EIL
Spurious free
dynamic range
16-bit single-ended mode
• Avg = 32
90
dB
Input leakage
error
IIn × RAS
mV
IIn =
leakage
current
(refer to
the MCU's
voltage
and current
operating
ratings)
Temp sensor
slope
Across the full temperature
range of the device
1.55
706
1.62
716
1.69
726
mV/°C
mV
8
VTEMP25 Temp sensor
voltage
25 °C
8
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1
MHz ADC conversion clock speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
8. ADC conversion clock < 3 MHz
KM Family Data Sheet, Rev. 1, 09/2014.
32
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Typical ADC 16-bit Single-Ended ENOB vs ADC Clock
100Hz, 90% FS Sine Input
14.00
13.75
13.50
13.25
13.00
12.75
12.50
12.25
12.00
11.75
11.50
11.25
11.00
Averaging of 4 samples
Averaging of 32 samples
1
2
3
4
5
6
7
8
9
10
11
12
ADC Clock Frequency (MHz)
Figure 3. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
6.4.2 CMP and 6-bit DAC electrical specifications
Table 29. Comparator and 6-bit DAC electrical specifications
Symbol
VDD
Description
Min.
1.71
—
Typ.
—
Max.
3.6
Unit
V
Supply voltage
IDDHS
IDDLS
VAIN
Supply current, High-speed mode (EN=1, PMODE=1)
Supply current, low-speed mode (EN=1, PMODE=0)
Analog input voltage
—
200
20
μA
μA
V
—
—
VSS – 0.3
—
—
VDD
20
VAIO
Analog input offset voltage
Analog comparator hysteresis1
• CR0[HYSTCTR] = 00
—
mV
VH
—
—
—
—
5
—
—
—
—
mV
mV
mV
mV
10
20
30
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
VCMPOh
VCMPOl
tDHS
Output high
Output low
VDD – 0.5
—
—
50
—
0.5
200
V
V
—
Propagation delay, high-speed mode (EN=1,
PMODE=1)
20
ns
tDLS
Propagation delay, low-speed mode (EN=1,
PMODE=0)
80
250
600
ns
Analog comparator initialization delay2
6-bit DAC current adder (enabled)
6-bit DAC integral non-linearity
—
—
—
7
40
—
μs
μA
LSB3
IDAC6b
INL
–0.5
–0.3
—
—
0.5
0.3
DNL
6-bit DAC differential non-linearity
LSB
KM Family Data Sheet, Rev. 1, 09/2014.
Freescale Semiconductor, Inc.
33
Peripheral operating requirements and behaviors
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to
CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and
CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
0.08
0.07
0.06
0.05
0.04
0.03
HYSTCTR
Setting
00
01
10
11
0.02
0.01
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 4. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
KM Family Data Sheet, Rev. 1, 09/2014.
34
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
0.18
0.16
0.14
0.12
HYSTCTR
Setting
0.1
00
01
10
11
0.08
0.06
0.04
0.02
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 5. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
6.4.3 Voltage reference electrical specifications
Table 30. 1.2 VREF full-range operating requirements
Symbol
VDDA
TA
Description
Min.
1.711
−40
Max.
3.6
Unit
V
Notes
Supply voltage
Temperature
85
°C
nF
CL
Output load capacitance
100
2, 3
1. AFE is enabled.
2. CL must be connected between VREFH and VREFL.
3. The load capacitance should not exceed 25% of the nominal specified CL value over the operating temperature range of
the device.
Table 31. VREF full-range operating behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
VREFH
Voltage reference output with factory
trim at nominal VDDA and temperature =
25 °C
1.1915
1.195
1.2027
V
Table continues on the next page...
KM Family Data Sheet, Rev. 1, 09/2014.
Freescale Semiconductor, Inc.
35
Peripheral operating requirements and behaviors
Table 31. VREF full-range operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
VREFH
Voltage reference output with — factory 1.1584
trim
—
1.2376
V
VREFH
VREFL
Vstep
Voltage reference output — user trim
Voltage reference output
1.178
0.38
—
—
0.4
0.5
18
1.202
0.42
—
V
V
Voltage reference trim step
mV
Vtdrift
Temperature drift when ICOMP = 0
across full temperature range
—
—
ppm/ºC
Temperature drift when ICOMP = 1
across full temperature range
—
—
—
10
9
—
—
—
ppm/°C
ppm/°C
ppm/°C
1
Temperature drift when ICOMP = 1
across -40 ºC to 70 ºC
1, 2
1, 2
Temperature drift when ICOMP = 1
across 0 ºC to 50 ºC
9
Ac
Ibg
Aging coefficient
—
—
—
—
—
—
—
—
—
—
400
80
uV/yr
µA
Bandgap only current
Low-power buffer current
High-power buffer current
VREF buffer current
Load regulation
2
2
Ilp
0.19
0.5
1
µA
Ihp
mA
mA
mV
2
ILOAD
ΔVLOAD
3
2, 4
• current = + 1.0 mA
• current = - 1.0 mA
—
2
5
—
Tstup
Buffer startup time
—
—
—
20
—
ms
Vvdrift
Voltage drift (VREFHmax -VREFHmin
across the full voltage range)
0.5
mV
2
1. ICOMP=1 is recommended to get best temperature drift. CHOPEN bit = 1 is also recommended.
2. See the chip's Reference Manual for the appropriate settings of VREF Status and Control register.
3. See the chip's Reference Manual for the appropriate settings of SIM Miscellaneous Control Register.
4. Load regulation voltage is the difference between VREFH voltage with no load vs. voltage with defined load.
NOTE
Temperature drift per degree is ( (VREFHmax-VREFHmin)/
(temperature range)/VREFHmin ) in ppm/ºC
Table 32. VREF limited-range operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
TA
Temperature
0
50
°C
KM Family Data Sheet, Rev. 1, 09/2014.
36
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 33. VREF limited-range operating behaviours
Symbol
Description
Min.
Max.
Unit
Notes
VREFH
Voltage reference
output with factory
trim
1.173
1.225
V
VREFL
Voltage reference
output
0.38
0.42
V
6.4.4 AFE electrical specifications
6.4.4.1 ΣΔ ADC + PGA specifications
Table 34. ΣΔ ADC + PGA specifications
Symbo Description
l
Conditions
Min
Typ1
Max
Unit
Notes
fNyq
Input bandwidth
Normal Mode
1.5
1.5
0
1.5
1.5
1.5
1.5
0.8
kHz
V
Low-Power Mode
VCM Input Common Mode
Reference
VINdiff Differential input range
Gain = 1 (PGA ON/OFF)2
Gain = 2
+/- 500
+/- 250
+/- 125
+/- 62
mV
mV
mV
mV
mV
mV
Gain = 4
Gain = 8
Gain = 16
+/- 31
Gain = 32
+/- 15
Table continues on the next page...
KM Family Data Sheet, Rev. 1, 09/2014.
Freescale Semiconductor, Inc.
37
Peripheral operating requirements and behaviors
Table 34. ΣΔ ADC + PGA specifications (continued)
Symbo Description
l
Conditions
Min
Typ1
Max
Unit
Notes
SNR Signal to Noise Ratio
Normal Mode
dB
90
92
• fIN=50Hz; gain=01, common
mode=0V, Vpp=1000mV (full
range diff.)
• fIN=50Hz; gain=02, common
mode=0V, Vpp= 500mV
(differential ended )
• fIN=50Hz; gain=04, common
mode=0V, Vpp= 250mV
(differential ended )
88
82
90
86
• fIN=50Hz; gain=08, common
mode=0V, Vpp= 125mV
(differential ended )
• fIN=50Hz; gain=16, common
mode=0V, Vpp= 62mV
(differential ended )
76
70
82
78
• fIN=50Hz; gain=32, common
mode=0V, Vpp= 31mV
(differential ended )
64
74
Low-Power Mode
dB
82
76
82
78
• fIN=50Hz; gain=01, common
mode=0V, Vpp=1000mV (full
range diff.)
• fIN=50Hz; gain=02, common
mode=0V, Vpp= 500mV
(differential ended )
• fIN=50Hz; gain=04, common
mode=0V, Vpp= 250mV
(differential ended )
• fIN=50Hz; gain=08, common
mode=0V, Vpp= 125mV
(differential ended )
70
64
74
70
• fIN=50Hz; gain=16, common
mode=0V, Vpp= 62mV
(differential ended )
• fIN=50Hz; gain=32, common
mode=0V, Vpp= 31mV
(differential ended )
58
52
66
62
78
SINAD Signal-to-Noise + Distortion Normal Mode
Ratio
dB
• fIN=50Hz; gain=01, common
mode=0V, Vpp=500mV
(differential ended )
Low-Power Mode
dB
dB
74
• fIN=50Hz; gain=01, common
mode=0V, Vpp=500mV
(differential ended )
CMMR Common Mode Rejection
Ratio
• fIN=50Hz; gain=01, common
mode=0V, Vid=100 mV
• fIN=50Hz; gain=32, common
mode=0V, Vid=100 mV
70
70
Table continues on the next page...
KM Family Data Sheet, Rev. 1, 09/2014.
38
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 34. ΣΔ ADC + PGA specifications (continued)
Symbo Description
l
Conditions
Min
Typ1
Max
Unit
Notes
Eoffset Offset Error
Gain=01, Vpp=1000 mV (full range
diff.)
+/- 5
mV
ΔOffset Offset Temperature Drift3
Temp
Gain=01, Vpp=1000mV (full range
diff.)
+/- 25 ppm/oC
+/- 75 ppm/oC
ΔGainTe Gain Temperate Drift - Gain
• Gain=01, Vpp=500mV
(differential ended )
• Gain=32, Vpp=15mV
(differential ended )
error caused by
mp
temperature drifts4
PSRRA AC Power Supply Rejection Gain=01, VCC = 3V 100mV, fIN
=
60
dB
Ratio
50 Hz
C
XT
Crosstalk (with the input of Gain=01, Vid = 500 mV, fIN = 50 Hz
-100
dB
the affected channel
grounded)
fMCLK Modulator Clock Frequency Normal Mode
0.03
0.03
6.5
1.6
2.6
MHz
mA
Range
Low-Power Mode
IDDA_PG Current consumption by
PGA (each channel)
Normal Mode (fMCLK = 6.144 MHz,
OSR= 2048)
5
A
0
Low-Power Mode (fMCLK = 0.768MHz,
OSR= 256)
IDDA_AD Current Consumption by
Normal Mode (fMCLK = 6.144 MHz,
OSR= 2048)
1.4
0.5
mA
kΩ
ADC (each chanel)
C
Low-Power Mode (fMCLK = 0.768MHz,
OSR= 256)
Ras
Equivalent input impedance PGA enabled
per single channel
8
1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fMCLK = 6.144 MHz, OSR = 2048 for Normal mode and fMCLK = 768
kHz, OSR = 256 for Low-Power Mode unless otherwise stated. Typical values are for reference only and are not tested in
production.
2. The full-scale input range in single-ended mode is 0.5Vpp
3. Represents combined offset temperature drift of the PGA, SD ADC and Internal 1.2 VREF blocks; Defined by shorting both
differential inputs to ground.
4. Represents combined gain temperature drift of the PGA, SD ADC and Internal 1.2 VREF blocks.
5. PGA is disabled in low-power modes.
6.4.4.2 ΣΔ ADC Standalone specifications
Table 35. ΣΔ ADC standalone specifications
Symbo Description
l
Conditions
Min
Typ1
Max
Unit
Notes
fNyq
Input bandwidth
Normal Mode
1.5
1.5
0
1.5
1.5
1.5
1.5
0.8
kHz
Low-Power Mode
VCM Input Common Mode
Reference
V
Table continues on the next page...
KM Family Data Sheet, Rev. 1, 09/2014.
Freescale Semiconductor, Inc.
39
Peripheral operating requirements and behaviors
Table 35. ΣΔ ADC standalone specifications (continued)
Symbo Description
l
Conditions
Min
Typ1
Max
Unit
Notes
VINdiff Input range
Differential
+/- 500
+/- 250
mV
mV
dB
Single Ended
Normal Mode
SNR Signal to Noise Ratio
88
76
90
78
• fIN=50Hz; common mode=0V,
Vpp= 500mV (differential
ended )
• fIN=50Hz; common mode=0V,
Vpp= 500mV (full range se.)
Low-Power Mode
• fIN=50Hz; common mode=0V,
Vpp=500mV (diff.)
• fIN=50Hz; common mode=0V,
Vpp=500mV (full range se.)
ΔGainTe Gain Temperate Drift - Gain
• Gain bypassed Vpp = 500 mV
(differential)
• PGA bypassed Vpp = 500 mV
(differential), VCM = 0 V
55
30
ppm/oC
error caused by
mp
temperature drifts 2
ΔOffset Offset Temperate Drift -
• Gain bypassed Vpp = 500 mV
(differential), VCM = 0 V
ppm/oC
dB
Offset error caused by
Temp
temperature drifts 3
SINAD Signal-to-Noise + Distortion Normal Mode
Ratio
80
74
• fIN=50Hz; common mode=0V,
Vpp= 500mV (diff.)
• fIN=50Hz; common mode=0V,
Vpp= 500mV (full range se.)
Low-Power Mode
• fIN=50Hz; common mode=0V,
Vpp=500mV (diff.)
• fIN=50Hz; common mode=0V,
Vpp=500mV (full range se.)
CMMR Common Mode Rejection
Ratio
• fIN=50Hz; common mode=0V,
Vid=100 mV
90
60
dB
dB
PSRRA AC Power Supply Rejection Gain=01, VCC = 3V 100mV, fIN
=
Ratio
50 Hz
C
XT
Crosstalk
Gain=01, Vid = 500 mV, fIN = 50 Hz
-100
6.5
dB
fMCLK Modulator Clock Frequency Normal Mode
0.03
0.03
MHz
Range
Low-Power Mode
1.6
IDDA_AD Current Consumption by
Normal Mode (fMCLK = 6.144 MHz,
OSR= 2048)
1.4
mA
kΩ
ADC (each channel)
C
0.5
Low-Power Mode (fMCLK = 0.768MHz,
OSR= 256)
Ras
Equivalent input impedance PGA disabled
at normal operating mode
(6.144 MHz)
73
KM Family Data Sheet, Rev. 1, 09/2014.
40
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fMCLK = 6.144 MHz, OSR = 2048 for Normal mode and fMCLK = 768
kHz, OSR = 256 for Low-Power Mode unless otherwise stated. Typical values are for reference only and are not tested in
production.
2. Represent combined gain temperature drift of the SD ADC, and Internal 1.2 VREF blocks.
3. Represent combined offset temperature drift of the SD ADC, and Internal 1.2 VREF blocks; Defined by shorting both
differential inputs to ground.
6.4.4.3 External modulator interface
The external modulator interface on this device comprises of a Clock signal and 1-bit
data signal. Depending on the modulator device being used the interface works as
follows:
• Clock supplied to external modulator which drives data on rising edge and the KM
device captures it on falling edge or next rising edge.
• Clock and data are supplied by external modulator and KM device can sample it on
falling edge or next rising edge.
Depending on control bit in AFE, the sampling edge is changed.
6.5 Timers
See General switching specifications.
6.6 Communication interfaces
6.6.1 I2C switching specifications
See General switching specifications.
6.6.2 UART switching specifications
See General switching specifications.
KM Family Data Sheet, Rev. 1, 09/2014.
Freescale Semiconductor, Inc.
41
Peripheral operating requirements and behaviors
6.6.3 SPI switching specifications
The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master and
slave operations. Many of the transfer attributes are programmable. The following table
provides some reference values to be met on SoC.
Table 36. SPI switching characteristics at 2.7 V ( 2.7 - 3.6)
Description
Frequency of operation (Fsys
Min.
—
Max.
Unit
Notes
)
50
MHz
1
3
SCK frequency
• Master
2
12.5
12.5
—
MHz
Mhz
—
• Slave
SCK Duty Cycle
50%
Data Setup Time (inputs, tSUI)
ns
25
3
• Master
• Slave
Input Data Hold Time (inputs, tHI)
ns
ns
ns
ns
ns
ns
ns
0
1
• Master
• Slave
Data hold time (outputs, tHO)
• Master
0
0
• Slave
Data Valid Out Time (after SCK edge, tDVO)
13
28
• Master
• Slave
Rise time input
• Master
1
1
• Slave
Fall time input
• Master
1
1
• Slave
Rise time output
• Master
8.9
8.9
• Slave
Fall time output
• Master
7.8
7.8
• Slave
1. SPI modules will work on core clock.
2. Fsys/(Max Divider Value from registers)
3. FSYS/2 in Master mode and FSYS/4 in Slave mode. FSYS/4 in Master as well as Slave Modes, where FSYS=50Mhz
NOTE
The values assumed for input transition and output load are:
Input transition = 1 ns Output load = 50 pF
Table 37. SPI switching characteristics at 1.7 V ( 1.7 - 3.6)
Description
Frequency of operation (Fsys
Min.
Max.
Unit
Notes
)
—
50
MHz
Table continues on the next page...
KM Family Data Sheet, Rev. 1, 09/2014.
42
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 37. SPI switching characteristics at 1.7 V ( 1.7 - 3.6) (continued)
Description
Min.
Max.
Unit
Notes
SCK frequency
• Master
9
9
MHz
Mhz
—
• Slave
SCK Duty Cycle
50%
—
Data Setup Time (inputs, tSUI)
ns
42
• Master
• Slave
3.5
Input Data Hold Time (inputs, tHI)
ns
ns
ns
ns
ns
ns
ns
0
1
• Master
• Slave
Data hold time (outputs, tHO)
• Master
-3
0
• Slave
Data Valid Out Time (tDVO)
• Master
1
16
44
• Slave
Rise time input
• Master
1
1
• Slave
Fall time input
• Master
1
1
• Slave
Rise time output
• Master
14.4
14.4
• Slave
Fall time output
• Master
12.4
12.4
• Slave
1. SCK frequency of 9 Mhz is applicable only in the case that the input setup time of the device outside is not more than 11.5
ns, else the frequency would need to be lowered.
The following table represents SPI Switching specification in OD cells
Table 38. SPI switching characteristics at 1.7 V ( 1.7 - 3.6)
Description
Min.
Max.
Unit
Notes
Data Setup Time (inputs, tSUI)
ns
51
4
• Master
• Slave
Input Data Hold Time (inputs, tHI)
ns
ns
ns
0
1
• Master
• Slave
Data hold time (outputs, tHO)
• Master
-15
0
• Slave
Data Valid Out Time (tDVO)
• Master
61
93
• Slave
Table continues on the next page...
KM Family Data Sheet, Rev. 1, 09/2014.
Freescale Semiconductor, Inc.
43
Peripheral operating requirements and behaviors
Table 38. SPI switching characteristics at 1.7 V ( 1.7 - 3.6) (continued)
Description
Min.
Max.
Unit
Notes
Rise time input
• Master
ns
1
1
• Slave
Fall time input
• Master
ns
ns
ns
1
1
• Slave
Rise time output
• Master
30.4
30.4
• Slave
Fall time output
• Master
33.5
29.0
• Slave
Table 39. SPI switching characteristics at 2.7 V ( 2.7 - 3.6)
Description
Min.
Max.
Unit
Notes
Data Setup Time (inputs, tSUI)
ns
29
4
• Master
• Slave
Input Data Hold Time (inputs, tHI)
ns
ns
ns
ns
ns
ns
ns
0
1
• Master
• Slave
Data hold time (outputs, tHO)
• Master
0
0
• Slave
Data Valid Out Time (after SCK edge, tDVO)
49
49
• Master
• Slave
Rise time input
• Master
1
1
• Slave
Fall time input
• Master
1
1
• Slave
Rise time output
• Master
17.3
17.3
• Slave
Fall time output
• Master
16.6
16.0
• Slave
6.7 Human-Machine Interfaces (HMI)
KM Family Data Sheet, Rev. 1, 09/2014.
44
Freescale Semiconductor, Inc.
Dimensions
Notes
6.7.1 LCD electrical characteristics
Table 40. LCD electricals
Symbol Description
fFrame LCD frame frequency
CLCD LCD charge pump capacitance — nominal value
CBYLCD LCD bypass capacitance — nominal value
Min.
28
—
Typ.
30
Max.
58
Unit
Hz
nF
100
100
2000
—
1
1
2
3
—
—
nF
CGlass
VIREG
LCD glass capacitance
VIREG
—
8000
pF
• HREFSEL=0, RVTRIM=1111
• HREFSEL=0, RVTRIM=1000
• HREFSEL=0, RVTRIM=0000
—
—
—
1.11
1.01
0.91
—
—
—
V
V
V
ΔRTRIM
IVIREG
IRBIAS
VIREG TRIM resolution
—
—
—
1
3.0
—
% VIREG
µA
VIREG current adder — RVEN = 1
RBIAS current adder
4
—
—
15
3
—
—
µA
µA
• LADJ = 10 or 11 — High load (LCD glass
capacitance ≤ 8000 pF)
• LADJ = 00 or 01 — Low load (LCD glass
capacitance ≤ 2000 pF)
VLL2
VLL3
VLL2 voltage
• HREFSEL = 0
2.0 − 5%
3.0 − 5%
2.0
3.0
—
—
V
V
VLL3 voltage
1. The actual value used could vary with tolerance.
2. For highest glass capacitance values, LCD_GCR[LADJ] should be configured as specified in the LCD Controller chapter
within the device's reference manual.
3. VIREG maximum should never be externally driven to any level other than VDD - 0.15 V.
4. 2000 pF load LCD, 32 Hz frame frequency.
NOTE
KM family devices have a 1/3 bias controller that works with a
1/3 bias LCD glass. To avoid ghosting, the LCD OFF threshold
should be greater than VLL1 level. If the LCD glass has an
OFF threshold less than VLL1 level, use the internal VREG
mode and generate VLL1 internally using RVTRIM option.
This can reduce VLL1 level to allow for a lower OFF threshold
LCD glass.
7 Dimensions
KM Family Data Sheet, Rev. 1, 09/2014.
Freescale Semiconductor, Inc.
45
Pinout
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to freescale.com and perform a keyword search for the
drawing’s document number:
If you want the drawing for this package
44-pin LGA
Then use this document number
98ASA00239D
64-pin LQFP
100-pin LQFP
98ASS23234W
98ASS23308W
8 Pinout
NOTE
VSS also connects to flag on 44 LGA.
8.1 Package Types
KM family of devices shall support the following packages options:
• 100-pin LQFP (14 x 14 mm2)
• 64-pin LQFP (10 x 10 mm2)
• 44-pin LGA (5 x 5 mm2)
NOTE
Pin muxing selection between TAMPER0 and WKUP is done
using control bit in RTC registers.
NOTE
All pin muxing configurations reset to default value on any
reset assertion (reset asserts on VLLSx mode exit).
When RESET pin is used as GPIO and pulled low; an internal
reset (e.g. VLLSx mode exit or WDOG reset, etc) will make
this pin function as RESET (default function) and since it is
pulled low, it will appear as if pin reset is asserted and will
cause full chip reset.
KM Family Data Sheet, Rev. 1, 09/2014.
46
Freescale Semiconductor, Inc.
Pinout
NOTE
• For devices other than MKMx4, the SDADP3 and
SDADM3 functions on the corresponding pins are disabled.
• All input pins including TAMPER pins must be pulled up
or down to avoid extra power consumption.
8.2 KM Signal Multiplexing and Pin Assignments
100
64
44
DEFAULT
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
QFP
QFP
LGA
1
2
1
2
—
—
—
—
1
Disabled
LCD23
PTA0
PTA1
PTA2
PTA3
PTA4
PTA5
PTA6
PTA7
PTB0
Disabled
Disabled
Disabled
NMI_B
LCD24
LCD25
LCD26
LCD27
LCD28
LCD29
LCD30
LCD31
VDD
3
3
4
—
4
5
LLWU_P15
CMP0OUT
NMI_B
6
5
2
Disabled
Disabled
Disabled
Disabled
VDD
7
6
3
PXBAR_IN0
PXBAR_OUT0
LLWU_P14
8
7
4
9
—
8
—
5
10
11
12
13
14
15
16
17
9
6
VSS
VSS
—
—
—
—
—
—
—
—
—
—
—
—
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
LCD32
LCD33
LCD34
LCD35
LCD36
PTB1
PTB2
PTB3
PTB4
PTB5
PTB6
LCD37/
CMP1P0
18
19
20
10
11
12
—
—
—
Disabled
Disabled
Disabled
LCD38
LCD39
PTB7
PTC0
PTC1
AFE_CLK
SCI3_RTS
SCI3_CTS
PXBAR_IN1
LCD40/
CMP1P1
21
22
13
14
—
—
Disabled
Disabled
LCD41
PTC2
PTC3
SCI3_TxD
SCI3_RxD
PXBAR_OUT1
LLWU_P13
LCD42/
CMP0P3
23
24
25
26
27
28
29
30
—
15
16
17
18
18
18
19
—
7
Disabled
VBAT
LCD43
PTC4
VBAT
8
XTAL32K
EXTAL32K
VSS
XTAL32K
EXTAL32K
VSS
9
10
10
10
11
TAMPER2
TAMPER1
WKUP
TAMPER2
TAMPER1
TAMPER0
KM Family Data Sheet, Rev. 1, 09/2014.
Freescale Semiconductor, Inc.
47
Pinout
100
64
44
DEFAULT
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
QFP
QFP
LGA
31
32
33
34
35
36
37
38
39
20
21
22
23
24
25
26
27
28
12
13
14
15
16
17
18
19
20
VDDA
VDDA
VSSA
VSSA
SDADP0
SDADM0
SDADP1
SDADM1
VREFH
VREFL
SDADP0
SDADM0
SDADP1
SDADM1
VREFH
VREFL
SDADP2/
CMP1P2
SDADP2/
CMP1P2
40
29
21
SDADM2/
CMP1P3
SDADM2/
CMP1P3
41
42
30
—
22
24
VREF
VREF
SDADP3/
CMP1P4
SDADP3/
CMP1P4
43
—
23
SDADM3/
CMP1P5
SDADM3/
CMP1P5
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
—
—
—
—
31
32
33
34
—
—
—
—
35
—
—
36
36
37
37
—
—
38
39
40
—
—
—
—
—
—
—
—
—
—
—
—
25
26
27
28
29
30
31
—
—
32
33
—
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
RESET_B
EXTAL1
XTAL1
AD0
PTC5
PTC6
PTC7
PTD0
PTD1
PTD2
PTD3
PTD4
PTD5
PTD6
PTD7
PTE0
PTE1
PTE2
PTE3
SCI0_RTS
SCI0_CTS
SCI0_TxD
SCI0_RxD
SCI1_TxD
SCI1_RxD
SCI1_CTS
SCI1_RTS
LPTIM2
LLWU_P12
QT1
AD1
AD2
PXBAR_OUT2
PXBAR_IN2
SPI0_SS_B
SPI0_SCK
SPI0_MOSI
SPI0_MISO
QT0
CMP0P0
LLWU_P11
PXBAR_OUT3
PXBAR_IN3
QT3
CMP0P1
LLWU_P10
AD3
LLWU_P9
SCI3_CTS
SCI3_RTS
SCI3_RxD
SCI3_TxD
AD4
AD5
LPTIM1
CMP1OUT
PXBAR_IN4
PXBAR_OUT4
LLWU_P8
LLWU_P7
CLKOUT
CMP0P4
I2C0_SCL
I2C0_SDA
RESET_B
EXTAL1
XTAL1
EWM_IN
PXBAR_IN6
AFE_CLK
I2C1_SDA
I2C1_SCL
EWM_OUT
VSS
VSS
SAR_VSSA
SAR_VDDA
VDD
SAR_VSSA
SAR_VDDA
VDD
Disabled
Disabled
SWD_IO
SWD_CLK
Disabled
PTE4
PTE5
PTE6
PTE7
PTF0
LPTIM0
SCI2_CTS
SCI2_RTS
SCI2_RxD
SCI2_TxD
QT2
EWM_IN
QT3
EWM_OUT
LLWU_P5
LLWU_P6
I2C0_SCL
I2C0_SDA
LLWU_P4
CMP0P2
AD6
PXBAR_IN5
PXBAR_OUT5
RTCCLKOUT
SWD_IO
SWD_CLK
AD7
CMP0OUT
KM Family Data Sheet, Rev. 1, 09/2014.
48
Freescale Semiconductor, Inc.
Pinout
100
64
44
DEFAULT
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
QFP
QFP
LGA
68
69
41
42
34
35
Disabled
LCD0/
AD8
PTF1
PTF2
QT0
PXBAR_OUT6
RTCCLKOUT
Disabled
LCD1/
AD9
CMP1OUT
70
71
72
73
74
75
76
43
44
45
46
47
48
49
—
—
—
—
—
—
36
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
LCD2
LCD3
LCD4
LCD5
LCD6
LCD7
PTF3
PTF4
PTF5
PTF6
PTF7
PTG0
PTG1
SPI1_SS_B
SPI1_SCK
SPI1_MISO
SPI1_MOSI
QT2
LPTIM1
SCI0_RxD
SCI0_TxD
LPTIM0
I2C1_SCL
I2C1_SDA
CLKOUT
LPTIM2
LLWU_P3
QT1
LCD8/
AD10
LLWU_P2
LPTIM0
77
50
37
Disabled
LCD9/
AD11
PTG2
SPI0_SS_B
LLWU_P1
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
51
52
53
54
—
—
—
—
—
—
—
—
—
55
56
57
58
59
60
61
62
63
64
38
39
40
—
—
—
—
—
—
—
—
41
42
43
44
—
—
—
—
—
—
—
—
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
VSS
LCD10
LCD11
LCD12
LCD13
LCD14
LCD15
LCD16
LCD17
LCD18
LCD19
LCD20
PTG3
PTG4
PTG5
PTG6
PTG7
PTH0
PTH1
PTH2
PTH3
PTH4
PTH5
PTH6
PTH7
PTI0
SPI0_SCK
SPI0_MOSI
SPI0_MISO
LLWU_P0
I2C0_SCL
I2C0_SDA
LPTIM1
LPTIM2
SCI1_CTS
SCI1_RTS
SCI1_RxD
SCI1_TxD
SPI1_SS_B
SPI1_SCK
PXBAR_IN7
PXBAR_OUT7
SPI1_MISO
SPI1_MOSI
CMP0P5
PXBAR_IN8
PXBAR_OUT8
SPI1_MOSI
SPI1_MISO
PTI1
LCD21
LCD22
VSS
PTI2
PTI3
VLL3
VLL3
VLL2
VLL2
VLL1
VLL1
VCAP2
VCAP1
VCAP2
VCAP1
8.3 KM Family Pinouts
KM Family Data Sheet, Rev. 1, 09/2014.
Freescale Semiconductor, Inc.
49
Pinout
8.3.1 100-pin LQFP
Figure below shows the KM 100 LQFP pinouts.
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PTA0/LCD23
PTA1/LCD24
PTG0/QT1/LPTIM2/LCD7
2
PTF7/QT2/CLKOUT/LCD6
3
PTA2/LCD25
PTF6/SPI1_MOSI/I2C1_SDA/LLWU_P3/LCD5
PTF5/SPI1_MISO/I2C1_SCL/LCD4
PTF4/SPI1_SCK/LPTIM0/SCI0_TxD/LCD3
PTF3/SPI1_SS_B/LPTIM1/SCI0_RxD/LCD2
PTF2/CMP1OUT/RTCCLKOUT/LCD1/AD9
PTF1/QT0/PXBAR_OUT6/LCD0/AD8
PTF0/RTCCLKOUT/QT2/CMP0OUT/LLWU_P4/AD7
SWD_CLK/PTE7/PXBAR_OUT5/SCI2_TxD/AD6
SWD_IO/PTE6/PXBAR_IN5/SCI2_RxD/LLWU_P5/I2C0_SCL/CMP0P2
PTE5/QT3/SCI2_RTS/EWM_OUT/LLWU_P6
PTE4/LPTIM0/SCI2_CTS/EWM_IN
VDD
4
PTA3/LCD26
5
NMI_B/PTA4/LLWU_P15/LCD27
PTA5/CMP0OUT/LCD28
PTA6/PXBAR_IN0/LLWU_P14/LCD29
PTA7/PXBAR_OUT0/LCD30
PTB0/LCD31
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VDD
VSS
PTB1/LCD32
PTB2/LCD33
PTB3/LCD34
SAR_VDDA
PTB4/LCD35
SAR_VSSA
PTB5/LCD36
VSS
PTB6/LCD37/CMP1P0
PTB7/AFE_CLK/LCD38
PTC0/SCI3_RTS/PXBAR_IN1/LCD39
PTC1/SCI3_CTS/LCD40/CMP1P1
PTC2/SCI3_TxD/PXBAR_OUT1/LCD41
PTC3/SCI3_RxD/LLWU_P13/LCD42/CMP0P3
PTC4/LCD43
PTE3/EWM_OUT/AFE_CLK/I2C1_SCL/XTAL1
PTE2/EWM_IN/PXBAR_IN6/I2C1_SDA/EXTAL1
RESET_B/PTE1
PTE0/I2C0_SDA/PXBAR_OUT4/SCI3_TxD/CLKOUT
PTD7/I2C0_SCL/PXBAR_IN4/SCI3_RxD/LLWU_P7/CMP0P4
PTD6/LPTIM1/CMP1OUT/SCI3_RTS/LLWU_P8/AD5
PTD5/LPTIM2/QT0/SCI3_CTS/AD4
PTD4/SCI1_RTS/SPI0_MISO/LLWU_P9/AD3
VBAT
XTAL32K
Figure 6. 100-pin LQFP Pinout Diagram
KM Family Data Sheet, Rev. 1, 09/2014.
50
Freescale Semiconductor, Inc.
Pinout
8.3.2 64-pin LQFP
Figure below shows the 64-pin LQFP pinouts.
PTA0/LCD23
PTA1/LCD24
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PTG0/QT1/LPTIM2/LCD7
2
PTF7/QT2/CLKOUT/LCD6
PTA2/LCD25
3
PTF6/SPI1_MOSI/I2C1_SDA/LLWU_P3/LCD5
PTF5/SPI1_MISO/I2C1_SCL/LCD4
NMI_B/PTA4/LLWU_P15/LCD27
PTA5/CMP0OUT/LCD28
PTA6/PXBAR_IN0/LLWU_P14/LCD29
PTA7/PXBAR_OUT0/LCD30
VDD
4
5
PTF4/SPI1_SCK/LPTIM0/SCI0_TxD/LCD3
PTF3/SPI1_SS_B/LPTIM1/SCI0_RxD/LCD2
PTF2/CMP1OUT/RTCCLKOUT/LCD1/AD9
PTF1/QT0/PXBAR_OUT6/LCD0/AD8
PTF0/RTCCLKOUT/QT2/CMP0OUT/LLWU_P4/AD7
SWD_CLK/PTE7/PXBAR_OUT5/SCI2_TxD/AD6
6
7
8
VSS
9
PTB7/AFE_CLK/LCD38
PTC0/SCI3_RTS/PXBAR_IN1/LCD39
PTC1/SCI3_CTS/LCD40/CMP1P1
PTC2/SCI3_TxD/PXBAR_OUT1/LCD41
PTC3/SCI3_RxD/LLWU_P13/LCD42/CMP0P3
VBAT
10
11
12
13
14
15
16
SWD_IO/PTE6/PXBAR_IN5/SCI2_RxD/LLWU_P5/I2C0_SCL/CMP0P2
SAR_VDDA VDD
VSS SAR_VSSA
RESET_B/PTE1
PTD4/SCI1_RTS/SPI0_MISO/LLWU_P9/AD3
PTD3/SCI1_CTS/SPI0_MOSI
XTAL32K
Figure 7. 64-pin LQFP Pinout Diagram
KM Family Data Sheet, Rev. 1, 09/2014.
Freescale Semiconductor, Inc.
51
Pinout
8.3.3 44-pin LGA
Figure below shows the 44-pin LGA pinouts.
SWD_CLK/PTE7/PXBAR_OUT5/SCI2_TxD/AD6
33
32
31
30
29
28
27
26
25
NMI_B/PTA4/LLWU_P15/LCD27
PTA5/CMP0OUT/LCD28
PTA6/PXBAR_IN0/LLWU_P14/LCD29
PTA7/PXBAR_OUT0/LCD30
VDD
1
2
SWD_IO/PTE6/PXBAR_IN5/SCI2_RxD/LLWU_P5/I2C0_SCL/CMP0P2
VDD
3
SAR_VDDA
4
SAR_VSSA
5
VSS
VSS
6
PTE3/EWM_OUT/AFE_CLK/I2C1_SCL/XTAL1
PTE2/EWM_IN/PXBAR_IN6/I2C1_SDA/EXTAL1
RESET_B/PTE1
VBAT
7
XTAL32K
8
EXTAL32K
9
VSS TAMPER2 TAMPER1
WKUP/TAMPER0
10
11
SDADM3/CMP1P5
SDADP3/CMP1P4
23
24
Figure 8. 44-pin LGA Pinout Diagram
NOTE
VSS also connects to flag on 44 LGA.
KM Family Data Sheet, Rev. 1, 09/2014.
52
Freescale Semiconductor, Inc.
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Document Number MKMxxZxxACxx5
Revision 1, 09/2014
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