MK20X512VMD100 [NXP]
RISC MICROCONTROLLER, PBGA144, 13 X 13 MM, MAPBGA-144;型号: | MK20X512VMD100 |
厂家: | NXP |
描述: | RISC MICROCONTROLLER, PBGA144, 13 X 13 MM, MAPBGA-144 时钟 外围集成电路 |
文件: | 总67页 (文件大小:997K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Document Number: K20P144M100SF2
Rev. 1, 11/2010
Freescale Semiconductor
Data Sheet: Product Preview
K20P144M100SF2
K20 Sub-Family Data Sheet
Supports the following:
MK20X128VLQ100,
MK20X128VMD100,
MK20X256VLQ100,
MK20X256VMD100,
MK20N512VLQ100,
MK20N512VMD100
Features
Security and integrity mods
– Hardware CRmoe to support fast cyclic
redundancy check
•
Operating Characteristics
– Voltage range: 1.71 to 3.6 V
– Flash write voltage range: 1.71 to 3.6 V
– Temperature range (ambient): -40 to 105°C
•
•
•
– 128-bit ue idication (ID) number per chip
Human-mhine interface
– Lo-powhardware touch sensor interface (TSI)
Genel-purpose input/output
•
Performance
– Up to 100 MHz ARM Cortex-M4 core with DSP
instructions delivering 1.25 Dhrystone MIPS per
MHz
Analomodules
16-bit SAR ADC with PGA (x64)
– 12-bit DAC
– Analog comparator (CMP) containing a 6-bit DAC
and programmable reference input
– Voltage reference
Memories and memory interfaces
– Up to 512 KB program flash memory on non-
FlexMemory devices
– Up to 256 KB program flash memory on
FlexMemory devices
– Up to 256 KB FlexNVM on FlexMemry ice
– 4 KB FlexRAM on FlexMemory dees
– Up to 128 KB RAM
Timers
•
– Programmable delay block
– Eight-channel motor control/general purpose/PWM
timers
– Serial programming intPort)
– FlexBus external bus inter
– Two-channel quadrature decoder/general purpose
timers
Clocks
– Periodic interrupt timers
– 16-bit low-power timer
– Carrier modulator transmitter
– Real-time clock
•
•
– 1 to 32 MHz crystal oscillator
– 32 kHz crystal oscillator
– Multi-purpose clock generator
System peripherals
Communication interfaces
– USB full-/low-speed On-the-Go controller with on-
chip transceiver
– Controller Area Network (CAN) module
– SPI modules
•
– 10 low-power modes to provide power optimization
based on application requirements
– Memory protection unit with multi-master
protection
– 16-channel DMA controller, supporting up to 64
request sources
– I2C modules
– UART modules
– External watchdog monitor
– Software watchdog
– Secure Digital host controller (SDHC)
– I2S
– Low-leakage wakeup unit
This document contains information on a product under development. Freescale
reserves the right to change or discontinue this product without notice.
© 2010–2010 Freescale Semiconductor, Inc.
Preliminary
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
2
Freescale Semiconductor, Inc.
Table of Contents
1 Ordering parts...........................................................................5
6.1 Core modules....................................................................20
6.1.1 Debug trace timing specifications.........................20
6.1.2 JTAG electricals....................................................21
6.2 System modules................................................................24
6.3 Clock modules...................................................................24
6.3.1 MCG Specifications...............................................24
6.3.2 Oscillator Electrical Characteristics.......................26
1.1 Determining valid orderable parts......................................5
2 Part identification......................................................................5
2.1 Description.........................................................................5
2.2 Format...............................................................................5
2.3 Fields.................................................................................5
2.4 Example............................................................................6
3 Terminology and guidelines......................................................6
3.1 Definition: Operating requirement......................................6
3.2 Definition: Operating behavior...........................................7
3.3 Definition: Attribute............................................................7
3.4 Definition: Rating...............................................................8
3.5 Result of exceeding a rating..............................................8
3.6 Relationship between ratings and operating
6.3.2.1
6.3.2.2
Oscillator DC Electrical Specifications 26
Oscillator frequenspecifications......27
6.3.3 32kHz Oscillator Electril Chacteristics............28
6.3.3.1
32kHz Ocillator DC ctrical
Specificas..................................28
32kscillator Frequency
6.3.3.2
Sations......................................28
requirements......................................................................8
3.7 Guidelines for ratings and operating requirements............9
3.8 Definition: Typical value.....................................................9
3.9 Typical Value Conditions...................................................10
4 Ratings......................................................................................10
4.1 Thermal handling ratings...................................................10
4.2 Moisture handling ratings.............................................11
4.3 ESD handling ratings........................................................
4.4 Voltage and current operating ratings...................11
5 General.........................................................................12
5.1 Nonswitching electrical specificns..........................12
5.1.1 Voltage and Curreg Requiments......12
5.1.2 LVD and POR operatquirements.................13
5.1.3 Voltage and current operag behaviors..............14
5.1.4 Power mode transition operating behaviors..........14
5.1.5 Power consumption operating behaviors..............15
6.4 Memories and mmory interfaces.....................................29
6.4.1 Fl(FTFL) Electrical Characteristics.................29
.4.1.1
6.4.1.2
6.4.1.3
Flash Timing Parameters — Program
and Erase............................................29
Flash Timing Parameters —
Commands..........................................29
Flash (FTFL) Current and Power
Parameters..........................................31
Reliability Characteristics....................31
Write Endurance to FlexRAM for
6.4.1.4
6.4.1.5
EEPROM.............................................32
6.4.2 EzPort Switching Specifications............................33
6.4.3 Flexbus Switching Specifications..........................34
6.5 Security and integrity modules..........................................36
6.6 Analog...............................................................................36
6.6.1 ADC electrical specifications.................................36
5.1.5.1
Diagram: Typical IDD_RUN operating
behavior...............................................17
6.6.1.1
6.6.1.2
6.6.1.3
16-bit ADC operating conditions..........37
16-bit ADC electrical characteristics....39
16-bit ADC with PGA operating
5.1.6 EMC radiated emissions operating behaviors.......18
5.1.7 Designing with radiated emissions in mind...........19
5.1.8 Capacitance attributes..........................................19
5.2 Switching electrical specifications.....................................19
5.3 Thermal specifications.......................................................19
5.3.1 Thermal operating requirements...........................20
5.3.2 Thermal attributes.................................................20
6 Peripheral operating requirements and behaviors....................20
conditions............................................42
16-bit ADC with PGA characteristics...43
6.6.1.4
6.6.2 CMP and 6-bit DAC electrical specifications.........44
6.6.3 12-bit DAC electrical characteristics.....................45
6.6.3.1
6.6.3.2
12-bit DAC operating requirements.....45
12-bit DAC operating behaviors..........46
6.6.4 Voltage Reference Electrical Specifications..........48
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
3
Preliminary
6.7 Timers................................................................................49
6.8 Communication interfaces.................................................49
6.8.1 USB electrical specifications.................................50
6.8.2 USB DCD Electrical Specifications.......................50
6.8.3 USB Voltage Regulator Electrical Specifications. .50
6.8.4 DSPI Switching Specifications for Low-speed
Operation..............................................................51
6.8.7 I2S Switching Specifications.................................55
6.9 Human-machine interfaces (HMI)......................................57
6.9.1 General Switching Specifications..........................57
6.9.2 TSI Electrical Specifications..................................58
7 Dimensions...............................................................................58
7.1 Obtaining package dimensions.........................................58
8 Pinout........................................................................................59
8.1 K20 Signal Multiplexing and Pin Assignments..................59
8.2 K20 Pinouts.......................................................................64
9 Revision History....................................................................66
6.8.5 DSPI Switching Specifications (High-speed
mode)....................................................................52
6.8.6 SDHC Specifications.............................................54
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
4
Freescale Semiconductor, Inc.
Preliminary
Ordering parts
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to www.freescale.com and perform a part number search for
the following device numbers: PK20 and MK20.
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the pecic part. You can use the
values of these fields to determine the specific part ou have received.
2.2 Format
Part numbers for this device have tfollowing format:
Q K## M FFF T PP CCC N
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
K##
M
Kinetis family
• K20
Flash memory type
• N = Program flash only
• X = Program flash and FlexMemory
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
Freescale Semiconductor, Inc.
5
Terminology and guidelines
Field
Description
Values
FFF
Program flash memory size
• 32 = 32 KB
• 64 = 64 KB
• 128 = 128 KB
• 256 = 256 KB
• 512 = 512 KB
• 1M0 = 1 MB
T
Temperature range (°C)
• V = –40 to 105
PP
Package identifier
• FM = 32 QFN (5 mm x 5 mm)
• FT = 48 QFN (7 mm x 7 mm)
• LF = 48 LQFP (7 mm x 7 mm)
• FX = 64 QFN (9 mm x 9 m)
• LH = 64 LQFP (10 mm x 1mm)
• LK = 80 LQFP (12 mx 12 m)
• MB = 81 MAPBG(8 mm mm)
• LL = 100 LQFP mm x 14 m)
• ML = 104 MAPBG8 mm x mm)
• LQ = 144 LQ(20 mm x 20 mm)
• MD = 144 MA (13 mm x 13 mm)
• MF 196 MGA (15 mm x 15 mm)
• MJ = 2MAPBGA (17 mm x 17 mm)
CCC
Maximum CPU frequency (MHz)
Packaging type
• 550 MHz
72 = 2 MHz
• 00 = 100 MHz
• 120 = 120 MHz
• 150 = 150 MHz
N
• R = Tape and reel
• (Blank) = Trays
2.4 Example
This is an example paber:
MK20N512VMD100
3 Terminology and guidelines
3.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
6
Freescale Semiconductor, Inc.
Preliminary
Terminology and guidelines
3.1.1 Example
This is an example of an operating requirement, which you must meet for the
accompanying operating behaviors to be guaranteed:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply volt‐ 0.9
age
1.1
V
3.2 Definition: Operating behavior
An operating behavior is a specified value or range of values for a tecnical
characteristic that are guaranteed during operation if you meet the erating requirements
and any other specified conditions.
3.2.1 Example
This is an example of an operating behavior, which is guaranteed if you meet the
accompanying operating requirements:
Symbol
Description
Mi.
Max.
Unit
IWP
Digital I/O weak pullu
pulldown current
130
µA
3.3 Definition: Atibute
An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.
3.3.1 Example
This is an example of an attribute:
Symbol
Description
Min.
Max.
Unit
CIN_D
Input capacitance: digi‐
tal pins
—
7
pF
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
Freescale Semiconductor, Inc.
7
Terminology and guidelines
3.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
3.4.1 Example
This is an example of an operating rating:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply volt‐ –0.3
age
1.2
V
3.5 Result of exceeding a rating
40
30
Tkelihd of permanent chip failure increases rapidly as
soocharacteristic begins to exceed one of its operating ratings.
20
10
0
Operating rating
Measured characteristic
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
8
Freescale Semiconductor, Inc.
Terminology and guidelines
3.6 Relationship between ratings and operating requirements
Fatal
range
Normal
operating
range
Fatal
range
- Probable permanent failure
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Correct operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- Probable permanent failure
Handling range
- No permanent failure
–∞
∞
3.7 Guidelines for ratings and operating requirents
Follow these guidelines for ratings and operating requirements
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of te chip’s operating requirements.
• If you must exceed an operating requiremenat times other than during normal
operation (for example, during power seqencing), limit the duration as much as
possible.
3.8 Definition: Typicavalue
A typical value is a spd vale for a technical characteristic that:
• Lies within the raf values specified by the operating behavior
• Given the typical maufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
3.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol
Description
Min.
Typ.
Max.
Unit
IWP
Digital I/O weak
pullup/pulldown
current
10
70
130
µA
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
Freescale Semiconductor, Inc.
9
Ratings
3.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
5000
4500
4000
TJ
3500
150 °C
3000
10C
2500
25 °C
2000
1500
1000
500
0
0.90
0.95
1.00
1.05
0
VDD (V)
3.9 Typical Value Conditins
Typical values assume meet he following conditions (or other conditions as
specified):
Symbol
Description
Value
Unit
TA
Ambient temperature
25
°C
V
VDD
3.3 V supply voltage
3.3
4 Ratings
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
10
Freescale Semiconductor, Inc.
Ratings
4.1 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
2
TSDR
Solder temperature, lead-free
Solder temperature, leaded
—
—
260
245
°C
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.2 Moisture handling ratings
Symbol
Description
Min.
Ma
Unit
Notes
MSL
Moisture sensitivity level
—
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Refloensitiy Classification for Nonhermetic
Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
VHBM
Electrostatic discharge voltage, human bodmodel
-2000
+2000
V
1
VCDM
ILAT
Electrostatic discharge voltage, ed-evice model
Latch-up current at ambienemperatre of 85°C
-500
-100
+500
+100
V
2
mA
1. Determined according to Jandard ESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDStandard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-WithstanThresholds of Microelectronic Components.
4.4 Voltage and current operating ratings
Symbol
Description
Min.
Max.
Unit
VDD
Digital supply voltage
–0.3
3.8
V
IDD
Digital supply current
—
185
5.5
mA
V
VDIO
VAIO
Digital input voltage (except RESET, EXTAL, and XTAL)
Analog, RESET, EXTAL, and XTAL input voltage
–0.3
–0.3
VDD + 0.3
V
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
Freescale Semiconductor, Inc.
11
General
Symbol
Description
Min.
Max.
Unit
ID
Instantaneous maximum current single pin limit (applies to all
port pins)
–25
25
mA
VDDA
IDDA
Analog supply voltage
VDD – 0.3
TBD
–0.3
VDD + 0.3
TBD
3.63
3.63
6.0
V
mA
V
Analog supply current1
VUSB_DP
VUSB_DM
VREGIN
VBAT
USB_DP input voltage
USB_DM input voltage
–0.3
V
USB regulator input
–0.3
V
RTC battery supply voltage
VDD voltage required to retain RAM
VBAT voltage required to retain the VBAT register file
–0.3
3.8
V
VRAM
1.2
—
V
VRFVBAT
TBD
—
V
1. The analog supply current is the sum of the active or disabled current for each of the aog mules on the device. See
each module's specification for its supply current.
5 General
5.1 Nonswitching electrical specfications
5.1.1 Voltage and Current eraing Requirements
Table 1. Voltagnd current operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
VDD
Supply voltage
1.71
3.6
V
VDDA
Analog supply volt
1.71
–0.1
–0.1
3.6
0.1
0.1
V
V
V
VDD – VDDA VDD-to-VDDA differentiavoltage
VSS – VSSA VSS-to-VSSA differential voltage
VIH
Input high voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
0.7 × VDD
—
—
V
V
0.75 × VDD
VIL
Input low voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
—
—
0.35 × VDD
0.3 × VDD
V
V
VHYS
Input hysteresis
0.06 × VDD
—
V
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
12
Freescale Semiconductor, Inc.
General
Table 1. Voltage and current operating requirements (continued)
Symbol
Description
Min.
Max.
Unit
Notes
IIC
DC injection current — single pin
• VIN > VDD
1
0
0
2
mA
mA
–0.2
• VIN < VSS
DC injection current — total MCU limit, includes sum
of all stressed pins
1
0
0
25
–5
mA
mA
• VIN > VDD
• VIN < VSS
1. All functional non-supply pins are internally clamped to VSS and VDD. Input must be current limito te value specified.
To determine the value of the required current-limiting resistor, calculate resistance values fopositive negative clamp
voltages, then use the larger of the two values. Power supply must maintain regulation withiperating VD range during
instantaneous and operating maximum current conditions. If positive injection current (Vn > V) is greaer than IDD, the
injection current may flow out of VDD and could result in external power supply goinout regulation. Ensure external
VDD load will shunt current greater than maximum injection current. This will be the gresk when the MCU is not
consuming power. Examples are: if no system clock is present, or if clock rate ery lohich would reduce overall
power consumption).
5.1.2 LVD and POR operating requiremets
Table 2. LVD and POR perting requirements
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VPOR
Falling VDD POR detect voltage
TBD
1.1
TBD
V
VLVDH
Falling low-voltage detect thresholh
range (LVDV=01)
TBD
2.56
TBD
V
Low-voltage warning threshls — higrange
• Level 1 fallinV=00
1
VLVW1
VLVW2
VLVW3
VLVW4
VHYS
TBD
TBD
TBD
TBD
2.70
2.80
2.90
3.00
TBD
TBD
TBD
TBD
V
V
V
V
• Level 2 fallWV=01)
• Level 3 falling (WV=10)
• Level 4 falling (LVWV=11)
Low-voltage inhibit reset/recover hysteresis —
high range
60
mV
V
VLVDL
Falling low-voltage detect threshold — low range
(LVDV=00)
TBD
TBD
TBD
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00)
1
VLVW1
VLVW2
VLVW3
VLVW4
TBD
TBD
TBD
TBD
1.80
1.90
2.00
2.10
TBD
TBD
TBD
TBD
V
V
V
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
Freescale Semiconductor, Inc.
13
General
Table 2. LVD and POR operating requirements (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VHYS
Low-voltage inhibit reset/recover hysteresis —
low range
40
mV
VBG
tLPO
Bandgap voltage reference
TBD
TBD
1.00
TBD
TBD
V
Internal low power oscillator period
factory trimmed
1000
μs
1. Rising thresholds are falling threshold + VHYS
5.1.3 Voltage and current operating behaviors
Table 3. Voltage and current operating behavior
Symbol
Description
Min.
Ma
Unit
Notes
VOH
Output high voltage — high drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -10mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3mA
VDD – 5
VD– 0.5
—
—
V
V
Output high voltage — low drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6mA
VDD – 0.5
VDD – 0.5
—
—
V
V
IOHT
VOL
Output high current total for all ports
—
100
mA
Output low voltage — high drive h
• 2.7 V ≤ VDD ≤ 3.6 V, IO= A
• 1.71 V ≤ VDD ≤ 2.7 VL = 3mA
—
—
0.5
0.5
V
V
Output low voltw drive strength
• 2.7 V ≤ VDD .6 V, IOL = 2mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 0.6mA
—
—
0.5
0.5
V
V
IOLT
IIN
Output low current total for all ports
Input leakage current (per pin)
—
—
—
30
100
1
mA
μA
μA
kΩ
IOZ
Hi-Z (off-state) leakage current (per pin)
Internal weak pullup and pulldown resistors
1
RPU and
RPD
50
1
1. Measured at VIL max and VDD min
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
14
Freescale Semiconductor, Inc.
General
5.1.4 Power mode transition operating behaviors
In the table below, all specifications except tPOR, assume the following clock
configuration:
• CPU and system clocks = 100MHz
• Bus and FlexBus clocks = 50 MHz
• Flash clock = 25 MHz
Table 4. Power mode transition operating behaviors
Symbol
Description
Min.
Max.
U
Notes
tPOR
After a POR event, amount of time from the point VDD
reaches 1.8V to execution of the first instruction
across the operating temperature range of the chip.
—
300
μ
1
RUN → VLLS1 → RUN
• RUN → VLLS1
—
—
μs
μs
• VLLS1 → RUN
23.8
RUN → VLLS2 → RUN
• RUN → VLLS2
—
—
4.1
μs
μs
• VLLS2 → RUN
49.3
RUN → VLLS3 → RUN
• RUN → VLLS3
—
—
4.1
μs
μs
• VLLS3 → RUN
49.2
RUN → LLS → RUN
• RUN → LLS
—
—
4.1
5.9
μs
μs
• LLS → RU
RUN → STOP → R
• RUN → STOP
—
—
4.1
4.2
μs
μs
• STOP → RUN
RUN → VLPS → RUN
• RUN → VLPS
—
—
4.1
5.8
μs
μs
• VLPS → RUN
1. Normal boot (FTFL_OPT[LPBOOT]=1)
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
Freescale Semiconductor, Inc.
15
General
5.1.5 Power consumption operating behaviors
Table 5. Power consumption operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDD_RUN Run mode current — all peripheral clocks disa‐
bled, code executing from flash
1
• @ 1.8V
• @ 3.0V
—
—
40
42
TBD
TBD
mA
mA
IDD_RUN Run mode current — all peripheral clocks ena‐
bled, code executing from flash
2
3
• @ 1.8V
• @ 3.0V
—
—
55
56
TBD
TBD
A
IDD_RUN_M Run mode current — all peripheral clocks ena‐
bled and peripherals active, code executing from
AX
flash
—
—
85
85
TBD
mA
mA
• @ 1.8V
• @ 3.0V
IDD_WAIT Wait mode current at 3.0 V — all peripheral
clocks disabled
—
1
TBD
mA
4
IDD_STOP Stop mode current at 3.0 V
—
—
1.4
TBD
TBD
mA
mA
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
1.25
5
6
7
IDD_VLPR Very-low-power run mode current at 3.0 — al
peripheral clocks enabled
—
TBD
TBD
mA
IDD_VLPW Very-low-power wait mode current V
IDD_VLPS Very-low-power stop mode cuent 3.0
—
—
—
1.05
30
TBD
TBD
TBD
mA
μA
μA
IDD_LLS
Low leakage stop mcurreat 3.0 V
12
IDD_VLLS3 Very low-leakagde 3 current at 3.0 V
• 128KB RAM dces
—
—
—
8
6
5
TBD
TBD
TBD
μA
μA
μA
• 64KB RAM device
• 32KB RAM devices
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
—
—
—
4
2
TBD
TBD
TBD
μA
μA
nA
IDD_VBAT Average current when CPU is not accessing
RTC registers at 3.0 V
550
1. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock . MCG configured for FEI mode.
All peripheral clocks disabled.
2. 100MHz core and system clock, 50MHz bus and FlexBus clocks, and 25MHz flash clock. MCG configured for FEI mode.
All peripheral clocks enabled, but peripherals are not in active operation.
3. 100MHz core and system clock, 50MHz bus and FlexBus clocks, and 25MHz flash clock. MCG configured for FEI mode.
All peripheral clocks enabled, and peripherals are in active operation.
4. 25MHz core and system clock, 25MHz bus clock, and 12.5MHz FlexBus and flash clocks. MCG configured for FEI mode.
5. 2 MHz core, system, bus and FlexBus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral
clocks disabled. Code executing from flash.
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
16
Freescale Semiconductor, Inc.
Preliminary
General
6. 2 MHz core, system, bus and FlexBus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral
clocks enabled but peripherals are not in active operation. Code executing from flash.
7. 2 MHz core, system, bus and FlexBus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral
clocks disabled.
5.1.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE)
• All peripheral clocks disabled except FTFL
• LVD disabled, USB regulator disabled
• No GPIOs toggled
• Code execution from flash
Figure 1. Run mode supply current vs. core frequency — all peripheral clocks disabled
The following data was measured under these conditions:
• MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE)
• All peripheral clocks enabled but peripherals are not in active operation
• LVD disabled, USB regulator disabled
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
17
Preliminary
General
• No GPIOs toggled
• Code execution from flash
Figure 2. Run mode supply crrent vs. core frequency — all peripheral clocks enabled
5.1.6 EMC radiated emissions operating behaviors
Table 6. EMC radiated emissions operating behaviors
Symbol
Description
Frequency
band (MHz)
Typ.
Unit
Notes
VRE1
VRE2
VRE3
VRE4
Radiated emissions voltage, band 1
Radiated emissions voltage, band 2
Radiated emissions voltage, band 3
Radiated emissions voltage, band 4
0.15–50
50–150
TBD
TBD
TBD
TBD
TBD
dBμV
1, 2
150–500
500–1000
0.15–1000
VRE_IEC_SAE IEC and SAE level
—
2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions, IEC Standard 61967-2, Integrated Circuits - Measurement of
Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method, and SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated Circuits—TEM/
Wideband TEM (GTEM) Cell Method.
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
18
Freescale Semiconductor, Inc.
Preliminary
General
2. VDD = 3 V, TA = 25 °C, fOSC = 16 MHz (crystal), fBUS = 20 MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method, and Appendix D of SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated
Circuits—TEM/Wideband TEM (GTEM) Cell Method.
5.1.7 Designing with radiated emissions in mind
1. To find application notes that provide guidance on designing your system to
minimize interference from radiated emissions, go to www.freescale.com and
perform a keyword search for “EMC design.”
5.1.8 Capacitance attributes
Table 7. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN_A
Input capacitance: analog pins
7
pF
CIN_D
Input capacitance: digital pins
—
7
pF
5.2 Switching electrical specifications
Table 8. Devicclock specifications
Symbol
Description
Min.
Max.
Unit
Notes
Normal run mode
fSYS
fBUS
System and cor
Bus clock
—
—
—
—
100
50
MHz
MHz
MHz
MHz
FB_CLK
fFLASH
FlexBus clock
Flash clock
50
25
VLPR mode
fSYS
fBUS
System and core clock
Bus clock
—
—
—
—
2
2
2
1
MHz
MHz
MHz
MHz
FB_CLK
fFLASH
FlexBus clock
Flash clock
5.3 Thermal specifications
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
Freescale Semiconductor, Inc.
19
Peripheral operating requirements and behaviors
5.3.1 Thermal operating requirements
Table 9. Thermal operating requirements
Symbol
Description
Min.
Max.
Unit
TJ
Die junction temperature
–40
125
°C
TA
Ambient temperature
–40
105
°C
5.3.2 Thermal attributes
Board Symbol Description
type
144
LQFP
144
Unit
°C/W
°C/W
°C/W
°C/W
Notes
MPBG
Single-
layer (1s)
RθJA
Thermal resistance, junction to ambient (natural 52
convection)
5
1
Four-layer RθJA
(2s2p)
Thermal resistance, junction to ambient (natural 4
convection)
30
41
27
1
1
1
Single-
layer (1s)
RθJMA
Thermal resistance, junction to ambient (200 ft./
min. air speed)
Four-layer RθJMA
(2s2p)
Thermal resistance, junction to ambien(0 ft./ 38
min. air speed)
—
—
—
RθJB
RθJC
ΨJT
Thermal resistance, junction to ard
Thermal resistance, junction case
33
11
2
17
10
2
°C/W
°C/W
°C/W
2
3
4
Thermal characterizatioaramr, junction to
package top outside (natural convection)
6 Peripheral oating requirements and behaviors
6.1 Core modules
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental Conditions—Forced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions
—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material between
the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
20
Freescale Semiconductor, Inc.
Preliminary
Peripheral operating requirements and behaviors
6.1.1 Debug trace timing specifications
Table 10. Debug trace operating behaviors
Symbol
Description
Min.
Max.
Unit
Tcyc
Clock period
Frequency dependent
MHz
Twl
Twh
Tr
Low pulse width
High pulse width
Clock and data rise time
Clock and data fall time
Data setup
2
2
—
—
3
ns
ns
ns
ns
ns
ns
—
—
3
Tf
3
Ts
—
Th
Data hold
2
Figure 3. TRACE_CLKOT spcifications
TRACE_CLKOUT
TRACE_D[3:0]
Th
Ts
Th
Figure 4. Trace data specifications
6.1.2 JTAG electricals
Table 11. JTAG electricals
Symbol
Description
Min.
Max.
Unit
V
Operating voltage
2.7
3.6
J1
TCLK frequency of operation
• JTAG and CJTAG
• Serial Wire Debug
MHz
0
0
25
50
J2
TCLK cycle period
1/J1
—
ns
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
Freescale Semiconductor, Inc.
21
Peripheral operating requirements and behaviors
Table 11. JTAG electricals (continued)
Symbol
Description
Min.
Max.
Unit
J3
TCLK clock pulse width
• JTAG and CJTAG
• Serial Wire Debug
ns
20
10
—
—
J4
J5
TCLK rise and fall times
—
20
0
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high-Z
TMS, TDI input data setup time to TCLK rise
TMS, TDI input data hold time after TCLK rise
TCLK low to TDO data valid
—
—
30
0
—
—
4
J6
J7
—
—
16
1
J8
J9
J10
J11
J12
J13
J14
—
—
100
8
TCLK low to TDO high-Z
4
TRST assert time
—
—
TRST setup time (negation) to TCLK high
J2
J4
J3
J3
TCLK (input)
Fiure . Test clock input timing
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
22
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
TCLK
J5
J6
Input data valid
Data inputs
Data outputs
Data outputs
Data outputs
J7
Output data valid
J8
J7
Output dad
Figure 6. Boundary scan (TAGtiming
TCLK
TDI/TMS
TDO
J9
J10
Input data valid
J11
Output data valid
J12
J11
TDO
Output data valid
TDO
Figure 7. Test Access Port timing
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
Freescale Semiconductor, Inc.
23
Peripheral operating requirements and behaviors
TCLK
J14
J13
TRST
Figure 8. TRST timing
6.2 System modules
There are no specifications necessary for the device's system modul.
6.3 Clock modules
6.3.1 MCG Specifications
Table 12. MCspecfications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fints_ft
fints_t
tirefsts
Internal reference frequency (slow clock) — cto‐
ry trimmed at nominal VDD and 25°
—
32.768
—
kHz
Internal reference frequency (slow k) user
trimmed
31.25
—
39.0625
kHz
Internal reference (ock) rtup time
—
—
TBD
0.1
4
µs
Δfdco_res_t Resolution of trimCO output frequency at
fixed voltage and terature — using SCTRIM
and SCFTRIM
0.3
%fdco
Δfdco_res_t Resolution of trimmed DCO output frequency at
fixed voltage and temperature — using SCTRIM
only
—
0.2
0.5
%fdco
Δfdco_t
Total deviation of trimmed DCO output frequency
over voltage and temperature
—
—
+ 0.5
- 1.0
0.5
3.5
%fdco
%fdco
Δfdco_t
Total deviation of trimmed DCO output frequency
over fixed voltage and temperature range of 0–
70°C
TBD
fintf_ft
Internal reference frequency (fast clock) — factory
trimmed at nominal VDD and 25°C
3.875
3
4
4.125
5
MHz
MHz
fintf_t
Internal reference frequency (fast clock) — user
trimmed
—
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
24
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 12. MCG specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
tirefstf
Internal reference startup time (fast clock)
—
TBD
TBD
µs
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
—
kHz
floc_high
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
—
—
kHz
FLL
fdco_t
DCO output fre‐
quency range —
user trimmed
Low range (DRS=00)
640 × fints_t
20
40
60
80
—
—
—
20.97
41.94
62.91
3.89
23.99
47.97
71.99
95.98
25
50
75
100
—
MHz
Mz
MHz
MHz
MHz
MHz
MHz
MHz
1, 2
and DMX32=0
Mid range (DRS=01)
1280 × fints_t
Mid-high range (DRS=10
192)0 × fints_t
High range (DRS=11)
2560 × fints_t
fdco_t_DMX3 DCO output fre‐
Low range (DRS=00)
732 × fints_t
3
quency range —
2
reference =
32,768Hz and
DMX32=1
Mid range (DRS=01)
1464 × fintt
—
Mid-high range (DR10)
2197 ×
—
High range RS=1)
29 × fints_t
—
Jcyc_fll
Jacc_fll
FLL period jitter
—
—
TBD
TBD
TBD
TBD
ps
ps
4
5
FLL accumulated jif DCO output over a 1µs
time window
tfll_acquire FLL target frequency acquisition time
—
—
1
ms
PLL
fvco
VCO operating frequency
48.0
2.0
—
—
—
100
4.0
—
MHz
MHz
ps
fpll_ref
Jcyc_pll
Jacc_pll
Dlock
PLL reference frequency range
PLL period jitter
400
TBD
—
6, 7
PLL accumulated jitter over 1µs window
Lock entry frequency tolerance
Lock exit frequency tolerance
Lock detector detection time
—
—
ps
6 , 7
1.49
4.47
—
2.98
5.97
%
Dunl
—
%
tpll_lock
—
0.15 +
ms
8
1075(1/
fpll_ref
)
1. The resulting system clock frequencies should not exceed their maximum specified values.
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
25
Preliminary
Peripheral operating requirements and behaviors
2. This specification includes the 2% precision of the internal reference frequency (slow clock).
3. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
4. This specification was obtained at TBD frequency.
5. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
6. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
7. This specification was obtained at internal frequency of TBD.
8. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
6.3.2 Oscillator Electrical Characteristics
This section provides the electrical characteristics of the module.
6.3.2.1 Oscillator DC Electrical Specifications
Table 13. Oscillator DC electrical specifications, (VSOSC= 0 VDC) (TA = TL to TH)
Symbol Description
M
yp.
Max.
Unit
Notes
VDD33OSC 3.3 V supply voltage
71
—
3.6
V
IDDOSC
Supply current — low-power mode
1
• 32 kHz
• 1 MHz
• 4 MHz
• 8 MHz
• 16 MHz
• 24 MHz
• 32 MHz
—
—
—
—
—
—
—
500
100
200
300
700
1.2
—
—
—
—
—
—
—
nA
μA
μA
μA
μA
mA
mA
1.5
IDDOSC
Supply current — high gin mode
• 32 kHz
1
—
—
—
—
—
—
—
25
200
400
800
1.5
3
—
—
—
—
—
—
—
μA
μA
• 1 MHz
• 4 MHz
μA
• 8 MHz
μA
• 16 MHz
mA
mA
mA
• 24 MHz
• 32 MHz
4
Cx
Cy
EXTAL load capacitance
XTAL load capacitance
—
—
—
—
—
—
2, 3
2 , 3
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
26
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 13. Oscillator DC electrical specifications, (VSSOSC= 0 VDC) (TA = TL to TH)
(continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
RF Feedback resistor — low-frequency, low-power
—
—
—
MΩ
2 , 3
mode
Feedback resistor — low-frequency, high-gain
mode
—
—
—
—
10
—
1
—
—
—
—
MΩ
MΩ
MΩ
k
Feedback resistor — high-frequency, low-power
mode (1 – 8 MHz, 8 – 32 MHz)
Feedback resistor — high-frequency, high-gain
mode (1 – 8 MHz, 8 – 32 MHz)
RS
Series resistor — low-frequency, low-power
mode
—
Series resistor — low-frequency, high-gain mode
—
—
200
—
—
kΩ
kΩ
Series resistor — high-frequency, low-power
mode
Series resistor — high-frequency, high-gain
mode
• 1 MHz resonator
• 2 MHz resonator
• 4 MHz resonator
• 8 MHz resonator
• 16 MHz resonator
• 20 MHz resonator
• 32 MHz resonator
—
—
—
—
—
—
—
6.6
3.3
0
—
—
—
—
—
—
—
—
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
V
0
0
0
0
Vpp
Peak-to-peak amplitude of osllation illator
mode) — low-freque, low-wer mode
0.6
Peak-to-peak aoscillaion (oscillator
mode) — low-freq, high-gain mode
0.75 ×
VDD33OSC
VDD33OSC
—
—
—
V
V
V
Peak-to-peak amplitudf oscillation (oscillator
mode) — high-frequency, low-power mode
—
0.6
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
0.75 ×
VDD33OSC
VDD33OSC
1. VDD33OSC=3.3 V, Temperature =27 °C, Cx/Cy=20 pF
2. See crystal or resonator manufacturer's recommendation
3. RF and Cx,Cy are integrated in low-frequency, low-power mode and must not be attached externally
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
27
Preliminary
Peripheral operating requirements and behaviors
6.3.2.2 Oscillator frequency specifications
Table 14. Oscillator frequency specifications, (VDD33OSC = VDD33OSC (min) to
VDD33OSC (max), TA = TL to TH)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fosc_lo
fosc_hi_1
fosc_hi_2
Oscillator crystal or resonator frequency — low
frequency mode
32
—
40
kHz
Oscillator crystal or resonator frequency — high
frequency mode (low range)
1
8
—
—
8
MHz
MHz
Oscillator crystal or resonator frequency — high
frequency mode (high range)
32
tdc_extal
tcst
Input clock duty cycle (external clock mode)
40
—
50
60
—
Crystal start-up time — 32 kHz low-frequency,
low-power mode
TBD
ms
1, 2, 3
Crystal start-up time — 32 kHz low-frequency,
high-gain mode
—
—
—
800
4
—
—
ms
ms
ms
Crystal start-up time — 8 MHz high-frequency,
low-power mode
Crystal start-up time — 8 MHz high-frequency,
high-gain mode
3
1. This parameter is characterized before qualification rather thn 1% tested.
2. Proper PC board layout procedures must be followeto acve spifications.
3. Crystal start up time is defined as the time between the oscillar being enabled and the OSCINIT bit in the MCG_S
register being set.
6.3.3 32kHz Oscillator Elecrical Characteristics
This section describes odulelectrical characteristics.
6.3.3.1 32kHz Oscillaor DC Electrical Specifications
Table 15. 32kHz Oscillator Module DC Electrical Specifications (VSSOSC= 0 VDC)
(TA = TL to TH)
Symbol
Description
Min.
Typ.
Max.
Unit
VBAT
Supply voltage
1.71
—
3.6
V
RF
Internal feedback resistor
—
—
—
—
100
2.5
15
—
—
—
—
MΩ
pF
pF
V
Cpara
Cload
Vpp
Parasitical capacitance of EXTAL32 and XTAL32
Internal load capacitance (programmable)
Peak-to-peak amplitude of oscillation
0.6
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
28
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.3.3.2 32kHz Oscillator Frequency Specifications
Table 16. 32kHz oscillator frequency specifications (VDD33OSC = VDD33OSC (min)
to VDD33OSC (max), TA = TL to TH)
Symbol Description
Min.
—
Typ.
32
Max.
—
Unit
kHz
ms
Notes
fosc_lo
tstart
Oscillator crystal
Crystal start-up time
—
1000
—
1, 2
1. This parameter is characterized before qualification rather than 100% tested.
2. Proper PC board layout procedures must be followed to achieve specifications.
6.4 Memories and memory interfaces
6.4.1 Flash (FTFL) Electrical Characteristics
This section describes the electrical characteristics of the FTFL module.
6.4.1.1 Flash Timing Parameters — Proram and Erase
The following characteristics represent the amunt of time the internal charge pumps are
active and do not include command ovrhead.
Table 17. NVM gram/erase timing characteristics
Symbol Description
Min.
Typ.
Max.
Unit
Notes
thvpgm4
thversscr
thversblk
Longword Prograoltage me
—
20
TBD
μs
Sector Erase highge time
Erase Block high-voltatime
—
—
20
100
800
ms
ms
1
1
160
1. Maximum time based on expectations at cycling end-of-life.
6.4.1.2 Flash Timing Parameters — Commands
Table 18. Flash command timing characteristics
Symbol Description
Min.
Typ.
Max.
Unit
Notes
trd1blk
Read 1s Block execution time
—
—
1.4
ms
trd1sec2k
Read 1s Section execution time (2 KB flash sec‐
tor)
—
—
40
μs
tpgmchk
Program Check execution time
—
—
35
μs
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
Freescale Semiconductor, Inc.
29
Peripheral operating requirements and behaviors
Table 18. Flash command timing characteristics (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
trdrsrc
tpgm4
tersblk
tersscr
Read Resource execution time
—
—
35
μs
1
Program Longword execution time
Erase Flash Block execution time
Erase Flash Sector execution time
—
—
—
—
50
160
20
TBD
800
100
TBD
μs
ms
ms
ms
2
2
tpgmsec2k Program Section execution time (2 KB flash sec‐
tor)
TBD
trd1all
Read 1s All Blocks execution time
Read Once execution time
—
—
—
—
—
—
—
—
—
2.8
35
ms
s
trdonce
1
tpgmonce Program Once execution time
50
TB
1600
μ
tersall
tvfykey
Erase All Blocks execution time
320
—
ms
μs
2
1
Verify Backdoor Access Key execution time
Program Partition for EEPROM execution time
tpgmpart
175
D
BD
TBD
ms
ms
tsetram32k Set FlexRAM Function execution time for 32 KB
of EEPROM backup
tsetram256k Set FlexRAM Function execution time for 256
KB of EEPROM backup
BD
TBD
ms
Byte-write to FlexRAM r EEOM operation
teewr8bers Byte-write to erased FlexRAM location execun
time
—
—
—
—
—
100
TBD
TBD
TBD
TBD
TBD
TBD
1.5
μs
ms
ms
ms
ms
3
teewr8b32k Byte-write to FlexRAM execution time (32 K
EEPROM backup)
teewr8b64k Byte-write to FlexRAM executn ti(64 B
EEPROM backup)
teewr8b128k Byte-write to Flexcution me (128 KB
EEPROM backu
TBD
2.5
teewr8b256k Byte-write to FlexRAexecution time (256 KB
EEPROM backup)
Word-write to FlexRAM for EEPROM operation
teewr16bers Word-write to erased FlexRAM location execu‐
tion time
—
—
—
—
—
100
TBD
TBD
TBD
TBD
TBD
TBD
1.5
μs
ms
ms
ms
ms
teewr16b32k Word-write to FlexRAM execution time (32 KB
EEPROM backup)
teewr16b64k Word-write to FlexRAM execution time (64 KB
EEPROM backup)
teewr16b128k Word-write to FlexRAM execution time (128 KB
EEPROM backup)
TBD
2.5
teewr16b256k Word-write to FlexRAM execution time (256 KB
EEPROM backup)
Longword-write to FlexRAM for EEPROM operation
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
30
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 18. Flash command timing characteristics (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
teewr32bers Longword-write to erased FlexRAM location exe‐
cution time
—
200
TBD
μs
teewr16b32k Longword-write to FlexRAM execution time (32
KB EEPROM backup)
—
—
—
—
TBD
TBD
TBD
TBD
TBD
2.7
ms
ms
ms
s
teewr16b64k Longword-write to FlexRAM execution time (64
KB EEPROM backup)
teewr32b128k Longword-write to FlexRAM execution time (128
KB EEPROM backup)
TBD
3.7
teewr32b256k Longword-write to FlexRAM execution time (256
KB EEPROM backup)
1. Assumes 25MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte use eraed.
6.4.1.3 Flash (FTFL) Current and Power Paramters
Table 19. Flash (FTFL) current and oweparameters
Symbol
Description
Typ.
Unit
mA
IDD_PGM
Worst case programming current in program fla
10
6.4.1.4 Reliability Characteristics
Table 20. VM reliability characteristics
Typ.1
Symbol Description
Min.
Program Flash
Max.
Unit
Notes
tnvmretp10k Data retention after to 10 K cycles
tnvmretp1k Data retention after up to 1 K cycles
tnvmretp100 Data retention after up to 100 cycles
nnvmcycp Cycling endurance
5
10
TBD
TBD
TBD
TBD
—
—
—
—
years
years
years
cycles
2
2
2
3
15
10 K
Data Flash
tnvmretd10k Data retention after up to 10 K cycles
tnvmretd1k Data retention after up to 1 K cycles
tnvmretd100 Data retention after up to 100 cycles
nnvmcycd Cycling endurance
5
TBD
TBD
TBD
TBD
—
—
—
—
years
years
years
cycles
2
2
2
3
10
15
10 K
FlexRAM as EEPROM
tnvmretee100 Data retention up to 100% of write endurance
5
TBD
—
years
2
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
Freescale Semiconductor, Inc.
31
Peripheral operating requirements and behaviors
Table 20. NVM reliability characteristics (continued)
Typ.1
Symbol Description
Min.
10
Max.
—
Unit
years
years
writes
Notes
tnvmretee10 Data retention up to 10% of write endurance
tnvmretee1 Data retention up to 1% of write endurance
TBD
2
2
4
15
TBD
TBD
—
nnvmwree16 Write endurance with an EEPROM backup to
FlexRAM ratio of 16
35 K
—
nnvmwree128 Write endurance with an EEPROM backup to
FlexRAM ratio of 128
315 K
1.27 M
10 M
TBD
TBD
TBD
TBD
—
—
—
—
writes
writes
wes
write
4
4
4
4
nnvmwree512 Write endurance with an EEPROM backup to
FlexRAM ratio of 512
nnvmwree4k Write endurance with an EEPROM backup to
FlexRAM ratio of 4096
nnvmwree32k Write endurance with an EEPROM backup to
FlexRAM ratio of 32,768
80 M
1. Typical data retention values are based on intrinsic capability of the technology measurhigh temperature derated to
25°C. For additional information on how Freescale defines typical data retentin, ease er to Engineering Bulletin
EB618.
2. Data retention is based on Tjavg = 55°C (temperature profile over the lifetime the application).
3. Cycling endurance represents number of program/erase cycles at -40°C Tj ≤ 15°C
4. Write endurance represents the number of writes to FlexRAM at -≤Tj 125°C influenced by the cycling endurance of
the FlexNVM (same value as data flash) and the allocated EEPROM bkup per subsystem. Minimum value assumes all
byte-writes to FlexRAM.
6.4.1.5 Write Endurance to FlexRAM for EEPROM
When the FlexNVM partition code not set to full data flash, the EEPROM data set size
can be set to any of several non-zevaues.
The bytes not assigned tata ash via the FlexNVM partition code are used by the
FTFL to obtain an efendurance increase for the EEPROM data. The built-in
EEPROM record manament system raises the number of program/erase cycles that can
be attained prior to device wear-out by cycling the EEPROM data through a larger
EEPROM NVM storage space.
While different partitions of the FlexNVM are available, the intention is that a single
choice for the FlexNVM partition code and EEPROM data set size are used throughout
the entire lifetime of a given application. The EEPROM endurance equation and graph
shown below assume that only one configuration is ever used.
EEPROM – 2 × EEESPLIT × EEESIZE
Writes_subsystem =
× Write_efficiency × nnvmcycd
EEESPLIT × EEESIZE
where
• Writes_subsystem — minimum writes to FlexRAM for subsystem (each subsystem
can have different endurance)
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
32
Freescale Semiconductor, Inc.
Preliminary
Peripheral operating requirements and behaviors
• EEPROM — allocated FlexNVM for each EEPROM subsystem based on DEPART;
entered with Program Partition command
• EEESPLIT — FlexRAM split factor for subsystem; entered with the Program
Partition command
• EEESIZE — total allocated FlexRAM based on DEPART; entered with Program
Partition command
• Write_efficiency —
• 0.25 for 8-bit writes to FlexRAM
• 0.50 for 16-bit or 32-bit writes to FlexRAM
• nnvmcycd — data flash cycling endurance
Figure 9. EEPROM backup writes to FlexRAM
6.4.2 EzPort Switching Specifications
Table 21. EzPort switching specifications
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
Freescale Semiconductor, Inc.
33
Peripheral operating requirements and behaviors
Table 21. EzPort switching specifications (continued)
Num
Description
Min.
Max.
Unit
EP1
EZP_CK frequency of operation (all commands except
READ)
—
fSYS/2
MHz
EP1a
EP2
EP3
EP4
EP5
EP6
EP7
EP8
EP9
EZP_CK frequency of operation (READ command)
EZP_CS negation to next EZP_CS assertion
EZP_CS input valid to EZP_CK high (setup)
EZP_CK high to EZP_CS input invalid (hold)
EZP_D input valid to EZP_CK high (setup)
EZP_CK high to EZP_D input invalid (hold)
EZP_CK low to EZP_Q output valid (setup)
EZP_CK low to EZP_Q output invalid (hold)
EZP_CS negation to EZP_Q tri-state
—
fSYS/8
—
MHz
ns
2 x tEZP_CK
5
5
—
ns
—
ns
2
—
ns
5
—
ns
—
0
12
—
ns
ns
—
12
ns
EZP_CK
EP3
EP4
2
EZP_CS
EP9
EP7
P8
EZP_Q (output)
EZP_D (input)
EP5
EP
Figure 10. EzPort Timing Diagram
6.4.3 Flexbus Switching Specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in
respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be
the same as the internal system bus frequency or an integer divider of that frequency.
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
34
Freescale Semiconductor, Inc.
Preliminary
Peripheral operating requirements and behaviors
The following timing numbers indicate when data is latched or driven onto the external
bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be
derived from these values.
Table 22. Flexbus switching specifications
Num
Description
Min.
2.7
—
Max.
3.6
50
Unit
V
Notes
Operating voltage
Frequency of operation
Clock period
Mhz
ns
FB1
FB2
FB3
FB4
FB5
20
—
Address, data, and control output valid
Address, data, and control output hold
Data and FB_TA input setup
Data and FB_TA input hold
TBD
0
11.5
—
1
1
2
2
ns
8.5
0.5
—
ns
ns
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FBT, FB_TSIZ[1:0], and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
FB1
FB_CLK
FB5
B3
FB_A[Y]
Adss
FB4
FB2
FB_D[X]
FB_RW
Address
Data
FB_TS
AA=1
AA=0
FB_CSn
FB_OEn
FB_BE/BWEn
FB_TA
FB4
FB5
AA=1
AA=0
FB_TSIZ[1:0]
TSIZ
Figure 11. FlexBus read timing diagram
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
Freescale Semiconductor, Inc.
35
Peripheral operating requirements and behaviors
FB1
FB_CLK
FB3
FB_A[Y]
Address
FB2
FB_D[X]
Address
Data
FB_RW
FB_TS
AA=1
AA=0
FB_CSn
FB_OEn
FB_BE/BWEn
FB_TA
FB4
FB5
AA=1
AA
FB_TSIZ[1:0]
TSI
Figur12. FlexBus write timing diagram
6.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
6.6 Analog
6.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 23 and Table 24 are achievable on the
differential pins (ADCx_DP0, ADCx_DM0, ADC, ADCx_DP1, ADCx_DM1,
ADCx_DP3, and ADCx_DP3). The ADCx_DP2 and ADCx_DM2 ADC inputs are used
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
36
Freescale Semiconductor, Inc.
Preliminary
Peripheral operating requirements and behaviors
as the PGA inputs and are not direct device pins. Accuracy specifications for these pins
are defined in Table 25 and Table 26. All other ADC channels meet the 13-bit
differential/12-bit single-ended accuracy specifications.
6.6.1.1 16-bit ADC operating conditions
Table 23. 16-bit ADC operating conditions
Typ.1
Symbol Description
Conditions
Absolute
Min.
1.71
-100
Max.
3.6
Unit
V
Notes
VDDA
Supply voltage
Supply voltage
—
ΔVDDA
Delta to VDD (VDD
-
0
+100
mV
2
2
VDDA
)
ΔVSSA
Ground voltage
Delta to VSS (VSS
-
-100
0
+100
mV
VSSA
)
VREFH
ADC reference
voltage high
1.13
VSSA
VREFL
VDDA
VSSA
—
VDDA
V
V
VREFL
Reference volt‐
age low
VA
VADIN
CADIN
Input voltage
VREFH
V
Input capaci‐
tance
• 16 bit modes
—
4
10
5
pF
• 8/10/12 bit
modes
RADIN
Input resistance
2
5
kΩ
Tantinuon the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
Freescale Semiconductor, Inc.
37
Peripheral operating requirements and behaviors
Table 23. 16-bit ADC operating conditions (continued)
Typ.1
Symbol Description
Conditions
Min.
Max.
Unit
Notes
RAS
Analog source
resistance
16 bit modes
External to MCU
• fADCK > 8MHz
—
—
—
—
—
—
0.5
1
kΩ
kΩ
kΩ
Assumes
ADLSMP=0
• fADCK = 4–8MHz
• fADCK < 4MHz
2
13/12 bit modes
• fADCK > 16MHz
• fADCK > 8MHz
• fADCK = 4–8MHz
• fADCK < 4MHz
—
—
—
—
—
—
—
—
0.5
1
kΩ
kΩ
kΩ
kΩ
2
5
11/10 bit modes
• fADCK > 8MHz
• fADCK = 4–8MHz
• fADCK < 4MHz
—
—
—
—
—
—
2
5
kΩ
kΩ
kΩ
10
9/8 bit modes
—
—
—
—
5
kΩ
kΩ
• fADCK > 8MHz
• fADCK < 8MHz
10
fADCK
ADC conversion ADLPC=0, ADHSC=
clock frequency
• 16 bit modes
1.0
1.0
—
—
TBD
TBD
MHz
MHz
• ≤13 bit m
ADLPC=ADHSC=0
6 bit des
1.0
1.0
—
—
8.0
MHz
MHz
≤13 bit modes
12.0
ADLPC=1, ADHSC=1
• 16 bit modes
1.0
1.0
—
—
5.0
8.0
MHz
MHz
• ≤13 bit modes
ADLPC=1, ADHSC=0
• 16 bit modes
1.0
1.0
—
—
2.5
5.0
MHz
MHz
• ≤13 bit modes
1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. DC potential difference.
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
38
Freescale Semiconductor, Inc.
Preliminary
Peripheral operating requirements and behaviors
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
Pad
ZAS
leakage
due to
input
CIRCUIT
ADC SAR
ENGINE
RAS
RADIN
protection
VADIN
CAS
VAS
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
RADIN
RADIN
CADIN
Figure 13. ADC input impedance euivalency diagram
6.6.1.2 16-bit ADC electrical characteristics
Table 24. 16-bit ADC characterstics (VREFH = VDDA, VREFL = VSSA
)
Conditions1
• ADC=1, AHSC=0
Typ.2
215
340
470
610
Symbol Description
Min.
—
Max.
—
Unit
Notes
IDDA
Supply current
μA
μA
μA
μA
ADLSMP=
0
DLP1, ADHSC=1
ADLPC=0, ADHSC=0
ADLPC=0, ADHSC=1
—
—
ADCO=1
—
—
—
—
Supply current
• Stop, reset, module off
• ADLPC=1, ADHSC=0
• ADLPC=1, ADHSC=1
• ADLPC=0, ADHSC=0
• ADLPC=0, ADHSC=1
—
0.01
2.4
4.0
5.2
6.2
0.8
μA
ADC asynchro‐
nous clock
source
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
tADACK = 1/
fADACK
MHz
MHz
MHz
MHz
fADACK
Sample Time
See Reference Manual chapter for sample times
Conversion Time See Reference Manual chapter for conversion times
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
Freescale Semiconductor, Inc.
39
Peripheral operating requirements and behaviors
Table 24. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Conditions1
• 16 bit differential
Typ.2
14.0
13.0
1.5
Symbol Description
Min.
—
Max.
TBD
TBD
TBD
TBD
TBD
TBD
1.0
Unit
Notes
LSB3
TUE
DNL
INL
Total unadjusted
error
Max hard‐
ware aver‐
aging
(AVGE =
%1, AVGS
= %11)
• 16 bit single-ended
• 13 bit differential
• 12 bit single-ended
• 11 bit differential
• 10 bit single-ended
• 9 bit differential
—
—
—
TBD
0.8
—
—
TBD
0.5
—
• 8 bit single-ended
—
0.5
1.0
LS
LSB3
LSB3
Differential non-
linearity
• 16 bit differential
• 16 bit single-ended
• 13 bit differential
• 12 bit single-ended
• 11 bit differential
• 10 bit single-ended
• 9 bit differential
—
—
—
—
—
—
—
—
2.5
2.5
0.7
0.7
0.5
TD
0.2
0.2
TB
TBD
D
D
TBD
TBD
0.5
Max hard‐
ware aver‐
aging
(AVGE =
%1, AVGS
= %11)
• 8 bit single-ended
0.5
Integral non-line‐
arity
• 16 bit differential
• 16 bit single-ded
• 13 bit differential
• 12 bit singed
• 11 bit diffntial
• 10 single-ended
bit difrential
—
—
—
—
—
—
—
—
-6 to +2.5
-2 to +12
1.0
—
Max aver‐
aging
—
TBD
TBD
TBD
TBD
0.5
1.0
0.5
0.5
0.3
8 bit single-ended
0.3
0.5
EZS
Zero-scale error
• 6 bit differential
• 16 bit single-ended
• 13 bit differential
• 12 bit single-ended
• 11 bit differential
• 10 bit single-ended
• 9 bit differential
—
—
—
—
—
—
—
—
4.0
4.0
0.7
0.7
0.4
0.4
0.2
0.2
—
VADIN
=
VSSA
—
TBD
TBD
TBD
TBD
0.5
• 8 bit single-ended
0.5
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
40
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 24. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Conditions1
• 16 bit differential
Typ.2
0 to +10
0 to +14
1.0
Symbol Description
Min.
—
Max.
—
Unit
Notes
LSB3
EFS
Full-scale error
VADIN
=
VDDA
• 16 bit single-ended
• 13 bit differential
• 12 bit single-ended
• 11 bit differential
• 10 bit single-ended
• 9 bit differential
—
—
—
TBD
TBD
TBD
TBD
0.5
—
TBD
0.4
—
—
0.4
—
0.2
• 8 bit single-ended
—
0.2
0.5
LS
EQ
Quantization er‐
ror
• 16 bit modes
• ≤13 bit modes
—
—
-1 to 0
—
—
0.5
ENOB
Effective number 16 bit differential mode
4
of bits
• Avg=32
TBD
TBD
TBD
TD
D
1.
BD
14.
BD
13.2
BD
TBD
TBD
TBD
TBD
bits
bits
bits
bits
bits
• Avg=16
• Avg=8
• Avg=4
• Avg=1
16 bit single-ended mode
• Avg=32
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
bits
bits
bits
bits
bits
• Avg=16
• Avg=8
• Avg4
Avg=
Signal-to-noise
plus distortion
ENOB
SINAD
THD
6.02 × ENOB + 1.76
dB
Total harmonic
distortion
16 bit differential mode
• Avg=32
4
4
—
—
-94
TBD
TBD
dB
dB
16 bit single-ended mode
• Avg=32
TBD
SFDR
Spurious free dy‐ 16 bit differential mode
namic range
• Avg=32
TBD
TBD
95
—
—
dB
dB
16 bit single-ended mode
• Avg=32
TBD
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
Freescale Semiconductor, Inc.
41
Peripheral operating requirements and behaviors
Table 24. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Conditions1
Typ.2
Symbol Description
Min.
Max.
Unit
Notes
EIL
Input leakage er‐
ror
IIn × RAS
mV
IIn = leak‐
age cur‐
rent
(refer to
the MCU's
voltage
and cur‐
rent oper‐
ating rat‐
ings)
Temp sensor
slope
• –40°C to 25°C
• 25°C to 105°C
—
—
TBD
TBD
—
—
m°C
mV/
VTEMP25 Temp sensor
voltage
25°C
—
TBD
—
mV
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 2.0 MHz unlestherwistated. Typical values are for
reference only and are not tested in production.
1 LSB = (VREFH - VREFL)/2N
3.
4. Input data is 1 kHz sine wave.
6.6.1.3 16-bit ADC with PGA operating conditions
Table 25. 16-bit ADC with GA operating conditions
Typ.1
Symbol Description
VDDA Supply voltage
VREFPGA PGA ref voltage
Conditions
Min.
Max.
Unit
V
Notes
Absolute
1.71
—
3.6
VREFOUT VREFOUT VREFOUT
V
2, 3
VADIN
RPGA
Input voltage
VSSA
—
VDDA
V
Input impedance G= 1, 2, 4, 8
Gain = 16, 32
TBD
TBD
TBD
TBD
TBD
TBD
—
64
32
TBD
TBD
TBD
TBD
TBD
TBD
—
kΩ
Gain = 64
16
RPGAD
Differntial input
impedance
Gain = 1, 2, 4, 8
Gain = 16, 32
Gain = 64
128
64
kΩ
IN+ to IN-
32
RAS
TS
Analog source
resistance
Gain = 16, 32
100
Ω
4
5
ADC sampling
time
Gain = 64
1.25
—
—
µs
1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 6 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. ADC must be configured to use the internal voltage reference (VREFOUT)
3. PGA reference connected to the VREFOUT pin. If the user wishes to drive VREFOUT with a voltage other than the output
of the VREF module, the VREF module must be disabled.
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
42
Freescale Semiconductor, Inc.
Preliminary
Peripheral operating requirements and behaviors
4. The analog source resistance (RAS), external to MCU, should be kept as minimum as possible. Increased RAS causes drop
in PGA gain without affecting other performances. This is not dependent on ADC clock frequency.
5. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs
time should be allowed for Fin=4 kHz at 16-bit differential mode. Recommended ADC setting is: ADLSMP=1, ADLSTS=2 at
8 MHz ADC clock. The ADLSTS bits can be adjusted for different ADC clock frequency
6.6.1.4 16-bit ADC with PGA characteristics
Table 26. 16-bit ADC with PGA characteristics
Typ.1
Symbol
Description
Conditions
Min.
TBD
—
Max.
TBD
TBD
Unit
μA
Notes
IDDA_PGA Supply current
590
ILKG
G
Leakage current
Gain2
PGA disabled
< 1
A
• PGAG=0
• PGAG=1
• PGAG=2
• PGAG=3
• PGAG=4
• PGAG=5
• PGAG=6
TBD
TBD
TBD
TBD
TBD
TBD
T
1
TBD
D
D
TBD
TBD
TBD
dB
dB
dB
dB
dB
dB
dB
R
AS < 100Ω
2
3.9
T
BD
29
BD
GA
Gain error
—
—
0.5
dB
RAS < 100Ω
BW
Input signal band‐
width
• 16-bit modes
• < 16-bit mod
—
—
—
—
4
kHz
kHz
dB
40
—
PSRR
CMRR
Power supply re‐ Gain=1
jection ration
TBD
TBD
VDDA= 3V
100mV,
fVDDA= 50Hz,
60Hz
Common mode
rejection ratio
Gain
TBD
TBD
TBD
TBD
—
—
dB
dB
VCM=
500mVpp,
fVCM= 50Hz,
100Hz
• Gain=64
VOFS
TGSW
dG/dT
Input offset volt‐
age
—
—
0.2
TBD
10
mV
µs
Gain=1, ADC
Averaging=32
Gain switching
settling time
TBD
3
Gain drift over
temperature
• Gain=1
• Gain=64
—
—
—
TBD
TBD
TBD
TBD
TBD
TBD
ppm/°C
ppm/°C
0 to 50°C
dVOFS/dT Offset drift over
temperature
Gain=1
ppm/°C 0 to 50°C, ADC
Averaging=32
dG/dVDDA Gain drift over
supply voltage
• Gain=1
• Gain=64
—
—
TBD
TBD
TBD
TBD
%/V
%/V
VDDA from 1.71
to 3.6V
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
Freescale Semiconductor, Inc.
43
Peripheral operating requirements and behaviors
Table 26. 16-bit ADC with PGA characteristics (continued)
Typ.1
Symbol
Description
Conditions
Min.
Max.
Unit
Notes
EIL
Input leakage er‐ All modes
ror
IIn × RAS
mV
IIn = leakage
current
(refer to the
MCU's voltage
and current op‐
erating ratings)
VPP,DIFF
Maximum differ‐
ential input signal
swing
[(VREFPGA × 2.33) - 0.2] / (2 ×
Gain)
V
4
SNR
THD
Signal-to-noise
ratio
• Gain=1
• Gain=64
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
D
TBD
TBD
TBD
TBD
TBD
TBD
TBD
8.3
57.7
87.3
85.3
92.42
2.54
13
12.7
8.4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
dB
dB
Average=32
Total harmonic
distortion
• Gain=1
• Gain=64
dB
Average=32,
fin=100Hz
dB
SFDR
ENOB
Spurious free dy‐
namic range
• Gain=1
• Gain=64
dB
Average=32,
fin=100Hz
dB
Effective number
of bits
• Gain=1, Average=4
• Gain=1, Average=8
• Gain=64, Average=4
• Gain=64, Average=8
• Gain=1, Average=2
• Gain=2, Avere=32
• Gain=4, Average=
• Gain=8rage=32
• Gan=16, age=32
Gai32, Average=32
Gain=64, Average=32
bits
bits
bits
bits
bits
bits
bits
bits
bits
bits
bits
8.7
13.4
13.1
12.6
11.8
11.1
10.2
9.3
SINAD
Signal-to-noise
plus distortion ra‐
tio
SENOB
6.02 × ENOB + 1.76
dB
1. Typical values assume VDDA =3.0V, Temp=25°C, fADCK=6MHz unless otherwise stated.
2.
Gain = 2PGAGx
3. When the PGA gain is changed, it takes some time to settle the output for the ADC to work properly. During a gain
switching, a few ADC outputs should be discarded (minimum two data samples, may be more depending on ADC
sampling rate and time of the switching).
4. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the
PGA reference voltage and gain setting.
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
44
Freescale Semiconductor, Inc.
Preliminary
Peripheral operating requirements and behaviors
6.6.2 CMP and 6-bit DAC electrical specifications
Table 27. Comparator and 6-bit DAC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDDHS
Supply current, High-speed mode (EN=1, PMODE=1,
—
—
200
μA
VDDA >= VLVI_trip
)
IDDLS
IDDOFF
VAIN
VAIO
VH
Supply current, low-speed mode (EN=1, PMODE=0)
Supply current, OFF Mode (EN=0,)
Analog input voltage
—
—
—
—
—
—
20
100
VD
μA
nA
V
VSS – 0.3
—
Analog input offset voltage
mV
Analog comparator hysteresis
• HYSTCTR = 00
—
—
—
—
5
—
—
—
—
mV
mV
mV
mV
• HYSTCTR = 01
20
30
• HYSTCTR = 10
• HYSTCTR = 11
VCMPOh
VCMPOl
tDHS
Output high
Output low
VDD – 5
—
—
50
—
0.5
120
V
V
Propagation delay, high-speed mode (EN=1,
PMODE=1)
20
ns
tDLS
Propagation delay, low-speed mode (EN1,
PMODE=1)
120
250
420
ns
Analog comparator initialization
6-bit DAC current adder (enbled)
6-bit DAC integraneari
6-bit DAC differeon-linearity
—
—
—
—
—
—
TBD
8
ns
IDAC6b
INL
μA
LSB1
LSB
–0.5
–0.3
0.5
0.3
DNL
1. 1 LSB = Vreference/64
6.6.3 12-bit DAC electrical characteristics
6.6.3.1 12-bit DAC operating requirements
Table 28. 12-bit DAC operating requirements
Symbol
Desciption
Min.
Max.
Unit
Notes
VDDA
Supply voltage
1.71
3.6
V
VDACR
TA
Reference voltage
Temperature
1.15
−40
3.6
V
1
105
°C
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
Freescale Semiconductor, Inc.
45
Peripheral operating requirements and behaviors
Table 28. 12-bit DAC operating requirements (continued)
Symbol
Desciption
Min.
Max.
Unit
Notes
CL
Output load capacitance
—
100
pF
2
IL
Output load current
—
1
mA
1. The DAC reference can be selected to be VDDA or the voltage output of the VREF module (VREFO)
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC
6.6.3.2 12-bit DAC operating behaviors
Table 29. 12-bit DAC operating behaviors
Symbol Description
Resolution
Min.
12
Typ.
—
Max.
12
Uit
b
Notes
n
IDDA_DACLP Supply current — low-power mode
—
—
150
μA
IDDA_DACH Supply current — high-speed mode
—
—
μA
P
tDACLP
Full-scale settling time (0x080 to 0xF7F) — low-
power mode
—
—
1
00
15
200
30
μs
μs
1
1
1
1
tDACHP
Full-scale settling time (0x080 to 0xF7F) — high-
power mode
tCCDACLP Code-to-code settling time (0xBF8 to 0xC08) —
low-power mode
—
5
μs
tCCDACHP Code-to-code settling time (0xBF8 to 0C08)
high-speed mode
TBD
100
—
—
μs
Vdacoutl
DAC output voltage range low — hipeed
mode, no load, DAC set to 0x000
0
—
mV
mV
Vdacouth DAC output voltage range hig— hi-seed
mode, no load, DAC t to 0FF
VDACR
−100
VDACR
INL
DNL
DNL
Integral non-line— high speed mode
Differential non-lineerror — VDACR > 2 V
3
—
—
—
8
1
1
LSB
LSB
LSB
2
3
4
0.5
0.5
Differential non-linearity rror — VDACR = VRE‐
FO (1.15 V)
VOFFSET Offset error
0.4
0.1
60
—
—
—
0.8
0.6
90
—
%FSR
%FSR
dB
5
5
EG
PSRR
TCO
Gain error
Power supply rejection ratio, VDDA > = 2.4 V
Temperature coefficient offset voltage
Temperature coefficient gain error
TBD
TBD
μV/C
TGE
—
—
ppm of
FSR/C
AC
Offset aging coefficient
—
—
—
—
TBD
250
μV/yr
Ω
Rop
Output resistance load = 3 kΩ
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
46
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 29. 12-bit DAC operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
SR
Slew rate -80h→ F7Fh→ 80h
• High power (SPHP
• Low power (SPLP
V/μs
)
1.2
1.7
—
—
0.05
0.12
)
CT
Channel to channel cross talk
3dB bandwidth
—
—
-80
dB
BW
kHz
• High power (SPHP
• Low power (SPLP
)
550
40
—
—
—
—
)
1. Settling within 1 LSB
2. The INL is measured for 0+100mV to VDACR−100 mV
3. The DNL is measured for 0+100 mV to VDACR−100 mV
4. The DNL is measured for 0+100mV to VDACR−100 mV with VDDA > 2.4V
5. Calculated by a best fit curve from VSS+100 mV to VREF−100 mV
Figure 14. Typical INL error vs. digital code
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
Freescale Semiconductor, Inc.
47
Peripheral operating requirements and behaviors
Figure 15. Offset half scale vs. temperature
6.6.4 Voltage RefeencElectrical Specifications
Tabl0. VREF full-range operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
VDDA
Supply voltage
1.71
3.6
V
TA
CL
Temperature
−40
—
105
100
°C
nF
Output load capacitance
Table 31. VREF full-range operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Vout
Vout
Vdrift
Voltage reference output with factory trim
TBD
1.2
TBD
V
V
Voltage reference output without factory trim
1.15
—
—
—
1.24
7
Temperature drift (Vmax -Vmin across the full
temperature range)
mV
See Fig‐
ure 16
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
48
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 31. VREF full-range operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Tc
Ac
Ioff
Temperature coefficient
—
—
TBD
ppm/°C
Aging coefficient
—
—
—
—
TBD
0.10
ppm/year
µA
Powered down current (off mode, VREFEN = 0,
VRSTEN = 0)
Ibg
Itr
Bandgap only (MODE_LV = 00) current
Tight-regulation buffer (MODE_LV =10) current
Load regulation (MODE_LV = 10) current
Buffer startup time
—
—
TBD
—
75
µA
mA
1.1
—
—
100
TBD
TBD
TBD
µV/mA
s
Tstup
DC
100
—
—
Line regulation (power supply rejection)
—
–60
—
dB
Table 32. VREF limited-range operating requients
Symbol
Description
Mi
Max.
Unit
Notes
Notes
TA
Temperature
0
50
°C
Table 33. VREF limited-ranopeating behaviors
Symbol
Description
Min.
Max.
Unit
Vout
Voltage reference output with factory m
TBD
TBD
µA
TBD
ure 16. Typical output vs.temperature
Figure 17. Typical output vs. VDD
TBD
6.7 Timers
See General Switching Specifications.
6.8 Communication interfaces
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
49
Preliminary
Peripheral operating requirements and behaviors
6.8.1 USB electrical specifications
The USB electricals for the USB On-the-Go module conform to the standards
documented by the Universal Serial Bus Implementers Forum. For the most up-to-date
standards, visit http://www.usb.org.
6.8.2 USB DCD Electrical Specifications
Table 34. USB DCD specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDP_SRC
USB_DP source voltage (up to 250 μA)
TBD
B
TBD
V
VLGC
Threshold voltage for logic high
USB_DP source current
USB_DM sink current
0.8
7
10
2.0
13
V
IDP_SRC
IDM_SINK
μA
μA
kΩ
V
50
100
—
150
24.8
0.4
RDM_DWN D- pulldown resistance for data pin contact detect
VDAT_REF Data detect voltage
14.2
5
TBD
6.8.3 USB Voltage Regulator Electrical Specifications
Table 35. USvoage regulator electrical specifications
Symbol Description
Min.
2.7
—
Typ.
—
Max.
5.5
Unit
V
Notes
VREGIN Input supply volt
IDDon
IDDstby
IDDoff
Quiescent current — n mode, load current
equal zero
120
—
μA
Quiescent current — Standby mode, load cur‐
rent equal zero
—
TBD
—
μA
Quiescent current — Shutdown mode
—
—
—
—
—
—
500
120
TBD
nA
mA
mA
ILOADrun Maximum load current — Run mode
ILOADstby Maximum load current — Standby mode
VReg33out Regulator output voltage — Input supply (VRE‐
GIN) > 3.6 V
1
• Run mode
3
3.3
TBD
—
3.6
TBD
3.6
V
V
V
• Standby mode
• Pass-through mode
TBD
2.3
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
50
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 35. USB voltage regulator electrical specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
COUT
ESR
External output capacitor
1.76
2.2
8.16
μF
External output capacitor equivalent series re‐
sistance
1
—
100
mΩ
ILIM
Current limitation threshold
185
290
395
mA
1. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad
.
6.8.4 DSPI Switching Specifications for Low-speed Operaton
The DMA Serial Peripheral Interface (DSPI) provides a synchronouserial bs with
master and slave operations. Many of the transfer attributes are programable. The tables
below provides DSPI timing characteristics for classic SPI timing des. Refer to the
DSPI chapter of the Reference Manual for information on the mofied transfer formats
used for communicating with slower peripheral devices.
Table 36. Master Mode DSPI Timing (ow-speed mode)
Num
Description
in.
1.71
Max.
3.6
Unit
V
Notes
Operating voltage
1
Frequency of operation
—
12.5
—
MHz
ns
DS1
DS2
DS3
DS4
DS5
DS6
DS7
DS8
DSPI_SCK output cycle time
4 x tBCLK
DSPI_SCK output high/low time
DSPI_PCSn to DSPI_SCK opulid
DSPI_SCK to DSPICSn tput hold
DSPI_SCK to UT valid
DSPI_SCK to DSPOUT invalid
DSPI_SIN to DSPI_SCinput setup
DSPI_SCK to DSPI_SIN input hold
(tSCK/2) - 4 (tSCK/2) + 4
ns
ns
ns
ns
ns
ns
ns
(tSCK/2) - 4
—
—
10
—
—
—
(tSCK/2) - 4
—
-2
15
0
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
51
Preliminary
Peripheral operating requirements and behaviors
DSPI_PCSn
DS1
DS3
DS2
DS4
DSPI_SCK
DS8
DS7
(CPOL=0)
Data
Last data
First data
DSPI_SIN
DS5
DS6
First data
Data
Last data
DSPI_SOUT
Figure 18. DSPI Classic SPI Timing — Master Mode
Table 37. Slave Mode DSPI Timing (Low-speed Mode)
Num
Description
Min.
1.7
Max.
3.6
Unit
V
Operating voltage
Frequency of operation
—
6.25
—
MHz
ns
DS9
DSPI_SCK input cycle time
8 x tBK
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSK/2) - 4
(tSCK/2) + 4
ns
ns
ns
ns
ns
ns
ns
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSIP_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOot driven
—
0
20
—
—
—
15
15
5
15
—
—
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DS12
DS16
DS11
First data
DS14
Last data
DSPI_SOUT
Data
Data
DS13
First data
Last data
DSPI_SIN
Figure 19. DSPI Classic SPI Timing — Slave Mode
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
52
Freescale Semiconductor, Inc.
Preliminary
Peripheral operating requirements and behaviors
6.8.5 DSPI Switching Specifications (High-speed mode)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provide DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 38. Master Mode DSPI Timing (High-speed mode)
Num
Description
Min.
2.7
Max.
3.6
Unit
V
Operating voltage
Frequency of operation
—
MHz
ns
DS1
DS2
DS3
DS4
DS5
DS6
DS7
DS8
DSPI_SCK output cycle time
2 x tBCLK
—
DSPI_SCK output high/low time
DSPI_PCSn to DSPI_SCK output valid
DSPI_SCK to DSPI_PCSn output hold
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
(tSCK/2) − 2
(tSK/2) + 2
ns
ns
ns
ns
ns
ns
ns
(tSCK/2) −
—
—
8.5
—
—
—
(tSCK− 2
—
−2
TBD
0
DSPI_PCSn
DS1
DS3
D
DS4
DSPI_SCK
(CPOL=0)
S8
Data
Last data
First data
DSPI_SIN
DS5
DS6
First data
Data
Last data
DSPI_SOUT
Figure 20. DSPI Classic SPI Timing — Master Mode
Table 39. Slave Mode DSPI Timing (High-speed mode)
Num
Description
Min.
Max.
3.6
Unit
V
Operating voltage
2.7
Frequency of operation
12.5
—
MHz
ns
DS9
DS10
DS11
DSPI_SCK input cycle time
DSPI_SCK input high/low time
DSPI_SCK to DSPI_SOUT valid
4 x tBCLK
(tSCK/2) − 2
—
(tSCK/2 + 2
TBD
ns
ns
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
Freescale Semiconductor, Inc.
53
Peripheral operating requirements and behaviors
Table 39. Slave Mode DSPI Timing (High-speed mode) (continued)
Num
DS12
DS13
DS14
DS15
DS16
Description
DSPI_SCK to DSPI_SOUT invalid
Min.
0
Max.
—
Unit
ns
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSIP_SIN input hold
2
—
ns
7
—
ns
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
—
—
14
ns
14
ns
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DS12
S16
DS11
First data
DS14
ast data
DSPI_SOUT
Data
Data
DS13
First data
Last data
DSPI_SIN
Figure 21. DSPI Classic SI Timing — Slave Mode
6.8.6 SDHC Specification
The following timing specs ardefined at the chip I/O pin and must be translated
appropriately to arrive ing pecs/constraints for the physical interface.
able 40. SDHC switching specifications
Num
Symbol
Descripon
Min.
Max.
Unit
Card input clock
SD1
fpp
fpp
fpp
fOD
tWL
tWH
tTLH
tTHL
Clock frequency (low speed)
Clock frequency (SD\SDIO full speed)
Clock frequency (MMC full speed)
Clock frequency (identification mode)
Clock low time
0
0
400
25
20
400
—
—
3
kHz
MHz
MHz
kHz
ns
0
0
SD2
SD3
SD4
SD5
7
Clock high time
7
ns
Clock rise time
—
—
ns
Clock fall time
3
ns
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
54
Freescale Semiconductor, Inc.
Preliminary
Peripheral operating requirements and behaviors
Table 40. SDHC switching specifications (continued)
Num
Symbol
Description
Min.
Max.
Unit
SD6
tOD
SDHC output delay (output valid)
-5
6.5
ns
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD7
SD8
tTHL
tTHL
SDHC input setup time
SDHC input hold time
5
0
—
—
ns
ns
SD3
SD6
SD2
SD1
SDHC_CLK
Output SDHC_CMD
Output SDHC_DAT[3:0]
Input SDHC_CMD
SD7
SD8
Input SDHC_DAT[3:0]
Figue 22. SDHC timing
I2S Switching Specifications
6.8.7
This section provides C timings for the I2S in master (clocks driven) and slave
modes (clocks input). Atimings are given for non-inverted serial clock polarity
(TCR[TSCKP] = 0, RCR[SCKP] = 0) and a non-inverted frame sync (TCR[TFSI] = 0,
RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all
the timings remain valid by inverting the clock signal (I2S_BCLK) and/or the frame sync
(I2S_FS) shown in the figures below.
I2S master mode timing
Table 41.
Num
Description
Min.
Max.
Unit
V
Operating voltage
I2S_MCLK cycle time
2.7
3.6
S1
S2
S3
S4
2 x tSYS
45%
ns
I2S_MCLK pulse width high/low
I2S_BCLK cycle time
55%
—
MCLK period
ns
5 x tSYS
45%
I2S_BCLK pulse width high/low
55%
BCLK period
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
Freescale Semiconductor, Inc.
55
Peripheral operating requirements and behaviors
I2S master mode timing (continued)
Table 41.
Num
S5
Description
Min.
Max.
15
—
Unit
ns
I2S_BCLK to I2S_FS output valid
I2S_BCLK to I2S_FS output invalid
I2S_BCLK to I2S_TXD valid
—
-2.5
—
S6
ns
S7
15
—
ns
S8
I2S_BCLK to I2S_TXD invalid
-3
ns
S9
I2S_RXD/I2S_FS input setup before I2S_BCLK
I2S_RXD/I2S_FS input hold after I2S_BCLK
20
0
—
ns
S10
—
ns
S1
S2
S2
I2S_MCLK (output)
I2S_BCLK (output)
I2S_FS (output)
I2S_FS (input)
I2S_TXD
S3
S4
S4
S5
S6
S10
S9
S8
S7
S8
S9
S10
I2S_RXD
Figure I2S timing — master mode
Tale 42.
I2S alave mode timing
Num
Description
Min.
Max.
3.6
Unit
V
Operating voltage
2.7
S11
S12
S13
S14
S15
S16
S17
S18
I2S_BCLK cycle time (input)
8 x tSYS
—
ns
I2S_BCLK pulse width high/low (input)
I2S_FS input setup before I2S_BCLK
I2S_FS input hold after I2S_BCLK
I2S_BCLK to I2S_TXD/I2S_FS output valid
I2S_BCLK to I2S_TXD/I2S_FS output invalid
I2S_RXD setup before I2S_BCLK
I2S_RXD hold after I2S_BCLK
45%
10
3
55%
—
MCLK period
ns
ns
ns
ns
ns
ns
—
—
0
20
—
10
2
—
—
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
56
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
S11
S12
I2S_BCLK (input)
I2S_FS (output)
I2S_FS (input)
I2S_TXD
S12
S15
S16
S13
S14
S15
S16
S15
S16
S17
S18
I2S_RXD
Figure 24. I2S timing — slave modes
6.9 Human-machine interfaces (HMI)
6.9.1 General Switching Specificatios
These general purpose specifications apply to all signals configured for GPIO, SCI,
FlexCAN, CMT, I2C, and IEEE 1588 imer signals.
Table 43. Generaswitching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse w(digital glitch filter disa‐
bled) — Synchroth
1.5
—
Bus clock
cycles
1
GPIO pin interre width (digital glitch filter disa‐
bled, analog filter bled) — Asynchronous path
100
16
—
—
ns
2
2
GPIO pin interrupt pulswidth (digital glitch filter disa‐
bled, analog filter disabled) — Asynchronous path
ns
External reset pulse width (digital glitch filter disabled)
TBD
2
—
—
Mode select (EZP_CS) hold time after reset deasser‐
tion
Bus clock
cycles
Port rise and fall time (high drive strength)
• Slew disabled
3
4
—
—
12
36
ns
ns
• Slew enabled
Port rise and fall time (low drive strength)
• Slew disabled
—
—
32
36
ns
ns
• Slew enabled
1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
Freescale Semiconductor, Inc.
57
Dimensions
3. 75pF load
4. 15pF load
6.9.2 TSI Electrical Specifications
Table 44. Touch Sensing Input module specifications
Symbol Description
VDDTSI Operating voltage
CELE
Min.
Typ.
Max.
Unit
Notes
1.71
—
3.6
V
Target electrode capacitance range
Reference oscillator frequency
1
20
5.5
0.5
1
500
TBD
T
BD
TBD
TBD
TBD
TBD
TBD
600
pF
Mz
MH
pF
1
fREFmax
fELEmax
CREF
—
Electrode oscillator frequency
—
Internal reference capacitor
TBD
TBD
TBD
TBD
—
VDELTA
IREF
Oscillator delta voltage
600
1
mV
μA
μA
%
Reference oscillator current source base current
Electrode oscillator current source base current
Electrode capacitance measurement precision
Electrode capacitance measurement precision
2
3
4
5
6
7
IELE
Pres5
Pres20
TBD
TBD
TBD
0.326
—
%
Pres100 Electrode capacitance measurement precision
—
%
Max‐
Max sensitivity @ 20pF electrode
.15
fF
Sens20
MaxSens Maximum sensitivity
0.006
—
0.326
—
24
16
fF
bits
μs
8
9
Res
Resolution
TCon20
Response time @ 20pF
—
30
—
ITSI_RUN Current added in e
ITSI_LP Low power mode t adder
—
TBD
1
—
μA
μA
—
TBD
1. The TSI module is functional with apacitance values outside of this range. However, optimal performance is not
guaranteed.
2. The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current
3. The programmable current source value is generated by multiplying the SCANC[EXTCHRG] value and the base current
4. Measured with a 5pF electrode, reference oscillator frequency of 10MHz, PS = 128, NCSC = 8; Iext = 16
5. Measured with a 20pF electrode, reference oscillator frequency of 10MHz, PS = 128, NCSC = 2; Iext = 16
6. Measured with a 20pF electrode, reference oscillator frequency of 10MHz, PS = 16, NCSC = 3; Iext = 16
7. 6.2ms scan time
8. 1pF electrode capacitance with 4.96ms scan time
9. Time that takes to do one complete measurement of the electrode. Sensitivity resolution of 0.0133pF
7 Dimensions
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
58
Freescale Semiconductor, Inc.
Preliminary
Pinout
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to www.freescale.com and perform a keyword search for
the drawing’s document number:
If you want the drawing for this package
144-pin LQFP
Then use this document number
98ASS23177W
98ASA00222D
144-pin MAPBGA
8 Pinout
8.1 K20 Signal Multiplexing and Pin Assignments
The following table shows the signals available on eacpin and the locations of these
pins on the devices supported by this document. ThPort Control Module is responsible
for selecting which ALT functionality is availabon each pin.
144
144
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
QFP BGA
—
—
—
—
—
1
C10 NC
B10 NC
A10 NC
L5
M5
D3
D2
D1
NC
NC
ADC1_SE4a
ADC1_SE5a
ADC1_SE6a
ADC1_SE4
ADC1_SE5a
ADC1_SE6a
E0
SPI1_PCS1
SPI1_SOUT
SPI1_SCK
UART1_TX
UART1_RX
SDHC0_D1
SDHC0_D0
I2C1_SDA
I2C1_SCL
2
P1
PTE2
3
UART1_CTS
_b
SDHC0_DCL
K
4
E4
ADC1_SE7a
ADC1_SE7a
PTE3
SPI1_SIN
UART1_RTS
_b
SDHC0_CMD
5
6
7
8
9
E5
F6
E3
E2
E1
VDD
VDD
VSS
VSS
DISABLED
DISABLED
DISABLED
PTE4
PTE5
PTE6
SPI1_PCS0
SPI1_PCS2
SPI1_PCS3
UART3_TX
UART3_RX
SDHC0_D3
SDHC0_D2
I2S0_MCLK
UART3_CTS
_b
I2S0_CLKIN
10
F4
DISABLED
PTE7
UART3_RTS
_b
I2S0_RXD
11
12
F3
F2
DISABLED
DISABLED
PTE8
PTE9
UART5_TX
UART5_RX
I2S0_RX_FS
I2S0_RX_BC
LK
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
Freescale Semiconductor, Inc.
59
Pinout
144
QFP BGA
144
Default
DISABLED
DISABLED
DISABLED
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
13
14
15
F1
G4
G3
PTE10
UART5_CTS
_b
I2S0_TXD
I2S0_TX_FS
PTE11
PTE12
UART5_RTS
_b
I2S0_TX_BC
LK
16
17
18
19
20
21
22
23
24
25
26
27
E6
F7
H3
H1
H2
G1
G2
J1
VDD
VDD
VSS
VSS
VSS
VSS
USB0_DP
USB0_DM
VOUT33
VREGIN
ADC0_DP1
ADC0_DM1
ADC1_DP1
ADC1_DM1
USB0_DP
USB0_DM
VOUT33
VREGIN
ADC0_DP1
ADC0_DM1
ADC1_DP1
ADC1_DM1
J2
K1
K2
L1
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DP/
ADC0_DP0/
ADC1_DP3
28
29
30
L2
M1
M2
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
PGA1_DM/
ADC1_DM0/
ADC0_DM
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
H5
G5
G6
H6
K3
J3
VDDA
VDDA
VREFH
VREFH
VREFL
VREFL
VSSA
VSSA
ADC1_SE16
ADC0_SE16
VREF_OUT
DAC0_OUT
DAC1_OUT
XTAL32
ADC1_SE16
ADC0_SE16
VREF_OUT
DAC0_OUT
DAC1_OUT
XTAL32
M3
L3
L4
M7
M6
L6
EXTAL32
VBAT
EXTAL32
VBAT
—
VDD
VDD
—
VSS
VSS
M4
ADC0_SE17
ADC0_SE17
PTE24
CAN1_TX
UART4_TX
EWM_OUT_b
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
60
Freescale Semiconductor, Inc.
Pinout
144
144
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
QFP BGA
46
47
K5
K4
ADC0_SE18
DISABLED
ADC0_SE18
PTE25
CAN1_RX
UART4_RX
EWM_IN
PTE26
UART4_CTS
_b
RTC_CLKOU USB_CLKIN
T
48
J4
DISABLED
PTE27
UART4_RTS
_b
49
50
H4
J5
DISABLED
PTE28
PTA0
JTAG_TCLK/ TSI0_CH1
SWD_CLK/
UART0_CTS
_b
FTM0_CH5
JTAG_TCLK/ EZP_CLK
SWD_CLK
EZP_CLK
51
52
J6
JTAG_TDI/
EZP_DI
TSI0_CH2
TSI0_CH3
PTA1
PTA2
UART0_RX
UART0_TX
FTM0_CH6
FTM0_CH7
JG_TDI
EZP_DI
K6
JTAG_TDO/
TRACE_SW
O/EZP_DO
JTADO/
TRACSW
O
EZP_DO
53
54
55
K7
L7
JTAG_TMS/
SWD_DIO
TSI0_CH4
TSI0_CH5
PTA3
PTA4
PTA5
UART0_RTS
_b
FTM0_CH0
FTM0_CH1
FTM0_CH2
JTAG_TMS/
SWD_DIO
NMI_b/
EZP_CS_b
NMI_b
EZP_CS_b
M8
JTAG_TRST
CM_OUT
I2S0_RX_BC JTAG_TRST
LK
56
57
58
E7
G7
J7
VDD
VDD
VSS
VSS
DISABLED
PTA6
M0_CH
TRACE_CLK
OUT
59
60
J8
ADC0_SE10
ADC0_SE11
ADC0_SE10
ADC0_SE11
PTA7
PTA8
TM0_CH4
FTM1_CH0
TRACE_D3
K8
FTM1_QD_P TRACE_D2
HA
61
62
63
64
65
66
L8
M9
L9
K9
J9
DISABLED
DISABLED
DISABLED
CMP2_IN0
CMP2_IN1
PTA9
FTM1_CH1
FTM2_CH0
FTM2_CH1
FTM1_CH0
FTM1_CH1
UART0_TX
UART0_RX
FTM1_QD_P TRACE_D1
HB
P11
PTA12
PTA13
PTA14
FTM2_QD_P TRACE_D0
HA
FTM2_QD_P
HB
CMP2_IN0
CMP2_IN1
CAN0_TX
CAN0_RX
SPI0_PCS0
I2S0_TXD
FTM1_QD_P
HA
I2S0_TX_FS
FTM1_QD_P
HB
L10 DISABLED
I2S0_TX_BC
LK
67
68
L11 DISABLED
K10 DISABLED
PTA15
PTA16
SPI0_SCK
I2S0_RXD
SPI0_SOUT
UART0_CTS
_b
I2S0_RX_FS
69
K11 ADC1_SE17
ADC1_SE17
PTA17
SPI0_SIN
UART0_RTS
_b
I2S0_MCLK
I2S0_CLKIN
70
71
72
E8
G8
VDD
VSS
VDD
VSS
M12 EXTAL
EXTAL
PTA18
FTM0_FLT2
FTM_CLKIN0
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
Freescale Semiconductor, Inc.
61
Pinout
144
144
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
QFP BGA
73
74
75
76
77
78
79
80
81
M11 XTAL
XTAL
PTA19
FTM1_FLT0
FTM_CLKIN1
LPT0_ALT1
L12 RESET_b
K12 DISABLED
J12 DISABLED
J11 DISABLED
J10 DISABLED
H12 DISABLED
H11 DISABLED
RESET_b
PTA24
PTA25
PTA26
PTA27
PTA28
PTA29
PTB0
FB_A29
FB_A28
FB_A27
FB_A26
FB_A25
FB_A24
H10 ADC0_SE8/
ADC1_SE8/
ADC0_SE8/
ADC1_SE8/
TSI0_CH0
I2C0_SCL
I2C0_SDA
FTM1_CH0
FTM1_CH1
FTM1_QD_P
HA
TSI0_CH0
82
H9
ADC0_SE9/
ADC1_SE9/
TSI0_CH6
ADC0_SE9/
ADC1_SE9/
TSI0_CH6
PTB1
FTM1D_P
B
83
84
G12 ADC0_SE12/ ADC0_SE12/ PTB2
TSI0_CH7 TSI0_CH7
I2C0_SCL
I2C0_SDA
UART0_RTS
_b
0_FLT3
FTM0_FLT0
G11 ADC0_SE13/ ADC0_SE13/ PTB3
UART0_CTS
_b
TSI0_CH8
TSI0_CH8
85
86
87
88
89
G10 ADC1_SE10
ADC1_SE10
ADC1_SE11
ADC1_SE12
ADC1_SE13
PTB4
PTB5
PTB6
PTB7
PTB8
FTM1_FLT0
FTM2_FLT0
G9
ADC1_SE11
F12 ADC1_SE12
F11 ADC1_SE13
F10 DISABLED
FB_AD23
FB_AD22
FB_AD21
UARTRTS
90
F9
DISABLED
PTB9
S1
UART3_CTS
_b
FB_AD20
91
92
93
94
95
96
97
E12 ADC1_SE14
E11 ADC1_SE15
ADC1_SE14
ADC1_SE
VSS
PTB10
SPI1_PCS0
PI1_SCK
UART3_RX
UART3_TX
FB_AD19
FB_AD18
FTM0_FLT1
FTM0_FLT2
H7
F5
VSS
VDD
VDD
E10 TSI0_CH9
E9 TSI0_CH10
TSI0_CH9
TSI0_CH10
TSI0_CH11
PTB16
PTB17
PTB18
SPI1_SOUT
SPI1_SIN
CAN0_TX
UART0_RX
UART0_TX
FTM2_CH0
FB_AD17
FB_AD16
FB_AD15
EWM_IN
EWM_OUT_b
D12 TSI0_CH11
D11 TSI0_CH12
D10 DISABLED
I2S0_TX_BC
LK
FTM2_QD_P
HA
98
TSI0_CH12
PTB19
CAN0_RX
FTM2_CH1
I2S0_TX_FS
FB_OE_b
FTM2_QD_P
HB
99
PTB20
PTB21
PTB22
PTB23
SPI2_PCS0
SPI2_SCK
SPI2_SOUT
SPI2_SIN
FB_AD31
FB_AD30
FB_AD29
FB_AD28
FB_AD14
CMP0_OUT
CMP1_OUT
CMP2_OUT
100
101
102
103
D9
DISABLED
C12 DISABLED
C11 DISABLED
SPI0_PCS5
B12 ADC0_SE14/ ADC0_SE14/ PTC0
TSI0_CH13 TSI0_CH13
SPI0_PCS4
PDB0_EXTR
G
I2S0_TXD
104
B11 ADC0_SE15/ ADC0_SE15/ PTC1
TSI0_CH14 TSI0_CH14
SPI0_PCS3
UART1_RTS
_b
FTM0_CH0
FB_AD13
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
62
Freescale Semiconductor, Inc.
Pinout
144
144
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
QFP BGA
105
A12 ADC0_SE4b/ ADC0_SE4b/ PTC2
SPI0_PCS2
UART1_CTS
_b
FTM0_CH1
FB_AD12
CMP1_IN0/
TSI0_CH15
CMP1_IN0/
TSI0_CH15
106
107
108
109
110
111
A11 CMP1_IN1
CMP1_IN1
VSS
PTC3
SPI0_PCS1
UART1_RX
FTM0_CH2
FB_CLKOUT
H8
—
VSS
VDD
VDD
A9
D8
C8
DISABLED
DISABLED
CMP0_IN0
PTC4
PTC5
PTC6
SPI0_PCS0
SPI0_SCK
SPI0_SOUT
UART1_TX
FTM0_CH3
LPT0_ALT2
FB_AD11
FB_AD10
FB_AD9
CMP1_OUT
CMP0_OUT
CMP0_IN0
CMP0_IN1
PDB0_EXTR
G
112
113
B8
A8
CMP0_IN1
PTC7
SPI0_SIN
FB_AD8
FB_AD7
ADC1_SE4b/ ADC1_SE4b/ PTC8
CMP0_IN2 CMP0_IN2
I2S0_MCLK
I2S0_CLKIN
114
115
D7
C7
ADC1_SE5b/ ADC1_SE5b/ PTC9
CMP0_IN3 CMP0_IN3
I2S0_RX_BC FB_AD6
LK
_FLT0
ADC1_SE6b/ ADC1_SE6b/ PTC10
I2C1_SCL
I2C1_SDA
I2S0_RX_FS
FB_AD
CMP0_IN4
ADC1_SE7b
DISABLED
CMP0_IN4
116
117
B7
A7
ADC1_SE7b
PTC11
PTC12
I2S0_R
FBW_b
FB_AD27
UART4_RTS
_b
118
D6
DISABLED
PTC13
UART4_TS
_b
FB_AD26
119
120
121
122
123
C6
B6
—
DISABLED
DISABLED
VSS
PTC14
PTC15
UA4_RX
UART4_X
FB_AD25
FB_AD24
VSS
VDD
—
VDD
A6
DISABLED
PTC16
17
PTC18
CAN1_RX
CAN1_TX
UART3_RX
UART3_TX
FB_CS5_b/
FB_TSIZ1/
FB_BE23_16
_BLS15_8_b
124
125
D5
C5
DISABLED
DISABLED
FB_CS4_b/
FB_TSIZ0/
FB_BE31_24
_BLS7_0_b
UART3_RTS
_b
FB_TBST_b/
FB_CS2_b/
FB_BE15_8_
BLS23_16_b
126
127
B5
A5
DISABLED
DISABLED
PTC19
PTD0
UART3_CTS
_b
FB_CS3_b/
FB_BE7_0_B
LS31_24_b
FB_TA_b
SPI0_PCS0
UART2_RTS
_b
FB_ALE/
FB_CS1_b/
FB_TS_b
128
129
D4
C4
ADC0_SE5b
DISABLED
ADC0_SE5b
PTD1
PTD2
SPI0_SCK
UART2_CTS
_b
FB_CS0_b
SPI0_SOUT
UART2_RX
FB_AD4
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
Freescale Semiconductor, Inc.
63
Pinout
144
144
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
QFP BGA
130
131
B4
A4
DISABLED
DISABLED
PTD3
SPI0_SIN
UART2_TX
FB_AD3
PTD4
PTD5
PTD6
SPI0_PCS1
UART0_RTS
_b
FTM0_CH4
FTM0_CH5
FTM0_CH6
FB_AD2
FB_AD1
FB_AD0
EWM_IN
132
A3
ADC0_SE6b
ADC0_SE6b
SPI0_PCS2
SPI0_PCS3
UART0_CTS
_b
EWM_OUT_b
FTM0_FLT0
133
134
135
136
137
138
139
A2
ADC0_SE7b
ADC0_SE7b
VSS
UART0_RX
M10 VSS
F8
A1
C9
B9
B3
VDD
VDD
DISABLED
DISABLED
DISABLED
DISABLED
PTD7
PTD8
PTD9
PTD10
CMT_IRO
I2C0_SCL
I2C0_SDA
UART0_TX
UART5_RX
UART5_TX
FTM0_CH7
FTM0_FLT1
FB_A16
FB_A7
UART5_RTS
_b
FB_A
140
B2
DISABLED
PTD11
SPI2_PCS0
UART5_CTS
_b
SDHC0_CLKI
N
9
141
142
143
144
B1
C3
C2
C1
DISABLED
DISABLED
DISABLED
DISABLED
PTD12
PTD13
PTD14
PTD15
SPI2_SCK
SPI2_SOUT
SPI2_SIN
SDHC0_D4
SDHC0D5
SDHC0_D6
SDHCD7
FB_A20
FB_A21
FB_A22
FB_A23
SPI2_PCS1
8.2 K20 Pinouts
The below figure shows the pinout diagrafor the devices supported by this document.
Many signals may be multiplexed to a single pin. To determine what signals can be
used on which pin, see the preious section.
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
64
Freescale Semiconductor, Inc.
Preliminary
Pinout
PTE0
1
108
107
106
105
104
103
102
101
100
99
VDD
PTE1
2
VSS
PTE2
3
PTC3
PTC2
PTC1
PTC0
PTB23
PTB22
PTB21
PTB20
PTB19
PTB18
PTB17
PTB16
VDD
PTE3
4
VDD
5
VSS
6
PTE4
7
PTE5
8
PTE6
9
PTE7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
PTE8
PTE9
PTE10
PTE11
95
PTE12
94
VDD
VSS
93
VSS
PTB11
PTB10
PTB9
92
VSS
91
USB0_DP
90
USB0_DM
PTB8
89
VOUT33
PTB7
88
VREGIN
PTB6
87
ADC0_DP1
PTB5
86
ADC0_DM1
PTB4
85
ADC1_DP1
PTB3
84
ADC1_DM1
PGA0_DP/ADC0_DP0/ADC1_DP3
PGA0_DM/ADC0_DM0/ADC1_DM3
PGA1_DP/ADC1_DP0/ADC0_DP3
PGA1_DM/ADC1_DM0/ADC0_DM3
VDDA
PTB2
83
PTB1
82
PTB0
81
PTA29
PTA28
PTA27
PTA26
PTA25
PTA24
RESET_b
PTA19
80
79
78
VREFH
77
VREFL
76
VSSA
75
ADC1_SE16
74
ADC0_SE16
73
Figure 25. K20 144 LQFP Pinout Diagram
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
Freescale Semiconductor, Inc.
65
Revision History
1
2
3
4
5
6
7
8
9
10
11
12
A
B
C
D
E
F
PTC8
PTC4
NC
PTC3
PTC2
A
B
C
D
E
F
PTD7
PTD12
PTD6
PTD5
PTD4
PTD0
PTC16
PTC12
PTD11
PTD14
PTE1
PTD10
PTD13
PTE0
PTE4
PTE8
PTE12
VSS
PTD3
PTC19
PTC18
PTC17
VDD
PTC15
PTC14
PTC13
VDD
PTC11
PTC10
PTC9
VDD
PTC7
PTC6
PTC5
VDD
PTD9
PTD8
NC
PTC1
PTB23
PTB19
P
PTB7
PTC0
PTB22
PTB18
PTB10
PTB6
PTD15
PTD2
NC
PTE2
PTD1
PTB21
PTB17
PTB
PTB20
PTB
8
PTB4
PTB0
PTA27
PTA16
PTA14
PTE6
PTE5
PTE3
PTE10
PTE9
PTE7
VDD
VSS
VSS
VDD
G
H
J
G
H
J
VOUT33
USB0_DP
ADC0_DP1
VREGIN
USB0_DM
PTE11
PTE28
VREFH
VDDA
PTA0
PT
NC
VREFL
VSSA
PT1
P
VBAT
VSS
VS
PTB
PTB3
PTB2
VS
VSS
PTB1
PTA29
PTA26
PTA17
PTA15
PTA28
PTA25
PTA24
RESET_b
ADC0_DM1 ADC0_SE16
PTE27
TA6
PTA3
PTA4
PTA7
PTA8
PTA9
PTA13
PTA12
PTA11
K
L
K
L
ADC1_DP1
PGA0_DP/
ADC1_DM1 ADC1_SE16
PGA0_DM/
PTE26
ADC0_DP0/ ADC0_DM0/
ADC1_DP3
DAC0_OUT DAC1_
ADC1_DM3
PGA1_DP/
PGA1_DM/
ADC1_DP0/ ADC1_DM0/
M
M
VREF_O
PTE24
NC
EXTAL32
XTAL32
PTA5
PTA10
VSS
PTA19
PTA18
ADC0_DP3
ADC0_DM3
1
2
3
4
5
6
7
8
9
10
11
12
Figure 26. K20 144 MAPBGA Pinout Diagram
9 Revision History
The following table provides a revision history for this document.
Table 45. Revision History
Rev. No.
Date
Substantial Changes
1
11/2010
Initial public revision
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Preliminary
66
Freescale Semiconductor, Inc.
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K20P144M100SF2
Rev. 1
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