MK20DX256ZVMB10R [NXP]
32-BIT, FLASH, 100MHz, RISC MICROCONTROLLER, PBGA81, 8 X 8 MM, MAPBGA-81;型号: | MK20DX256ZVMB10R |
厂家: | NXP |
描述: | 32-BIT, FLASH, 100MHz, RISC MICROCONTROLLER, PBGA81, 8 X 8 MM, MAPBGA-81 时钟 外围集成电路 |
文件: | 总75页 (文件大小:2276K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Document Number: K20P81M100SF2
Rev. 7, 02/2013
Freescale Semiconductor
Data Sheet: Technical Data
K20P81M100SF2
K20 Sub-Family Data Sheet
Supports the following:
MK20DX256ZVLK10,
MK20DN512ZVLK10,
MK20DX256ZVMB10,
MK20DN512ZVMB10
Features
Security and integrity modules
– Hardware CRC module to support fast cyclic
redundancy checks
•
Operating Characteristics
•
•
•
– Voltage range: 1.71 to 3.6 V
– Flash write voltage range: 1.71 to 3.6 V
– Temperature range (ambient): -40 to 105°C
– 128-bit unique identification (ID) number per chip
Human-machine interface
– Low-power hardware touch sensor interface (TSI)
– General-purpose input/output
•
•
Performance
– Up to 100 MHz ARM Cortex-M4 core with DSP
instructions delivering 1.25 Dhrystone MIPS per
MHz
Analog modules
– Two 16-bit SAR ADCs
– Programmable gain amplifier (PGA) (up to x64)
integrated into each ADC
– 12-bit DAC
Memories and memory interfaces
– Up to 512 KB program flash memory on non-
FlexMemory devices
– Up to 256 KB program flash memory on
FlexMemory devices
– Up to 256 KB FlexNVM on FlexMemory devices
– 4 KB FlexRAM on FlexMemory devices
– Up to 128 KB RAM
– Three analog comparators (CMP) containing a 6-bit
DAC and programmable reference input
– Voltage reference
Timers
•
– Programmable delay block
– Eight-channel motor control/general purpose/PWM
timer
– Serial programming interface (EzPort)
– FlexBus external bus interface
Clocks
– Two 2-channel quadrature decoder/general purpose
timers
– Periodic interrupt timers
– 16-bit low-power timer
– Carrier modulator transmitter
– Real-time clock
•
•
– 3 to 32 MHz crystal oscillator
– 32 kHz crystal oscillator
– Multi-purpose clock generator
System peripherals
– Multiple low-power modes to provide power
optimization based on application requirements
– Memory protection unit with multi-master
protection
Communication interfaces
– USB full-/low-speed On-the-Go controller with on-
chip transceiver
•
– 16-channel DMA controller, supporting up to 63
request sources
– Two Controller Area Network (CAN) modules
– Two SPI modules
– External watchdog monitor
– Software watchdog
– Two I2C modules
– Four UART modules
– Low-leakage wakeup unit
– Secure Digital host controller (SDHC)
– I2S module
Freescale reserves the right to change the detail specifications as may be
required to permit improvements in the design of its products.
© 2011–2013 Freescale Semiconductor, Inc.
Table of Contents
1 Ordering parts...........................................................................4
6 Peripheral operating requirements and behaviors....................23
6.1 Core modules....................................................................23
1.1 Determining valid orderable parts......................................4
2 Part identification......................................................................4
2.1 Description.........................................................................4
2.2 Format...............................................................................4
2.3 Fields.................................................................................4
2.4 Example............................................................................5
3 Terminology and guidelines......................................................5
3.1 Definition: Operating requirement......................................5
3.2 Definition: Operating behavior...........................................6
3.3 Definition: Attribute............................................................6
3.4 Definition: Rating...............................................................7
3.5 Result of exceeding a rating..............................................7
3.6 Relationship between ratings and operating
6.1.1
6.1.2
Debug trace timing specifications.......................23
JTAG electricals..................................................24
6.2 System modules................................................................27
6.3 Clock modules...................................................................27
6.3.1
6.3.2
6.3.3
MCG specifications.............................................27
Oscillator electrical specifications.......................29
32 kHz Oscillator Electrical Characteristics........31
6.4 Memories and memory interfaces.....................................32
6.4.1
6.4.2
6.4.3
Flash electrical specifications.............................32
EzPort Switching Specifications.........................36
Flexbus Switching Specifications........................37
6.5 Security and integrity modules..........................................40
6.6 Analog...............................................................................40
requirements......................................................................7
3.7 Guidelines for ratings and operating requirements............8
3.8 Definition: Typical value.....................................................8
3.9 Typical value conditions....................................................9
4 Ratings......................................................................................10
4.1 Thermal handling ratings...................................................10
4.2 Moisture handling ratings..................................................10
4.3 ESD handling ratings.........................................................10
4.4 Voltage and current operating ratings...............................10
5 General.....................................................................................11
5.1 AC electrical characteristics..............................................11
5.2 Nonswitching electrical specifications...............................11
6.6.1
6.6.2
6.6.3
6.6.4
ADC electrical specifications..............................40
CMP and 6-bit DAC electrical specifications......48
12-bit DAC electrical characteristics...................50
Voltage reference electrical specifications..........53
6.7 Timers................................................................................54
6.8 Communication interfaces.................................................54
6.8.1
6.8.2
6.8.3
6.8.4
6.8.5
USB electrical specifications...............................54
USB DCD electrical specifications......................55
USB VREG electrical specifications...................55
CAN switching specifications..............................56
DSPI switching specifications (limited voltage
range).................................................................56
DSPI switching specifications (full voltage
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.2.7
5.2.8
Voltage and current operating requirements......12
LVD and POR operating requirements...............13
Voltage and current operating behaviors............13
Power mode transition operating behaviors.......15
Power consumption operating behaviors............16
EMC radiated emissions operating behaviors....19
Designing with radiated emissions in mind.........20
Capacitance attributes........................................20
6.8.6
range).................................................................57
Inter-Integrated Circuit Interface (I2C) timing.....59
UART switching specifications............................60
SDHC specifications...........................................60
6.8.7
6.8.8
6.8.9
6.8.10 I2S switching specifications................................61
6.9 Human-machine interfaces (HMI)......................................64
5.3 Switching specifications.....................................................20
6.9.1
TSI electrical specifications................................64
5.3.1
5.3.2
Device clock specifications.................................20
General switching specifications.........................20
7 Dimensions...............................................................................65
7.1 Obtaining package dimensions.........................................65
8 Pinout........................................................................................65
8.1 K20 Signal Multiplexing and Pin Assignments..................65
8.2 K20 Pinouts.......................................................................70
5.4 Thermal specifications.......................................................21
5.4.1
5.4.2
Thermal operating requirements.........................21
Thermal attributes...............................................22
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
2
Freescale Semiconductor, Inc.
9 Revision History........................................................................72
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
3
Ordering parts
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to freescale.com and perform a part number search for the
following device numbers: PK20 and MK20 .
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format:
Q K## A M FFF R T PP CC N
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
K##
A
Kinetis family
Key attribute
• K20
• D = Cortex-M4 w/ DSP
• F = Cortex-M4 w/ DSP and FPU
M
Flash memory type
• N = Program flash only
• X = Program flash and FlexMemory
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
4
Freescale Semiconductor, Inc.
Terminology and guidelines
Values
Field
Description
Program flash memory size
FFF
• 32 = 32 KB
• 64 = 64 KB
• 128 = 128 KB
• 256 = 256 KB
• 512 = 512 KB
• 1M0 = 1 MB
• 2M0 = 2 MB
R
Silicon revision
• Z = Initial
• (Blank) = Main
• A = Revision after main
T
Temperature range (°C)
Package identifier
• V = –40 to 105
• C = –40 to 85
PP
• FM = 32 QFN (5 mm x 5 mm)
• FT = 48 QFN (7 mm x 7 mm)
• LF = 48 LQFP (7 mm x 7 mm)
• LH = 64 LQFP (10 mm x 10 mm)
• MP = 64 MAPBGA (5 mm x 5 mm)
• LK = 80 LQFP (12 mm x 12 mm)
• LL = 100 LQFP (14 mm x 14 mm)
• MC = 121 MAPBGA (8 mm x 8 mm)
• LQ = 144 LQFP (20 mm x 20 mm)
• MD = 144 MAPBGA (13 mm x 13 mm)
• MJ = 256 MAPBGA (17 mm x 17 mm)
CC
N
Maximum CPU frequency (MHz)
Packaging type
• 5 = 50 MHz
• 7 = 72 MHz
• 10 = 100 MHz
• 12 = 120 MHz
• 15 = 150 MHz
• R = Tape and reel
• (Blank) = Trays
2.4 Example
This is an example part number:
MK20DN512ZVMD10
3 Terminology and guidelines
3.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
5
Terminology and guidelines
3.1.1 Example
This is an example of an operating requirement:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
0.9
1.1
V
3.2 Definition: Operating behavior
An operating behavior is a specified value or range of values for a technical
characteristic that are guaranteed during operation if you meet the operating requirements
and any other specified conditions.
3.2.1 Example
This is an example of an operating behavior:
Symbol
Description
Min.
Max.
Unit
IWP
Digital I/O weak pullup/ 10
pulldown current
130
µA
3.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.
3.3.1 Example
This is an example of an attribute:
Symbol
Description
Min.
Max.
Unit
CIN_D
Input capacitance:
digital pins
—
7
pF
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
6
Freescale Semiconductor, Inc.
Terminology and guidelines
3.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
3.4.1 Example
This is an example of an operating rating:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
–0.3
1.2
V
3.5 Result of exceeding a rating
40
30
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
20
10
0
Operating rating
Measured characteristic
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
7
Terminology and guidelines
3.6 Relationship between ratings and operating requirements
Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Correct operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
Expected permanent failure
–∞
∞
Operating (power on)
Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
–∞
∞
Handling (power off)
3.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
3.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
8
Freescale Semiconductor, Inc.
Terminology and guidelines
3.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol
Description
Min.
Typ.
Max.
Unit
IWP
Digital I/O weak
pullup/pulldown
current
10
70
130
µA
3.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
5000
4500
4000
TJ
3500
150 °C
3000
105 °C
2500
25 °C
2000
–40 °C
1500
1000
500
0
0.90
0.95
1.00
1.05
1.10
VDD (V)
3.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Ambient temperature
3.3 V supply voltage
Value
Unit
TA
25
°C
V
VDD
3.3
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
9
Ratings
4 Ratings
4.1 Thermal handling ratings
Symbol
TSTG
Description
Min.
–55
—
Max.
150
260
245
Unit
°C
Notes
Storage temperature
Solder temperature, lead-free
Solder temperature, leaded
1
2
TSDR
°C
—
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.2 Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol
VHBM
VCDM
ILAT
Description
Min.
-2000
-500
Max.
+2000
+500
Unit
V
Notes
Electrostatic discharge voltage, human body model
Electrostatic discharge voltage, charged-device model
Latch-up current at ambient temperature of 105°C
1
2
3
V
-100
+100
mA
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
4.4 Voltage and current operating ratings
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
10
Freescale Semiconductor, Inc.
General
Unit
Symbol
VDD
Description
Min.
–0.3
Max.
3.8
Digital supply voltage
V
mA
V
IDD
Digital supply current
—
185
VDIO
Digital input voltage (except RESET, EXTAL, and XTAL)
Analog1, RESET, EXTAL, and XTAL input voltage
Maximum current single pin limit (applies to all digital pins)
Analog supply voltage
–0.3
5.5
VAIO
–0.3
VDD + 0.3
25
V
ID
–25
mA
V
VDDA
VDD – 0.3
–0.3
VDD + 0.3
3.63
VUSB_DP
VUSB_DM
VREGIN
VBAT
USB_DP input voltage
V
USB_DM input voltage
–0.3
3.63
V
USB regulator input
–0.3
6.0
V
RTC battery supply voltage
–0.3
3.8
V
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
5 General
5.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
Figure 1. Input signal measurement reference
All digital I/O switching characteristics assume:
1. output pins
• have CL=30pF loads,
• are configured for fast slew rate (PORTx_PCRn[SRE]=0), and
• are configured for high drive strength (PORTx_PCRn[DSE]=1)
2. input pins
• have their passive filter disabled (PORTx_PCRn[PFE]=0)
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
11
General
5.2 Nonswitching electrical specifications
5.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol
VDD
Description
Min.
1.71
1.71
–0.1
–0.1
1.71
Max.
3.6
3.6
0.1
0.1
3.6
Unit
V
Notes
Supply voltage
VDDA
Analog supply voltage
V
VDD – VDDA VDD-to-VDDA differential voltage
VSS – VSSA VSS-to-VSSA differential voltage
V
V
VBAT
VIH
RTC battery supply voltage
Input high voltage
V
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
0.7 × VDD
—
—
V
V
0.75 × VDD
VIL
Input low voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
—
—
0.35 × VDD
0.3 × VDD
V
V
VHYS
IICDIO
Input hysteresis
0.06 × VDD
-5
—
—
V
Digital pin negative DC injection current — single pin
• VIN < VSS-0.3V
1
3
mA
IICAIO
Analog2, EXTAL, and XTAL pin DC injection current —
single pin
mA
-5
—
• VIN < VSS-0.3V (Negative current injection)
• VIN > VDD+0.3V (Positive current injection)
—
+5
IICcont
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
-25
—
—
mA
• Negative current injection
• Positive current injection
+25
VODPU
VRAM
Open drain pullup voltage level
VDD
1.2
VDD
—
V
V
V
4
VDD voltage required to retain RAM
VRFVBAT
VBAT voltage required to retain the VBAT register file
VPOR_VBAT
—
1. All 5 V tolerant digital I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode
connection to VDD. If VIN is less than VDIO_MIN, a current limiting resistor is required. The negative DC injection current
limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IICDIO|.
2. Analog pins are defined as pins that do not have an associated general purpose I/O port function. Additionally, EXTAL and
XTAL are analog pins.
3. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is less than VAIO_MIN or greater
than VAIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as
R=(VAIO_MIN-VIN)/|IICAIO|. The positive injection current limiting resistor is calculated as R=(VIN-VAIO_MAX)/|IICAIO|. Select the
larger of these two calculated resistances if the pin is exposed to positive and negative injection currents.
4. Open drain outputs must be pulled to VDD.
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
12
Freescale Semiconductor, Inc.
General
5.2.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol Description
Min.
0.8
Typ.
1.1
Max.
1.5
Unit
V
Notes
VPOR
Falling VDD POR detect voltage
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV=00)
1
VLVW1H
VLVW2H
VLVW3H
VLVW4H
2.62
2.72
2.82
2.92
2.70
2.80
2.90
3.00
2.78
2.88
2.98
3.08
V
V
V
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
VHYSH
VLVDL
Low-voltage inhibit reset/recover hysteresis —
high range
—
80
—
mV
V
Falling low-voltage detect threshold — low range
(LVDV=00)
1.54
1.60
1.66
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00)
1
VLVW1L
VLVW2L
VLVW3L
VLVW4L
1.74
1.84
1.94
2.04
1.80
1.90
2.00
2.10
1.86
1.96
2.06
2.16
V
V
V
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
—
60
—
mV
VBG
tLPO
Bandgap voltage reference
0.97
900
1.00
1.03
V
Internal low power oscillator period — factory
trimmed
1000
1100
μs
1. Rising thresholds are falling threshold + hysteresis voltage
Table 3. VBAT power operating requirements
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VPOR_VBAT Falling VBAT supply POR detect voltage
0.8
1.1
1.5
V
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
13
General
5.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol Description
Min.
Typ.1
Max.
Unit
Notes
VOH
Output high voltage — high drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -9mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3mA
VDD – 0.5
VDD – 0.5
—
—
—
—
V
V
Output high voltage — low drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6mA
VDD – 0.5
VDD – 0.5
—
—
—
—
V
V
IOHT
VOL
Output high current total for all ports
Output low voltage — high drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 9mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 3mA
—
—
100
mA
2
—
—
—
—
0.5
0.5
V
V
Output low voltage — low drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 0.6mA
—
—
—
—
0.5
0.5
V
V
IOLT
IINA
Output low current total for all ports
—
—
100
mA
Input leakage current, analog pins and digital
pins configured as analog inputs
3, 4
• VSS ≤ VIN ≤ VDD
• All pins except EXTAL32, XTAL32,
EXTAL, XTAL
—
—
—
0.002
0.004
0.075
0.5
1.5
10
μA
μA
μA
• EXTAL (PTA18) and XTAL (PTA19)
• EXTAL32, XTAL32
IIND
Input leakage current, digital pins
• VSS ≤ VIN ≤ VIL
4, 5
• All digital pins
—
0.002
0.5
μA
• VIN = VDD
—
—
0.002
0.004
0.5
1
μA
μA
• All digital pins except PTD7
• PTD7
IIND
Input leakage current, digital pins
• VIL < VIN < VDD
• VDD = 3.6 V
4, 5, 6
—
—
—
—
18
12
8
26
49
13
6
μA
μA
μA
μA
• VDD = 3.0 V
• VDD = 2.5 V
• VDD = 1.7 V
3
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
14
Freescale Semiconductor, Inc.
General
Table 4. Voltage and current operating behaviors (continued)
Symbol Description
Min.
Typ.1
Max.
Unit
Notes
IIND
Input leakage current, digital pins
4, 5
• VDD < VIN < 5.5 V
—
1
50
μA
ZIND
Input impedance examples, digital pins
• VDD = 3.6 V
4, 7
—
—
—
—
—
—
—
—
48
55
57
85
kΩ
kΩ
kΩ
kΩ
• VDD = 3.0 V
• VDD = 2.5 V
• VDD = 1.7 V
RPU
RPD
Internal pullup resistors
20
20
35
35
50
50
kΩ
kΩ
8
9
Internal pulldown resistors
1. Typical values characterized at 25°C and VDD = 3.6 V unless otherwise noted.
2. Open drain outputs must be pulled to VDD
3. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
.
4. Digital pins have an associated GPIO port function and have 5V tolerant inputs, except EXTAL and XTAL.
5. Internal pull-up/pull-down resistors disabled.
6. Characterized, not tested in production.
7. Examples calculated using VIL relation, VDD, and max IIND: ZIND=VIL/IIND. This is the impedance needed to pull a high
signal to a level below VIL due to leakage when VIL < VIN < VDD. These examples assume signal source low = 0 V.
8. Measured at VDD supply voltage = VDD min and Vinput = VSS
9. Measured at VDD supply voltage = VDD min and Vinput = VDD
I
IND
Digital input
Z
IND
+
–
Source
5.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx→RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = 100 MHz
• Bus clock = 50 MHz
• FlexBus clock = 50 MHz
• Flash clock = 25 MHz
• MCG mode: FEI
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
15
General
Table 5. Power mode transition operating behaviors
Symbol
tPOR
Description
Min.
Max.
Unit
Notes
After a POR event, amount of time from the point VDD
reaches 1.71 V to execution of the first instruction
across the operating temperature range of the chip.
μs
1
—
—
300
• VDD slew rate ≥ 5.7 kV/s
• VDD slew rate < 5.7 kV/s
1.7 V / (VDD
slew rate)
—
—
—
—
—
—
134
μs
μs
μs
μs
μs
μs
• VLLS1 → RUN
• VLLS2 → RUN
• VLLS3 → RUN
• LLS → RUN
96
96
6.2
5.9
5.9
• VLPS → RUN
• STOP → RUN
1. Normal boot (FTFL_OPT[LPBOOT]=1)
5.2.5 Power consumption operating behaviors
Table 6. Power consumption operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA
Analog supply current
—
—
See note
mA
1
2
IDD_RUN Run mode current — all peripheral clocks
disabled, code executing from flash
• @ 1.8V
• @ 3.0V
—
—
45
47
70
72
mA
mA
IDD_RUN Run mode current — all peripheral clocks
enabled, code executing from flash
3, 4
• @ 1.8V
• @ 3.0V
• @ 25°C
• @ 125°C
—
61
85
mA
—
—
—
63
72
35
71
87
—
mA
mA
mA
IDD_WAIT Wait mode high frequency current at 3.0 V — all
peripheral clocks disabled
2
5
6
IDD_WAIT Wait mode reduced frequency current at 3.0 V —
all peripheral clocks disabled
—
—
15
—
—
mA
mA
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
N/A
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
16
Freescale Semiconductor, Inc.
General
Table 6. Power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
—
N/A
—
mA
7
IDD_VLPW Very-low-power wait mode current at 3.0 V — all
peripheral clocks disabled
—
N/A
—
mA
8
IDD_STOP Stop mode current at 3.0 V
• @ –40 to 25°C
—
—
—
0.59
2.26
5.94
1.4
7.9
mA
mA
mA
• @ 70°C
• @ 105°C
19.2
IDD_VLPS Very-low-power stop mode current at 3.0 V
• @ –40 to 25°C
• @ 70°C
—
—
—
93
435
2000
4000
μA
μA
μA
520
• @ 105°C
1350
IDD_LLS Low leakage stop mode current at 3.0 V
9
9
• @ –40 to 25°C
• @ 70°C
—
—
—
4.8
28
20
68
μA
μA
μA
• @ 105°C
126
270
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
• @ –40 to 25°C
• @ 70°C
—
—
—
3.1
17
82
8.9
35
μA
μA
μA
• @ 105°C
148
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
• @ –40 to 25°C
• @ 70°C
—
—
—
2.2
7.1
41
5.4
12.5
125
μA
μA
μA
• @ 105°C
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
• @ –40 to 25°C
• @ 70°C
—
—
—
2.1
6.2
30
7.6
13.5
46
μA
μA
μA
• @ 105°C
IDD_VBAT Average current with RTC and 32kHz disabled at
3.0 V
• @ –40 to 25°C
• @ 70°C
—
—
—
0.33
0.60
1.97
0.39
0.78
2.9
μA
μA
μA
• @ 105°C
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
17
General
Table 6. Power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDD_VBAT Average current when CPU is not accessing RTC
registers
10
• @ 1.8V
• @ –40 to 25°C
• @ 70°C
—
—
—
0.71
1.01
2.82
0.81
1.3
μA
μA
μA
• @ 105°C
• @ 3.0V
4.3
• @ –40 to 25°C
• @ 70°C
—
—
—
0.84
1.17
3.16
0.94
1.5
μA
μA
μA
• @ 105°C
4.6
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock . MCG configured for FEI mode.
All peripheral clocks disabled.
3. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock. MCG configured for FEI mode. All
peripheral clocks enabled.
4. Max values are measured with CPU executing DSP instructions.
5. 25MHz core and system clock, 25MHz bus clock, and 12.5MHz FlexBus and flash clock. MCG configured for FEI mode.
6. 2 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
disabled. Code executing from flash.
7. 2 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
enabled but peripherals are not in active operation. Code executing from flash.
8. 2 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
disabled.
9. Data reflects devices with 128 KB of RAM. For devices with 64 KB of RAM, power consumption is reduced by 2 μA.
10. Includes 32kHz oscillator current and RTC operation.
5.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at greater
than 50 MHz frequencies.
• USB regulator disabled
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFL
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
18
Freescale Semiconductor, Inc.
General
Figure 2. Run mode supply current vs. core frequency
5.2.6 EMC radiated emissions operating behaviors
Table 7. EMC radiated emissions operating behaviors as measured on 144LQFP and
144MAPBGA packages
Symbol Description
Frequency
band (MHz)
144LQFP 144MAPBGA
Unit
Notes
VRE1
VRE2
VRE3
VRE4
Radiated emissions voltage, band 1
0.15–50
50–150
23
27
28
14
K
12
24
27
11
K
dBμV
dBμV
dBμV
dBμV
—
1 , 2
Radiated emissions voltage, band 2
Radiated emissions voltage, band 3
Radiated emissions voltage, band 4
150–500
500–1000
0.15–1000
VRE_IEC IEC level
2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of
Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported
emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the
measured orientations in each frequency range.
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
19
General
2. VDD = 3.3 V, TA = 25 °C, fOSC = 12 MHz (crystal), fSYS = 96 MHz, fBUS = 48MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method
5.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.freescale.com.
2. Perform a keyword search for “EMC design.”
5.2.8 Capacitance attributes
Table 8. Capacitance attributes
Symbol
CIN_A
Description
Min.
—
Max.
Unit
pF
Input capacitance: analog pins
Input capacitance: digital pins
7
7
CIN_D
—
pF
5.3 Switching specifications
5.3.1 Device clock specifications
Table 9. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Notes
Normal run mode
fSYS
System and core clock
—
100
—
MHz
MHz
fSYS_USB
System and core clock when Full Speed USB in
operation
20
fBUS
FB_CLK
fFLASH
Bus clock
—
—
—
—
50
50
25
25
MHz
MHz
MHz
MHz
FlexBus clock
Flash clock
LPTMR clock
fLPTMR
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
20
Freescale Semiconductor, Inc.
General
5.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CAN, CMT, and I2C signals.
Table 10. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1, 2
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
100
16
—
—
ns
ns
ns
3
3
3
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
External reset pulse width (digital glitch filter disabled)
100
2
—
—
Mode select (EZP_CS) hold time after reset
deassertion
Bus clock
cycles
Port rise and fall time (high drive strength)
• Slew disabled
4
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
12
6
ns
ns
• Slew enabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
36
24
ns
ns
Port rise and fall time (low drive strength)
• Slew disabled
5
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
12
6
ns
ns
• Slew enabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
36
24
ns
ns
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be
recognized in that case.
2. The greater synchronous and asynchronous timing must be met.
3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and
VLLSx modes.
4. 75 pF load
5. 15 pF load
5.4 Thermal specifications
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
21
General
5.4.1 Thermal operating requirements
Table 11. Thermal operating requirements
Symbol
TJ
Description
Min.
–40
–40
Max.
125
Unit
°C
Die junction temperature
Ambient temperature
TA
105
°C
5.4.2 Thermal attributes
Board type
Symbol
Description
81 MAPBGA 80 LQFP
Unit
Notes
Single-layer
(1s)
RθJA
Thermal
resistance,
junction to
ambient (natural
convection)
65
36
52
31
17
50
35
39
29
19
°C/W
1
Four-layer
(2s2p)
RθJA
Thermal
resistance,
junction to
ambient (natural
convection)
°C/W
°C/W
°C/W
°C/W
1
1
1
2
Single-layer
(1s)
RθJMA
RθJMA
RθJB
Thermal
resistance,
junction to
ambient (200 ft./
min. air speed)
Four-layer
(2s2p)
Thermal
resistance,
junction to
ambient (200 ft./
min. air speed)
—
Thermal
resistance,
junction to
board
—
—
RθJC
Thermal
resistance,
junction to case
13
3
8
2
°C/W
°C/W
3
4
ΨJT
Thermal
characterization
parameter,
junction to
package top
outside center
(natural
convection)
1.
Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental Conditions—Forced Convection (Moving Air).
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
22
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
2.
3.
Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material
between the top of the package and the cold plate.
4.
Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
6 Peripheral operating requirements and behaviors
6.1 Core modules
6.1.1 Debug trace timing specifications
Table 12. Debug trace operating behaviors
Symbol
Tcyc
Twl
Description
Min.
Max.
Unit
MHz
ns
Clock period
Frequency dependent
Low pulse width
High pulse width
Clock and data rise time
Clock and data fall time
Data setup
2
2
—
—
3
Twh
Tr
ns
—
—
3
ns
Tf
3
ns
Ts
—
—
ns
Th
Data hold
2
ns
Figure 3. TRACE_CLKOUT specifications
TRACE_CLKOUT
TRACE_D[3:0]
Ts
Th
Ts
Th
Figure 4. Trace data specifications
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
23
Peripheral operating requirements and behaviors
6.1.2 JTAG electricals
Table 13. JTAG limited voltage range electricals
Symbol
Description
Min.
Max.
Unit
V
Operating voltage
2.7
3.6
J1
TCLK frequency of operation
• Boundary Scan
MHz
0
0
0
10
25
50
• JTAG and CJTAG
• Serial Wire Debug
J2
J3
TCLK cycle period
TCLK clock pulse width
• Boundary Scan
1/J1
—
ns
50
20
10
—
—
—
ns
ns
ns
• JTAG and CJTAG
• Serial Wire Debug
J4
J5
TCLK rise and fall times
—
20
0
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high-Z
TMS, TDI input data setup time to TCLK rise
TMS, TDI input data hold time after TCLK rise
TCLK low to TDO data valid
—
—
25
25
—
—
17
17
—
—
J6
J7
—
—
8
J8
J9
J10
J11
J12
J13
J14
1
—
—
100
8
TCLK low to TDO high-Z
TRST assert time
TRST setup time (negation) to TCLK high
Table 14. JTAG full voltage range electricals
Symbol
Description
Min.
Max.
Unit
V
Operating voltage
1.71
3.6
J1
TCLK frequency of operation
• Boundary Scan
MHz
0
0
0
10
20
40
• JTAG and CJTAG
• Serial Wire Debug
J2
TCLK cycle period
1/J1
—
ns
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
24
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 14. JTAG full voltage range electricals (continued)
Symbol
Description
Min.
Max.
Unit
J3
TCLK clock pulse width
• Boundary Scan
50
25
—
—
—
ns
ns
ns
• JTAG and CJTAG
• Serial Wire Debug
12.5
J4
J5
TCLK rise and fall times
—
20
0
3
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high-Z
TMS, TDI input data setup time to TCLK rise
TMS, TDI input data hold time after TCLK rise
TCLK low to TDO data valid
J6
—
J7
—
—
8
25
25
—
J8
J9
J10
J11
J12
J13
J14
1.4
—
—
100
8
—
22.1
22.1
—
TCLK low to TDO high-Z
TRST assert time
TRST setup time (negation) to TCLK high
—
J2
J4
J3
J3
TCLK (input)
J4
Figure 5. Test clock input timing
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
25
Peripheral operating requirements and behaviors
TCLK
J5
J6
Input data valid
Data inputs
Data outputs
Data outputs
Data outputs
J7
Output data valid
J8
J7
Output data valid
Figure 6. Boundary scan (JTAG) timing
TCLK
TDI/TMS
TDO
J9
J10
Input data valid
J11
Output data valid
J12
J11
TDO
Output data valid
TDO
Figure 7. Test Access Port timing
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
26
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
TCLK
TRST
J14
J13
Figure 8. TRST timing
6.2 System modules
There are no specifications necessary for the device's system modules.
6.3 Clock modules
6.3.1 MCG specifications
Table 15. MCG specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fints_ft Internal reference frequency (slow clock) —
—
32.768
—
kHz
factory trimmed at nominal VDD and 25 °C
fints_t
Internal reference frequency (slow clock) — user
trimmed — over fixed voltage and temperature
range of 0–70°C
31.25
—
—
38.2
0.6
kHz
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
0.3
1.5
%fdco
%fdco
1
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
—
4.5
fintf_ft
fintf_t
floc_low
floc_high
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
—
3
4
—
5
MHz
MHz
kHz
kHz
Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
—
—
—
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
—
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
FLL
ffll_ref
FLL reference frequency range
31.25
—
39.0625
kHz
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
27
Peripheral operating requirements and behaviors
Table 15. MCG specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fdco
DCO output
frequency range
Low range (DRS=00)
640 × ffll_ref
20
20.97
25
MHz
2, 3
Mid range (DRS=01)
1280 × ffll_ref
40
60
80
—
—
—
—
41.94
62.91
83.89
23.99
47.97
71.99
95.98
50
75
100
—
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
Mid-high range (DRS=10)
1920 × ffll_ref
High range (DRS=11)
2560 × ffll_ref
fdco_t_DMX32 DCO output
frequency
Low range (DRS=00)
732 × ffll_ref
4, 5
Mid range (DRS=01)
1464 × ffll_ref
—
Mid-high range (DRS=10)
2197 × ffll_ref
—
High range (DRS=11)
2929 × ffll_ref
—
Jcyc_fll
FLL period jitter
—
—
180
150
—
—
• fVCO = 48 MHz
• fVCO = 98 MHz
tfll_acquire FLL target frequency acquisition time
—
—
1
ms
6
PLL
fvco
Ipll
VCO operating frequency
48.0
—
—
100
—
MHz
µA
PLL operating current
7
7
1060
• PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref
2 MHz, VDIV multiplier = 48)
=
=
Ipll
PLL operating current
—
600
—
—
µA
• PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref
2 MHz, VDIV multiplier = 24)
fpll_ref
PLL reference frequency range
PLL period jitter (RMS)
• fvco = 48 MHz
2.0
4.0
MHz
Jcyc_pll
8
8
—
—
120
50
—
—
ps
ps
• fvco = 100 MHz
Jacc_pll
PLL accumulated jitter over 1µs (RMS)
• fvco = 48 MHz
—
—
1350
600
—
—
ps
ps
• fvco = 100 MHz
Dlock
Dunl
Lock entry frequency tolerance
Lock exit frequency tolerance
Lock detector detection time
1.49
4.47
—
—
—
—
2.98
5.97
150 × 10-6
+ 1075(1/
%
%
s
tpll_lock
9
fpll_ref
)
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
28
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation
(Δfdco_t) over voltage and temperature should be considered.
4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
6. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
7. Excludes any oscillator currents that are also consuming power while PLL is in operation.
8. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
9. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
6.3.2 Oscillator electrical specifications
This section provides the electrical characteristics of the module.
6.3.2.1 Oscillator DC electrical specifications
Table 16. Oscillator DC electrical specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
Supply current — low-power mode (HGO=0)
1
• 32 kHz
—
—
—
—
—
—
500
200
300
950
1.2
—
—
—
—
—
—
nA
μA
μA
μA
mA
mA
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz
1.5
IDDOSC
Supply current — high gain mode (HGO=1)
1
• 32 kHz
—
—
—
—
—
—
25
400
500
2.5
3
—
—
—
—
—
—
μA
μA
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
μA
mA
mA
mA
• 24 MHz
• 32 MHz
4
Cx
Cy
EXTAL load capacitance
XTAL load capacitance
—
—
—
—
—
—
2, 3
2, 3
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
29
Peripheral operating requirements and behaviors
Table 16. Oscillator DC electrical specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
RF Feedback resistor — low-frequency, low-power
—
—
—
MΩ
2, 4
mode (HGO=0)
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
—
—
—
—
—
10
—
—
—
—
—
—
—
MΩ
MΩ
MΩ
kΩ
Feedback resistor — high-frequency, low-power
mode (HGO=0)
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
1
RS
Series resistor — low-frequency, low-power
mode (HGO=0)
—
Series resistor — low-frequency, high-gain mode
(HGO=1)
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
kΩ
Series resistor — high-frequency, high-gain
mode (HGO=1)
—
—
0
—
—
kΩ
V
5
Vpp
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
0.6
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
—
—
VDD
0.6
—
—
—
V
V
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
VDD
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx,Cy can be provided by using either the integrated capacitors or by using external components.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any
other devices.
6.3.2.2 Oscillator frequency specifications
Table 17. Oscillator frequency specifications
Symbol Description
fosc_lo Oscillator crystal or resonator frequency — low
frequency mode (MCG_C2[RANGE]=00)
Min.
Typ.
Max.
Unit
Notes
32
—
40
kHz
fosc_hi_1 Oscillator crystal or resonator frequency — high
frequency mode (low range)
3
—
8
MHz
(MCG_C2[RANGE]=01)
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
30
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 17. Oscillator frequency specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fosc_hi_2 Oscillator crystal or resonator frequency — high
frequency mode (high range)
8
—
32
MHz
(MCG_C2[RANGE]=1x)
fec_extal
tdc_extal
tcst
Input clock frequency (external clock mode)
Input clock duty cycle (external clock mode)
—
40
—
—
50
50
60
—
MHz
%
1, 2
3, 4
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
750
ms
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
—
250
0.6
—
—
ms
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
2. When transitioning from FBE to FEI mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it
remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register
being set.
NOTE
The 32 kHz oscillator works in low power mode by default and
cannot be moved into high power/gain mode.
6.3.3 32 kHz Oscillator Electrical Characteristics
This section describes the module electrical characteristics.
6.3.3.1 32 kHz oscillator DC electrical specifications
Table 18. 32kHz oscillator DC electrical specifications
Symbol
VBAT
RF
Description
Min.
1.71
—
Typ.
—
Max.
3.6
—
Unit
V
Supply voltage
Internal feedback resistor
Parasitical capacitance of EXTAL32 and XTAL32
Peak-to-peak amplitude of oscillation
100
5
MΩ
pF
V
Cpara
—
7
1
Vpp
—
0.6
—
1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to
required oscillator components and must not be connected to any other devices.
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
31
Peripheral operating requirements and behaviors
6.3.3.2 32 kHz oscillator frequency specifications
Table 19. 32 kHz oscillator frequency specifications
Symbol Description
Min.
—
Typ.
32.768
1000
32.768
—
Max.
—
Unit
kHz
ms
Notes
fosc_lo
tstart
Oscillator crystal
Crystal start-up time
—
—
1
2
fec_extal32 Externally provided input clock frequency
vec_extal32 Externally provided input clock amplitude
—
—
kHz
mV
700
VBAT
2, 3
1. Proper PC board layout procedures must be followed to achieve specifications.
2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The
oscillator remains enabled and XTAL32 must be left unconnected.
3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied
clock must be within the range of VSS to VBAT
.
6.4 Memories and memory interfaces
6.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
6.4.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 20. NVM program/erase timing specifications
Symbol Description
Min.
—
Typ.
7.5
Max.
18
Unit
μs
Notes
thvpgm4
Longword Program high-voltage time
thversscr Sector Erase high-voltage time
thversblk256k Erase Block high-voltage time for 256 KB
—
13
113
3616
ms
ms
1
1
—
416
1. Maximum time based on expectations at cycling end-of-life.
6.4.1.2 Flash timing specifications — commands
Table 21. Flash command timing specifications
Symbol Description
Read 1s Block execution time
• 256 KB program/data flash
Min.
Typ.
Max.
Unit
Notes
trd1blk256k
—
—
—
—
1.7
60
ms
μs
trd1sec2k Read 1s Section execution time (flash sector)
1
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
32
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 21. Flash command timing specifications (continued)
Symbol Description
tpgmchk Program Check execution time
trdrsrc
Min.
—
Typ.
—
Max.
45
Unit
μs
Notes
1
1
Read Resource execution time
Program Longword execution time
Erase Flash Block execution time
• 256 KB program/data flash
—
—
30
μs
tpgm4
—
65
145
μs
2
2
tersblk256k
tersscr
—
—
435
14
3700
114
ms
ms
Erase Flash Sector execution time
Program Section execution time
• 512 bytes flash
tpgmsec512
tpgmsec1k
tpgmsec2k
—
—
—
2.4
4.7
9.3
—
—
—
ms
ms
ms
• 1 KB flash
• 2 KB flash
trd1all
Read 1s All Blocks execution time
Read Once execution time
—
—
—
—
—
—
—
1.8
25
ms
μs
μs
ms
μs
trdonce
1
tpgmonce Program Once execution time
65
870
—
—
tersall
Erase All Blocks execution time
Verify Backdoor Access Key execution time
Swap Control execution time
• control code 0x01
7400
30
2
1
tvfykey
tswapx01
tswapx02
tswapx04
tswapx08
—
—
—
—
200
70
70
—
—
150
150
30
μs
μs
μs
μs
• control code 0x02
• control code 0x04
• control code 0x08
Program Partition for EEPROM execution time
• 256 KB FlexNVM
tpgmpart64k
tpgmpart256k
—
—
ms
450
Set FlexRAM Function execution time:
• Control Code 0xFF
tsetramff
tsetram32k
tsetram64k
tsetram256k
—
—
—
—
70
0.8
1.3
4.5
—
μs
ms
ms
ms
• 32 KB EEPROM backup
• 64 KB EEPROM backup
• 256 KB EEPROM backup
1.2
1.9
5.5
Byte-write to FlexRAM for EEPROM operation
teewr8bers Byte-write to erased FlexRAM location execution
time
—
175
260
μs
3
Byte-write to FlexRAM execution time:
teewr8b32k
teewr8b64k
teewr8b128k
teewr8b256k
• 32 KB EEPROM backup
• 64 KB EEPROM backup
• 128 KB EEPROM backup
• 256 KB EEPROM backup
—
—
—
—
385
475
1800
2000
2400
3200
μs
μs
μs
μs
650
1000
Word-write to FlexRAM for EEPROM operation
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
33
Peripheral operating requirements and behaviors
Table 21. Flash command timing specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
teewr16bers Word-write to erased FlexRAM location
execution time
—
175
260
μs
Word-write to FlexRAM execution time:
teewr16b32k
teewr16b64k
teewr16b128k
teewr16b256k
• 32 KB EEPROM backup
• 64 KB EEPROM backup
• 128 KB EEPROM backup
• 256 KB EEPROM backup
—
—
—
—
385
475
1800
2000
2400
3200
μs
μs
μs
μs
650
1000
Longword-write to FlexRAM for EEPROM operation
teewr32bers Longword-write to erased FlexRAM location
execution time
—
360
540
μs
Longword-write to FlexRAM execution time:
teewr32b32k
teewr32b64k
teewr32b128k
teewr32b256k
• 32 KB EEPROM backup
• 64 KB EEPROM backup
• 128 KB EEPROM backup
• 256 KB EEPROM backup
—
—
—
—
630
810
2050
2250
2675
3500
μs
μs
μs
μs
1200
1900
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased.
6.4.1.3 Flash high voltage current behaviors
Table 22. Flash high voltage current behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
IDD_PGM
Average current adder during high voltage
flash programming operation
—
2.5
6.0
mA
IDD_ERS
Average current adder during high voltage
flash erase operation
—
1.5
4.0
mA
6.4.1.4 Reliability specifications
Table 23. NVM reliability specifications
Symbol Description
Min.
Program Flash
Typ.1
Max.
Unit
Notes
tnvmretp10k Data retention after up to 10 K cycles
tnvmretp1k Data retention after up to 1 K cycles
nnvmcycp Cycling endurance
5
50
—
—
—
years
years
cycles
20
100
50 K
10 K
2
Data Flash
tnvmretd10k Data retention after up to 10 K cycles
5
50
—
years
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
34
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 23. NVM reliability specifications (continued)
Symbol Description
Min.
Typ.1
Max.
—
Unit
years
cycles
Notes
tnvmretd1k Data retention after up to 1 K cycles
nnvmcycd Cycling endurance
20
10 K
100
50 K
—
2
FlexRAM as EEPROM
tnvmretee100 Data retention up to 100% of write endurance
tnvmretee10 Data retention up to 10% of write endurance
Write endurance
5
50
—
—
years
years
20
100
3
nnvmwree16
nnvmwree128
nnvmwree512
nnvmwree4k
nnvmwree32k
• EEPROM backup to FlexRAM ratio = 16
• EEPROM backup to FlexRAM ratio = 128
• EEPROM backup to FlexRAM ratio = 512
• EEPROM backup to FlexRAM ratio = 4096
35 K
315 K
1.27 M
10 M
175 K
1.6 M
6.4 M
50 M
—
—
—
—
—
writes
writes
writes
writes
writes
• EEPROM backup to FlexRAM ratio =
32,768
80 M
400 M
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant
25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering
Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C.
3. Write endurance represents the number of writes to each FlexRAM location at -40°C ≤Tj ≤ 125°C influenced by the cycling
endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup per subsystem. Minimum and
typical values assume all byte-writes to FlexRAM.
6.4.1.5 Write endurance to FlexRAM for EEPROM
When the FlexNVM partition code is not set to full data flash, the EEPROM data set size
can be set to any of several non-zero values.
The bytes not assigned to data flash via the FlexNVM partition code are used by the flash
memory module to obtain an effective endurance increase for the EEPROM data. The
built-in EEPROM record management system raises the number of program/erase cycles
that can be attained prior to device wear-out by cycling the EEPROM data through a
larger EEPROM NVM storage space.
While different partitions of the FlexNVM are available, the intention is that a single
choice for the FlexNVM partition code and EEPROM data set size is used throughout the
entire lifetime of a given application. The EEPROM endurance equation and graph
shown below assume that only one configuration is ever used.
EEPROM – 2 × EEESPLIT × EEESIZE
Writes_subsystem =
× Write_efficiency × nnvmcycd
where
• Writes_subsystem — minimum number of writes to each FlexRAM location for
subsystem (each subsystem can have different endurance)
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
35
Peripheral operating requirements and behaviors
• EEPROM — allocated FlexNVM for each EEPROM subsystem based on DEPART;
entered with the Program Partition command
• EEESPLIT — FlexRAM split factor for subsystem; entered with the Program
Partition command
• EEESIZE — allocated FlexRAM based on DEPART; entered with the Program
Partition command
• Write_efficiency —
• 0.25 for 8-bit writes to FlexRAM
• 0.50 for 16-bit or 32-bit writes to FlexRAM
• nnvmcycd — data flash cycling endurance (the following graph assumes 10,000
cycles)
Figure 9. EEPROM backup writes to FlexRAM
6.4.2 EzPort Switching Specifications
Table 24. EzPort switching specifications
Num
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
36
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 24. EzPort switching specifications (continued)
Num
Description
Min.
Max.
Unit
EP1
EZP_CK frequency of operation (all commands except
—
fSYS/2
MHz
READ)
EP1a
EP2
EP3
EP4
EP5
EP6
EP7
EP8
EP9
EZP_CK frequency of operation (READ command)
EZP_CS negation to next EZP_CS assertion
EZP_CS input valid to EZP_CK high (setup)
EZP_CK high to EZP_CS input invalid (hold)
EZP_D input valid to EZP_CK high (setup)
EZP_CK high to EZP_D input invalid (hold)
EZP_CK low to EZP_Q output valid
—
fSYS/8
—
MHz
ns
2 x tEZP_CK
5
5
—
ns
—
ns
2
—
ns
5
—
ns
—
0
16
—
ns
EZP_CK low to EZP_Q output invalid (hold)
EZP_CS negation to EZP_Q tri-state
ns
—
12
ns
EZP_CK
EZP_CS
EP3
EP4
EP2
EP9
EP8
EP7
EZP_Q (output)
EZP_D (input)
EP5
EP6
Figure 10. EzPort Timing Diagram
6.4.3 Flexbus Switching Specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in
respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be
the same as the internal system bus frequency or an integer divider of that frequency.
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
37
Peripheral operating requirements and behaviors
The following timing numbers indicate when data is latched or driven onto the external
bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be
derived from these values.
Table 25. Flexbus limited voltage range switching specifications
Num
Description
Min.
2.7
—
Max.
3.6
Unit
V
Notes
Operating voltage
Frequency of operation
Clock period
FB_CLK
—
MHz
ns
FB1
FB2
FB3
FB4
FB5
20
Address, data, and control output valid
Address, data, and control output hold
Data and FB_TA input setup
Data and FB_TA input hold
—
11.5
—
ns
1
1
2
2
0.5
8.5
0.5
ns
—
ns
—
ns
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
Table 26. Flexbus full voltage range switching specifications
Num
Description
Min.
1.71
—
Max.
3.6
Unit
V
Notes
Operating voltage
Frequency of operation
Clock period
FB_CLK
—
MHz
ns
FB1
FB2
FB3
FB4
FB5
1/FB_CLK
—
Address, data, and control output valid
Address, data, and control output hold
Data and FB_TA input setup
Data and FB_TA input hold
13.5
—
ns
1
1
2
2
0
ns
13.7
0.5
—
ns
—
ns
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
38
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
FB1
FB_CLK
FB_A[Y]
FB_D[X]
FB_RW
FB_TS
FB3
FB5
Address
FB4
FB2
Address
Data
FB_ALE
FB_CSn
FB_OEn
FB_BEn
FB_TA
AA=1
AA=0
FB4
FB5
AA=1
AA=0
FB_TSIZ[1:0]
TSIZ
Figure 11. FlexBus read timing diagram
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
39
Peripheral operating requirements and behaviors
FB1
FB_CLK
FB2
FB3
FB_A[Y]
FB_D[X]
FB_RW
FB_TS
Address
Address
Data
FB_ALE
FB_CSn
FB_OEn
FB_BEn
FB_TA
AA=1
AA=0
FB4
FB5
AA=1
AA=0
FB_TSIZ[1:0]
TSIZ
Figure 12. FlexBus write timing diagram
6.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
6.6 Analog
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
40
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 27 and Table 28 are achievable on the
differential pins ADCx_DP0, ADCx_DM0, ADCx_DP1, ADCx_DM1, ADCx_DP3, and
ADCx_DM3.
The ADCx_DP2 and ADCx_DM2 ADC inputs are connected to the PGA outputs and are
not direct device pins. Accuracy specifications for these pins are defined in Table 29 and
Table 30.
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
6.6.1.1 16-bit ADC operating conditions
Table 27. 16-bit ADC operating conditions
Symbol Description
Conditions
Min.
1.71
-100
-100
1.13
Typ.1
Max.
3.6
Unit
V
Notes
VDDA
ΔVDDA
ΔVSSA
VREFH
Supply voltage
Supply voltage
Ground voltage
Absolute
—
Delta to VDD (VDD - VDDA
)
0
+100
+100
VDDA
mV
mV
V
2
2
Delta to VSS (VSS - VSSA
)
0
ADC reference
voltage high
VDDA
VREFL
VADIN
ADC reference
voltage low
VSSA
VSSA
VSSA
V
V
Input voltage
• 16-bit differential mode
• All other modes
• 16-bit mode
VREFL
VREFL
—
—
31/32 *
VREFH
VREFH
CADIN
Input capacitance
—
—
8
4
10
5
pF
• 8-bit / 10-bit / 12-bit
modes
RADIN
RAS
Input resistance
—
—
2
5
5
kΩ
kΩ
Analog source
resistance
13-bit / 12-bit modes
fADCK < 4 MHz
3
—
fADCK
fADCK
Crate
ADC conversion ≤ 13-bit mode
clock frequency
1.0
2.0
—
—
18.0
12.0
MHz
MHz
4
4
5
ADC conversion 16-bit mode
clock frequency
ADC conversion ≤ 13-bit modes
rate
No ADC hardware averaging
20.000
—
818.330
Ksps
Continuous conversions
enabled, subsequent
conversion time
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
41
Peripheral operating requirements and behaviors
Table 27. 16-bit ADC operating conditions (continued)
Symbol Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
Crate
ADC conversion 16-bit mode
rate
5
No ADC hardware averaging
37.037
—
461.467
Ksps
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The RAS/CAS
time constant should be kept to < 1 ns.
4. To use the maximum ADC conversion clock frequency, the ADHSC bit must be set and the ADLPC bit must be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
SIMPLIFIED
INPUT PIN EQUIVALENT
ZADIN
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
ZAS
ADC SAR
ENGINE
RAS
RADIN
VADIN
CAS
VAS
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 13. ADC input impedance equivalency diagram
6.6.1.2 16-bit ADC electrical characteristics
Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA
)
Symbol Description
Conditions1
Min.
Typ.2
Max.
Unit
Notes
IDDA_ADC Supply current
0.215
—
1.7
mA
3
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
42
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
Conditions1
Min.
1.2
2.4
3.0
4.4
Typ.2
Max.
3.9
Unit
Notes
ADC
asynchronous
• ADLPC = 1, ADHSC = 0
• ADLPC = 1, ADHSC = 1
• ADLPC = 0, ADHSC = 0
• ADLPC = 0, ADHSC = 1
2.4
tADACK = 1/
fADACK
MHz
MHz
MHz
MHz
4.0
6.1
clock source
fADACK
5.2
7.3
6.2
9.5
Sample Time
See Reference Manual chapter for sample times
TUE
DNL
Total unadjusted
error
• 12-bit modes
• <12-bit modes
—
—
4
6.8
2.1
LSB4
LSB4
5
5
1.4
Differential non-
linearity
• 12-bit modes
—
0.7
-1.1 to +1.9
-0.3 to 0.5
• <12-bit modes
• 12-bit modes
—
—
0.2
1.0
INL
EFS
Integral non-
linearity
-2.7 to +1.9
-0.7 to +0.5
LSB4
5
• <12-bit modes
• 12-bit modes
• <12-bit modes
—
—
—
0.5
-4
Full-scale error
-5.4
-1.8
LSB4
LSB4
VADIN =
VDDA
-1.4
5
EQ
Quantization
error
• 16-bit modes
• ≤13-bit modes
—
—
-1 to 0
—
—
0.5
ENOB
Effective number 16-bit differential mode
6
of bits
• Avg = 32
12.8
11.9
14.5
13.8
—
—
bits
bits
• Avg = 4
16-bit single-ended mode
• Avg = 32
12.2
11.4
13.9
13.1
—
—
bits
bits
• Avg = 4
Signal-to-noise
plus distortion
See ENOB
SINAD
THD
6.02 × ENOB + 1.76
dB
Total harmonic
distortion
16-bit differential mode
• Avg = 32
7
7
—
—
–94
-85
—
—
dB
dB
16-bit single-ended mode
• Avg = 32
SFDR
Spurious free
dynamic range
16-bit differential mode
• Avg = 32
82
78
95
90
—
—
dB
dB
16-bit single-ended mode
• Avg = 32
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
43
Peripheral operating requirements and behaviors
Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
Conditions1
Min.
Typ.2
Max.
Unit
Notes
IIn
leakage
current
EIL
Input leakage
error
IIn × RAS
mV
=
(refer to
the MCU's
voltage
and current
operating
ratings)
Temp sensor
slope
Across the full temperature
range of the device
1.55
706
1.62
716
1.69
726
mV/°C
mV
VTEMP25 Temp sensor
voltage
25 °C
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and the ADLPC bit (low power).
For lowest power operation the ADLPC bit must be set, the HSC bit must be clear with 1 MHz ADC conversion clock
speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
Figure 14. Typical ENOB vs. ADC_CLK for 16-bit differential mode
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
44
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Figure 15. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
6.6.1.3 16-bit ADC with PGA operating conditions
Table 29. 16-bit ADC with PGA operating conditions
Symbol Description
VDDA Supply voltage
VREFPGA PGA ref voltage
Conditions
Min.
Typ.1
Max.
Unit
V
Notes
Absolute
1.71
—
3.6
VREF_OU VREF_OU VREF_OU
V
2, 3
T
T
T
VADIN
VCM
Input voltage
VSSA
VSSA
—
—
VDDA
VDDA
V
V
Input Common
Mode range
RPGAD
Differential input Gain = 1, 2, 4, 8
—
—
—
—
128
64
—
—
—
—
kΩ
IN+ to IN-4
impedance
Gain = 16, 32
Gain = 64
32
RAS
TS
Analog source
resistance
100
Ω
5
6
ADC sampling
time
1.25
—
—
µs
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
45
Peripheral operating requirements and behaviors
Table 29. 16-bit ADC with PGA operating conditions (continued)
Symbol Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
Crate
ADC conversion ≤ 13 bit modes
18.484
—
450
Ksps
7
rate
No ADC hardware
averaging
Continuous conversions
enabled
Peripheral clock = 50
MHz
16 bit modes
37.037
—
250
Ksps
8
No ADC hardware
averaging
Continuous conversions
enabled
Peripheral clock = 50
MHz
1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 6 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. ADC must be configured to use the internal voltage reference (VREF_OUT)
3. PGA reference is internally connected to the VREF_OUT pin. If the user wishes to drive VREF_OUT with a voltage other
than the output of the VREF module, the VREF module must be disabled.
4. For single ended configurations the input impedance of the driven input is RPGAD/2
5. The analog source resistance (RAS), external to MCU, should be kept as minimum as possible. Increased RAS causes drop
in PGA gain without affecting other performances. This is not dependent on ADC clock frequency.
6. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs
time should be allowed for Fin=4 kHz at 16-bit differential mode. Recommended ADC setting is: ADLSMP=1, ADLSTS=2 at
8 MHz ADC clock.
7. ADC clock = 18 MHz, ADLSMP = 1, ADLST = 00, ADHSC = 1
8. ADC clock = 12 MHz, ADLSMP = 1, ADLST = 01, ADHSC = 1
6.6.1.4 16-bit ADC with PGA characteristics
Table 30. 16-bit ADC with PGA characteristics
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
IDDA_PGA Supply current
Low power
—
420
644
μA
2
(ADC_PGA[PGALPb]=0)
IDC_PGA
Input DC current
A
3
Gain =1, VREFPGA=1.2V,
VCM=0.5V
—
—
1.54
0.57
—
—
μA
μA
Gain =64, VREFPGA=1.2V,
VCM=0.1V
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
46
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 30. 16-bit ADC with PGA characteristics (continued)
Symbol
Description
Conditions
• PGAG=0
• PGAG=1
• PGAG=2
• PGAG=3
• PGAG=4
• PGAG=5
• PGAG=6
Min.
0.95
1.9
Typ.1
Max.
1.05
2.1
Unit
Notes
G
Gain4
1
R
AS < 100Ω
2
3.8
4
4.2
7.6
8
8.4
15.2
30.0
58.8
16
31.6
63.3
16.6
33.2
67.8
BW
Input signal
bandwidth
• 16-bit modes
• < 16-bit modes
—
—
—
—
—
4
kHz
kHz
dB
40
—
PSRR
Power supply
rejection ratio
Gain=1
-84
VDDA= 3V
100mV,
fVDDA= 50Hz,
60Hz
CMRR
Common mode
rejection ratio
• Gain=1
—
—
-84
-85
—
—
dB
dB
VCM=
500mVpp,
fVCM= 50Hz,
100Hz
• Gain=64
VOFS
TGSW
EIL
Input offset
voltage
—
—
0.2
—
—
mV
µs
Output offset =
VOFS*(Gain+1)
Gain switching
settling time
10
5
Input leakage
error
All modes
IIn × RAS
mV
IIn = leakage
current
(refer to the
MCU's voltage
and current
operating
ratings)
VPP,DIFF Maximum
differential input
V
6
signal swing
where VX = VREFPGA × 0.583
SNR
THD
Signal-to-noise
ratio
• Gain=1
80
52
90
66
—
—
dB
dB
16-bit
differential
mode,
• Gain=64
Average=32
Total harmonic
distortion
• Gain=1
85
49
100
95
—
—
dB
dB
16-bit
differential
mode,
• Gain=64
Average=32,
fin=100Hz
SFDR
Spurious free
dynamic range
• Gain=1
85
53
105
88
—
—
dB
dB
16-bit
differential
mode,
• Gain=64
Average=32,
fin=100Hz
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
47
Peripheral operating requirements and behaviors
Table 30. 16-bit ADC with PGA characteristics (continued)
Symbol
Description
Conditions
• Gain=1, Average=4
Min.
11.6
7.2
Typ.1
13.4
9.6
Max.
—
Unit
bits
bits
bits
bits
bits
bits
bits
bits
bits
Notes
ENOB
Effective number
of bits
16-bit
differential
mode,fin=100Hz
• Gain=64, Average=4
• Gain=1, Average=32
• Gain=2, Average=32
• Gain=4, Average=32
• Gain=8, Average=32
• Gain=16, Average=32
• Gain=32, Average=32
• Gain=64, Average=32
—
12.8
11.0
7.9
14.5
14.3
13.8
13.1
12.5
11.5
10.6
—
—
—
7.3
—
6.8
—
6.8
—
7.5
—
SINAD
Signal-to-noise
plus distortion
ratio
See ENOB
6.02 × ENOB + 1.76
dB
1. Typical values assume VDDA =3.0V, Temp=25°C, fADCK=6MHz unless otherwise stated.
2. This current is a PGA module adder, in addition to ADC conversion currents.
3. Between IN+ and IN-. The PGA draws a DC current from the input terminals. The magnitude of the DC current is a strong
function of input common mode voltage (VCM) and the PGA gain.
4. Gain = 2PGAG
5. After changing the PGA gain setting, a minimum of 2 ADC+PGA conversions should be ignored.
6. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the
PGA reference voltage and gain setting.
6.6.2 CMP and 6-bit DAC electrical specifications
Table 31. Comparator and 6-bit DAC electrical specifications
Symbol
VDD
Description
Min.
1.71
—
Typ.
—
Max.
3.6
Unit
V
Supply voltage
IDDHS
IDDLS
VAIN
Supply current, High-speed mode (EN=1, PMODE=1)
Supply current, low-speed mode (EN=1, PMODE=0)
Analog input voltage
—
200
20
μA
μA
V
—
—
VSS – 0.3
—
—
VDD
20
VAIO
Analog input offset voltage
Analog comparator hysteresis1
• CR0[HYSTCTR] = 00
—
mV
VH
—
—
—
—
5
—
—
—
—
mV
mV
mV
mV
• CR0[HYSTCTR] = 01
10
20
30
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
VCMPOh
VCMPOl
tDHS
Output high
Output low
VDD – 0.5
—
—
50
—
0.5
200
V
V
—
Propagation delay, high-speed mode (EN=1,
PMODE=1)
20
ns
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
48
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 31. Comparator and 6-bit DAC electrical specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
tDLS
Propagation delay, low-speed mode (EN=1,
PMODE=0)
80
250
600
ns
Analog comparator initialization delay2
6-bit DAC current adder (enabled)
6-bit DAC integral non-linearity
—
—
—
7
40
—
μs
μA
LSB3
IDAC6b
INL
–0.5
–0.3
—
—
0.5
0.3
DNL
6-bit DAC differential non-linearity
LSB
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD-0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN,
VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
0.08
0.07
0.06
HYSTCTR
Setting
0.05
00
0.04
01
10
11
0.03
0.02
0.01
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vinlevel (V)
Figure 16. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0)
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
49
Peripheral operating requirements and behaviors
0.18
0.16
0.14
0.12
0.1
HYSTCTR
Setting
00
01
10
11
0.08
0.06
0.04
0.02
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vinlevel (V)
Figure 17. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=1)
6.6.3 12-bit DAC electrical characteristics
6.6.3.1 12-bit DAC operating requirements
Table 32. 12-bit DAC operating requirements
Symbol
VDDA
VDACR
TA
Desciption
Min.
1.71
1.13
Max.
3.6
Unit
V
Notes
Supply voltage
Reference voltage
Temperature
3.6
V
1
Operating temperature
range of the device
°C
CL
IL
Output load capacitance
Output load current
—
—
100
1
pF
2
mA
1. The DAC reference can be selected to be VDDA or the voltage output of the VREF module (VREF_OUT)
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
50
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.6.3.2 12-bit DAC operating behaviors
Table 33. 12-bit DAC operating behaviors
Symbol Description
Min.
Typ.
Max.
150
Unit
Notes
IDDA_DACL Supply current — low-power mode
—
—
μA
P
IDDA_DACH Supply current — high-speed mode
—
—
—
—
—
—
100
15
0.7
—
700
200
30
μA
μs
P
tDACLP Full-scale settling time (0x080 to 0xF7F) —
low-power mode
1
1
1
tDACHP Full-scale settling time (0x080 to 0xF7F) —
high-power mode
μs
tCCDACLP Code-to-code settling time (0xBF8 to 0xC08)
— low-power mode and high-speed mode
1
μs
Vdacoutl DAC output voltage range low — high-speed
mode, no load, DAC set to 0x000
100
VDACR
8
mV
mV
LSB
LSB
LSB
Vdacouth DAC output voltage range high — high-
speed mode, no load, DAC set to 0xFFF
VDACR
−100
—
INL
DNL
DNL
Integral non-linearity error — high speed
mode
—
—
—
—
2
3
4
Differential non-linearity error — VDACR > 2
V
—
1
Differential non-linearity error — VDACR
VREF_OUT
=
—
1
VOFFSET Offset error
EG Gain error
PSRR Power supply rejection ratio, VDDA ≥ 2.4 V
—
—
60
—
—
—
0.4
0.1
0.8
0.6
90
%FSR
%FSR
dB
5
5
—
TCO
TGE
Rop
SR
Temperature coefficient offset voltage
Temperature coefficient gain error
Output resistance load = 3 kΩ
Slew rate -80h→ F7Fh→ 80h
3.7
—
μV/C
%FSR/C
Ω
6
0.000421
—
—
250
V/μs
• High power (SPHP
• Low power (SPLP
)
1.2
1.7
—
—
)
0.05
0.12
CT
Channel to channel cross talk
3dB bandwidth
—
—
-80
dB
BW
kHz
• High power (SPHP
• Low power (SPLP
)
550
40
—
—
—
—
)
1. Settling within 1 LSB
2. The INL is measured for 0 + 100 mV to VDACR −100 mV
3. The DNL is measured for 0 + 100 mV to VDACR −100 mV
4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V
5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to
0x800, temperature range is across the full range of the device
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
51
Peripheral operating requirements and behaviors
Figure 18. Typical INL error vs. digital code
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
52
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Figure 19. Offset at half scale vs. temperature
6.6.4 Voltage reference electrical specifications
Table 34. VREF full-range operating requirements
Symbol
VDDA
TA
Description
Supply voltage
Temperature
Min.
Max.
Unit
V
Notes
1.71
3.6
Operating temperature
range of the device
°C
CL
Output load capacitance
100
nF
1, 2
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range of
the device.
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
53
Peripheral operating requirements and behaviors
Table 35. VREF full-range operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim at
1.1915
1.195
1.1977
V
nominal VDDA and temperature=25C
Voltage reference output — factory trim
Voltage reference trim step
Vout
Vstep
Vtdrift
1.1584
—
—
0.5
—
1.2376
—
V
mV
mV
Temperature drift (Vmax -Vmin across the full
temperature range)
—
80
Ibg
Ilp
Bandgap only current
—
—
—
—
—
—
80
360
1
µA
uA
1
1
Low-power buffer current
High-power buffer current
Ihp
mA
mV
1
ΔVLOAD Load regulation
• current = + 1.0 mA
1, 2
—
—
2
5
—
—
• current = - 1.0 mA
Tstup
Buffer startup time
—
—
—
2
100
—
µs
Vvdrift
Voltage drift (Vmax -Vmin across the full voltage
range)
mV
1
1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 36. VREF limited-range operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
TA
Temperature
0
50
°C
Table 37. VREF limited-range operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim
1.173
1.225
V
6.7 Timers
See General switching specifications.
6.8 Communication interfaces
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
54
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.8.1 USB electrical specifications
The USB electricals for the USB On-the-Go module conform to the standards
documented by the Universal Serial Bus Implementers Forum. For the most up-to-date
standards, visit usb.org.
6.8.2 USB DCD electrical specifications
Table 38. USB DCD electrical specifications
Symbol
VDP_SRC
VLGC
Description
Min.
0.5
Typ.
—
Max.
0.7
Unit
V
USB_DP source voltage (up to 250 μA)
Threshold voltage for logic high
USB_DP source current
USB_DM sink current
0.8
—
2.0
V
IDP_SRC
IDM_SINK
7
10
13
μA
μA
kΩ
V
50
100
—
150
24.8
0.4
RDM_DWN D- pulldown resistance for data pin contact detect
VDAT_REF Data detect voltage
14.25
0.25
0.33
6.8.3 USB VREG electrical specifications
Table 39. USB VREG electrical specifications
Symbol Description
Min.
2.7
—
Typ.1
Max.
5.5
Unit
Notes
VREGIN Input supply voltage
—
V
IDDon
IDDstby
IDDoff
Quiescent current — Run mode, load current
equal zero, input supply (VREGIN) > 3.6 V
120
186
μA
Quiescent current — Standby mode, load current
equal zero
—
1.27
30
μA
Quiescent current — Shutdown mode
—
—
650
—
—
4
nA
μA
• VREGIN = 5.0 V and temperature=25 °C
• Across operating voltage and temperature
ILOADrun Maximum load current — Run mode
ILOADstby Maximum load current — Standby mode
—
—
—
—
120
1
mA
mA
VReg33out Regulator output voltage — Input supply
(VREGIN) > 3.6 V
• Run mode
3
3.3
2.8
—
3.6
3.6
3.6
V
V
V
• Standby mode
2.1
2.1
VReg33out Regulator output voltage — Input supply
(VREGIN) < 3.6 V, pass-through mode
2
COUT
ESR
External output capacitor
1.76
1
2.2
—
8.16
100
μF
External output capacitor equivalent series
resistance
mΩ
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
55
Peripheral operating requirements and behaviors
Table 39. USB VREG electrical specifications
(continued)
Symbol Description
ILIM Short circuit current
Min.
Typ.1
Max.
Unit
Notes
—
290
—
mA
1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated.
2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad
.
6.8.4 CAN switching specifications
See General switching specifications.
6.8.5 DSPI switching specifications (limited voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provide DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 40. Master mode DSPI timing (limited voltage range)
Num
Description
Min.
2.7
Max.
3.6
25
Unit
V
Notes
Operating voltage
Frequency of operation
—
MHz
ns
DS1
DS2
DS3
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
2 x tBUS
—
(tSCK/2) − 2 (tSCK/2) + 2
ns
(tBUS x 2) −
2
—
ns
1
2
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
2
—
ns
DS5
DS6
DS7
DS8
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
—
−2
15
0
8.5
—
—
—
ns
ns
ns
ns
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
56
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
DSPI_PCSn
DS1
DS3
DS2
DS4
DSPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
DSPI_SIN
DS5
DS6
First data
Data
Last data
DSPI_SOUT
Figure 20. DSPI classic SPI timing — master mode
Table 41. Slave mode DSPI timing (limited voltage range)
Num
Description
Min.
Max.
Unit
V
Operating voltage
2.7
3.6
Frequency of operation
12.5
MHz
ns
DS9
DSPI_SCK input cycle time
4 x tBUS
—
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSCK/2) − 2
(tSCK/2) + 2
ns
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
—
0
10
—
—
—
14
14
ns
ns
2
ns
7
ns
—
—
ns
ns
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DS12
DS16
DS11
First data
DS14
Last data
DSPI_SOUT
Data
Data
DS13
First data
Last data
DSPI_SIN
Figure 21. DSPI classic SPI timing — slave mode
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
57
Peripheral operating requirements and behaviors
6.8.6 DSPI switching specifications (full voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provides DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 42. Master mode DSPI timing (full voltage range)
Num
Description
Min.
1.71
Max.
3.6
Unit
V
Notes
Operating voltage
1
Frequency of operation
—
12.5
—
MHz
ns
DS1
DS2
DS3
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
4 x tBUS
(tSCK/2) - 4 (tSCK/2) + 4
ns
(tBUS x 2) −
4
—
ns
2
3
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
4
—
ns
DS5
DS6
DS7
DS8
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
—
-4.5
20.5
0
10
—
—
—
ns
ns
ns
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DS1
DS3
DS2
DS4
DSPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
DSPI_SIN
DS5
DS6
First data
Data
Last data
DSPI_SOUT
Figure 22. DSPI classic SPI timing — master mode
Table 43. Slave mode DSPI timing (full voltage range)
Num
Description
Min.
1.71
—
Max.
3.6
Unit
V
Operating voltage
Frequency of operation
6.25
MHz
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
58
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 43. Slave mode DSPI timing (full voltage range) (continued)
Num
DS9
Description
DSPI_SCK input cycle time
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
8 x tBUS
—
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSCK/2) - 4
(tSCK/2) + 4
DSPI_SCK to DSPI_SOUT valid
—
0
20
—
—
—
19
19
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
2
7
—
—
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DS12
DS16
DS11
First data
DS14
Last data
DSPI_SOUT
Data
Data
DS13
First data
Last data
DSPI_SIN
Figure 23. DSPI classic SPI timing — slave mode
6.8.7 Inter-Integrated Circuit Interface (I2C) timing
Table 44. I 2C timing
Characteristic
Symbol
Standard Mode
Minimum Maximum
100
Fast Mode
Unit
Minimum
Maximum
400
SCL Clock Frequency
fSCL
0
0
kHz
µs
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
tHD; STA
4
—
0.6
—
LOW period of the SCL clock
HIGH period of the SCL clock
tLOW
tHIGH
4.7
4
—
—
—
1.3
0.6
0.6
—
—
—
µs
µs
µs
Set-up time for a repeated START
condition
tSU; STA
4.7
Data hold time for I2C bus devices
Data set-up time
tHD; DAT
tSU; DAT
tr
01
2504
—
3.452
—
03
1002, 5
0.91
—
µs
ns
ns
6
Rise time of SDA and SCL signals
1000
20 +0.1Cb
300
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
59
Peripheral operating requirements and behaviors
Table 44. I 2C timing (continued)
Characteristic
Symbol
Standard Mode
Minimum Maximum
300
Fast Mode
Unit
Minimum Maximum
5
Fall time of SDA and SCL signals
Set-up time for STOP condition
tf
—
20 +0.1Cb
0.6
300
—
ns
µs
µs
tSU; STO
tBUF
4
—
—
Bus free time between STOP and
START condition
4.7
1.3
—
Pulse width of spikes that must be
suppressed by the input filter
tSP
N/A
N/A
0
50
ns
1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL
lines.
2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
3. Input signal Slew = 10ns and Output Load = 50pf
4. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
5. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns must
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a
device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU; DAT
= 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.
6. Cb = total capacitance of the one bus line in pF.
SDA
tSU; DAT
tf
tr
tBUF
tf
tr
tHD; STA
tSP
tLOW
SCL
tSU; STA
tHD; STA
tSU; STO
S
SR
P
S
tHD; DAT
tHIGH
Figure 24. Timing definition for fast and standard mode devices on the I2C bus
6.8.8 UART switching specifications
See General switching specifications.
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
60
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.8.9 SDHC specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
Table 45. SDHC switching specifications
Num
Symbol
Description
Min.
Max.
Unit
Card input clock
SD1
fpp
fpp
fpp
fOD
tWL
tWH
tTLH
tTHL
Clock frequency (low speed)
0
0
400
25\50
20\50
400
—
kHz
MHz
MHz
kHz
ns
Clock frequency (SD\SDIO full speed\high speed)
Clock frequency (MMC full speed\high speed)
Clock frequency (identification mode)
Clock low time
0
0
SD2
SD3
SD4
SD5
7
Clock high time
7
—
ns
Clock rise time
—
—
3
ns
Clock fall time
3
ns
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SDHC output delay (output valid) -5 8.3
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD6
tOD
ns
SD7
SD8
tISU
tIH
SDHC input setup time
SDHC input hold time
5
0
—
—
ns
ns
SD3
SD6
SD2
SD1
SDHC_CLK
Output SDHC_CMD
Output SDHC_DAT[3:0]
Input SDHC_CMD
SD7
SD8
Input SDHC_DAT[3:0]
Figure 25. SDHC timing
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
61
Peripheral operating requirements and behaviors
6.8.10 I2S switching specifications
This section provides the AC timings for the I2S in master (clocks driven) and slave
modes (clocks input). All timings are given for non-inverted serial clock polarity
(TCR[TSCKP] = 0, RCR[RSCKP] = 0) and a non-inverted frame sync (TCR[TFSI] = 0,
RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all
the timings remain valid by inverting the clock signal (I2S_BCLK) and/or the frame sync
(I2S_FS) shown in the figures below.
Table 46. I2S master mode timing (limited voltage range)
Num
Description
Min.
2.7
Max.
Unit
Operating voltage
3.6
V
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
I2S_MCLK cycle time
2 x tSYS
45%
5 x tSYS
45%
—
ns
I2S_MCLK pulse width high/low
I2S_BCLK cycle time
55%
—
MCLK period
ns
I2S_BCLK pulse width high/low
I2S_BCLK to I2S_FS output valid
I2S_BCLK to I2S_FS output invalid
I2S_BCLK to I2S_TXD valid
I2S_BCLK to I2S_TXD invalid
I2S_RXD/I2S_FS input setup before I2S_BCLK
I2S_RXD/I2S_FS input hold after I2S_BCLK
55%
15
BCLK period
ns
ns
ns
ns
ns
ns
-2.5
—
—
15
-3
—
20
—
0
—
S1
S2
S2
I2S_MCLK (output)
I2S_BCLK (output)
I2S_FS (output)
I2S_FS (input)
I2S_TXD
S3
S4
S4
S5
S6
S10
S9
S7
S8
S7
S8
S9
S10
I2S_RXD
Figure 26. I2S timing — master mode
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
62
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 47. I2S slave mode timing (limited voltage range)
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
—
V
S11
S12
S13
S14
S15
S16
S17
S18
I2S_BCLK cycle time (input)
8 x tSYS
ns
I2S_BCLK pulse width high/low (input)
I2S_FS input setup before I2S_BCLK
I2S_FS input hold after I2S_BCLK
I2S_BCLK to I2S_TXD/I2S_FS output valid
I2S_BCLK to I2S_TXD/I2S_FS output invalid
I2S_RXD setup before I2S_BCLK
I2S_RXD hold after I2S_BCLK
45%
10
3
55%
—
MCLK period
ns
ns
ns
ns
ns
ns
—
—
0
20
—
10
2
—
—
S11
S12
I2S_BCLK (input)
I2S_FS (output)
I2S_FS (input)
I2S_TXD
S12
S15
S16
S13
S14
S15
S16
S15
S16
S17
S18
I2S_RXD
Figure 27. I2S timing — slave modes
Table 48. I2S master mode timing (full voltage range)
Num
Description
Min.
1.71
2 x tSYS
45%
5 x tSYS
45%
—
Max.
Unit
Operating voltage
3.6
V
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
I2S_MCLK cycle time
ns
I2S_MCLK pulse width high/low
I2S_BCLK cycle time
55%
—
MCLK period
ns
I2S_BCLK pulse width high/low
I2S_BCLK to I2S_FS output valid
I2S_BCLK to I2S_FS output invalid
I2S_BCLK to I2S_TXD valid
55%
15
BCLK period
ns
ns
ns
ns
ns
ns
-4.3
—
—
15
I2S_BCLK to I2S_TXD invalid
I2S_RXD/I2S_FS input setup before I2S_BCLK
I2S_RXD/I2S_FS input hold after I2S_BCLK
-4.6
—
23.9
0
—
—
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
63
Peripheral operating requirements and behaviors
Table 49. I2S slave mode timing (full voltage range)
Num
Description
Min.
1.71
8 x tSYS
45%
10
Max.
3.6
—
Unit
Operating voltage
V
S11
S12
S13
S14
S15
S16
S17
S18
I2S_BCLK cycle time (input)
ns
I2S_BCLK pulse width high/low (input)
I2S_FS input setup before I2S_BCLK
I2S_FS input hold after I2S_BCLK
I2S_BCLK to I2S_TXD/I2S_FS output valid
I2S_BCLK to I2S_TXD/I2S_FS output invalid
I2S_RXD setup before I2S_BCLK
I2S_RXD hold after I2S_BCLK
55%
—
MCLK period
ns
ns
ns
ns
ns
ns
3.5
—
—
28.6
—
0
10
—
2
—
6.9 Human-machine interfaces (HMI)
6.9.1 TSI electrical specifications
Table 50. TSI electrical specifications
Symbol Description
VDDTSI Operating voltage
CELE Target electrode capacitance range
Min.
1.71
1
Typ.
—
Max.
3.6
Unit
V
Notes
20
500
12.7
4.0
pF
1
2
3
fREFmax Reference oscillator frequency
fELEmax Electrode oscillator frequency
—
5.5
0.5
1
MHz
MHz
pF
—
CREF
VDELTA
IREF
Internal reference capacitor
Oscillator delta voltage
0.5
100
1.2
600
760
mV
μA
4
Reference oscillator current source base current
• 1uA setting (REFCHRG=0)
3 , 5
—
—
1.133
36
1.5
50
• 32uA setting (REFCHRG=31)
IELE
Electrode oscillator current source base current
• 1uA setting (EXTCHRG=0)
μA
3 , 6
—
—
1.133
36
1.5
50
• 32uA setting (EXTCHRG=31)
Pres5
Electrode capacitance measurement precision
—
8.3333
8.3333
8.3333
12.5
—
38400
38400
38400
—
fF/count
fF/count
fF/count
fF/count
bits
7
8
Pres20 Electrode capacitance measurement precision
Pres100 Electrode capacitance measurement precision
MaxSens Maximum sensitivity
—
—
9
0.003
—
10
Res
Resolution
16
TCon20
Response time @ 20 pF
8
15
25
μs
11
12
ITSI_RUN Current added in run mode
ITSI_LP Low power mode current adder
—
55
—
μA
—
1.3
2.5
μA
1. The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed.
2. CAPTRM=7, DELVOL=7, and fixed external capacitance of 20 pF.
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
64
Freescale Semiconductor, Inc.
Dimensions
3. CAPTRM=0, DELVOL=2, and fixed external capacitance of 20 pF.
4. CAPTRM=0, EXTCHRG=9, and fixed external capacitance of 20 pF.
5. The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current.
6. The programmable current source value is generated by multiplying the SCANC[EXTCHRG] value and the base current.
7. Measured with a 5 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 8; Iext = 16.
8. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 2; Iext = 16.
9. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 16, NSCN = 3; Iext = 16.
10. Sensitivity defines the minimum capacitance change when a single count from the TSI module changes, it is equal to (Cref
* Iext)/( Iref * PS * NSCN). Sensitivity depends on the configuration used. The typical value listed is based on the following
configuration: Iext = 5 μA, EXTCHRG = 4, PS = 128, NSCN = 2, Iref = 16 μA, REFCHRG = 15, Cref = 1.0 pF. The
minimum sensitivity describes the smallest possible capacitance that can be measured by a single count (this is the best
sensitivity but is described as a minimum because it’s the smallest number). The minimum sensitivity parameter is based
on the following configuration: Iext = 1 μA, EXTCHRG = 0, PS = 128, NSCN = 32, Iref = 32 μA, REFCHRG = 31, Cref= 0.5
pF
11. Time to do one complete measurement of the electrode. Sensitivity resolution of 0.0133 pF, PS = 0, NSCN = 0, 1
electrode, DELVOL = 2, EXTCHRG = 15.
12. CAPTRM=7, DELVOL=2, REFCHRG=0, EXTCHRG=4, PS=7, NSCN=0F, LPSCNITV=F, LPO is selected (1 kHz), and
fixed external capacitance of 20 pF. Data is captured with an average of 7 periods window.
7 Dimensions
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to freescale.com and perform a keyword search for the
drawing’s document number:
If you want the drawing for this package
80-pin LQFP
Then use this document number
98ASS23174W
98ASA00344D
81-pin MAPBGA
8 Pinout
8.1 K20 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
65
Pinout
NOTE
The 81-pin ballmap assignments are currently being developed.
The • in the entries in this package column indicate which
signals are present on the package.
81
80
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
MAP
BGA
LQFP
E4
E3
1
2
PTE0
ADC1_SE4a
ADC1_SE5a
ADC1_SE4a
ADC1_SE5a
PTE0
SPI1_PCS1
SPI1_SOUT
UART1_TX
UART1_RX
SDHC0_D1
SDHC0_D0
I2C1_SDA
I2C1_SCL
PTE1/
PTE1/
LLWU_P0
LLWU_P0
E2
F4
3
4
PTE2/
LLWU_P1
ADC1_SE6a
ADC1_SE7a
ADC1_SE6a
ADC1_SE7a
PTE2/
LLWU_P1
SPI1_SCK
SPI1_SIN
UART1_CTS_
b
SDHC0_DCLK
SDHC0_CMD
PTE3
PTE3
UART1_RTS_
b
E7
F7
H7
—
—
5
VDD
VSS
VDD
VDD
VSS
VSS
PTE4/
LLWU_P2
DISABLED
PTE4/
LLWU_P2
SPI1_PCS0
SPI1_PCS2
UART3_TX
UART3_RX
SDHC0_D3
SDHC0_D2
G4
E6
G7
L6
6
7
PTE5
DISABLED
VDD
PTE5
VDD
VDD
8
VSS
VSS
VSS
—
9
VSS
VSS
VSS
F1
F2
G1
G2
K1
USB0_DP
USB0_DM
VOUT33
VREGIN
USB0_DP
USB0_DM
VOUT33
VREGIN
USB0_DP
USB0_DM
VOUT33
VREGIN
10
11
12
13
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DP/
ADC0_DP0/
ADC1_DP3
K2
L1
L2
14
15
16
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
F5
G5
G6
F6
L3
17
18
19
20
21
VDDA
VREFH
VREFL
VSSA
VDDA
VREFH
VREFL
VSSA
VDDA
VREFH
VREFL
VSSA
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
66
Freescale Semiconductor, Inc.
Pinout
81
80
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
MAP
BGA
LQFP
K5
22
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
L4
L5
K6
J6
23
24
25
26
XTAL32
EXTAL32
VBAT
XTAL32
EXTAL32
VBAT
XTAL32
EXTAL32
VBAT
PTA0
JTAG_TCLK/
SWD_CLK/
EZP_CLK
TSI0_CH1
PTA0
UART0_CTS_
b
FTM0_CH5
JTAG_TCLK/
SWD_CLK
EZP_CLK
H8
J7
27
28
PTA1
PTA2
JTAG_TDI/
EZP_DI
TSI0_CH2
TSI0_CH3
PTA1
PTA2
UART0_RX
UART0_TX
FTM0_CH6
FTM0_CH7
JTAG_TDI
EZP_DI
JTAG_TDO/
TRACE_SWO/
EZP_DO
JTAG_TDO/
TRACE_SWO
EZP_DO
H9
J8
29
30
31
PTA3
JTAG_TMS/
SWD_DIO
TSI0_CH4
TSI0_CH5
PTA3
UART0_RTS_
b
FTM0_CH0
FTM0_CH1
FTM0_CH2
JTAG_TMS/
SWD_DIO
PTA4/
LLWU_P3
NMI_b/
EZP_CS_b
PTA4/
LLWU_P3
NMI_b
EZP_CS_b
K7
PTA5
DISABLED
PTA5
CMP2_OUT
I2S0_RX_
BCLK
JTAG_TRST
E5
G3
K8
—
—
32
VDD
VDD
VDD
VSS
VSS
VSS
PTA12
CMP2_IN0
CMP2_IN0
PTA12
CAN0_TX
CAN0_RX
SPI0_PCS0
FTM1_CH0
FTM1_CH1
UART0_TX
UART0_RX
I2S0_TXD
FTM1_QD_
PHA
L8
K9
33
34
PTA13/
LLWU_P4
CMP2_IN1
DISABLED
CMP2_IN1
PTA13/
LLWU_P4
I2S0_TX_FS
FTM1_QD_
PHB
PTA14
PTA14
I2S0_TX_
BCLK
L9
35
36
PTA15
PTA16
DISABLED
DISABLED
PTA15
PTA16
SPI0_SCK
I2S0_RXD
J10
SPI0_SOUT
UART0_CTS_
b
I2S0_RX_FS
H10
37
PTA17
ADC1_SE17
ADC1_SE17
PTA17
SPI0_SIN
UART0_RTS_
b
I2S0_MCLK
LPT0_ALT1
I2S0_CLKIN
L10
K10
L11
K11
J11
G11
38
39
40
41
42
43
VDD
VDD
VDD
VSS
VSS
VSS
PTA18
PTA19
RESET_b
EXTAL
XTAL
EXTAL
XTAL
PTA18
PTA19
FTM0_FLT2
FTM1_FLT0
FTM_CLKIN0
FTM_CLKIN1
RESET_b
RESET_b
PTB0/
LLWU_P5
ADC0_SE8/
ADC1_SE8/
TSI0_CH0
ADC0_SE8/
ADC1_SE8/
TSI0_CH0
PTB0/
LLWU_P5
I2C0_SCL
I2C0_SDA
I2C0_SCL
FTM1_CH0
FTM1_CH1
FTM1_QD_
PHA
G10
G9
44
45
PTB1
PTB2
ADC0_SE9/
ADC1_SE9/
TSI0_CH6
ADC0_SE9/
ADC1_SE9/
TSI0_CH6
PTB1
PTB2
FTM1_QD_
PHB
ADC0_SE12/
TSI0_CH7
ADC0_SE12/
TSI0_CH7
UART0_RTS_
b
FTM0_FLT3
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
67
Pinout
81
80
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
MAP
BGA
LQFP
G8
46
PTB3
ADC0_SE13/
TSI0_CH8
ADC0_SE13/
TSI0_CH8
PTB3
I2C0_SDA
UART0_CTS_
b
FTM0_FLT0
D10
C10
—
47
48
49
50
51
52
53
PTB10
PTB11
VSS
ADC1_SE14
ADC1_SE15
VSS
ADC1_SE14
ADC1_SE15
VSS
PTB10
PTB11
SPI1_PCS0
SPI1_SCK
UART3_RX
UART3_TX
FB_AD19
FB_AD18
FTM0_FLT1
FTM0_FLT2
—
VDD
VDD
VDD
B10
E9
PTB16
PTB17
PTB18
TSI0_CH9
TSI0_CH10
TSI0_CH11
TSI0_CH9
TSI0_CH10
TSI0_CH11
PTB16
PTB17
PTB18
SPI1_SOUT
SPI1_SIN
CAN0_TX
UART0_RX
UART0_TX
FTM2_CH0
FB_AD17
FB_AD16
FB_AD15
EWM_IN
EWM_OUT_b
D9
I2S0_TX_
BCLK
FTM2_QD_
PHA
C9
B9
D8
C8
54
55
56
57
PTB19
PTC0
TSI0_CH12
TSI0_CH12
PTB19
PTC0
CAN0_RX
FTM2_CH1
I2S0_TX_FS
FB_OE_b
FB_AD14
FB_AD13
FB_AD12
FTM2_QD_
PHB
ADC0_SE14/
TSI0_CH13
ADC0_SE14/
TSI0_CH13
SPI0_PCS4
SPI0_PCS3
SPI0_PCS2
PDB0_EXTRG I2S0_TXD
PTC1/
LLWU_P6
ADC0_SE15/
TSI0_CH14
ADC0_SE15/
TSI0_CH14
PTC1/
LLWU_P6
UART1_RTS_
b
FTM0_CH0
FTM0_CH1
PTC2
ADC0_SE4b/
CMP1_IN0/
TSI0_CH15
ADC0_SE4b/
CMP1_IN0/
TSI0_CH15
PTC2
UART1_CTS_
b
B8
58
PTC3/
LLWU_P7
CMP1_IN1
CMP1_IN1
PTC3/
LLWU_P7
SPI0_PCS1
UART1_RX
UART1_TX
FTM0_CH2
FB_CLKOUT
—
—
59
60
61
VSS
VDD
VSS
VDD
VSS
VDD
A8
PTC4/
LLWU_P8
PTC4/
LLWU_P8
SPI0_PCS0
SPI0_SCK
SPI0_SOUT
SPI0_SIN
FTM0_CH3
LPT0_ALT2
FB_AD11
FB_AD10
FB_AD9
CMP1_OUT
CMP0_OUT
D7
C7
62
63
PTC5/
LLWU_P9
PTC5/
LLWU_P9
PTC6/
LLWU_P10
CMP0_IN0
CMP0_IN1
CMP0_IN0
CMP0_IN1
PTC6/
LLWU_P10
PDB0_EXTRG
I2S0_MCLK
B7
A7
64
65
PTC7
PTC8
PTC7
PTC8
FB_AD8
FB_AD7
ADC1_SE4b/
CMP0_IN2
ADC1_SE4b/
CMP0_IN2
I2S0_CLKIN
D6
C6
C5
66
67
68
PTC9
ADC1_SE5b/
CMP0_IN3
ADC1_SE5b/
CMP0_IN3
PTC9
I2S0_RX_
BCLK
FB_AD6
FB_AD5
FB_RW_b
FTM2_FLT0
PTC10
ADC1_SE6b/
CMP0_IN4
ADC1_SE6b/
CMP0_IN4
PTC10
I2C1_SCL
I2C1_SDA
I2S0_RX_FS
PTC11/
ADC1_SE7b
ADC1_SE7b
PTC11/
I2S0_RXD
LLWU_P11
LLWU_P11
—
—
69
70
71
VSS
VSS
VDD
VSS
VDD
VDD
D5
PTC16
PTC16
PTC17
CAN1_RX
CAN1_TX
UART3_RX
UART3_TX
FB_CS5_b/
FB_TSIZ1/
FB_BE23_16_
b
C4
72
PTC17
FB_CS4_b/
FB_TSIZ0/
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
68
Freescale Semiconductor, Inc.
Pinout
81
80
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
MAP
BGA
LQFP
FB_BE31_24_
b
D4
73
PTD0/
LLWU_P12
PTD0/
LLWU_P12
SPI0_PCS0
UART2_RTS_
b
FB_ALE/
FB_CS1_b/
FB_TS_b
D3
C3
74
75
PTD1
ADC0_SE5b
ADC0_SE5b
PTD1
SPI0_SCK
UART2_CTS_
b
FB_CS0_b
PTD2/
PTD2/
SPI0_SOUT
UART2_RX
FB_AD4
LLWU_P13
LLWU_P13
B3
A3
76
77
PTD3
PTD3
SPI0_SIN
UART2_TX
FB_AD3
FB_AD2
PTD4/
LLWU_P14
PTD4/
LLWU_P14
SPI0_PCS1
UART0_RTS_
b
FTM0_CH4
FTM0_CH5
FTM0_CH6
FTM0_CH7
EWM_IN
A2
B2
78
79
PTD5
ADC0_SE6b
ADC0_SE7b
ADC0_SE6b
ADC0_SE7b
PTD5
SPI0_PCS2
SPI0_PCS3
CMT_IRO
UART0_CTS_
b
FB_AD1
FB_AD0
EWM_OUT_b
FTM0_FLT0
FTM0_FLT1
PTD6/
LLWU_P15
PTD6/
LLWU_P15
UART0_RX
A1
L7
80
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PTD7
RESERVED
NC
PTD7
UART0_TX
RESERVED
NC
RESERVED
NC
A11
B11
C11
K3
NC
NC
NC
NC
NC
NC
NC
NC
NC
H4
F3
NC
NC
NC
NC
NC
NC
H1
H2
J1
NC
NC
NC
NC
NC
NC
NC
NC
NC
J2
NC
NC
NC
J3
NC
NC
NC
H3
K4
NC
NC
NC
NC
NC
NC
H5
J5
NC
NC
NC
NC
NC
NC
H6
J9
NC
NC
NC
NC
NC
NC
J4
NC
NC
NC
H11
F11
E11
D11
E10
F10
F9
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
69
Pinout
81
80
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
MAP
BGA
LQFP
F8
E8
B6
A6
A5
B5
B4
A4
A10
A9
B1
C2
C1
D2
D1
E1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
8.2 K20 Pinouts
The below figure shows the pinout diagram for the devices supported by this document.
Many signals may be multiplexed onto a single pin. To determine what signals can be
used on which pin, see the previous section.
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
70
Freescale Semiconductor, Inc.
Pinout
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
H
J
PTD7
PTD5
PTD4
NC
NC
NC
PTC8
PTC4
NC
NC
NC
A
B
C
D
E
F
G
H
J
NC
NC
PTD6
NC
PTD3
PTD2
PTD1
PTE1
NC
NC
PTC17
PTD0
PTE0
PTE3
PTE5
NC
NC
PTC11
PTC16
VDD
NC
PTC10
PTC9
VDD
PTC7
PTC6
PTC5
VDD
PTC3
PTC2
PTC1
NC
PTC0
PTB19
PTB18
PTB17
NC
PTB16
PTB11
PTB10
NC
NC
NC
NC
NC
NC
NC
PTE2
USB0_DM
VREGIN
NC
NC
USB0_DP
VOUT33
NC
VDDA
VREFH
NC
VSSA
VREFL
NC
VSS
NC
NC
NC
VSS
NC
VSS
PTB3
PTA1
PTA4
PTA12
PTB2
PTA3
NC
PTB1
PTA17
PTA16
VSS
PTB0
NC
PTE4
PTA2
PTA5
NC
NC
NC
NC
NC
PTA0
VBAT
RESET_b
PTA19
PGA0_DP/
PGA0_DM/
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
ADC0_DP0/ ADC0_DM0/
ADC1_DP3 ADC1_DM3
K
L
NC
NC
PTA14
K
L
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
PGA1_DP/
PGA1_DM/
ADC1_DP0/ ADC1_DM0/
ADC0_DP3 ADC0_DM3
XTAL32
4
EXTAL32
5
VSS
6
RESERVED
7
PTA13
8
PTA15
9
VDD
10
PTA18
11
1
2
3
Figure 28. K20 81 MAPBGA Pinout Diagram
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
71
Revision History
1
PTE0
PTE1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
VDD
2
VSS
3
PTE2
PTC3
PTC2
PTC1
PTC0
PTB19
PTB18
PTB17
PTB16
VDD
4
PTE3
5
PTE4
6
PTE5
7
VDD
8
VSS
9
USB0_DP
10
11
12
13
14
15
16
17
18
19
20
USB0_DM
VOUT33
VREGIN
PGA0_DP/ADC0_DP0/ADC1_DP3
PGA0_DM/ADC0_DM0/ADC1_DM3
PGA1_DP/ADC1_DP0/ADC0_DP3
PGA1_DM/ADC1_DM0/ADC0_DM3
VDDA
VSS
PTB11
PTB10
PTB3
PTB2
PTB1
PTB0
RESET_b
PTA19
VREFH
VREFL
VSSA
Figure 29. K20 80 LQFP Pinout Diagram
9 Revision History
The following table provides a revision history for this document.
Table 51. Revision History
Rev. No.
Date
Substantial Changes
1
11/2010
Initial public revision
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
72
Freescale Semiconductor, Inc.
Revision History
Table 51. Revision History (continued)
Rev. No.
Date
Substantial Changes
2
3/2011
Many updates throughout
Corrected 81- and 104-pin package codes
Added sections that were inadvertently removed in previous revision
3
4
3/2011
3/2011
Reworded IIC footnote in "Voltage and Current Operating Requirements" table.
Added paragraph to "Peripheral operating requirements and behaviors" section.
Added "JTAG full voltage range electricals" table to the "JTAG electricals" section.
5
6/2011
• Changed supported part numbers per new part number scheme
• Changed DC injection current specs in "Voltage and current operating requirements"
table
• Changed Input leakage current and internal pullup/pulldown resistor specs in "Voltage
and current operating behaviors" table
• Split Low power stop mode current specs by temperature range in "Power
consumption operating behaviors" table
• Changed typical IDD_VBAT spec in "Power consumption operating behaviors" table
• Added LPTMR clock specs to "Device clock specifications" table
• Changed Minimum external reset pulse width in "General switching specifications"
table
• Changed PLL operating current in "MCG specifications" table
• Added footnote to PLL period jitter in "MCG specifications" table
• Changed Supply current in "Oscillator DC electrical specifications" table
• Changed Crystal startup time in "Oscillator frequency specifications" table
• Changed Operating voltage in "EzPort switching specifications" table
• Changed title of "FlexBus switching specifications" table and added Output valid and
hold specs
• Added "FlexBus full range switching specifications" table
• Changed ADC asynchronous clock source specs in "16-bit ADC characteristics" table
• Changed Gain spec in "16-bit ADC with PGA characteristics" table
• Added typical Input DC current to "16-bit ADC with PGA characteristics" table
• Changed Input offset voltage and ENOB notes field in "16-bit ADC with PGA
characteristics" table
• Changed Analog comparator initialization delay in "Comparator and 6-bit DAC
electrical specifications"
• Changed Code-to-code settling time, DAC output voltage range low, and Temperature
coefficient offset voltage in "12-bit DAC operating behaviors" table
• Changed Temperature drift and Load regulation in "VREF full-range operating
behaviors" table
• Changed Regulator output voltage in "USB VREG electrical specifications" table
• Changed ILIM description and specs in "USB VREG electrical specifications" table
• Changed DSPI_SCK cycle time specs in "DSPI timing" tables
• Changed DSPI_SS specs in "Slave mode DSPI timing (low-speed mode)" table
• Changed DSPI_SCK to DSPI_SOUT valid spec in "Slave mode DSPI timing (high-
speed mode)" table
• Changed Reference oscillator current source base current spec and added Low-power
current adder footer in "TSI electrical specifications" table
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
73
Revision History
Table 51. Revision History (continued)
Rev. No.
Date
Substantial Changes
6
01/2012
• Added AC electrical specifications.
• Replaced TBDs with silicon data throughout.
• In "Power mode transition operating behaviors" table, removed entry times.
• Updated "EMC radiated emissions operating behaviors" to remove SAE level and also
added data for 144LQFP.
• Clarified "EP7" in "EzPort switching specifications" table and "EzPort Timing Diagram".
• Added "ENOB vs. ADC_CLK for 16-bit differential and 16-bit single-ended modes"
figures.
• Updated IDD_RUN numbers in 'Power consumption operating behaviors' section.
• Clarified 'Diagram: Typical IDD_RUN operating behavior' section and updated 'Run
mode supply current vs. core frequency — all peripheral clocks disabled' figure.
• In 'Voltage reference electrical specifications' section, updated CL, Vtdrift, and Vvdrift
values.
• In 'USB electrical specifications' section, updated VDP_SRC, IDDstby, and 'VReg33out
values.
7
02/2013
• In "ESD handling ratings", added a note for ILAT.
• Updated "Voltage and current operating requirements".
• Updated "Voltage and current operating behaviors".
• Updated "Power mode transition operating behaviors".
• Updated "EMC radiated emissions operating behaviors" to add MAPBGA data.
• In "MCG specifications", updated the description of fints_t
.
• In "16-bit ADC operating conditions", updated the max spec of VADIN
.
• In "16-bit ADC electrical characteristics", updated the temp sensor slope and voltage
specs.
• Updated "I2C switching specifications".
• In "SDHC specifications", removed the operating voltage limits and updated the SD1
and SD6 specs.
• In "I2S switching specifications", added separate specification tables for the full
operating voltage range.
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
74
Freescale Semiconductor, Inc.
Information in this document is provided solely to enable system and software
implementers to use Freescale Semiconductors products. There are no express or implied
copyright licenses granted hereunder to design or fabricate any integrated circuits or
integrated circuits based on the information in this document.
How to Reach Us:
Home Page:
www.freescale.com
Freescale Semiconductor reserves the right to make changes without further notice to any
products herein. Freescale Semiconductor makes no warranty, representation, or
guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale Semiconductor assume any liability arising out of the application or use of any
product or circuit, and specifically disclaims any liability, including without limitation
consequential or incidental damages. "Typical" parameters that may be provided in
Freescale Semiconductor data sheets and/or specifications can and do vary in different
applications and actual performance may vary over time. All operating parameters,
including "Typicals", must be validated for each customer application by customer's
technical experts. Freescale Semiconductor does not convey any license under its patent
rights nor the rights of others. Freescale Semiconductor products are not designed,
intended, or authorized for use as components in systems intended for surgical implant
into the body, or other applications intended to support or sustain life, or for any other
application in which failure of the Freescale Semiconductor product could create a
situation where personal injury or death may occur. Should Buyer purchase or use
Freescale Semiconductor products for any such unintended or unauthorized application,
Buyer shall indemnify Freescale Semiconductor and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury
or death associated with such unintended or unauthorized use, even if such claims alleges
that Freescale Semiconductor was negligent regarding the design or manufacture of
the part.
Web Support:
http://www.freescale.com/support
USA/Europe or Locations Not Listed:
Freescale Semiconductor
Technical Information Center, EL516
2100 East Elliot Road
Tempe, Arizona 85284
+1-800-521-6274 or +1-480-768-2130
www.freescale.com/support
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
www.freescale.com/support
RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and
electrical characteristics as their non-RoHS-complaint and/or non-Pb-free counterparts.
For further information, see http://www.freescale.com or contact your Freescale
sales representative.
Japan:
For information on Freescale's Environmental Products program, go to
http://www.freescale.com/epp.
Freescale Semiconductor Japan Ltd.
Headquarters
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
All other product or service names are the property of their respective owners.
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku,
Tokyo 153-0064
© 2011–2013 Freescale Semiconductor, Inc.
Japan
0120 191014 or +81 3 5437 9125
support.japan@freescale.com
Asia/Pacific:
Freescale Semiconductor China Ltd.
Exchange Building 23F
No. 118 Jianguo Road
Chaoyang District
Beijing 100022
China
+86 10 5879 8000
support.asia@freescale.com
Document Number: K20P81M100SF2
Rev. 7, 02/2013
相关型号:
©2020 ICPDF网 联系我们和版权申明