MFRC63103HNTRAYB [NXP]
High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus;型号: | MFRC63103HNTRAYB |
厂家: | NXP |
描述: | High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus |
文件: | 总149页 (文件大小:1444K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MFRC631
High-performance ISO/IEC 14443 A/B frontend MFRC631 and
MFRC631 plus
Rev. 4.5 — 12 September 2018
227445
Product data sheet
COMPANY PUBLIC
1 General description
MFRC631, the cost efficient NFC frontend for payment.
The MFRC631 multi-protocol NFC frontend IC supports the following operating modes:
• Read/write mode supporting ISO/IEC 14443 type A and MIFARE Classic
communication mode
• Read/write mode supporting ISO/IEC 14443B
The MFRC631’s internal transmitter is able to drive a reader/writer antenna designed
to communicate with ISO/IEC 14443A and MIFARE Classic IC-based cards and
transponders without additional active circuitry. The digital module manages the
complete ISO/IEC 14443A framing and error detection functionality (parity and CRC).
The MFRC631 supports MIFARE Classic with 1 kB memory, MIFARE Classic with 4 kB
memory, MIFARE Ultralight, MIFARE Ultralight C, MIFARE Plus and MIFARE DESFire
products. The MFRC631 supports higher transfer speeds of the MIFARE product family
up to 848 kbit/s in both directions.
The MFRC631 supports layer 2 and 3 of the ISO/IEC 14443B reader/writer
communication scheme except anticollision. The anticollision needs to be implemented in
the firmware of the host controller as well as in the upper layers.
The following host interfaces are supported:
• Serial Peripheral Interface (SPI)
• Serial UART (similar to RS232 with voltage levels dependent on pin voltage supply)
• I2C-bus interface (two versions are implemented: I2C and I2CL)
The MFRC631 supports the connection of a secure access module (SAM). A dedicated
separate I2C interface is implemented for a connection of the SAM. The SAM can be
used for high secure key storage and acts as a very performant crypto coprocessor. A
dedicated SAM is available for connection to the MFRC631.
In this document the term „MIFARE Classic card“ refers to a MIFARE Classic IC-based
contactless card.
NXP Semiconductors
MFRC631
High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
2 Features and benefits
• Includes NXP ISO/IEC14443-A and Innovatron ISO/IEC14443-B intellectual property
licensing rights
• High-performance multi-protocol NFC frontend for transfer speed up to 848 kbit/s
• Supports ISO/IEC 14443 type A, MIFARE Classic and ISO/IEC 14443 B modes
• Supports MIFARE Classic product encryption by hardware in read/write mode
Allows reading cards based on MIFARE Ultralight, MIFARE Classic with 1 kB memory,
MIFARE Classic with 4 kB memory, MIFARE DESFire EV1, MIFARE DESFire EV2 and
MIFARE Plus ICs.
• Low-power card detection
• Compliance to "EMV contactless protocol specification V2.3.1" on RF level can be
achieved
• Antenna connection with minimum number of external components
• Supported host interfaces:
– SPI up to 10 Mbit/s
– I2C-bus interfaces up to 400 kBd in Fast mode, up to 1000 kBd in Fast mode plus
– RS232 Serial UART up to 1228.8 kBd, with voltage levels dependent on pin voltage
supply
• Separate I2C-bus interface for connection of a secure access module (SAM)
• FIFO buffer with size of 512 byte for highest transaction performance
• Flexible and efficient power saving modes including hard power down, standby and
low-power card detection
• Cost saving by integrated PLL to derive system clock from 27.12 MHz RF quartz crystal
• 3 V to 5.5 V power supply (MFRC63102)
2.5 V to 5.5 V power supply (MFRC63103)
• Up to 8 free programmable input/output pins
• Typical operating distance in read/write mode for communication to a ISO/IEC 14443
type A and MIFARE Classic card up to 12 cm, depending on the antenna size and
tuning
The version CLRC63103 offers a more flexible configuration for Low-Power Card
detection compared to the CLRC63102 with the new register LPCD_OPTIONS. In
addition, the CLRC63103 offers new additional settings for the Load Protocol which fit
very well to smaller antennas. The CLRC63103 is therefore the recommended version
for new designs.
MFRC631
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Product data sheet
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NXP Semiconductors
MFRC631
High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
3 Quick reference data
Table 1.ꢀQuick reference data MFRC63102HN
Symbol
VDD
Parameter
Conditions
Min
3.0
3.0
3.0
-
Typ
5.0
5.0
5.0
8
Max
5.5
VDD
5.5
40
Unit
V
supply voltage
[1]
[2]
VDD(PVDD)
VDD(TVDD)
Ipd
PVDD supply voltage
TVDD supply voltage
power-down current
supply current
V
V
PDOWN pin pulled HIGH
no supply voltage applied
nA
mA
mA
°C
IDD
-
17
20
IDD(TVDD)
Tamb
TVDD supply current
operating ambient temperature
storage temperature
-
100
+25
+25
250
+85
-25
-55
Tstg
+125 °C
[1] VDD(PVDD) must always be the same or lower voltage than VDD.
[2] Ipd is the sum of all supply currents
Table 2.ꢀQuick reference data MFRC63103HN
Symbol
VDD
Parameter
Conditions
Min
2.5
2.5
2.5
-
Typ
5.0
5.0
5.0
8
Max
5.5
VDD
5.5
40
Unit
supply voltage
V
[1]
[2]
VDD(PVDD)
VDD(TVDD)
Ipd
PVDD supply voltage
TVDD supply voltage
power-down current
supply current
V
V
PDOWN pin pulled HIGH
absolute limiting value
nA
mA
mA
mA
IDD
-
17
20
IDD(TVDD)
TVDD supply current
-
180
-
350
500
-
Tamb
Tstg
operating ambient temperature device mounted on PCB which
allows sufficient heat dissipation
-40
+25
+105 °C
storage temperature
no supply voltage applied
-55
+25
+125 °C
[1] VDD(PVDD) must always be the same or lower voltage than VDD.
[2] Ipd is the sum of all supply currents
MFRC631
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Product data sheet
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NXP Semiconductors
MFRC631
High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
4 Ordering information
Table 3.ꢀOrdering information
Type number
Package
Name
Description
Version
MFRC63102HN/TRAYBM[1] HVQFN32
MFRC63102HN/T/R[2]
plastic thermal enhanced very thin quad flat package; no
leads; MSL1, 32 terminals + 1 central ground; body 5 × 5 ×
0.85 mm
SOT617-1
MFRC63103HN/TRAYB[3]
MFRC63103HN/T/R[2]
plastic thermal enhanced very thin quad flat package; no
leads; MSL2, 32 terminals + 1 central ground; body 5 x 5 x
0.85 mm, wettable flanks
SOT617-1
[1] Delivered in five trays; MOQ: 5x 490 pcs
[2] Delivered on reel with 6000 pieces; MOQ: 6000 pcs
[3] Delivered in one tray, MOQ (Minimum order quantity) : 490 pcs
MFRC631
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NXP Semiconductors
MFRC631
High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
5 Block diagram
The analog interface handles the modulation and demodulation of the antenna signals for
the contactless interface.
The contactless UART manages the protocol dependency of the contactless interface
settings managed by the host.
The FIFO buffer ensures fast and convenient data transfer between host and the
contactless UART.
The register bank contains the settings for the analog and digital functionality.
REGISTER BANK
ANALOG
INTERFACE
CONTACTLESS
UART
ANTENNA
FIFO
BUFFER
SERIAL UART
SPI
I C-BUS
HOST
2
001aaj627
Figure 1.ꢀSimplified block diagram of the MFRC631
MFRC631
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NXP Semiconductors
MFRC631
High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
6 Pinning information
terminal 1
index area
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
TDO/OUT0
TDI/OUT1
TMS/OUT2
TCK/OUT3
SIGIN/OUT7
SIGOUT
SDA
(1)
SCL
CLKOUT/OUT6
PDOWN
XTAL2
XTAL1
TVDD
heatsink
DVDD
VDD
TX1
001aam004
Transparent top view
1. Pin 33 VSS - heatsink connection
Figure 2.ꢀPinning configuration HVQFN32 (SOT617-1)
6.1 Pin description
Table 4.ꢀPin description
Pin
1
Symbol
TDO / OUT0
TDI / OUT1
TMS / OUT2
TCK / OUT3
SIGIN /OUT7
SIGOUT
DVDD
Type
Description
O
test data output for boundary scan interface / general purpose output 0
test data input boundary scan interface / general purpose output 1
test mode select boundary scan interface / general purpose output 2
test clock boundary scan interface / general purpose output 3
Contactless communication interface output. / general purpose output 7
Contactless communication interface input.
2
I
3
I
4
I
5
I/O
O
6
7
PWR
PWR
PWR
O
digital power supply buffer [1]
8
VDD
power supply
analog power supply buffer [1]
9
AVDD
10
11
12
13
14
15
16
17
AUX1
auxiliary outputs: Pin is used for analog test signal
auxiliary outputs: Pin is used for analog test signal
receiver input pin for the received RF signal.
AUX2
O
RXP
I
RXN
I
receiver input pin for the received RF signal.
internal receiver reference voltage [1]
VMID
PWR
O
TX2
transmitter 2: delivers the modulated 13.56 MHz carrier
transmitter ground, supplies the output stage of TX1, TX2
transmitter 1: delivers the modulated 13.56 MHz carrier
TVSS
PWR
O
TX1
MFRC631
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NXP Semiconductors
MFRC631
High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
Pin
18
Symbol
TVDD
Type
Description
PWR
I
transmitter voltage supply
19
XTAL1
crystal oscillator input: Input to the inverting amplifier of the oscillator. This pin is
also the input for an externally generated clock (fosc = 27.12 MHz)
20
21
22
23
24
25
26
27
28
XTAL2
O
crystal oscillator output: output of the inverting amplifier of the oscillator
Power Down (RESET)
PDOWN
CLKOUT / OUT6
SCL
I
O
clock output / general purpose output 6
Serial Clock line
O
SDA
I/O
Serial Data Line
PVDD
PWR
pad power supply
IFSEL0 / OUT4
IFSEL1 / OUT5
IF0
I
host interface selection 0 / general purpose output 4
host interface selection 1 / general purpose output 5
I
I/O
interface pin, multifunction pin: Can be assigned to host interface RS232, SPI,
I2C, I2C-L
29
30
IF1
IF2
I/O
I/O
interface pin, multifunction pin: Can be assigned to host interface SPI, I2C, I2C-L
interface pin, multifunction pin: Can be assigned to host interface RS232, SPI,
I2C, I2C-L
31
IF3
I/O
interface pin, multifunction pin: Can be assigned to host interface RS232, SPI,
I2C, I2C-L
32
33
IRQ
O
interrupt request: output to signal an interrupt event
ground and heat sink connection
VSS
PWR
[1] This pin is used for connection of a buffer capacitor. Connection of a supply voltage might damage the device.
MFRC631
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NXP Semiconductors
MFRC631
High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
7 Functional description
SAM interface
2
SDA
SCL
I C,
FIFO
512 Bytes
EEPROM
8 kByte
LOGICAL
SPI
host interfaces
RESET
LOGIC
IFSEL1
IFSEL0
PDOWN
2
I C
IF0
IF1
IF2
IF3
REGISTERS
UART
SPI
STATEMACHINES
ANALOGUE FRONT-END
VDD
VSS
VOLTAGE
REGULATOR
3/5 V =>
1.8 V
VOLTAGE
REGULATOR
3/5 V =>
1.8 V
PVDD
TVDD
TVSS
AVDD
DVDD
TCK
TDI
TMS
TDO
BOUNDARY
SCAN
DVDD
AVDD
POR
ADC
RNG
PLL
TIMER4
(WAKE-UP
TIMER)
TX
CODEC
RX
DECOD
TIMER0..3
LFO
TX
CLKOUT
CL-
COPRO
AUX1
AUX2
SIGIN/
SIGOUT
CONTROL
INTERRUPT
CONTROLLER
CRC
SIGPRO
RX
OSC
RXP
VMID RXN
TX2
TX1
XTAL2
XTAL1
IRQ
SIGIN SIGOUT
001aam005
Figure 3.ꢀDetailed block diagram of the MFRC631
7.1 Interrupt controller
The interrupt controller handles the enabling/disabling of interrupt requests. All of the
interrupts can be configured by firmware. Additionally, the firmware has possibilities to
trigger interrupts or clear pending interrupt requests. Two 8-bit interrupt registers IRQ0
and IRQ1 are implemented, accompanied by two 8-bit interrupt enable registers IRQ0En
and IRQ1En. A dedicated functionality of bit 7 to set and clear bits 0 to 6 in this interrupt
controller registers is implemented.
The MFRC631 indicates certain events by setting bit IRQ in the register Status1Reg and
additionally, if activated, by pin IRQ. The signal on pin IRQ may be used to interrupt the
host using its interrupt handling capabilities. This allows the implementation of efficient
host software.
Table 4. shows the available interrupt bits, the corresponding source and the condition
for its activation. The interrupt bits Timer0IRQ, Timer1IRQ, Timer2IRQ, Timer3OIRQ, in
register IRQ1 indicate an interrupt set by the timer unit. The setting is done if the timer
underflows.
MFRC631
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NXP Semiconductors
MFRC631
High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
The TxIRQ bit in register IRQ0 indicates that the transmission is finished. If the state
changes from sending data to transmitting the end of the frame pattern, the transmitter
unit sets the interrupt bit automatically.
The bit RxIRQ in register IRQ0 indicates an interrupt when the end of the received data is
detected.
The bit IdleIRQ in register IRQ0 is set if a command finishes and the content of the
command register changes to idle.
The register WaterLevel defines both - minimum and maximum warning levels - counting
from top and from bottom of the FIFO by a single value.
The bit HiAlertIRQ in register IRQ0 is set to logic 1 if the HiAlert bit is set to logic 1, that
means the FIFO data number has reached the top level as configured by the register
WaterLevel and bit WaterLevelExtBit.
The bit LoAlertIRQ in register IRQ0 is set to logic 1 if the LoAlert bit is set to logic 1, that
means the FIFO data number has reached the bottom level as configured by the register
WaterLevel.
The bit ErrIRQ in register IRQ0 indicates an error detected by the contactless UART
during receive. This is indicated by any bit set to logic 1 in register Error.
The bit LPCDIRQ in register IRQ0 indicates a card detected.
The bit RxSOFIRQ in register IRQ0 indicates a detection of a SOF or a subcarrier by the
contactless UART during receiving.
The bit GlobalIRQ in register IRQ1 indicates an interrupt occurring at any other interrupt
source when enabled.
Table 5.ꢀInterrupt sources
Interrupt bit
Timer0IRQ
Timer1IRQ
Timer2IRQ
Timer3IRQ
TxIRQ
Interrupt source
Timer Unit
Is set automatically, when
the timer register T0 CounterVal underflows
the timer register T1 CounterVal underflows
the timer register T2 CounterVal underflows
the timer register T3 CounterVal underflows
a transmitted data stream ends
Timer Unit
Timer Unit
Timer Unit
Transmitter
RxIRQ
Receiver
a received data stream ends
IdleIRQ
Command Register
FIFO-buffer pointer
a command execution finishes
HiAlertIRQ
the FIFO data number has reached the top level as
configured by the register WaterLevel
LoAlertIRQ
FIFO-buffer pointer
the FIFO data number has reached the bottom level as
configured by the register WaterLevel
ErrIRQ
contactless UART
LPCD
a communication error had been detected
LPCDIRQ
a card was detected when in low-power card detection
mode
RxSOFIRQ
GlobalIRQ
Receiver
detection of a SOF or a subcarrier
all interrupt sources
will be set if another interrupt request source is set
MFRC631
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MFRC631
High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
7.2 Timer module
Timer module overview
The MFRC631 implements five timers. Four timers -Timer0 to Timer3 - have an input
clock that can be configured by register T(x)Control to be 13.56 MHz, 212 kHz, (derived
from the 27.12 MHz quartz) or to be the underflow event of the fifth Timer (Timer4). Each
timer implements a counter register which is 16 bit wide. A reload value for the counter
is defined in a range of 0000h to FFFFh in the registers TxReloadHi and TxReloadLo.
The fifth timer Timer4 is intended to be used as a wakeup timer and is connected to the
internal LFO (Low Frequency Oscillator) as input clock source.
The TControl register allows the global start and stop of each of the four timers Timer0
to Timer3. Additionally, this register indicates if one of the timers is running or stopped.
Each of the five timers implements an individual configuration register set defining timer
reload value (e.g. T0ReloadHi,T0ReloadLo), the timer value (e.g. T0CounterValHi,
T0CounterValLo) and the conditions which define start, stop and clockfrequency (e.g.
T0Control).
The external host may use these timers to manage timing relevant tasks. The timer unit
may be used in one of the following configurations:
• Time-out counter
• Watch-dog counter
• Stop watch
• Programmable one-shot timer
• Periodical trigger
The timer unit can be used to measure the time interval between two events or to
indicate that a specific event has occurred after an elapsed time. The timer register
content is modified by the timer unit, which can be used to generate an interrupt to allow
an host to react on this event.
The counter value of the timer is available in the registers T(x)CounterValHi,
T(x)CounterValLo. The content of these registers is decremented at each timer clock.
If the counter value has reached a value of 0000h and the interrupts are enabled for this
specific timer, an interrupt will be generated as soon as the next clock is received.
If enabled, the timer event can be indicated on the pin IRQ (interrupt request). The bit
Timer(x)IRQ can be set and reset by the host controller. Depending on the configuration,
the timer will stop counting at 0000h or restart with the value loaded from registers
T(x)ReloadHi, T(x)ReloadLo.
The counting of the timer is indicated by bit TControl.T(x)Running.
The timer can be started by setting bits TControl.T(x)Running and
TControl.T(x)StartStopNow or stopped by setting the bits TControl.T(x)StartStopNow and
clearing TControl.T(x)Running.
Another possibility to start the timer is to set the bit T(x)Mode.T(x)Start, this can be useful
if dedicated protocol requirements need to be fulfilled.
7.2.1 Timer modes
MFRC631
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MFRC631
High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
7.2.1.1 Time-Out- and Watch-Dog-Counter
Having configured the timer by setting register T(x)ReloadValue and starting the counting
of Timer(x) by setting bit TControl.T(x)StartStop and TControl.T(x)Running, the timer unit
decrements the T(x)CounterValue Register beginning with the configured start event. If
the configured stop event occurs before the Timer(x) underflows (e.g. a bit is received
from the card), the timer unit stops (no interrupt is generated).
If no stop event occurs, the timer unit continues to decrement the counter registers
until the content is zero and generates a timer interrupt request at the next clock cycle.
This allows to indicate to a host that the event did not occur during the configured time
interval.
7.2.1.2 Wake-up timer
The wake-up Timer4 allows to wakeup the system from standby after a predefined time.
The system can be configured in such a way that it is entering the standby mode again in
case no card had been detected.
This functionality can be used to implement a low-power card detection (LPCD). For
the low-power card detection it is recommended to set T4Control.T4AutoWakeUp and
T4Control.T4AutoRestart, to activate the Timer4 and automatically set the system
in standby. The internal low frequency oscillator (LFO) is then used as input clock
for this Timer4. If a card is detected the host-communication can be started. If bit
T4Control.T4AutoWakeUp is not set, the MFRC631 will not enter the standby mode
again in case no card is detected but stays fully powered.
7.2.1.3 Stop watch
The elapsed time between a configured start- and stop event may be measured by the
MFRC631 timer unit. By setting the registers T(x)ReloadValueHi, T(x)reloadValueLo the
timer starts to decrement as soon as activated. If the configured stop event occurs, the
timers stops decrementing. The elapsed time between start and stop event can then be
calculated by the host dependent on the timer interval TTimer:
(1)
If an underflow occurred which can be identified by evaluating the corresponding IRQ bit,
the performed time measurement according to the formula above is not correct.
7.2.1.4 Programmable one-shot timer
The host configures the interrupt and the timer, starts the timer and waits for the interrupt
event on pin IRQ. After the configured time the interrupt request will be raised.
7.2.1.5 Periodical trigger
If the bit T(x)Control.T(x)AutoRestart is set and the interrupt is activated, an interrupt
request will be indicated periodically after every elapsed timer period.
MFRC631
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MFRC631
High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
7.3 Contactless interface unit
The contactless interface unit of the MFRC631 supports the following read/write
operating modes:
• ISO/IEC14443 type A and MIFARE Classic
• ISO/IEC14443B
BATTERY/POWER SUPPLY
READER IC
ISO/IEC 14443 A CARD
MICROCONTROLLER
reader/writer
001aal996
Figure 4.ꢀRead/write mode
A typical system using the MFRC631 is using a microcontroller to implement the higher
levels of the contactless communication protocol and a power supply (battery or external
supply).
7.3.1 Communication mode for ISO/IEC14443 type A and for MIFARE Classic
The physical level of the communication is shown in Figure 5.
(1)
ISO/IEC 14443 A
ISO/IEC 14443 A CARD
READER
(2)
001aam268
1. Reader to Card 100 % ASK, Miller Coded, Transfer speed 106 kbit/s to 848 kbit/s
2. Card to Reader, Subcarrier Load Modulation Manchester Coded or BPSK, transfer speed 106
kbit/s to 848 kbit/s
Figure 5.ꢀRead/write mode for ISO/IEC 14443 type A and read/write mode for MIFARE
Classic
The physical parameters are described in Table 5.
Table 6.ꢀRead/write mode for ISO/IEC 14443 type A and read/write mode for MIFARE Classic
Communication
direction
Signal type
Transfer speed
106 kbit/s
212 kbit/s
424 kbit/s
848 kbit/s
Reader to card
(send data from the
MFRC631 to a card)
reader side
modulation
100 % ASK
100% ASK
100% ASK
100% ASK
bit encoding
modified Miller
encoding
modified Miller
encoding
modified Miller
encoding
modified Miller
encoding
fc = 13.56 MHz
bit rate [kbit/s]
fc / 128
fc / 64
fc / 32
fc / 16
Card to reader
(MFRC631 receives
data from a card)
card side
modulation
subcarrier load
modulation
subcarrier load
modulation
subcarrier load
modulation
subcarrier load
modulation
subcarrier
frequency
fc / 16
fc / 16
fc / 16
fc / 16
MFRC631
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MFRC631
High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
Communication
direction
Signal type
Transfer speed
106 kbit/s
212 kbit/s
424 kbit/s
848 kbit/s
bit encoding
Manchester
encoding
BPSK
BPSK
BPSK
The MFRC631 connection to a host is required to manage the complete ISO/IEC 14443
type A and MIFARE Classic communication protocol. Figure 6 shows the data coding
and framing according to ISO/IEC 14443 type A and MIFARE Classic.
ISO/IEC 14443 A framing at 106 kBd
start
8-bit data
8-bit data
8-bit data
odd
odd
odd
parity
parity
parity
start bit is 1
ISO/IEC 14443 A framing at 212 kBd, 424 kBd and 848 kBd
start
even
parity
8-bit data
8-bit data
8-bit data
odd
odd
parity
parity
start bit is 0
burst of 32
subcarrier clocks
even parity at the
end of the frame
001aak585
Figure 6.ꢀData coding and framing according to ISO/IEC 14443 A
The internal CRC coprocessor calculates the CRC value based on ISO/IEC 14443 A part
3 and handles parity generation internally according to the transfer speed.
7.3.2 ISO/IEC14443B functionality
The physical level of the communication is shown in Figure 7.
(1)
ISO/IEC 14443 B
ISO/IEC 14443 B CARD
READER
(2)
001aal997
1. Reader to Card NRZ, Miller coded, transfer speed 106 kbit/s to 848 kbit/s
2. Card to reader, Subcarrier Load Modulation Manchester Coded or BPSK, transfer speed 106
kbit/s to 848 kbit/s
Figure 7.ꢀRead/write mode for ISO/IEC 14443 type A and read/write mode for MIFARE
Classic
The physical parameters are described in Table 6.
MFRC631
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Table 7.ꢀCommunication overview for ISO/IEC 14443 B reader/writer
Communication
direction
Signal type
Transfer speed
106 kbit/s
212 kbit/s
424 kbit/s
848 kbit/s
Reader to card
(send data from the
MFRC631 to a card)
reader side
modulation
10 % ASK
10 % ASK
10 % ASK
10 % ASK
bit encoding
NRZ
NRZ
NRZ
NRZ
fc = 13.56 MHz
bit rate [kbit/s]
128 / fc
64 / fc
32 / fc
16 / fc
Card to reader
(MFRC631 receives
data from a card)
card side
modulation
subcarrier load
modulation
subcarrier load
modulation
subcarrier load
modulation
subcarrier load
modulation
subcarrier
frequency
fc / 16
fc / 16
fc / 16
fc / 16
bit encoding
BPSK
BPSK
BPSK
BPSK
The MFRC631 connected to a host is required to manage the complete ISO/IEC 14443
B protocol. The following Figure 8 "SOF and EOF according to ISO/IEC 14443 B" shows
the ISO/IEC 14443B SOF and EOF.
Start of Frame (SOF)
sequence
9.44 µs
UNMODULATED (SUB)
''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0''
''1'' ''1''
DATA
CARRIER
End of Frame (EOF)
sequence
9.44 µs
UNMODULATED (SUB)
CARRIER
LAST CHARACTER
''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0''
001aam270
Figure 8.ꢀ SOF and EOF according to ISO/IEC 14443 B
7.4 Host interfaces
7.4.1 Host interface configuration
The MFRC631 supports direct interfacing of various hosts as the SPI, I2C, I2CL and
serial UART interface type. The MFRC631 resets its interface and checks the current
host interface type automatically having performed a power-up or resuming from power
down. The MFRC631 identifies the host interface by the means of the logic levels on
the control pins after the Cold Reset Phase. This is done by a combination of fixed
pin connections.The following table shows the possible configurations defined by
IFSEL1,IFSEL0:
MFRC631
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Table 8.ꢀConnection scheme for detecting the different interface types
Pin
28
29
30
31
26
27
Pin Symbol
IF0
UART
RX
SPI
I2C
I2C-L
MOSI
SCK
ADR1
SCL
ADR1
IF1
n.c.
SCL
IF2
TX
MISO
NSS
ADR2
SDA
SDA
IF3
PAD_VDD
VSS
ADR2
IFSEL0
IFSEL1
VSS
PAD_VDD
VSS
PAD_VDD
PAD_VDD
VSS
PAD_VDD
7.4.2 SPI interface
7.4.2.1 General
READER IC
SCK
IF1
IF0
IF2
IF3
MOSI
MISO
NSS
001aal998
Figure 9.ꢀConnection to host with SPI
The MFRC631 acts as a slave during the SPI communication. The SPI clock SCK has to
be generated by the master. Data communication from the master to the slave uses the
Line MOSI. Line MISO is used to send data back from the MFRC631 to the master.
A serial peripheral interface (SPI compatible) is supported to enable high speed
communication to a host. The implemented SPI compatible interface is according to a
standard SPI interface. The SPI compatible interface can handle data speed of up to
10 Mbit/s. In the communication with a host MFRC631 acts as a slave receiving data
from the external host for register settings and to send and receive data relevant for the
communication on the RF interface.
NSS (Not Slave Select) enables or disables the SPI interface. When NSS is logical high,
the interface is disabled and reset. Between every SPI command the NSS must go to
logical high to be able to start the next command read or write.
On both data lines (MOSI, MISO) each data byte is sent by MSB first. Data on MOSI
line shall be stable on rising edge of the clock line (SCK) and is allowed to change on
falling edge. The same is valid for the MISO line. Data is provided by the MFRC631 on
the falling edge and is stable on the rising edge.The polarity of the clock is low at SPI
idle.
7.4.2.2 Read data
To read out data from the MFRC631 by using the SPI compatible interface the following
byte order has to be used.
The first byte that is sent defines the mode (LSB bit) and the address.
MFRC631
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Table 9.ꢀByte Order for MOSI and MISO
byte 0
byte 1
byte 2
byte 3 to n-1
……..
byte n
byte n+1
00h
MOSI address 0
address 1
data 0
address 2
data 1
address n
data n - 1
MISO
X
……..
data n
Remark: The Most Significant Bit (MSB) has to be sent first.
7.4.2.3 Write data
To write data to the MFRC631 using the SPI interface the following byte order has to
be used. It is possible to write more than one byte by sending a single address byte
(see.8.5.2.4).
The first send byte defines both, the mode itself and the address byte.
Table 10.ꢀByte Order for MOSI and MISO
byte 0
address 0
X
byte 1
data 0
X
byte 2
data 1
X
3 to n-1
……..
byte n
data n - 1
X
byte n + 1
data n
X
MOSI
MISO
……..
Remark: The Most Significant Bit (MSB) has to be sent first.
7.4.2.4 Address byte
The address byte has to fulfil the following format:
The LSB bit of the first byte defines the used mode. To read data from the MFRC631 the
LSB bit is set to logic 1. To write data to the MFRC631 the LSB bit has to be cleared. The
bits 6 to 0 define the address byte.
NOTE: When writing the sequence [address byte][data0][data1][data2]..., [data0] is
written to address [address byte], [data1] is written to address [address byte + 1] and
[data2] is written to [address byte + 2].
Exception: This auto increment of the address byte is not performed if data is written to
the FIFO address
Table 11.ꢀAddress byte 0 register; address MOSI
7
6
5
4
3
2
1
0
address 6 address 5 address 4 address 3 address 2 address 1 address 0 1 (read)
0 (write)
MSB
LSB
7.4.2.5 Timing Specification SPI
The timing condition for SPI interface is as follows:
Table 12.ꢀTiming conditions SPI
Symbol
tSCKL
Parameter
Min
50
Typ
Max
Unit
SCK LOW time
SCK HIGH time
-
-
-
-
ns
ns
tSCKH
50
MFRC631
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Symbol
Parameter
Min
25
25
-
Typ
Max
Unit
ns
th(SCKH-D)
tsu(D-SCKH)
th(SCKL-Q)
t(SCKL-NSSH)
tNSSH
SCK HIGH to data input hold time
data input to SCK HIGH set-up time
SCK LOW to data output hold time
SCK LOW to NSS HIGH time
NSS HIGH time
-
-
-
-
-
-
-
ns
25
-
ns
0
ns
50
-
ns
t
t
t
t
SCKL
NSSH
SCKL
SCKH
SCK
t
h(SCKL-Q)
t
su(D-SCKH)
t
h(SCKH-D)
MOSI
MISO
MSB
MSB
LSB
LSB
t
(SCKL-NSSH)
NSS
aaa-016093
Figure 10.ꢀConnection to host with SPI
Remark: To send more bytes in one data stream the NSS signal must be LOW during
the send process. To send more than one data stream the NSS signal must be HIGH
between each data stream.
7.4.3 RS232 interface
7.4.3.1 Selection of the transfer speeds
The internal UART interface is compatible to a RS232 serial interface. The levels
supplied to the pins are between VSS and PVDD. To achieve full compatibility of the
voltage levels to the RS232 specification, a RS232 level shifter is required.
Table 13 "Selectable transfer speeds" describes examples for different transfer speeds
and relevant register settings. The resulting transfer speed error is less than 1.5 % for all
described transfer speeds. The default transfer speed is 115.2 kbit/s.
To change the transfer speed, the host controller has to write a value for the new transfer
speed to the register SerialSpeedReg. The bits BR_T0 and BR_T1 define factors to set
the transfer speed in the SerialSpeedReg.
Table 12 "Settings of BR_T0 and BR_T1" describes the settings of BR_T0 and BR_T1.
Table 13.ꢀSettings of BR_T0 and BR_T1
BR_T0
0
1
2
3
4
5
6
7
MFRC631
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factor BR_T0
1
1
2
4
8
16
32
64
range BR_T1 1 to 32
33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64
Table 14.ꢀSelectable transfer speeds
Transfer speed (kbit/s)
Serial SpeedReg
Transfer speed accuracy (%)
(Hex.)
FA
EB
DA
CB
AB
9A
7.2
-0.25
0.32
-0.25
0.32
0.32
-0.25
-0.25
-0.06
-0.25
-0.25
1.45
0.32
9.6
14.4
19.2
38.4
57.6
115.2
128
7A
74
230.4
460.8
921.6
1228.8
5A
3A
1C
15
The selectable transfer speeds as shown are calculated according to the following
formulas:
if BR_T0 = 0: transfer speed = 27.12 MHz / (BR_T1 + 1)
if BR_T0 > 0: transfer speed = 27.12 MHz / (BR_T1 + 33)/2(BR_T0 - 1)
Remark: Transfer speeds above 1228.8 kBits/s are not supported.
7.4.3.2 Framing
Table 15.ꢀUART framing
Bit
Length
1 bit
Value
0
Start bit (Sa)
Data bits
8 bit
Data
1
Stop bit (So)
1 bit
Remark: For data and address bytes the LSB bit has to be sent first. No parity bit is
used during transmission.
Read data: To read out data using the UART interface the flow described below has to
be used. The first send byte defines both the mode itself and the address.The Trigger on
pin IF3 has to be set, otherwise no read of data is possible.
Table 16.ꢀByte Order to Read Data
Mode
byte 0
byte 1
RX
address
-
MFRC631
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Mode
byte 0
byte 1
TX
-
data 0
ADDRESS
RX
Sa
A0
A1
A2
A3
A4
A5
A6 RD/ So
NWR
DATA
TX
Sa
D0
D1
D2
D3
D4
D5
D6
D7
So
001aam298
Figure 11.ꢀExample for UART Read
Write data:
To write data to the MFRC631 using the UART interface the following sequence has to
be used.
The first send byte defines both, the mode itself and the address.
Table 17.ꢀByte Order to Write Data
Mode
RX
byte 0
byte 1
address 0
data 0
TX
address 0
ADDRESS
DATA
RX
Sa
A0
A1
A2
A3
A4
A5
A6 RD/ So
NWR
Sa
D0
D1
D2
D3
D4
D5
D6
D7
So
ADDRESS
TX
Sa
A0
A1
A2
A3
A4
A5
A6 RD/ So
NWR
001aam299
Figure 12.ꢀExample diagram for a UART write
Remark: Data can be sent before address is received.
7.4.4 I2C-bus interface
MFRC631
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7.4.4.1 General
An Inter IC (I2C) bus interface is supported to enable a low cost, low pin count serial bus
interface to the host. The implemented I2C interface is mainly implemented according the
NXP Semiconductors I2C interface specification, rev. 3.0, June 2007. The MFRC631 can
act as a slave receiver or slave transmitter in standard mode, fast mode and fast mode
plus.
The following features defined by the NXP Semiconductors I2C interface specification,
rev. 3.0, June 2007 are not supported:
• The MFRC631 I2C interface does not stretch the clock
• The MFRC631 I2C interface does not support the general call. This means that the
MFRC631 does not support a software reset
• The MFRC631 does not support the I2C device ID
• The implemented interface can only act in slave mode. Therefore no clock generation
and access arbitration is implemented in the MFRC631.
• High speed mode is not supported by the MFRC631
PULL-UP
NETWORK
PULL-UP
NETWORK
READER IC
MICROCONTROLLER
SDA
SCL
001aam000
Figure 13.ꢀI2C-bus interface
The voltage level on the I2C pins is not allowed to be higher than PVDD.
SDA is a bidirectional line, connected to a positive supply voltage via a pull-up resistor.
Both lines SDA and SCL are set to HIGH level if no data is transmitted. Data on the I2C-
bus can be transferred at data rates of up to 400 kbit/s in fast mode, up to 1 Mbit/s in the
fast mode+.
If the I2C interface is selected, a spike suppression according to the I2C interface
specification on SCL and SDA is automatically activated.
For timing requirements refer to Table 197 "I2C-bus timing in fast mode and fast mode
plus"
7.4.4.2 I2C Data validity
Data on the SDA line shall be stable during the HIGH period of the clock. The HIGH state
or LOW state of the data line shall only change when the clock signal on SCL is LOW.
SDA
SCL
change
data line stable;
data valid
of data
allowed
001aam300
Figure 14.ꢀBit transfer on the I2C-bus.
MFRC631
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7.4.4.3 I2C START and STOP conditions
To handle the data transfer on the I2C-bus, unique START (S) and STOP (P) conditions
are defined.
A START condition is defined with a HIGH-to-LOW transition on the SDA line while SCL
is HIGH.
A STOP condition is defined with a LOW-to-HIGH transition on the SDA line while SCL is
HIGH.
The master always generates the START and STOP conditions. The bus is considered to
be busy after the START condition. The bus is considered to be free again a certain time
after the STOP condition.
The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition.
In this respect, the START (S) and repeated START (Sr) conditions are functionally
identical. Therefore, the S symbol will be used as a generic term to represent both the
START and repeated START (Sr) conditions.
SDA
SCL
SDA
SCL
S
P
START condition
STOP condition
001aam301
Figure 15.ꢀSTART and STOP conditions
7.4.4.4 I2C byte format
Each byte has to be followed by an acknowledge bit. Data is transferred with the MSB
first, see Figure 15 "START and STOP conditions". The number of transmitted bytes
during one data transfer is unrestricted but shall fulfil the read/write cycle format.
7.4.4.5 I2C Acknowledge
An acknowledge at the end of one data byte is mandatory. The acknowledge-related
clock pulse is generated by the master. The transmitter of data, either master or slave,
releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver shall pull
down the SDA line during the acknowledge clock pulse so that it remains stable LOW
during the HIGH period of this clock pulse.
The master can then generate either a STOP (P) condition to stop the transfer, or a
repeated START (Sr) condition to start a new transfer.
A master-receiver shall indicate the end of data to the slave- transmitter by not
generating an acknowledge on the last byte that was clocked out by the slave. The slave-
transmitter shall release the data line to allow the master to generate a STOP (P) or
repeated START (Sr) condition.
MFRC631
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DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVERER
acknowledge
SCL FROM
MASTER
1
2
8
9
S
clock pulse for
acknowledgement
START
condition
001aam302
Figure 16.ꢀAcknowledge on the I2C- bus
P
MSB
acknowledgement
signal from slave
acknowledgement
signal from receiver
Sr
byte complete,
interrupt within slave
clock line held low while
interrupts are serviced
S
or
Sr
Sr
or
P
1
2
7
8
9
1
2
3 - 8
9
ACK
ACK
001aam303
Figure 17.ꢀData transfer on the I2C- bus
7.4.4.6 I2C 7-bit addressing
During the I2C-bus addressing procedure, the first byte after the START condition is used
to determine which slave will be selected by the master.
Alternatively the I2C address can be configured in the EEPROM. Several address
numbers are reserved for this purpose. During device configuration, the designer has to
ensure, that no collision with these reserved addresses in the system is possible. Check
the corresponding I2C specification for a complete list of reserved addresses.
For all MFRC631 devices the upper 5 bits of the device bus address are reserved by
NXP and set to 01010(bin). The remaining 2 bits (ADR_2, ADR_1) of the slave address
can be freely configured by the customer in order to prevent collisions with other I2C
devices by using the interface pins (refer to Table 7) or the value of the I2C address
EEPROM register (refer to Table 29).
MSB
LSB
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W
slave address
001aam304
Figure 18.ꢀFirst byte following the START procedure
MFRC631
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7.4.4.7 I2C-register write access
To write data from the host controller via I2C to a specific register of the MFRC631 the
following frame format shall be used.
The read/write bit shall be set to logic 0.
The first byte of a frame indicates the device address according to the I2C rules. The
second byte indicates the register address followed by up to n-data bytes. In case the
address indicates the FIFO, in one frame all n-data bytes are written to the FIFO register
address. This enables for example a fast FIFO access.
7.4.4.8 I2C-register read access
To read out data from a specific register address of the MFRC631 the host controller
shall use the procedure:
First a write access to the specific register address has to be performed as indicated in
the following frame:
The first byte of a frame indicates the device address according to the I2C rules. The
second byte indicates the register address. No data bytes are added.
The read/write bit shall be logic 0.
Having performed this write access, the read access starts. The host sends the device
address of the MFRC631. As an answer to this device address the MFRC631 responds
with the content of the addressed register. In one frame n-data bytes could be read
using the same register address. The address pointing to the register is incremented
automatically (exception: FIFO register address is not incremented automatically).
This enables a fast transfer of register content. The address pointer is incremented
automatically and data is read from the locations [address], [address+1], [address+2]...
[address+(n-1)]
In order to support a fast FIFO data transfer, the address pointer is not incremented
automatically in case the address is pointing to the FIFO.
The read/write bit shall be set to logic 1.
MFRC631
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Write Cycle
0
(W)
I2C slave address
A7-A0
Frontend IC register
address A6-A0
DATA
[7..0]
SA
Ack
0
Ack
[0..n]
Ack
SO
SO
Read Cycle
0
(W)
I2C slave address
A7-A0
Frontend IC register
address A6-A0
SA
Ack
0
Ack
Optional, if the previous access was on the same register address
0..n
1
(R)
I2C slave address
A7-A0
DATA
[7..0]
SA
Ack
[0..n]
Ack
sent by master
sent by slave
DATA
[7..0]
Nack
SO
001aam305
Figure 19.ꢀRegister read and write access
7.4.4.9 I2CL-bus interface
The MFRC631 provides an additional interface option for connection of a SAM. This
logical interface fulfills the I2C specification, but the rise/fall timings will not be compliant
to the I2C standard. The I2CL interface uses standard I/O pads, and the communication
speed is limited to 5 MBaud. The protocol itself is equivalent to the fast mode protocol of
I2C. The SCL levels are generated by the host in push/pull mode. The RC631 does not
stretch the clock. During the high period of SCL the status of the line is maintained by a
bus keeper.
The address is 01010xxb, where the last two bits of the address can be defined by the
application. The definition of this bits can be done by two options. With a pin, where the
higher bit is fixed to 0 or the configuration can be defined via EEPROM. Refer to the
EEPROM configuration in Section 7.7.
Table 18.ꢀTiming parameter I2CL
Parameter
fSCL
Min
0
Max
Unit
MHz
ns
5
-
tHD;STA
tLOW
80
100
100
80
0
-
ns
tHIGH
-
ns
tSU;SDA
tHD;DAT
tSU;DAT
tSU;STO
tBUF
-
ns
50
20
-
ns
0
ns
80
200
ns
-
ns
MFRC631
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The pull-up resistor is not required for the I2CL interface. Instead, a on chip buskeeper
is implemented in the MFRC631 for SDA of the I2CL interface. This protocol is intended
to be used for a point to point connection of devices over a short distance and does
not support a bus capability.The driver of the pin must force the line to the desired
logic voltage. To avoid that two drivers are pushing the line at the same time following
regulations must be fulfilled:
SCL: As there is no clock stretching, the SCL is always under control of the Master.
SDA: The SDA line is shared between master and slave. Therefore the master and the
slave must have the control over the own driver enable line of the SDA pin. The following
rules must be followed:
• In the idle phase the SDA line is driven high by the master
• In the time between start and stop condition the SDA line is driven by master or slave
when SCL is low. If SCL is high the SDA line is not driven by any device
• To keep the value on the SDA line a on chip buskeeper structure is implemented for
the line
7.4.5 SAM interface
7.4.5.1 SAM functionality
The MFRC631 implements a dedicated I2C or SPI interface to integrate a MIFARE SAM
(Secure Access Module) in a very convenient way into applications (e.g. a proximity
reader).
The SAM can be connected to the microcontroller to operate like a cryptographic co-
processor. For any cryptographic task, the microcontroller requests a operation from the
SAM, receives the answer and sends it over a host interface (e.g. I2C, SPI) interface to
the connected reader IC.
The MIFARE SAM supports a optimized method to integrate the SAM in a very efficient
way to reduce the protocol overhead. In this system configuration, the SAM is integrated
between the microprocessor and the reader IC, connected by one interface to the reader
IC and by another interface to the microcontroller. In this application the microcontroller
accesses the SAM using the T=1 protocol and the SAM accesses the reader IC using
an I2C interface. The I2C SAM address is always defined by EEPROM register.
Default value is 0101100. As the SAM is directly communicating with reader IC, the
communication overhead is reduced. In this configuration, a performance boost of up to
40% can be achieved for a transaction time.
The MIFARE SAM supports applications using MIFARE product-based cards. For multi
application purposes an architecture connecting the microcontroller additionally directly
to the reader IC is recommended. This is possible by connecting the MFRC631 on
one interface (SAM Interface SDA, SCL) with the MIFARE SAM AV2.6 (P5DF081XX/
T1AR1070) and by connecting the microcontroller to the S2C or SPI interface.
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T=1
I2C
SAM
AV2.6
READER
IC
µC
I2C
Reader
aaa-002963
Figure 20.ꢀI2C interface enables convenient MIFARE SAM integration
7.4.5.2 SAM connection
The MFRC631 provides an interface to connect a SAM dedicated to the MFRC631. Both
interface options of the MFRC631, I2C, I2CL or SPI can be used for this purpose. The
interface option of the SAM itself is configured by a host command sent from the host to
the SAM.
The I2CL interface is intended to be used as connection between two IC’s over a short
distance. The protocol fulfills the I2C specification, but does support a single device
connected to the bus only.
The SPI block for SAM connection is identical with the SPI host interface block.
The pins used for the SAM SPI are described in Table 18.
Table 19.ꢀSPI SAM connection
SPI functionality
PIN
MISO
SCL
SDA2
SCL2
IFSEL1
IFSEL0
MOSI
NSS
7.4.6 Boundary scan interface
The MFRC631 provides a boundary scan interface according to the IEEE 1149.1. This
interface allows to test interconnections without using physical test probes. This is done
by test cells, assigned to each pin, which override the functionality of this pin.
To be able to program the test cells, the following commands are supported:
Table 20.ꢀBoundary scan command
Value
Command
Parameter in
Parameter out
(decimal)
0
1
1
2
3
4
bypass
-
-
preload
data (24)
-
sample
-
-
-
-
data (24)
data (32)
data (32)
-
ID code (default)
USER code
Clamp
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Value
Command
Parameter in
Parameter out
(decimal)
5
HIGH Z
-
-
7
extest
data (24)
data (24)
8
interface on/off
register access read
register access write
interface (1)
address (7)
address (7) - data (8)
-
9
data (8)
-
10
The Standard IEEE 1149.1 describes the four basic blocks necessary to use this
interface: Test Access Port (TAP), TAP controller, TAP instruction register, TAP data
register;
7.4.6.1 Interface signals
The boundary scan interface implements a four line interface between the chip and the
environment. There are three Inputs: Test Clock (TCK); Test Mode Select (TMS); Test
Data Input (TDI) and one output Test Data Output (TDO). TCK and TMS are broadcast
signals, TDI to TDO generate a serial line called Scan path.
Advantage of this technique is that independent of the numbers of boundary scan
devices the complete path can be handled with four signal lines.
The signals TCK, TMS are directly connected with the boundary scan controller. Because
these signals are responsible for the mode of the chip, all boundary scan devices in one
scan path will be in the same boundary scan mode.
7.4.6.2 Test Clock (TCK)
The TCK pin is the input clock for the module. If this clock is provided, the test logic
is able to operate independent of any other system clocks. In addition, it ensures that
multiple boundary scan controllers that are daisy-chained together can synchronously
communicate serial test data between components. During normal operation, TCK
is driven by a free-running clock. When necessary, TCK can be stopped at 0 or 1 for
extended periods of time. While TCK is stopped at 0 or 1, the state of the boundary scan
controller does not change and data in the Instruction and Data Registers is not lost.
The internal pull-up resistor on the TCK pin is enabled. This assures that no clocking
occurs if the pin is not driven from an external source.
7.4.6.3 Test Mode Select (TMS)
The TMS pin selects the next state of the boundary scan controller. TMS is sampled on
the rising edge of TCK. Depending on the current boundary scan state and the sampled
value of TMS, the next state is entered. Because the TMS pin is sampled on the rising
edge of TCK, the IEEE Standard 1149.1 expects the value on TMS to change on the
falling edge of TCK.
Holding TMS high for five consecutive TCK cycles drives the boundary scan controller
state machine to the Test-Logic-Reset state. When the boundary scan controller enters
the Test-Logic-Reset state, the Instruction Register (IR) resets to the default instruction,
IDCODE. Therefore, this sequence can be used as a reset mechanism.
The internal pull-up resistor on the TMS pin is enabled.
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7.4.6.4 Test Data Input (TDI)
The TDI pin provides a stream of serial information to the IR chain and the DR chains.
TDI is sampled on the rising edge of TCK and, depending on the current TAP state and
the current instruction, presents this data to the proper shift register chain. Because the
TDI pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the
value on TDI to change on the falling edge of TCK.
The internal pull-up resistor on the TDI pin is enabled.
7.4.6.5 Test Data Output (TDO)
The TDO pin provides an output stream of serial information from the IR chain or the
DR chains. The value of TDO depends on the current TAP state, the current instruction,
and the data in the chain being accessed. In order to save power when the port is not
being used, the TDO pin is placed in an inactive drive state when not actively shifting out
data. Because TDO can be connected to the TDI of another controller in a daisy-chain
configuration, the IEEE Standard 1149.1 expects the value on TDO to change on the
falling edge of TCK.
7.4.6.6 Data register
According to the IEEE1149.1 standard there are two types of data register defined:
bypass and boundary scan
The bypass register enable the possibility to bypass a device when part of the scan
path.Serial data is allowed to be transferred through a device from the TDI pin to the
TDO pin without affecting the operation of the device.
The boundary scan register is the scan-chain of the boundary cells. The size of this
register is dependent on the command.
7.4.6.7 Boundary scan cell
The boundary scan cell opens the possibility to control a hardware pin independent of its
normal use case. Basically the cell can only do one of the following: control, output and
input.
IC1
IC2
Boundary scan cell
TDI
TDO
TDI
TDO
TAP
TAP
TCK
TMS
TCK
TMS
001aam306
Figure 21.ꢀBoundary scan cell path structure
7.4.6.8 Boundary scan path
This chapter shows the boundary scan path of the MFRC631.
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Table 21.ꢀBoundary scan path of the MFRC631
Number (decimal)
Cell
Port
Function
Control
Bidir
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
BC_1
BC_8
BC_1
BC_8
BC_1
BC_8
BC_1
BC_8
BC_1
BC_8
BC_1
BC_8
BC_1
BC_8
BC_1
BC_8
BC_1
BC_4
BC_1
BC_8
BC_1
BC_8
BC_1
BC_8
-
CLKOUT
-
Control
Bidir
SCL2
-
Control
Bidir
SDA2
-
Control
Bidir
IFSEL0
-
Control
Bidir
IFSEL1
-
Control
Bidir
IF0
-
Control
Bidir
IF1
-
Control
Bidir
8
IF2
7
IF2
Output2
Bidir
6
IF3
5
-
Control
Bidir
4
IRQ
3
-
Control
Bidir
2
SIGIN
-
1
Control
Bidir
0
SIGOUT
Refer to the MFRC631 BSDL file.
7.4.6.9 Boundary Scan Description Language (BSDL)
All of the boundary scan devices have a unique boundary structure which is necessary to
know for operating the device. Important components of this language are:
• available test bus signal
• compliance pins
• command register
• data register
• boundary scan structure (number and types of the cells, their function and the
connection to the pins.)
The MFRC631 is using the cell BC_8 for the IO-Lines. The I2C Pin is using a BC_4 cell.
For all pad enable lines the cell BC1 is used.
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The manufacturer's identification is 02Bh.
• attribute IDCODEISTER of MFRC631: entity is "0001" and -- version
• "0011110010000010b" and -- part number (3C82h)
• "00000010101b" and -- manufacturer (02Bh)
• "1b"; -- mandatory
The user code data is coded as followed:
• product ID (3 bytes)
• version
These four bytes are stored as the first four bytes in the EEPROM.
7.4.6.10 Non-IEEE1149.1 commands
Interface on/off
With this command the host/SAM interface can be deactivated and the Read and Write
command of the boundary scan interface is activated. (Data = 1). With Update-DR the
value is taken over.
Register Access Read
At Capture-DR the actual address is read and stored in the DR. Shifting the DR is shifting
in a new address. With Update-DR this address is taken over into the actual address.
Register Access Write
At the Capture-DR the address and the data is taken over from the DR. The data is
copied into the internal register at the given address.
7.5 Buffer
7.5.1 Overview
An 512 × 8-bit FIFO buffer is implemented in the MFRC631. It buffers the input and
output data stream between the host and the internal state machine of the MFRC631.
Thus, it is possible to handle data streams with lengths of up to 512 bytes without taking
timing constraints into account. The FIFO can also be limited to a size of 255 byte. In
this case all the parameters (FIFO length, Watermark...) require a single byte only for
definition. In case of a 512 byte FIFO length the definition of this values requires 2 bytes.
7.5.2 Accessing the FIFO buffer
When the μ-Controller starts a command, the MFRC631 may, while the command is in
progress, access the FIFO-buffer according to that command. Physically only one FIFO-
buffer is implemented, which can be used in input and output direction. Therefore the μ-
Controller has to take care, not to access the FIFO buffer in a way that corrupts the FIFO
data.
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7.5.3 Controlling the FIFO buffer
Besides writing to and reading from the FIFO buffer, the FIFO-buffer pointers might be
reset by setting the bit FIFOFlush in FIFOControl to 1. Consequently, the FIFOLevel bits
are set to logic 0, the actually stored bytes are not accessible any more and the FIFO
buffer can be filled with another 512 bytes (or 255 bytes if the bit FIFOSize is set to 1)
again.
7.5.4 Status Information about the FIFO buffer
The host may obtain the following data about the FIFO-buffers status:
• Number of bytes already stored in the FIFO-buffer. Writing increments, reading
decrements the FIFO level: FIFOLength in register FIFOLength (and FIFOControl
Register in 512 byte mode)
• Warning, that the FIFO-buffer is almost full: HiAlert in register FIFOControl according
to the value of the water level in register WaterLevel (Register 02h bit [2], Register 03h
bit[7:0])
• Warning, that the FIFO-buffer is almost empty: LoAlert in register FIFOControl
according to the value of the water level in register WaterLevel (Register 02h bit [2],
Register 03h bit[7:0])
• FIFOOvl bit indicates, that bytes were written to the FIFO buffer although it was already
full: ErrIRQ in register IRQ0.
WaterLevel is one single value defining both HiAlert (counting from the FIFO top) and
LoAlert (counting from the FIFO bottom). The MFRC631 can generate an interrupt signal
if:
• LoAlertIRQEn in register IRQ0En is set to logic 1 it will activate pin IRQ when LoAlert in
the register FIFOControl changes to 1.
• HiAlertIRQEN in register IRQ0En is set to logic 1 it will activate pin IRQ when HiAlert in
the register FIFOControl changes to 1.
The bit HiAlert is set to logic 1 if maximum water level bytes (as set in register
WaterLevel) or less can be stored in the FIFO-buffer. It is generated according to the
following equation:
(2)
The bit LoAlert is set to logic 1 if water level bytes (as set in register WaterLevel) or less
are actually stored in the FIFO-buffer. It is generated according to the following equation:
(3)
7.6 Analog interface and contactless UART
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7.6.1 General
The integrated contactless UART supports the external host online with framing and
error checking of the protocol requirements up to 848 kbit/s. An external circuit can be
connected to the communication interface pins SIGIN and SIGOUT to modulate and
demodulate the data.
The contactless UART handles the protocol requirements for the communication
schemes in co-operation with the host. The protocol handling itself generates bit- and
byte-oriented framing and handles error detection like Parity and CRC according to the
different contactless communication schemes.
The size, the tuning of the antenna, and the supply voltage of the output drivers have an
impact on the achievable field strength. The operating distance between reader and card
depends additionally on the type of card used.
7.6.2 TX transmitter
The signal delivered on pin TX1 and pin TX2 is the 13.56 MHz carrier modulated by an
envelope signal for energy and data transmission. It can be used to drive an antenna
directly, using a few passive components for matching and filtering, see Section 13
"Application information". The signal on TX1 and TX2 can be configured by the register
DrvMode, see Section 8.8.1 "TxMode".
The modulation index can be set by the TxAmp.
Following figure shows the general relations during modulation
influenced by set_clk_mode
envelope
TX ASK100
(1)
TX ASK10
(2)
time
001aan355
1: Defined by set_cw_amplitude.
2: Defined by set_residual_carrier.
Figure 22.ꢀGeneral dependences of modulation
Note: When changing the continuous carrier amplitude, the residual carrier amplitude
also changes, while the modulation index remains the same.
The registers Section 8.8 and Section 8.10 control the data rate, the framing during
transmission and the setting of the antenna driver to support the requirements at the
different specified modes and transfer speeds.
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Table 22.ꢀSettings for TX1 and TX2
TxClkMode
(binary)
Tx1 and TX2 output
Remarks
000
001
010
110
High impedance
-
0
output pulled to 0 in any case
output pulled to 1 in any case
1
RF high side push
open drain, only high side (push) MOS supplied
with clock, clock parity defined by invtx; low
side MOS is off
101
111
RF low side pull
open drain, only low side (pull) MOS supplied
with clock, clock parity defined by invtx; high
side MOS is off
13.56 MHz clock derived
from 27.12 MHz quartz
divided by 2
push/pull Operation, clock polarity defined by
invtx; setting for 10% modulation
Register TXamp and the bits for set_residual_carrier define the modulation index:
Table 23.ꢀSetting residual carrier and modulation index by TXamp.set_residual_carrier
set_residual_carrier (decimal)
residual carrier [%]
modulation index [%]
0
99
98
96
94
91
89
87
86
85
84
83
82
81
80
79
78
77
76
75
74
72
70
0.5
1
1.0
2
2.0
3
3.1
4
4.7
5
5.8
6
7.0
7
7.5
8
8.1
9
8.7
10
11
12
13
14
15
16
17
18
19
20
21
9.3
9.9
10.5
11.1
11.7
12.4
13.0
13.6
14.3
14.9
16.3
17.6
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set_residual_carrier (decimal)
residual carrier [%]
modulation index [%]
22
23
24
25
26
27
28
29
30
31
68
65
60
55
50
45
40
35
30
25
19.0
21.2
25.0
29.0
33.3
37.9
42.9
48.1
53.8
60.0
Note: At VDD(TVDD) <5 V and residual carrier settings <50%, the accuracy of the
modulation index may be low in dependency of the antenna tuning impedance
7.6.2.1 Overshoot protection
The MFRC631 provides an overshoot protection for 100% ASK to avoid overshoots
during a PCD communication. Therefore two timers overshoot_t1 and overshoot_t2 can
be used.
During the timer overshoot_t1 runs an amplitude defined by set_cw_amplitude bits is
provided to the output driver. Followed by an amplitude denoted by set_residual_carrier
bits with the duration of overshoot_t2.
7.0
(V)
5.0
3.0
1.0
-1.0
2.50
3.03
3.56
4.10
time ( s)
001aan356
Figure 23.ꢀExample 1: overshoot_t1 = 2d; overhoot_t2 = 5d.
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7.0
5.0
3.0
1.0
(V)
-1.0
0
1
2
3
4
5
time ( s)
001aan357
Figure 24.ꢀExample 2: overshoot_t1 = 0d; overhoot_t2 = 5d
7.6.2.2 Bit generator
The default coding of a data stream is done by using the Bit-Generator. It is activated
when the value of TxFrameCon.DCodeType is set to 0000 (bin). The Bit-Generator
encodes the data stream byte-wise and can apply the following encoding steps to each
data byte.
1. Add a start-bit of specified type at beginning of every byte
2. Add a stop-bit and EGT bits of a specified type. The maximum number of EGT bit is 6,
only full bits are supported
3. Add a parity-bit of a specified type
4. TxLastBits (skips a given number of bits at the end of the last byte in a frame)
5. Encrypt data-bit (MIFARE Classic encryption)
It is not possible to skip more than 8 bit of a single byte!
By default, data bytes are always treated LSB first.
7.6.3 Receiver circuitry
7.6.3.1 General
The MFRC631 features a versatile quadrature receiver architecture with fully differential
signal input at RXP and RXN. It can be configured to achieve optimum performance for
reception of various 13.56 MHz based protocols.
For all processing units various adjustments can be made to obtain optimum
performance.
7.6.3.2 Block diagram
Figure 25 shows the block diagram of the receiver circuitry. The receiving process
includes several steps. First the quadrature demodulation of the carrier signal of 13.56
MHz is done. Several tuning steps in this circuit are possible.
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fully/quasi-differential
rcv_hpcf<1:0>
rcv_gain<1:0>
rx_p
rx_n
mix_out_i_p
out_i_p
out_i_n
mixer
DATA
mix_out_i_n
2-stage BBA
clk_27 MHz
2-stage BBA
I-clks
rx_p
rx_n
13.56 MHz
I/O CLOCK
GENERATION
TIMING
GENERATION
ADC
clk_27 MHz
Adc_data_ready
DATA
Q-clks
rx_p
rx_n
mix_out_q_p
mix_out_q_n
out_q_p
out_q_n
mixer
rcv_gain<1:0>
rcv_hpcf<1:0>
fully/quasi-differential
001aan358
Figure 25.ꢀBlock diagram of receiver circuitry
The receiver can also be operated in a single ended mode. In this case the
Rcv_RX_single bit has to be set. In the single ended mode, the two receiver pins RXP
and RXN need to be connected together and will provide a single ended signal to the
receiver circuitry.
When using the receiver in a single ended mode the receiver sensitivity is decreased
and the achievable reading distance might be reduced, compared to the fully differential
mode.
Table 24.ꢀConfiguration for single or differential receiver
Mode
rcv_rx_single
pins RXP and RXN
Fully differential
0
provide differential signal from
differential antenna by separate rx-
coupling branches
Quasi differential
1
connect RXP and RXN together
and provide single ended signal
from antenna by a single rx-
coupling branch
The quadrature-demodulator uses two different clocks, Q-clock and I-clock, with a
phase shift of 90° between them. Both resulting baseband signals are amplified, filtered,
digitized and forwarded to a correlation circuitry.
The typical application is intended to implement the Fully differential mode and
will deliver maximum reader/writer distance. The Quasi differential mode can be
used together with dedicated antenna topologies that allow a reduction of matching
components at the cost of overall reading performance.
During low power card detection the DC levels at the I- and Q-channel mixer outputs
are evaluated. This requires that mixers are directly connected to the ADC. This can be
configured by setting the bit Rx_ADCmode in register Rcv (38h).
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7.6.4 Active antenna concept
Two main blocks are implemented in the MFRC631. A digital circuitry, comprising state
machines, coder and decoder logic and an analog circuitry with the modulator and
antenna drivers, receiver and amplification circuitry. For example, the interface between
these two blocks can be configured in the way, that the interfacing signals may be routed
to the pins SIGIN and SIGOUT. The most important use of this topology is the active
antenna concept where the digital and the analog blocks are separated. This opens the
possibility to connect e.g. an additional digital block of another MFRC631 device with a
single analog antenna front-end.
SIGIN
SIGOUT
SIGIN
READER IC
(DIGITAL)
READER IC
(ANTENNA)
SIGOUT
001aam307
Figure 26.ꢀBlock diagram of the active Antenna concept
The Table 24 and Table 25 describe the necessary register configuration for the use
case active antenna concept.
Table 25.ꢀRegister configuration of MFRC631 active antenna concept (DIGITAL)
Register
Value (binary)
Description
SigOut.SigOutSel
Rcv.SigInSel
0100
TxEnvelope
10
11
Receive over SigIn (ISO/IEC14443A)
Receive over SigIn (Generic Code)
DrvCon.TxSel
00
Low (idle)
Table 26.ꢀRegister configuration of MFRC631 active antenna concept (Antenna)
Register
Value (binary)
Description
SigOut.SigOutSel
0110
0111
Generic Code (Manchester)
Manchester with Subcarrier (ISO/IEC14443A)
Rcv.SigInSel
01
10
1
Internal
DrvCon.TxSel
RxCtrl.RxMultiple
External (SigIn)
RxMultiple on
The interface between these two blocks can be configured in the way, that the interfacing
signals may be routed to the pins SIGIN and SIGOUT (see Figure 27 "Overview SIGIN/
SIGOUT Signal Routing").
This topology supports, that some parts of the analog part of the MFRC631 may be
connected to the digital part of another device.
The switch SigOutSel in registerSigOut can be used to measure signals. This is
especially important during the design In phase or for test purposes to check the
transmitted and received data.
However, the most important use of SIGIN/SIGOUT pins is the active antenna concept.
An external active antenna circuit can be connected to the digital circuit of the MFRC631.
SigOutSel has to be configured in that way that the signal of the internal Miller Coder
MFRC631
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is sent to SIGOUT pin (SigOutSel = 4). SigInSel has to be configured to receive
Manchester signal with sub-carrier from SIGIN pin (SigInSel = 1).
It is possible, to connect a passive antenna to pins TX1, TX2 and RX (via the appropriate
filter and matching circuit) and at the same time an active antenna to the pins SIGOUT
and SIGIN. In this configuration, two RF-parts may be driven (one after another) by a
single host processor.
MFRC631
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SIGOUT
tri-state 0, 1
No_nodulation
TX envelope
SIGIN
0
1
2
3
TX2
TX1
TX bit stream
MODULATOR
DRIVER
CODER
LOW
HIGH
2
3
4
5
6
7
8
9
SIGOUTSel[4:0]
TxCon.TxSel
[1:0]
TX envelope
TX active
RFU
S3C signal
RX envelope
RX active
DIGITAL MODULE
ANALOG MODULE
RX bit signal
SUBCARRIER
DEMODULATOR
0
1
2
3
tri-state
internal analog block
SIGIN over envelope
SIGIN generic
RX bit stream
DECODER
RXN
RXP
DEMODULATOR
Sigpro_in_sel
[1:0]
SIGIN
001aam001
Figure 27.ꢀOverview SIGIN/SIGOUT Signal Routing
MFRC631
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7.6.5 Symbol generator
The symbol generator is used to create various protocol symbols. These can be e.g.
SOF or EOF symbols as they are used by the ISO14443 protocols or proprietary protocol
symbols.
Symbols are defined by means of the symbol definition registers and the mode registers.
Four different symbols can be used. Two of them, Symbol0 and Symbol1 have a
maximum pattern length of 16 bit and feature a burst length of up to 256 bits of either
logic "0" or logic "1". The Symbol2 and Symbol3 are limited to 8 bit pattern length and do
not support a burst.
The definition of symbol patterns is done by writing the bit sequence of the pattern to
the appropriate register. The last bit of the pattern to be sent is located at the LSB of
the register. By setting the symbol length in the symbol-length register (TxSym10Len
and TxSym32Len) the definition of the symbol pattern is completed. All other bits at bit-
position higher than the symbol length in the definition register are ignored. (Example:
length of Symbol2 = 5, bit7 and bit6 are ignored, bit5 to bit0 define the symbol pattern,
bit5 is sent first)
Which symbol-pattern is sent can be configured in the TxFrameCon register. Symbol0,
Symbol1 and Symbol2 can be sent before data packets, Symbol1, Symbol2 and Symbol3
can be sent after data packets. Each symbol is defined by a set of registers. Symbols are
configured by a pair of registers. Symbol0 and Symbol1 share the same configuration
and Symbol2 and Symbol3 share the same configuration. The configuration includes
setting of bit-clock- and subcarrier-frequency, as well as selection of the pulse type/length
and the envelope type.
7.7 Memory
7.7.1 Memory overview
The MFRC631 implements three different memories: EEPROM, FIFO and Registers.
At startup, the initialization of the registers which define the behavior of the IC is
performed by an automatic copy of an EEPROM area (read/write EEPROM section1 and
section2, register reset) into the registers. The behavior of the MFRC631 can be changed
by executing the command LoadProtocol, which copies a selected default protocol from
the EEPROM (read only EEPROM section4, register Set Protocol area) into the registers.
The read/write EEPROM section2 can be used to store any user data or predefined
register settings. These predefined settings can be copied with the command
"LoadRegister" into the internal registers.
The FIFO is used as Input/Out buffer and is able to improve the performance of a system
with limited interface speed.
7.7.2 EEPROM memory organization
The MFRC631 has implemented a EEPROM non-volatile memory with a size of 8
kB.The EEPROM is organized in pages of 64 bytes. One page of 64 bytes can be
programmed at a time. Defined purposes had been assigned to specific memory areas
MFRC631
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of the EEPROM, which are called Sections. Five sections 0..4 with different purpose do
exist.
Table 27.ꢀEEPROM memory organization
Section
Page
Byte
addresses
Access Memory content
rights
0
0
00 to 31
r
product information and configuration
32 to 63
r/w
r/w
r/w
w
product configuration
register reset
1
2
3
4
1 to 2
64 to 191
3 to 95
192 to 6143
6144 to 7167
7168 to 8191
free
96 to 111
112 to 128
MIFARE Classic key
Register Set Protocol (RSP)
r
The following figure show the structure of the EEPROM:
Section 0:
Section 1:
Production and config
Register reset
Section 2:
Free
MIFARE Classic
key area (MKA)
Section 3:
Section 4_TX:
Section 4_RX:
RSP-Area for TX
RSP-Area for RX
001aan359
Figure 28.ꢀSector arrangement of the EEPROM
7.7.2.1 Product information and configuration - Page 0
The first EEPROM page includes production data as well as configuration information.
Table 28.ꢀProduction area (Page 0)
Address
(Hex.)
0
1
2
3
4
5
6
7
00
08
ProductID
Version
Unique Identifier
Unique Identifier
Manufacturer
Data
10
18
ManufacturerData
ManufacturerData
MFRC631
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ProductID: Identifier for this MFRC631 product, only address 01h shall be evaluated for
identifying the Product of the CLRC663 family, address 00h and 02h shall be ignored by
software.
Table 29.ꢀProduct ID overview of CLRC663 family
Address 01h
CLRC663
MFRC631
MFRC630
SLRC610
Product ID
01h
C0h
80h
20h
Version: This register indicates the version of the EEPROM initialization data during
production. (Identification of the Hardware version is available in the register 7Fh, not in
the EEPROM Version address. The hardware information in register 7Fh is hardwired
and therefore independent from any EEPROM configuration.)
Unique Identifier: Unique number code for this device
Manufacturer Data: This data is programmed during production. The content is not
intended to be used by any application and might be not the same for different devices.
Therefore this content needs to be considered to be undefined.
Table 30.ꢀConfiguration area (Page 0)
Address
(Hex.)
0
1
2
3
4
5
6
7
20
28
30
38
I2C_Address
Interface I2C SAM_Address DefaultProtRx DefaultProtTx
-
-
TxCRCPreset
RxCRCPreset
-
-
-
-
-
-
-
I2C-Address
Two possibilities exist to define the address of the I2C interface. This can be done either
by configuring the pins IF0, IF2 (address is then 10101xx, xx is defined by the interface
pins IF0, IF2) or by writing value into the I2C address area. The selection, which of this
2-information pin configuration or EEPROM content - is used as I2C-address is done at
EEPROM address 21h (Interface, bit4)
Interface
This section describes the interface byte configuration.
Table 31.ꢀInterface byte
Bit
7
6
5
4
3
2
1
0
I2C_HSP
-
-
I2C_Address
r/w
Boundary Scan
r/w
Host
-
access rights
r/w
RFU
RFU
-
-
MFRC631
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Table 32.ꢀInterface bits
Bit
Symbol
Description
7
I2C_HSP
when cleared, the high speed mode is used
when set, the high speed+ mode is used (default)
6, 5
4
RFU
-
I2C_Address
when cleared, the pins are used (default)
when set, the EEPROM is used
3
Boundary
Scan
when cleared, the boundary scan interface is ON (default)
when set, the boundary scan is OFF
2 to 0
Host
000b - RS232
001b - I2C
010b - SPI
011b - I2CL
1xxb - pin selection
I2C_SAM_Address
The I2C SAM Address is always defined by the EEPROM content.
The Register Set Protocol (RSP) Area contains settings for the TX registers (16 bytes)
and for the RX registers (8 bytes).
Table 33.ꢀTx and Rx arrangements in the register set protocol area
Section
Section 4 TX
Section 4 TX
Section 4 Rx
Section 4 Rx
Tx0
Tx4
RX0
RX8
Tx1
TX2
Tx3
Tx5
TX6
TX7
RX6
RX14
RX1
RX9
RX2
RX10
RX3
RX4
RX12
RX5
RX7
RX11
RX13
RX15
TxCrcPreset
The data bits are send by the analog module and are automatically extended by a CRC.
7.7.3 EEPROM initialization content LoadProtocol
The MFRC631 EEPROM is initialized at production with values which are used to reset
certain registers of the MFRC631 to default settings by copying the EEprom content
to the registers. Only registers or bits with "read/write" or "dynamic" access rights are
initialized with this default values copied from the EEProm.
Note that the addresses used for copying reset values from EEprom to registers are
dependent on the configured protocol and can be changed by the user.
Table 34.ꢀRegister reset values (Hex.) (Page0)
Address 0 (8)
1 (9)
2 (A)
3 (B)
4 (C)
5 (D)
6 (E)
7 (F)
Function Product ID
Version
Unique Identifier
MFRC631
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Address 0 (8)
00 XX
1 (9)
2 (A)
3 (B)
4 (C)
5 (D)
6 (E)
7 (F)
see table 30 XX
XX
XX
XX
XX
XX
Function Unique Identifier
08 XX XX
Factory trim values
Factory trim
value
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
Function TrimLFO
10 XX
XX
XX
XX
XX
Function Factory trim values
18....
XX
XX
Factory trim values
XX XX
....38
The register reset values are configuration parameters used after startup of the IC. They
can be changed to modify the default behavior of the device. In addition to this register
reset values, is the possibility to load settings for various user implemented protocols.The
load protocol command is used for this purpose.
Table 35.ꢀRegister reset values (Hex.)(Page1 and page 2)
Address 0 (8)
Command
40
1 (9)
HostCtrl
00
2 (A)
3 (B)
4 (C)
5 (D)
6 (E)
IRQ0
00
7 (F)
IRQ1
00
FiFoControl WaterLevel FiFoLength FiFoData
40
80
05
00
00
IRQ0En
10
IRQ1En
00
Error
00
Status
00
RxBitCtrl
00
RxColl
00
TControl
00
T0Control
00
48
T0ReloadHi T0ReloadLo T0Counter
ValHi
T0Counter
ValLo
T1Control
T1ReloadHi T1ReloadLo T1Counter
ValHi
50
58
60
68
70
00
80
00
00
00
00
80
00
T1Counter
ValLo
T2Control
T2ReloadHi T2ReloadLo T2Counter
ValHi
T2Counter
ValLo
T3Control
T3ReloadHi
00
00
00
80
00
00
00
00
T3ReloadLo T3Counter
ValHi
T3Counter
ValHi
T4Control
T4ReloadHi T4ReloadLo T4Counter
ValHi
T4Counter
ValLo
80
00
00
00
00
80
00
00
DrvMode
TxAmp
DrvCon
Txl
TxCRC
Preset
RxCRC
Preset
TxDataNum TxModWith
86
15
11
06
18
18
08
27
TxSym10
BurstLen
TxWaitCtrl
TxWaitLo
FrameCon
RxSofD
RxCtrl
RxWait
RxThres
hold
00
C0
12
CF
00
04
90
3F
Rcv
12
RxAna
0A
RFU
00
SerialSpeed LFO_trimm PLL_Ctrl
7A 80 04
PLL_Div
20
LPCD_QMin
48
78
MFRC631
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Address 0 (8)
LPCD_
1 (9)
2 (A)
3 (B)
4 (C)
5 (D)
6 (E)
7 (F)
LPCD_IMin LPCD
LPCD
PadEn
PadOut
PadIn
SigOut
_result_I
00
_result_Q
QMax
80
88
12
88
00
00
00
00
00
TxBitMod
20
RFU
xx
TxDataCon TxDataMod TxSymFreq TxSym0H
TySym0L
00
TxSym1H
00
04
50
40
00
TxSym1L
0x00
TxSym2
0x00
TxSym3
TxSym10Le TxSym32Le TxSym32Bu TxSym10M TxSym32M
ngth
ngth
rstCtrl
od
od
90
98
0x00
0x00
0x00
0x00
0x00
0x50
RxBitMod
0x02
RxEOFSym RxSyncValH RxSyncValL RxSyncMod RxMod
0x00 0x00 0x01 0x00 0x08
RXCorr
0x08
FabCal
0xB2
7.8 Clock generation
7.8.1 Crystal oscillator
The clock applied to the MFRC631 acts as time basis for generation of the carrier sent
out at TX and for the quadrature mixer I and Q clock generation as well as for the coder
and decoder of the synchronous system. Therefore stability of the clock frequency is an
important factor for proper performance. To obtain highest performance, clock jitter has
to be as small as possible. This is best achieved by using the internal oscillator buffer
with the recommended circuitry.
READER IC
XTAL1 XTAL2
27.12 MHz
001aam308
Figure 29.ꢀQuartz connection
Table 36.ꢀCrystal requirements recommendations
Symbol
fxtal
Parameter
Conditions
Min
-
Typ
27.12
-
max
-
Unit
MHz
ppm
crystal frequency
Δfxtal/fxtal
relative crystal
-250
+250
frequency variation
ESR
equivalent series
resistance
-
50
100
Ω
CL
load capacitance
-
-
10
50
-
pF
Pxtal
crystal power
dissipation
100
μW
MFRC631
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7.8.2 IntegerN PLL clock line
The MFRC631 is able to provide a clock with configurable frequency at CLKOUT from
1 MHz to 24 MHz (PLL_Ctrl and PLL_DIV). There it can serve as a clock source to a
microcontroller which avoids the need of a second crystal oscillator in the reader system.
Clock source for the IntegerN-PLL is the 27.12 MHz crystal oscillator.
Two dividers are determining the output frequency. First a feedback integer-N divider
configures the VCO frequency to be N × fin/2 (control signal pll_set_divfb). As supported
Feedback Divider Ratios are 23, 27 and 28, VCO frequencies can be 23 × fin / 2 (312
MHz), 27 × fin / 2 (366 MHz) and 28 × fin / 2 (380 MHz).
The VCO frequency is divided by a factor which is defined by the output divider
(pll_set_divout). Table 36 "Divider values for selected frequencies using the integerN
PLL" shows the accuracy achieved for various frequencies (integer multiples of 1 MHz
and some typical RS232 frequencies) and the divider ratios to be used. The register bit
ClkOutEn enables the clock at CLKOUT pin.
The following formula can be used to calculate the output frequency:
fout = 13.56 MHz × PLLDiv_FB /PLLDiv_Out
Table 37.ꢀDivider values for selected frequencies using the integerN PLL
Frequency [MHz]
PLLDiv_FB
4
6
8
10
28
38
12
23
26
20
28
19
24
23
16
1.8432 3.6864
23
78
27
61
23
39
28
28
PLLDiv_Out
206
103
0.01
accuracy [%]
0.04 0.03 0.04 0.08 0.04 0.08 0.04 0.01
7.8.3 Low Frequency Oscillator (LFO)
The MFRC631 implements an Low-Frequency Oscillator (LFO). Timer T4 can be
configured to use a clock generated by this LFO as input clock, and can be configured
as wakeup counter. As wakeup counter, the timer T4 allows to wake up the system in
regular time intervals which allows to design a reader that is regularly polling for card
presence or implements a low-power card detection (LPCD).
The LFO is trimmed during chip production to run at 16 kHz. Unless a high accuracy
of the LFO is required by the application, and the device is operated in an environment
with changing ambient temperatures, trimming of the LFO is not required. For a typical
application making use of the LFO for wake-up from power saving mode, the trim value
set during production can be used.
Optional trimming to achieve a higher accuracy of the 16 kHz LFO clock is supported by
a digital state machine which compares LFO-clock to a reference clock generated by the
connected 27.12Mhz crystal. As reference clock frequency for trimming of the LFO, a
13.56 MHz clock (27.12Mhz divided by 2 ) input clock to one of the timers T0,T1,T2 or T3
is used.
One of the timers T0,T1,T2,T3 with an input clock of 13,56 MHz crystal clock is used to
count one clock period of the LFO. For an LFO Clock running at 16KHz this would result
in 848 wakeup timer clocks of timer Tx (T0, T1, T2, T3). Therefrore, the timer count value
Tx at the end of a trimming cycle is expected to be 176 (wakeup timer is counting down:
1023-848=175, +/- 1 tolerance is accepted). The trim cycle is executed once in the T4
timer cycle. Therefore the T4 autoload value shall be bigger than 0x05 to ensure that
one trimming cycle takes place before T4 expires. The Tx timer value is reloaded to 1023
MFRC631
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during the start of an Auto trim cycle. This happens every time, once after the T4 timer
underflows.
At the end of each trim cycle, the timer value is checked:
• Timer Tx value < 174: LFO Frequency is too low and the trim value is incremented by 1
on T4 Timer event
• Timer Tx value > 176: LFO Frequency is too high and the trim value is decremented by
1 on T4 Timer event
• Timer Tx value is within 174 and 176: LFO Frequency = 16 KHz and trimming
procedure is stopped
The cycle proceeds until the autotrimm function is stopped (Timer Tx value is within 174
and 176).
In addition, the trimming cycle can be aborted by sending an IDLE Command from the
host to cancel the current command execution. T3 is not allowed to be used in case
T4AutoLPCD is set in parallel. It is not required to configure a TXStart condition with
underflow. The T0/1/2/3 timer will typically not underflow. It may happen if the LPO clock
is very slow, but it is not required to take an action to generate this event.
7.9 Power management
7.9.1 Supply concept
The MFRC631 is supplied by VDD (Supply Voltage), PVDD (Pad Supply) and TVDD
(Transmitter Power Supply). These three voltages are independent from each other.
To connect the MFRC631 to a Microcontroller supplied by 3.3 V, PVDD and VDD shall be
at a level of 3.3 V, TVDD can be in a range from 3.3 V to 5.0 V. A higher supply voltage
at TVDD will result in a higher field strength.
Independent of the voltage it is recommended to buffer these supplies with blocking
capacitances close to the terminals of the package. VDD and PVDD are recommended to
be blocked with a capacitor of 100 nF min, TVDD is recommended to be blocked with 2
capacitors, 100 nF parallel to 1.0 μF
AVDD and DVDD are not supply input pins. They are output pins and shall be connected
to blocking capacitors 470 nF each.
7.9.2 Power reduction mode
7.9.2.1 Power-down
A hard power-down is enabled with HIGH level on pin PDOWN. This turns off the internal
1.8 V voltage regulators for the analog and digital core supply as well as the oscillator.
All digital input buffers are separated from the input pads and clamped internally (except
pin PDOWN itself). The output pins are switched to high impedance. HardPowerDown is
performing a reset of the IC. All registers will be reset, the Fifo will be cleared.
To leave the power-down mode the level at the pin PDOWN as to be set to LOW. This
will start the internal start-up sequence.
MFRC631
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7.9.2.2 Standby mode
The standby mode is entered immediately after setting the bit PowerDown in the register
Command. All internal current sinks are switched off. Voltage references and voltage
regulators will be set into stand-by mode.
In opposition to the power-down mode, the digital input buffers are not separated by the
input pads and keep their functionality. The digital output pins do not change their state.
During standby mode, all registers values, the FIFO’s content and the configuration itself
will keep its current content.
To leave the standby mode the bit PowerDown in the register Command is cleared. This
will trigger the internal start-up sequence. The reader IC is in full operation mode again
when the internal start-up sequence is finalized (the typical duration is 15 us).
A value of 55h must be sent to the MFRC631 using the RS232 interface to leave the
standby mode. This is must at RS232, but cannot be used for the I2C/SPI interface. Then
read accesses shall be performed at address 00h until the device returns the content of
this address. The return of the content of address 00h indicates that the device is ready
to receive further commands and the internal start-up sequence is finalized.
7.9.2.3 Modem off mode
When the ModemOff bit in the register Control is set the antenna transmitter and the
receiver are switched off.
To leave the modem off mode clears the ModemOff bit in the register Control.
7.9.3 Low-Power Card Detection (LPCD)
The low-power card detection is an energy saving mode in which the MFRC631 is not
fully powered permanently.
The LPCD works in two phases. First the standby phase is controlled by the wake-up
counter (WUC), which defines the duration of the standby of the MFRC631. Second
phase is the detection-phase. In this phase the values of the I and Q channel are
detected and stored in the register map. (LPCD_I_Result, LPCD_Q_Result).This time
period can be handled with Timer3. The value is compared with the min/max values in
the registers (LPCD_IMin, LPCD_IMax; LPCD_QMin, LPCD_QMax). If it exceeds the
limits, a LPCDIRQ is raised.
After the command LPCD the standby of the MFRC631 is activated, if selected.
The wake-up Timer4 can activate the system after a given time. For the LPCD it is
recommended to set T4AutoWakeUp and T4AutoRestart, to start the timer and then go
to standby. If a card is detected the communication can be started. If T4AutoWakeUp is
not set, the IC will not enter Standby mode in case no card is detected.
7.9.4 Reset and start-up time
A 10 μs constant high level at the PDOWN pin starts the internal reset procedure.
The following figure shows the internal voltage regulator:
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V
DD
PVDD
AVDD
DVDD
1.8 V
GLITCH
FILTER
INTERNAL VOLTAGE
REGULATOR
PDown
1.8 V
V
SS
V
SS
001aan360
Figure 30.ꢀInternal PDown to voltage regulator logic
When the MFRC631 has finished the reset phase and the oscillator has entered a stable
working condition the IC is ready to be used. A typical duration before the IC is ready to
receive commands after the reset had been released is 2.5ms.
7.10 Command set
7.10.1 General
The behavior is determined by a state machine capable to perform a certain set of
commands. By writing a command-code to the command register the command is
executed.
Arguments and/or data necessary to process a command, are exchanged via the FIFO
buffer.
• Each command that needs a certain number of arguments will start processing only
when it has received the correct number of arguments via the FIFO buffer.
• The FIFO buffer is not cleared automatically at command start. It is recommended to
write the command arguments and/or the data bytes into the FIFO buffer and start the
command afterwards.
• Each command may be stopped by the host by writing a new command code into the
command register e.g.: the Idle-Command.
7.10.2 Command set overview
Table 38.ꢀCommand set
Command
Idle
No.
00h
01h
02h
Parameter (bytes)
Short description
-
-
no action, cancels current command execution
low-power card detection
LPCD
LoadKey
(keybyte1),(keybyte2), (keybyte3),
(keybyte4), (keybyte5),(keybyte6);
reads a MIFARE Classic key (size of 6 bytes) from
FIFO buffer ant puts it into Key buffer
MFAuthent
03h
60h or 61h, (block address), (card
serial number byte0),(card serial
number byte1), (card serial number
byte2),(card serial number byte3);
performs the MIFARE Classic authentication
AckReq
04h
-
performs a query, an Ack and a Req-Rn for ISO/IEC
18000-3 mode 3/ EPC Class-1 HF
Receive
Transmit
05h
06h
-
activates the receive circuit
bytes to send: byte1, byte2,....
transmits data from the FIFO buffer
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Command
No.
Parameter (bytes)
Short description
Transceive
07h
bytes to send: byte1, byte2,....
transmits data from the FIFO buffer and automatically
activates the receiver after transmission finished
WriteE2
08h
09h
0Ah
0Ch
addressH, addressL, data;
gets one byte from FIFO buffer and writes it to the
internal EEPROM
WriteE2Page
ReadE2
(page Address), data0,
[data1 ..data63];
gets up to 64 bytes (one EEPROM page) from the FIFO
buffer and writes it to the EEPROM
addressH, address L, length;
reads data from the EEPROM and copies it into the
FIFO buffer
LoadReg
(EEPROM addressH), (EEPROM
addressL), RegAdr, (number of
Register to be copied);
reads data from the internal EEPROM and initializes
the MFRC631 registers. EEPROM address needs to be
within EEPROM sector 2
LoadProtocol
0Dh
(Protocol number RX), (Protocol
number TX);
reads data from the internal EEPROM and initializes the
MFRC631 registers needed for a Protocol change
LoadKeyE2
StoreKeyE2
0Eh
0Fh
KeyNr;
copies a key from the EEPROM into the key buffer
KeyNr, byte1,byte2, byte3, byte4,
byte5,byte6;
stores a MIFARE Classic key (size of 6 bytes) into the
EEPROM
ReadRNR
Soft Reset
1Ch
1Fh
-
Copies bytes from the Random Number generator into
the FIFO until the FiFo is full
-
resets the MFRC631
7.10.3 Command functionality
7.10.3.1 Idle command
Command (00h);
This command indicates that the MFRC631 is in idle mode. This command is also used
to terminate the actual command.
7.10.3.2 LPCD command
Command (01h);
This command performs a low-power card detection and/or an automatic trimming of
the LFO. After wakeup from standby, the values of the sampled I and Q channels are
compared with the min/max threshold values in the registers. If it exceeds the limits, an
LPCD_IRQ will be raised. After the LPCD command the standby is activated, if selected.
7.10.3.3 Load key command
Command (02h), Parameter1 (key byte1),..., Parameter6 (key byte6);
Loads a MIFARE Classic key (6 bytes) for Authentication from the FIFO into the crypto
unit.
Abort condition: Less than 6 bytes written to the FIFO.
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7.10.3.4 MFAuthent command
Command (03h), Parameter1 (Authentication command code 60h or 61h), Parameter2
(block address), Parameter3 (card serial number byte0), Parameter4 (card serial number
byte1), Parameter5 (card serial number byte2), Parameter6 (card serial number byte3);
This command handles the MIFARE Classic authentication in Reader/Writer mode to
ensure a secure communication to any MIFARE Classic card.
When the MFAuthent command is active, any FIFO access is blocked. Anyhow if there is
an access to the FIFO, the bit WrErr in the Error register is set.
This command terminates automatically when the MIFARE Classic card is authenticated
and the bit MFCrypto1On is set to logic 1.
This command does not terminate automatically, when the card does not answer,
therefore the timer should be initialized to automatic mode. In this case, beside the bit
IdleIRQ the bit TimerIRQ can be used as termination criteria. During authentication
processing the bits RxIRQ and TxIRQ are blocked. The Crypto1On shows if the
authentication was successful. The Crypto1On is always valid.
In case there is an error during authentication, the bit ProtocolErr in the Error register is
set to logic 1 and the bit Crypto1On in register Status2Reg is set to logic 0.
7.10.3.5 Receive command
Command (05h);
The MFRC631 activates the receiver path and waits for any data stream to be received,
according to its register settings. The registers must be set before starting this command
according to the used protocol and antenna configuration. The correct settings have to be
chosen before starting the command.
This command terminates automatically when the received data stream ends. This
is indicated either by the end of frame pattern or by the length byte depending on the
selected framing and speed.
7.10.3.6 Transmit command
Command (06h); data to transmit
The content of the FIFO is transmitted immediately after starting the command. Before
transmitting the FIFO all relevant registers have to be set to transmit data.
This command terminates automatically when the FIFO gets empty. It can be terminated
by any other command written to the command register.
7.10.3.7 Transceive command
Command (07h); data to transmit
This command transmits data from FIFO buffer and automatically activates the receiver
after a transmission is finished.
Each transmission process starts by writing the command into CommandReg.
Remark: If the bit RxMultiple in register RxModeReg is set to logic 1, this command will
never leave the receiving state, because the receiving will not be cancelled automatically.
MFRC631
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7.10.3.8 WriteE2 command
Command (08h), Parameter1 (addressH), Parameter2 (addressL), Parameter3 (data);
This command writes one byte into the EEPROM. If the FIFO contains no data, the
command will wait until the data is available.
Abort condition: Address-parameter outside of allowed range 0x00 – 0x7F.
7.10.3.9 WriteE2PAGE command
Command (09h), Parameter1 (page address), Parameter2..63 (data0, data1...data63);
This command writes up to 64 bytes into the EEPROM. The addresses are not allowed
to wrap over a page border. If this is the case, this additional data be ignored and stays
in the fifo. The programming starts after 64 bytes are read from the FIFO or the FIFO is
empty.
Abort condition: Insufficient parameters in FIFO; Page address parameter outside of
range 0x00 – 0x7F.
7.10.3.10 ReadE2 command
Command (0Ah), Parameter1 (addressH), Parameter2 (addressL), Parameter3 (length);
Reads up to 256 bytes from the EEPROM to the FIFO. If a read operation exceeds the
address 1FFFh, the read operation continues from address 0000h.
Abort condition: Insufficient parameter in FIFO; Address parameter outside of range.
7.10.3.11 LoadReg command
Command (0Ch), Parameter1 (EEPROM addressH),Parameter2 (EEPROM addressL),
Parameter3 (RegAdr), Parameter4 (number);
Read a defined number of bytes from the EEPROM and copies the value into the
Register set, beginning at the given address RegAdr.
Abort condition: Insufficient parameter in FIFO; Address parameter outside of range.
7.10.3.12 LoadProtocol command
Command (0Dh), Parameter1 (Protocol number RX), Parameter2 (Protocol number TX);
Reads out the EEPROM Register Set Protocol Area and overwrites the content of the
Rx- and Tx- related registers. These registers are important for a Protocol selection.
Abort condition: Insufficient parameter in FIFO
Table 39.ꢀPredefined protocol overview RX[1]
Protocol
Number
(decimal)
Protocol
Receiver speed
[kbits/s]
Receiver Coding
00
01
02
ISO/IEC14443 A
ISO/IEC14443 A
ISO/IEC14443 A
106
212
424
Manchester SubC
BPSK
BPSK
MFRC631
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Protocol
Number
Protocol
Receiver speed
[kbits/s]
Receiver Coding
(decimal)
03
04
05
06
07
ISO/IEC14443 A
ISO/IEC14443 B
ISO/IEC14443 B
ISO/IEC14443 B
ISO/IEC14443 B
848
106
212
424
848
BPSK
BPSK
BPSK
BPSK
BPSK
[1] For more protocol details please refer to Section 7 "Functional description".
Table 40.ꢀPredefined protocol overview TX[1]
Protocol
Number
(decimal)
Protocol
Transmitter speed Transmitter Coding
[kbits/s]
00
01
02
03
04
05
06
07
ISO/IEC14443 A
ISO/IEC14443 A
ISO/IEC14443 A
ISO/IEC14443 A
ISO/IEC14443 B
ISO/IEC14443 B
ISO/IEC14443 B
ISO/IEC14443 B
106
212
424
848
106
212
424
848
Miller
Miller
Miller
Miller
NRZ
NRZ
NRZ
NRZ
[1] For more protocol details please refer to Section 7 "Functional description".
7.10.3.13 LoadKeyE2 command
Command (0Eh), Parameter1 (key number);
Loads a MIFARE Classic key for authentication from the EEPROM into the crypto 1 unit.
Abort condition: Insufficient parameter in FIFO; KeyNr is outside the MIFARE Classic key
area.
7.10.3.14 StoreKeyE2 command
Command (0Fh), Parameter1 (KeyNr), Parameter2(keybyte1), Parameter3(keybyte2),
Parameter4(keybyte3), Parameter5(keybyte4), Parameter6(keybyte5), Parameter7
(keybyte6);
Stores MIFARE Classic keys into the EEPROM. The key number parameter indicates
the first key (n) in the MKA that will be written. If more than one MIFARE Classic key is
available in the FIFO then the next key (n+1) will be written until the FIFO is empty. If an
incomplete key (less than 6 bytes) is written into the FIFO, this key will be ignored and
will remain in the FIFO.
Abort condition: Insufficient parameter in FIFO; KeyNr is outside the MKA;
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7.10.3.15 GetRNR command
Command (1Ch);
This command is reading Random Numbers from the random number generator of the
MFRC631. The Random Numbers are copied to the FIFO until the FIFO is full.
7.10.3.16 SoftReset command
Command (1Fh);
This command is performing a soft reset. Triggered by this command all the default
values for the register setting will be read from the EEPROM and copied into the register
set.
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8 MFRC631 registers
8.1 Register bit behavior
Depending on the functionality of a register, the access conditions to the register can
vary. In principle, bits with same behavior are grouped in common registers. The access
conditions are described in Table 40.
Table 41.ꢀBehavior of register bits and their designation
Abbreviation
Behavior
Description
r/w
read and write These bits can be written and read via the host interface. Since
they are used only for control purposes, the content is not
influenced by the state machines but can be read by internal
state machines.
dy
r
dynamic
These bits can be written and read via the host interface. They
can also be written automatically by internal state machines,
for example Command register changes its value automatically
after the execution of the command.
read only
These register bits indicates hold values which are determined
by internal states only.
w
write only
-
Reading these register bits always returns zero.
RFU
These bits are reserved for future use and must not be
changed. In case of a required write access, it is recommended
to write a logic 0.
8.2 MFRC631 registers overview
The following table gives an overview on the registers which can be modified by the
host. Please note that not all registers available for the CLRC663 are available on the
MFRC631.
Table 42.ꢀMFRC631 registers overview
Address
00h
Register name
Command
HostCtrl
Function
Starts and stops command execution
Host control register
01h
02h
FIFOControl
WaterLevel
FIFOLength
FIFOData
IRQ0
Control register of the FIFO
03h
Level of the FIFO underflow and overflow warning
Length of the FIFO
04h
05h
Data In/Out exchange register of FIFO buffer
Interrupt register 0
06h
07h
IRQ1
Interrupt register 1
08h
IRQ0En
Interrupt enable register 0
09h
IRQ1En
Interrupt enable register 1
0Ah
0Bh
MFRC631
Error
Error bits showing the error status of the last command execution
Contains status of the communication
Status
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Address
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
Register name
RxBitCtrl
Function
Control register for anticollision adjustments for bit oriented protocols
Collision position register
RxColl
TControl
Control of Timer 0..3
T0Control
Control of Timer0
T0ReloadHi
T0ReloadLo
T0CounterValHi
T0CounterValLo
T1Control
High register of the reload value of Timer0
Low register of the reload value of Timer0
Counter value high register of Timer0
Counter value low register of Timer0
Control of Timer1
T1ReloadHi
T1ReloadLo
T1CounterValHi
T1CounterValLo
T2Control
High register of the reload value of Timer1
Low register of the reload value of Timer1
Counter value high register of Timer1
Counter value low register of Timer1
Control of Timer2
T2ReloadHi
T2ReloadLo
T2CounterValHi
T2CounterValLo
T3Control
High byte of the reload value of Timer2
Low byte of the reload value of Timer2
Counter value high byte of Timer2
Counter value low byte of Timer2
Control of Timer3
T3ReloadHi
T3ReloadLo
T3CounterValHi
T3CounterValLo
T4Control
High byte of the reload value of Timer3
Low byte of the reload value of Timer3
Counter value high byte of Timer3
Counter value low byte of Timer3
Control of Timer4
T4ReloadHi
T4ReloadLo
T4CounterValHi
T4CounterValLo
DrvMod
High byte of the reload value of Timer4
Low byte of the reload value of Timer4
Counter value high byte of Timer4
Counter value low byte of Timer4
Driver mode register
TxAmp
Transmitter amplifier register
DrvCon
Driver configuration register
Txl
Transmitter register
TxCrcPreset
RxCrcPreset
TxDataNum
TxModWidth
TxSym10BurstLen
Transmitter CRC control register, preset value
Receiver CRC control register, preset value
Transmitter data number register
Transmitter modulation width register
Transmitter symbol 1 + symbol 0 burst length register
MFRC631
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Address
31h
Register name
TXWaitCtrl
TxWaitLo
FrameCon
RxSofD
Function
Transmitter wait control
Transmitter wait low
Transmitter frame control
Receiver start of frame detection
Receiver control register
Receiver wait register
Receiver threshold register
Receiver register
32h
33h
34h
35h
RxCtrl
36h
RxWait
37h
RxThreshold
Rcv
38h
39h
RxAna
Receiver analog register
-
3Ah
MFRC63102: RFU
MFRC63103: LPCD options
SerialSpeed
LFO_Trimm
PLL_Ctrl
LPCD settings only available for MFRC63103
Serial speed register
3Bh
3Ch
3Dh
3Eh
3Fh
40h
Low-power oscillator trimming register
IntegerN PLL control register, for microcontroller clock output adjustment
IntegerN PLL control register, for microcontroller clock output adjustment
Low-power card detection Q channel minimum threshold
Low-power card detection Q channel maximum threshold
Low-power card detection I channel minimum threshold
Low-power card detection I channel result register
Low-power card detection Q channel result register
PIN enable register
PLL_DivOut
LPCD_QMin
LPCD_QMax
LPCD_IMin
LPCD_I_Result
LPCD_Q_Result
PadEn
41h
42h
43h
44h
45h
PadOut
PIN out register
46h
PadIn
PIN in register
47h
SigOut
Enables and controls the SIGOUT Pin
-
48h-5Fh
7Fh
RFU
Version
Version and subversion register
8.3 Command configuration
8.3.1 Command
Starts and stops command execution.
Table 43.ꢀCommand register (address 00h)
Bit
7
6
5
4
3
2
1
0
Symbol Standby
Modem
Off
RFU
Command
MFRC631
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Bit
7
6
5
4
3
2
1
0
Access
rights
dy
r/w
-
dy
Table 44.ꢀCommand bits
Bit
7
Symbol
Description
Standby
ModemOff
Set to 1, the IC is entering power-down mode.
6
Set to logic 1, the receiver and the transmitter circuit is powering
down.
5
RFU
-
4 to 0
Command
Defines the actual command for the MFRC631.
8.4 SAM configuration register
8.4.1 HostCtrl
Via the HostCtrl Register the interface access right can be controlled
Table 45.ꢀHostCtrl register (address 01h);
Bit
7
RegEn
dy
6
5
4
RFU
-
3
SAMInterface
r/w
2
SAMInterface
r/w
1
RFU
-
0
Symbol
BusHost
r/w
BusSAM
r/w
RFU
-
Access
rights
Table 46.ꢀHostCtrl bits
Bit
Symbol
Description
7
RegEn
If this bit is set to logic 1, the register HostCtrl_reg can be changed
at the next register access. The next write access clears this bit
automatically.
6
5
BusHost
BusSAM
RFU
Set to logic 1, the bus is controlled by the host. This bit cannot be set
together with the bit BusSAM. This bit can only be set if the bit RegEn
is previously set.
Set to logic 1, the bus is controlled by the SAM. This bit cannot be
set together with BusHost. This bit can only be set if the bit RegEn is
previously set.
4
-
3 to 2
SAMInterface 0h:SAM Interface switched off
1h:SAM Interface SPI active
2h:SAM Interface I2CL active
3h:SAM Interface I2C active
1 to 0
RFU
-
MFRC631
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8.5 FIFO configuration register
8.5.1 FIFOControl
FIFOControl defines the characteristics of the FIFO
Table 47.ꢀFIFOControl register (address 02h);
Bit
7
6
5
4
3
2
1
0
Symbol
FIFOSize
HiAlert
LoAlert
FIFOFlush
RFU
WaterLe
velExtBit
FIFOLengthExtBits
Access
rights
r/w
r
r
w
-
r/w
r
Table 48.ꢀFIFOControl bits
Bit
Symbol
Description
7
FIFOSize
Set to logic 1, FIFO size is 255 bytes;
Set to logic 0, FIFO size is 512 bytes.
It is recommended to change the FIFO size only, when the FIFO
content had been cleared.
6
5
4
HiAlert
Set to logic 1, when the number of bytes stored in the FIFO
buffer fulfils the following equation:
HiAlert = (FIFOSize - FIFOLength) <= WaterLevel
LoAlert
Set to logic 1, when the number of bytes stored in the FIFO
buffer fulfils the following conditions:
LoAlert =1 if FIFOLength <= WaterLevel
FIFOFlush
Set to logic 1 clears the FIFO buffer. Reading this bit will always
return 0
3
2
RFU
-
WaterLevelExtBit
Defines the bit 8 (MSB) for the waterlevel (extension of register
WaterLevel). This bit is only evaluated in the 512-byte FIFO
mode. Bits 7..0 are defined in register WaterLevel.
1 to 0
FIFOLengthExtBits Defines the bit9 (MSB) and bit8 for the FIFO length (extension of
FIFOLength). These two bits are only evaluated in the 512-byte
FIFO mode, The bits 7..0 are defined in register FIFOLength.
8.5.2 WaterLevel
Defines the level for FIFO under- and overflow warning levels.This register is extended
by 1 bit in FIFOControl in case the 512-byte FIFO mode is activated by setting bit
FIFOControl.FIFOSize.
Table 49.ꢀWaterLevel register (address 03h);
Bit
7
6
5
4
3
2
1
0
Symbol
WaterLevelBits
r/w r/w
Access
rights
r/w
r/w
r/w
r/w
r/w
r/w
MFRC631
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Table 50.ꢀWaterLevel bits
Bit
Symbol
Description
7 to 0
WaterLevelBits
Sets a level to indicate a FIFO-buffer state which can be read
from bits HighAlert and LowAlert in the FifoControl. In 512-byte
FIFO mode, the register is extended by bit WaterLevelExtBit in the
FIFOControl. This functionality can be used to avoid a FIFO buffer
overflow or underflow:
The bit HiAlert bit in FIFO Control is read logic 1, if the number of
bytes in the FIFO-buffer is equal or less than the number defined by
the waterlevel configuration.
The bit LoAlert bit in FIFO control is read logic 1, if the number of
bytes in the FIFO buffer is equal or less than the number defined by
the waterlevel configuration.
Note: For the calculation of HiAlert and LoAlert see register
description of these bits (Section 8.4.1 "FIFOControl").
8.5.3 FIFOLength
Number of bytes in the FIFO buffer. In 512-byte mode this register is extended by
FIFOControl.FifoLength.
Table 51.ꢀFIFOLength register (address 04h); reset value: 00h
Bit
7
6
5
4
3
2
1
0
Symbol
FIFOLength
dy
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Table 52.ꢀFIFOLength bits
Bit
Symbol
Description
7 to 0
FIFOLength
Indicates the number of bytes in the FIFO buffer. In 512-byte
mode this register is extended by the bits FIFOLength in the
FIFOControl register. Writing to the FIFOData register increments,
reading decrements the number of available bytes in the FIFO.
8.5.4 FIFOData
In- and output of FIFO buffer. Contrary to any read/write access to other addresses,
reading or writing to the FIFO address does not increment the address pointer. Writing
to the FIFOData register increments, reading decrements the number of bytes present in
the FIFO.
Table 53.ꢀFIFOData register (address 05h);
Bit
7
6
5
4
3
2
1
0
Symbol
FIFOData
dy
Access
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dy
dy
dy
dy
dy
dy
dy
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Table 54.ꢀFIFOData bits
Bit
Symbol
Description
7 to 0
FIFOData
Data input and output port for the internal FIFO buffer. Refer to
Section 7.5 "Buffer".
8.6 Interrupt configuration registers
The Registers IRQ0 register and IRQ1 register implement a special functionality to avoid
the unintended modification of bits.
The mechanism of changing register contents requires the following consideration:
IRQ(x).Set indicates, if a set bit on position 0 to 6 shall be cleared or set. Depending
on the content of IRQ(x).Set, a write of a 1 to positions 0 to 6 either clears or sets the
corresponding bit. With this register the application can modify the interrupt status which
is maintained by the MFRC631.
Bit 7 indicates, if the intended modification is a setting or clearance of a bit. Any 1 written
to a bit position 6...0 will trigger the setting or clearance of this bit as defined by bit 7.
Example: writing FFh sets all bits 6..0, writing 7Fh clears all bits 6..0 of the interrupt
request register
8.6.1 IRQ0 register
Interrupt request register 0.
Table 55.ꢀIRQ0 register (address 06h); reset value: 00h
Bit
7
6
5
4
3
2
1
0
Symbol
Set
Hi AlertIRQ
Lo
AlertIRQ
IdleIRQ
TxIRQ
RxIRQ
ErrIRQ
RxSOF
IRQ
Access
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w
dy
dy
dy
dy
dy
dy
dy
Table 56.ꢀIRQ0 bits
Bit
Symbol
Description
7
Set
1: writing a 1 to a bit position 6..0 sets the interrupt request
0: Writing a 1 to a bit position 6..0 clears the interrupt request
6
5
4
HiAlerIRQ Set, when bit HiAlert in register Status1Reg is set. In opposition to HiAlert,
HiAlertIRQ stores this event.
LoAlertIRQ Set, when bit LoAlert in register Status1 is set. In opposition to LoAlert,
LoAlertIRQ stores this event.
IdleIRQ
Set, when a command terminates by itself e.g. when the Command
changes its value from any command to the Idle command. If an unknown
command is started, the Command changes its content to the idle state and
the bit IdleIRQ is set. Starting the Idle command by the Controller does not
set bit IdleIRQ. .
3
TxIRQ
Set, when data transmission is completed, which is immediately after the
last bit is sent.
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Bit
Symbol
Description
2
RxIRQ
Set, when the receiver detects the end of a data stream.
Note: This flag is no indication that the received data stream is correct. The
error flags have to be evaluated to get the status of the reception.
1
0
ErrIRQ
Set, when the one of the following errors is set:
FifoWrErr, FiFoOvl, ProtErr, NoDataErr, IntegErr.
RxSOFlrq Set, when a SOF or a subcarrier is detected.
8.6.2 IRQ1 register
Interrupt request register 1.
Table 57.ꢀIRQ1 register (address 07h)
Bit
7
Set
w
6
5
4
3
2
Timer2IRQ
dy
1
0
Symbol
GlobalIRQ LPCD_IRQ Timer4IRQ Timer3IRQ
Timer1IRQ Timer0IRQ
dy dy
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dy
dy
dy
dy
Table 58.ꢀIRQ1 bits
Bit
Symbol
Description
7
Set
1: writing a 1 to a bit position 5..0 sets the interrupt request
0: Writing a 1 to a bit position 5..0 clears the interrupt request
6
5
4
3
2
1
0
GlobalIRQ Set, if an enabled IRQ occurs.
LPCD_IRQ Set if a card is detected in Low-power card detection sequence.
Timer4IRQ Set to logic 1 when Timer4 has an underflow.
Timer3IRQ Set to logic 1 when Timer3 has an underflow.
Timer2IRQ Set to logic 1 when Timer2 has an underflow.
Timer1IRQ Set to logic 1 when Timer1 has an underflow.
Timer0IRQ Set to logic 1 when Timer0 has an underflow.
8.6.3 IRQ0En register
Interrupt request enable register for IRQ0. This register allows to define if an interrupt
request is processed by the MFRC631.
Table 59.ꢀIRQ0En register (address 08h)
Bit
7
6
5
4
3
2
1
0
Symbol
IRQ_Inv Hi AlertIRQEn LoAlertIRQEn IdleIRQEn
TxIRQEn
RxIRQEn ErrIRQEn
RxSOF
IRQEn
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r/w r/w r/w r/w
r/w
r/w r/w
r/w
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Table 60.ꢀIRQ0En bits
Bit
7
Symbol
Description
IRQ_Inv
Set to one the signal of the IRQ pin is inverted
6
Hi AlerIRQEn Set to logic 1, it allows the High Alert interrupt Request (indicated by the
bit HiAlertIRQ) to be propagated to the GlobalIRQ
5
4
3
2
1
0
Lo AlertIRQEn Set to logic 1, it allows the Low Alert Interrupt Request (indicated by the
bit LoAlertIRQ) to be propagated to the GlobalIRQ
IdleIRQEn
TxIRQEn
RxIRQEn
ErrIRQEn
Set to logic 1, it allows the Idle interrupt request (indicated by the bit
IdleIRQ) to be propagated to the GlobalIRQ
Set to logic 1, it allows the transmitter interrupt request (indicated by the
bit TxtIRQ) to be propagated to the GlobalIRQ
Set to logic 1, it allows the receiver interrupt request (indicated by the bit
RxIRQ) to be propagated to the GlobalIRQ
Set to logic 1, it allows the Error interrupt request (indicated by the bit
ErrorIRQ) to be propagated to the GlobalIRQ
RxSOFIRQEn Set to logic 1, it allows the RxSOF interrupt request (indicated by the bit
RxSOFIRQ) to be propagated to the GlobalIRQ
8.6.4 IRQ1En
Interrupt request enable register for IRQ1.
Table 61.ꢀIRQ1EN register (address 09h);
Bit
Symbol IRQPushPull IRQPinEn LPCD_IRQEn
7
6
5
4
3
2
1
0
Timer4
IRQEn
Timer3
IRQEn
Timer2
IRQEn
Timer1
IRQEn
Timer0
IRQEn
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r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Table 62.ꢀIRQ1EN bits
Bit
Symbol
Description
7
IRQPushPull
Set to 1 the IRQ-pin acts as PushPull pin, otherwise it acts as
OpenDrain pin
6
5
4
3
2
1
IRQPinEN
Set to logic 1, it allows the global interrupt request (indicated by the bit
GlobalIRQ) to be propagated to the interrupt pin
LPCD_IRQEN
Timer4IRQEn
Timer3IRQEn
Timer2IRQEn
Timer1IRQEn
Set to logic 1, it allows the LPCDinterrupt request (indicated by the bit
LPCDIRQ) to be propagated to the GlobalIRQ
Set to logic 1, it allows the Timer4 interrupt request (indicated by the bit
Timer4IRQ) to be propagated to the GlobalIRQ
Set to logic 1, it allows the Timer3 interrupt request (indicated by the bit
Timer3IRQ) to be propagated to the GlobalIRQ
Set to logic 1, it allows the Timer2 interrupt request (indicated by the bit
Timer2IRQ) to be propagated to the GlobalIRQ
Set to logic 1, it allows the Timer1 interrupt request (indicated by the bit
Timer1IRQ) to be propagated to the GlobalIRQ
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Bit
Symbol
Description
0
Timer0IRQEn
Set to logic 1, it allows the Timer0 interrupt request (indicated by the bit
Timer0IRQ) to be propagated to the GlobalIRQ
8.7 Contactless interface configuration registers
8.7.1 Error
Error register.
Table 63.ꢀError register (address 0Ah)
Bit
7
EE_Err
dy
6
FiFoWrErr
dy
5
FIFOOvl
dy
4
MinFrameErr
dy
3
NoDataErr
dy
2
CollDet
dy
1
ProtErr
dy
0
IntegErr
dy
Symbol
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Table 64.ꢀError bits
Bit
Symbol
Description
7
EE_Err
An error appeared during the last EEPROM command. For
details see the descriptions of the EEPROM commands
6
FIFOWrErr Data was written into the FIFO, during a transmission of a possible
CRC, during "RxWait", "Wait for data" or "Receiving" state, or during an
authentication command. The Flag is cleared when a new CL command is
started. If RxMultiple is active, the flag is cleared after the error flags have
been written to the FIFO.
5
4
FIFOOvl
Data is written into the FIFO when it is already full. The data that is already in
the FIFO will remain untouched. All data that is written to the FIFO after this
Flag is set to 1 will be ignored.
Min
A valid SOF was received, but afterwards less then 4 bits of data were
received.
FrameErr
Note: Frames with less than 4 bits of data are automatically discarded and
the RxDecoder stays enabled. Furthermore no RxIRQ is set. The same is
valid for less than 3 Bytes if the EMD suppression is activated
Note: MinFrameErr is automatically cleared at the start of a receive or
transceive command. In case of a transceive command, it is cleared at the
start of the receiving phase ("Wait for data" state)
3
2
NoDataErr Data should be sent, but no data is in FIFO
CollDet
A collision has occurred. The position of the first collision is shown in the
register RxColl.
Note: CollDet is automatically cleared at the start of a receive or transceive
command. In case of a transceive command, it is cleared at the start of the
receiving phase ("Wait for data" state).
Note: If a collision is part of the defined EOF symbol, CollDet is not set to 1.
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Bit
Symbol
Description
1
ProtErr
A protocol error has occurred. A protocol error can be a wrong stop bit,
a missing or wrong ISO/IEC14443B EOF or SOF or a wrong number of
received data bytes. When a protocol error is detected, data reception is
stopped.
Note: ProtErr is automatically cleared at start of a receive or transceive
command. In case of a transceive command, it is cleared at the start of the
receiving phase ("Wait for data" state).
Note: When a protocol error occurs the last received data byte is not written
into the FIFO.
0
IntegErr
A data integrity error has been detected. Possible cause can be a wrong
parity or a wrong CRC. In case of a data integrity error the reception is
continued.
Note: IntegErr is automatically cleared at start of a Receive or Transceive
command. In case of a Transceive command, it is cleared at the start of the
receiving phase ("Wait for data" state).
Note: If the NoColl bit is set, also a collision is setting the IntegErr.
8.7.2 Status
Status register.
Table 65.ꢀStatus register (address 0Bh)
Bit
7
-
6
-
5
Crypto1On
dy
4
-
3
-
2
1
0
Symbol
ComState
r
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RFU
RFU
RFU
Table 66.ꢀStatus bits
Bit
7 to 6
5
Symbol
Description
-
RFU
Crypto1On Indicates if the MIFARE Classic Crypto is on. Clearing this bit is switching
the MIFARE Classic Crypto off. The bit can only be set by the MFAuthent
command.
4 to 3
-
RFU
2 to 0 ComState ComState shows the status of the transmitter and receiver state machine:
000b ... Idle
001b ... TxWait
011b ... Transmitting
101b ... RxWait
110b ... Wait for data
111b ... Receiving
100b ... not used
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8.7.3 RxBitCtrl
Receiver control register.
Table 67.ꢀRxBitCtrl register (address 0Ch);
Bit
7
ValuesAfterColl
r/w
6
5
4
3
2
1
RxLastBits
w
0
Symbol
RxAlign
r/w
NoColl
r/w
Access
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r/w
r/w
w
w
Table 68.ꢀRxBitCtrl bits
Bit
Symbol
Description
7
ValuesAfter If cleared, every received bit after a collision is replaced by a zero. This
Coll
function is needed for ISO/IEC14443 anticollision
6 to 4
RxAlign
Used for reception of bit oriented frames: RxAlign defines the bit position
length for the first bit received to be stored. Further received bits are
stored at the following bit positions.
Example:
RxAlign = 0h - the LSB of the received bit is stored at bit 0, the second
received bit is stored at bit position 1.
RxAlign = 1h - the LSB of the received bit is stored at bit 1, the second
received bit is stored at bit position 2.
RxAlign = 7h - the LSB of the received bit is stored at bit 7, the second
received bit is stored in the following byte at position 0.
Note: If RxAlign = 0, data is received byte-oriented, otherwise bit-
oriented.
3
NoColl
If this bit is set, a collision will result in an IntegErr
2 to 0
RxLastBits
Defines the number of valid bits of the last data byte received in bit-
oriented communications. If zero the whole byte is valid.
Note: These bits are set by the RxDecoder in a bit-oriented
communication at the end of the communication. They are reset at start
of reception.
8.7.4 RxColl
Receiver collision register.
Table 69.ꢀRxColl register (address 0Dh);
Bit
7
6
5
4
3
2
1
0
Symbol
CollPosValid
r
CollPos
r
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Table 70.ꢀRxColl bits
Bit
Symbol
Description
7
CollPos
Valid
If set to 1, the value of CollPos is valid. Otherwise no collision is detected or
the position of the collision is out of the range of bits CollPos.
6 to 0 CollPos
These bits show the bit position of the first detected collision in a received
frame (only data bits are interpreted). CollPos can only be displayed for the
first 8 bytes of a data stream.
Example:
00h indicates a bit collision in the 1st bit
01h indicates a bit collision in the 2nd bit
08h indicates a bit collision in the 9th bit (1st bit of 2nd byte)
3Fh indicates a bit collision in the 64th bit (8th bit of the 8th byte)
These bits shall only be interpreted in Passive communication mode at 106
kbit/s or ISO/IEC 14443 type A and read/write mode for MIFARE Classic if
bit CollPosValid is set.
Note: If RxBitCtrl.RxAlign is set to a value different to 0, this value is
included in the CollPos.
Example: RxAlign = 4h, a collision occurs in the 4th received bit (which is
the last bit of that UID byte). The CollPos = 7h in this case.
8.8 Timer configuration registers
8.8.1 TControl
Control register of the timer section.
The TControl implements a special functionality to avoid the not intended modification of
bits.
Bit 3..0 indicates, which bits in the positions 7..4 are intended to be modified.
Example: writing FFh sets all bits 7..4, writing F0h does not change any of the bits 7..4
Table 71.ꢀTControl register (address 0Eh)
Bit
7
6
5
4
3
2
1
0
Symbol
T3Running T2Running T1Running T0Running
T3Start
T2Start
T1Start
T0Start
StopNow
StopNow
StopNow
StopNow
Access
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dy
dy
dy
dy
w
w
w
w
Table 72.ꢀTControl bits
Bit
Symbol
Description
7
T3Running
Indicates Timer3 is running.If the bit T3startStopNow is set/reset, this
bit and the timer can be started/stopped
6
5
T2Running
T1Running
Indicates Timer2 is running. If the bit T2startStopNow is set/reset, this
bit and the timer can be started/stopped
Indicates tTmer1 is running. If the bit T1startStopNow is set/reset, this
bit and the timer can be started/stopped
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Bit
Symbol
Description
4
T0Running
Indicates Timer0 is running. If the bit T0startStopNow is set/reset, this
bit and the timer can be started/stopped
3
2
1
0
T3StartStop
Now
The bit 7 of TControl T3Running can be modified if set
The bit 6of TControl T2Running can be modified if set
The bit 5of TControl T1Running can be modified if set
The bit 4 of TControl T0Running can be modified if set
T2StartStop
Now
T1StartStop
Now
T0StartStop
Now
8.8.2 T0Control
Control register of the Timer0.
Table 73.ꢀT0Control register (address 0Fh);
Bit
7
6
-
5
4
3
T0AutoRestart
r/w
2
-
1
0
Symbol
T0StopRx
r/w
T0Start
r/w
T0Clk
r/w
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RFU
Table 74.ꢀT0Control bits
Bit
Symbol
Description
7
T0StopRx
If set, the timer stops immediately after receiving the first 4 bits. If
cleared the timer does not stop automatically.
Note: If LFO Trimming is selected by T0Start, this bit has no effect.
6
-
RFU
5 to 4
T0Start
00b: The timer is not started automatically
01 b: The timer starts automatically at the end of the transmission
10 b: Timer is used for LFO trimming without underflow (Start/Stop on
PosEdge)
11 b: Timer is used for LFO trimming with underflow (Start/Stop on
PosEdge)
3
T0AutoRestart 1: the timer automatically restarts its count-down from
T0ReloadValue, after the counter value has reached the value zero.
0: the timer decrements to zero and stops.
The bit Timer1IRQ is set to logic 1 when the timer underflows.
2
-
RFU
1 to 0
T0Clk
00 b: The timer input clock is 13.56 MHz.
01 b: The timer input clock is 211,875 kHz.
10 b: The timer input clock is an underflow of Timer2.
11 b: The timer input clock is an underflow of Timer1.
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8.8.2.1 T0ReloadHi
High byte reload value of the Timer0.
Table 75.ꢀT0ReloadHi register (address 10h);
Bit
7
6
5
4
3
2
1
0
Symbol
T0Reload Hi
r/w
Access
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Table 76.ꢀT0ReloadHi bits
Bit
Symbol
Description
7 to 0
T0ReloadHi
Defines the high byte of the reload value of the timer. With the start
event the timer loads the value of the registers T0ReloadValHi,
T0ReloadValLo. Changing this register affects the timer only at the
next start event.
8.8.2.2 T0ReloadLo
Low byte reload value of the Timer0.
Table 77.ꢀT0ReloadLo register (address 11h);
Bit
7
6
5
4
3
2
1
0
Symbol
T0ReloadLo
r/w
Access
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Table 78.ꢀT0ReloadLo bits
Bit
Symbol
Description
7 to0
T0ReloadLo
Defines the low byte of the reload value of the timer. With the
start event the timer loads the value of the T0ReloadValHi,
T0ReloadValLo. Changing this register affects the timer only at the
next start event.
8.8.2.3 T0CounterValHi
High byte of the counter value of Timer0.
Table 79.ꢀT0CounterValHi register (address 12h)
Bit
7
6
5
4
3
2
1
0
Symbol
T0CounterValHi
dy
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Table 80.ꢀT0CounterValHi bits
Bit
Symbol
Description
7to0
T0Counter
ValHi
High byte value of the Timer0.
This value shall not be read out during reception.
8.8.2.4 T0CounterValLo
Low byte of the counter value of Timer0.
Table 81.ꢀT0CounterValLo register (address 13h)
Bit
7
6
5
4
3
2
1
0
Symbol
T0CounterValLo
dy
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Table 82.ꢀT0CounterValLo bits
Bit
Symbol
Description
7 to 0
T0CounterValLo
Low byte value of the Timer0.
This value shall not be read out during reception.
8.8.2.5 T1Control
Control register of the Timer1.
Table 83.ꢀT1Control register (address 14h);
Bit
7
6
-
5
4
3
T1AutoRestart
r/w
2
-
1
0
Symbol
T1StopRx
r/w
T1Start
r/w
T1Clk
r/w
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RFU
RFU
Table 84.ꢀT1Control bits
Bit
Symbol
Description
7
T1StopRx
If set, the timer stops after receiving the first 4 bits. If cleared, the
timer is not stopped automatically.
Note: If LFO trimming is selected by T1start, this bit has no effect.
6
-
RFU
5 to 4
T1Start
00b: The timer is not started automatically
01 b: The timer starts automatically at the end of the transmission
10 b: Timer is used for LFO trimming without underflow (Start/Stop on
PosEdge)
11 b: Timer is used for LFO trimming with underflow (Start/Stop on
PosEdge)
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Bit
Symbol
Description
3
T1AutoRestart Set to logic 1, the timer automatically restarts its countdown from
T1ReloadValue, after the counter value has reached the value zero.
Set to logic 0 the timer decrements to zero and stops.
The bit Timer1IRQ is set to logic 1 when the timer underflows.
2
-
RFU
1 to 0
T1Clk
00 b: The timer input clock is 13.56 MHz
01 b: The timer input clock is 211,875 kHz.
10 b: The timer input clock is an underflow of Timer0
11 b: The timer input clock is an underflow of Timer2
8.8.2.6 T1ReloadHi
High byte (MSB) reload value of the Timer1.
Table 85.ꢀT0ReloadHi register (address 15h)
Bit
7
6
5
4
3
2
1
0
Symbol
T1ReloadHi
r/w
Access
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Table 86.ꢀT1ReloadHi bits
Bit
Symbol
Description
7 to 0
T1ReloadHi
Defines the high byte reload value of the Timer 1. With the start event
the timer loads the value of the T1ReloadValHi and T1ReloadValLo.
Changing this register affects the Timer only at the next start event.
8.8.2.7 T1ReloadLo
Low byte (LSB) reload value of the Timer1.
Table 87.ꢀT1ReloadLo register (address 16h)
Bit
7
6
5
4
3
2
1
0
Symbol
T1ReloadLo
r/w
Access
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Table 88.ꢀT1ReloadValLo bits
Bit
Symbol
Description
7 to 0
T1ReloadLo
Defines the low byte of the reload value of the Timer1. Changing this
register affects the timer only at the next start event.
8.8.2.8 T1CounterValHi
High byte (MSB) of the counter value of byte Timer1.
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Table 89.ꢀT1CounterValHi register (address 17h)
Bit
7
6
5
4
3
2
1
0
0
0
Symbol
T1CounterValHi
dy
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Table 90.ꢀT1CounterValHi bits
Bit
Symbol
Description
7 to 0
T1Counter
ValHi
High byte of the current value of the Timer1.
This value shall not be read out during reception.
8.8.2.9 T1CounterValLo
Low byte (LSB) of the counter value of byte Timer1.
Table 91.ꢀT1CounterValLo register (address 18h)
Bit
7
6
5
4
3
2
1
Symbol
T1CounterValLo
dy
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Table 92.ꢀT1CounterValLo bits
Bit
Symbol
Description
7 to 0
T1Counter
ValLo
Low byte of the current value of the counter 1.
This value shall not be read out during reception.
8.8.2.10 T2Control
Control register of the Timer2.
Table 93.ꢀT2Control register (address 19h)
Bit
7
6
-
5
4
3
T2AutoRestart
r/w
2
-
1
Symbol
T2StopRx
r/w
T2Start
r/w
T2Clk
r/w
Access
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RFU
Table 94.ꢀT2Control bits
Bit
Symbol
Description
7
T2StopRx
If set the timer stops immediately after receiving the first 4 bits. If
cleared indicates, that the timer is not stopped automatically.
Note: If LFO Trimming is selected by T2Start, this bit has no effect.
6
-
RFU
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Bit
Symbol
Description
5 to 4
T2Start
00 b: The timer is not started automatically.
01 b: The timer starts automatically at the end of the transmission.
10 b: Timer is used for LFO trimming without underflow (Start/Stop on
PosEdge).
11 b: Timer is used for LFO trimming with underflow (Start/Stop on
PosEdge).
3
T2AutoRestart Set to logic 1, the timer automatically restarts its countdown from
T2ReloadValue, after the counter value has reached the value
zero. Set to logic 0 the timer decrements to zero and stops. The bit
Timer2IRQ is set to logic 1 when the timer underflows
2
-
RFU
1 to 0
T2Clk
00 b: The timer input clock is 13.56 MHz.
01 b: The timer input clock is 212 kHz.
10 b: The timer input clock is an underflow of Timer0
11b: The timer input clock is an underflow of Timer1
8.8.2.11 T2ReloadHi
High byte of the reload value of Timer2.
Table 95.ꢀT2ReloadHi register (address 1Ah)
Bit
7
6
5
4
3
2
1
0
Symbol
T2ReloadHi
r/w
Access
rights
Table 96.ꢀT2Reload bits
Bit
Symbol
Description
7 to 0
T2ReloadHi
Defines the high byte of the reload value of the Timer2. With the
start event the timer load the value of the T2ReloadValHi and
T2ReloadValLo. Changing this register affects the timer only at the
next start event.
8.8.2.12 T2ReloadLo
Low byte of the reload value of Timer2.
Table 97.ꢀT2ReloadLo register (address 1Bh)
Bit
7
6
5
4
3
2
1
0
Symbol
T2ReloadLo
r/w
Access
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Table 98.ꢀT2ReloadLo bits
Bit
Symbol
Description
7 to 0
T2ReloadLo
Defines the low byte of the reload value of the Timer2. With the
start event the timer load the value of the T2ReloadValHi and
T2RelaodVaLo. Changing this register affects the timer only at the
next start event.
8.8.2.13 T2CounterValHi
High byte of the counter register of Timer2.
Table 99.ꢀT2CounterValHi register (address 1Ch)
Bit
7
6
5
4
3
2
1
0
0
0
Symbol
T2CounterValHi
dy
Access
rights
Table 100.ꢀT2CounterValHi bits
Bit
Symbol
Description
7 to 0
T2Counter
ValHi
High byte current counter value of Timer2.
This value shall not be read out during reception.
8.8.2.14 T2CounterValLoReg
Low byte of the current value of Timer 2.
Table 101.ꢀT2CounterValLo register (address 1Dh)
Bit
7
6
5
4
3
2
1
Symbol
T2CounterValLo
dy
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Table 102.ꢀT2CounterValLo bits
Bit
Symbol
Description
7 to 0
T2Counter
ValLo
Low byte of the current counter value of Timer1Timer2.
This value shall not be read out during reception.
8.8.2.15 T3Control
Control register of the Timer 3.
Table 103.ꢀT3Control register (address 1Eh)
Bit
7
6
-
5
4
3
T3AutoRestart
r/w
2
-
1
Symbol
T3StopRx
r/w
T3Start
r/w
T3Clk
r/w
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RFU
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Table 104.ꢀT3Control bits
Bit
Symbol
Description
7
T3StopRx
If set, the timer stops immediately after receiving the first 4 bits. If
cleared, indicates that the timer is not stopped automatically.
Note: If LFO Trimming is selected by T3Start, this bit has no effect.
6
-
RFU
5 to 4
T3Start
00b - timer is not started automatically
01 b - timer starts automatically at the end of the transmission
10 b - timer is used for LFO trimming without underflow (Start/Stop on
PosEdge)
11 b - timer is used for LFO trimming with underflow (Start/Stop on
PosEdge).
3
T3AutoRestart Set to logic 1, the timer automatically restarts its countdown from
T3ReloadValue, after the counter value has reached the value zero.
Set to logic 0 the timer decrements to zero and stops.
The bit Timer1IRQ is set to logic 1 when the timer underflows.
2
-
RFU
1 to 0
T3Clk
00 b - the timer input clock is 13.56 MHz.
01 b - the timer input clock is 211,875 kHz.
10 b - the timer input clock is an underflow of Timer0
11 b - the timer input clock is an underflow of Timer1
8.8.2.16 T3ReloadHi
High byte of the reload value of Timer3.
Table 105.ꢀT3ReloadHi register (address 1Fh);
Bit
7
6
5
4
3
2
1
0
Symbol
T3ReloadHi
r/w
Access
rights
Table 106.ꢀT3ReloadHi bits
Bit
Symbol
Description
7 to 0
T3ReloadHi
Defines the high byte of the reload value of the Timer3. With the
start event the timer load the value of the T3ReloadValHi and
T3ReloadValLo. Changing this register affects the timer only at the
next start event.
8.8.2.17 T3ReloadLo
Low byte of the reload value of Timer3.
Table 107.ꢀT3ReloadLo register (address 20h)
Bit
7
6
5
4
3
2
1
0
Symbol
T3ReloadLo
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Bit
7
6
5
4
3
2
1
0
Access
rights
r/w
Table 108.ꢀT3ReloadLo bits
Bit
Symbol
Description
7 to 0
T3ReloadLo
Defines the low byte of the reload value of Timer3. With the
start event the timer load the value of the T3ReloadValHi and
T3RelaodValLo. Changing this register affects the timer only at the
next start event.
8.8.2.18 T3CounterValHi
High byte of the current counter value the 16-bit Timer3.
Table 109.ꢀT3CounterValHi register (address 21h)
Bit
7
6
5
4
3
2
1
0
Symbol
T3CounterValHi
dy
Access
rights
Table 110.ꢀT3CounterValHi bits
Bit
Symbol
Description
7 to 0
T3Counter
ValHi
High byte of the current counter value of Timer3.
This value shall not be read out during reception.
8.8.2.19 T3CounterValLo
Low byte of the current counter value the 16-bit Timer3.
Table 111.ꢀT3CounterValLo register (address 22h)
Bit
7
6
5
4
3
2
1
0
Symbol
T3CounterValLo
dy
Access
rights
Table 112.ꢀT3CounterValLo bits
Bit
Symbol
Description
7 to 0
T3Counter
ValLo
Low byte current counter value of Timer3.
This value shall not be read out during reception.
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8.8.2.20 T4Control
The wake-up timer T4 activates the system after a given time. If enabled, it can start the
low power card detection function.
Table 113.ꢀT4Control register (address 23h)
Bit
7
6
5
4
3
2
1
0
Symbol
T4Running
T4Start
T4Auto
Trimm
T4Auto
LPCD
T4Auto
Restart
T4AutoWakeUp
T4Clk
r/w
StopNow
Access
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dy
w
r/w
r/w
r/w
r/w
Table 114.ꢀT4Control bits
Bit
Symbol
Description
7
T4Running
Shows if the timer T4 is running. If the bit T4StartStopNow is set,
this bit and the timer T4 can be started/stopped.
6
5
T4Start
if set, the bit T4Running can be changed.
StopNow
T4AutoTrimm
If set to one, the timer activates an LFO trimming procedure when it
underflows. For the T4AutoTrimm function, at least one timer (T0 to
T3) has to be configured properly for trimming (T3 is not allowed if
T4AutoLPCD is set in parallel).
4
T4AutoLPCD
If set to one, the timer activates a low-power card detection
sequence. If a card is detected an interrupt request is raised and
the system remains active if enabled. If no card is detected the
MFRC631 enters the Power down mode if enabled. The timer is
automatically restarted (no gap). Timer 3 is used to specify the time
where the RF field is enabled to check if a card is present. Therefor
you may not use Timer 3 for T4AutoTrimm in parallel.
3
2
T4AutoRestart
Set to logic 1, the timer automatically restarts its countdown from
T4ReloadValue, after the counter value has reached the value
zero. Set to logic 0 the timer decrements to zero and stops. The bit
Timer4IRQ is set to logic 1 at timer underflow.
T4AutoWakeUp If set, the MFRC631 wakes up automatically, when the timer T4 has
an underflow. This bit has to be set if the IC should enter the Power
down mode after T4AutoTrimm and/or T4AutoLPCD is finished and
no card has been detected. If the IC should stay active after one of
these procedures this bit has to be set to 0.
1 to 0
T4Clk
00b - the timer input clock is the LFO clock
01b - the timer input clock is the LFO clock/8
10b - the timer input clock is the LFO clock/16
11b - the timer input clock is the LFO clock/32
8.8.2.21 T4ReloadHi
High byte of the reload value of the 16-bit timer 4.
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Table 115.ꢀT4ReloadHi register (address 24h)
Bit
7
6
5
4
3
2
1
0
Symbol
T4ReloadHi
r/w
Access
rights
Table 116.ꢀT4ReloadHi bits
Bit
Symbol
Description
7 to 0
T4ReloadHi
Defines high byte of the for the reload value of timer 4. With the start
event the timer 4 loads the T4ReloadVal. Changing this register
affects the timer only at the next start event.
8.8.2.22 T4ReloadLo
Low byte of the reload value of the 16-bit timer 4.
Table 117.ꢀT4ReloadLo register (address 25h)
Bit
7
6
5
4
3
2
1
0
Symbol
T4ReloadLo
r/w
Access
rights
Table 118.ꢀT4ReloadLo bits
Bit
Symbol
Description
7 to 0
T4ReloadLo
Defines the low byte of the reload value of the timer 4. With the start
event the timer loads the value of the T4ReloadVal. Changing this
register affects the timer only at the next start event.
8.8.2.23 T4CounterValHi
High byte of the counter value of the 16-bit timer 4.
Table 119.ꢀT4CounterValHi register (address 26h)
Bit
7
6
5
4
3
2
1
0
Symbol
T4CounterValHi
dy
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rights
Table 120.ꢀT4CounterValHi bits
Bit
Symbol
Description
High byte of the current counter value of timer 4.
7 to 0
T4CounterValHi
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8.8.2.24 T4CounterValLo
Low byte of the counter value of the 16-bit timer 4.
Table 121.ꢀT4CounterValLo register (address 27h)
Bit
7
6
5
4
3
2
1
0
Symbol
T4CounterValLo
dy
Access
rights
Table 122.ꢀT4CounterValLo bits
Bit
Symbol
Description
Low byte of the current counter value of the timer 4.
7 to 0
T4CounterValLo
8.9 Transmitter configuration registers
8.9.1 TxMode
Table 123.ꢀDrvMode register (address 28h)
Bit
7
6
5
-
4
-
3
2
1
TxClk Mode
r/w
0
Symbol
Tx2Inv
r/w
Tx1Inv
r/w
TxEn
r/w
Access
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RFU
RFU
Table 124.ꢀDrvMode bits
Bit
Symbol
Tx2Inv
Tx1Inv
Description
7
Inverts transmitter 2 at TX2 pin
6
Inverts transmitter 1 at TX1 pin
5
RFU
RFU
4
-
3
TxEn
If set to 1 both transmitter pins are enabled
2 to 0
TxClkMode
Transmitter clock settings (see 8.6.2. Table 27). Codes 011b and
0b110 are not supported. This register defines, if the output is
operated in open drain, push-pull, at high impedance or pulled to a fix
high or low level.
8.9.2 TxAmp
With the set_cw_amplitude register output power can be traded off against power supply
rejection. Spending more headroom leads to better power supply rejection ration and
better accuracy of the modulation degree.
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With CwMax set, the voltage of TX1 will be pulled to the maximum possible. This register
overrides the settings made by set_cw_amplitude.
Table 125.ꢀTxAmp register (address 29h)
Bit
7
6
5
-
4
3
2
set_residual_carrier
r/w
1
0
Symbol
set_cw_amplitude
r/w
Access
rights
RFU
Table 126.ꢀTxAmp bits
Bit
Symbol
Description
7 to 6
set_cw_amplitude
Allows to reduce the output amplitude of the transmitter by a
fix value.
Four different preset values that are subtracted from TVDD
can be selected:
0: TVDD -100 mV
1: TVDD -250 mV
2: TVDD -500 mV
3: TVDD -1000 mV
5
RFU
-
4 to 0
set_residual_ carrier Set the residual carrier percentage. refer to Section 7.6.2
8.9.3 TxCon
Table 127.ꢀTxCon register (address 2Ah)
Bit
7
6
5
OvershootT2
r/w
4
3
2
1
0
Symbol
CwMax
r/w
TxInv
r/w
TxSel
r/w
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Table 128.ꢀTxCon bits
Bit
Symbol
Description
7 to 4
OvershootT2 Specifies the length (number of carrier clocks) of the additional
modulation for overshoot prevention. Refer to Section 7.6.2.1
"Overshoot protection"
3
Cwmax
Set amplitude of continuous wave carrier to the maximum.
If set, set_cw_amplitude in Register TxAmp has no influence on the
continuous amplitude.
2
TxInv
TxSel
If set, the resulting modulation signal defined by TxSel is inverted
1 to 0
Defines which signal is used as source for modulation
00b ... no modulation
01b ... TxEnvelope
10b ... SigIn
11b ... RFU
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8.9.4 Txl
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High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
Table 129.ꢀTxl register (address 2Bh)
Bit
7
6
5
OvershootT1
r/w
4
3
2
1
0
Symbol
tx_set_iLoad
r/w
Access
rights
Table 130.ꢀTxl bits
Bit
Symbol
Description
7 to 4
OvershootT1 Overshoot value for Timer1. Refer to Section 7.6.2.1 "Overshoot
protection"
3 to 0
tx_set_iLoad
Factory trim value, sets the expected Tx load current. This value is
used to control the modulation index in an optimized way dependent
on the expected TX load current.
8.10 CRC configuration registers
8.10.1 TxCrcPreset
Table 131.ꢀTXCrcPreset register (address 2Ch)
Bit
7
RFU
-
6
5
4
3
2
1
TxCRCInvert
r/w
0
Symbol
TXPresetVal
r/w
TxCRCtype
r/w
TxCRCEn
r/w
Access
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Table 132.ꢀTxCrcPreset bits
Bit
Symbol
Description
7
RFU
-
6 to 4
3 to 2
TXPresetVal
TxCRCtype
Specifies the CRC preset value for transmission (see Table 132).
Defines which type of CRC (CRC8/CRC16/CRC5) is calculated:
• 00h -- CRC5
• 01h -- CRC8
• 02h -- CRC16
• 03h -- RFU
1
0
TxCRCInvert if set, the resulting CRC is inverted and attached to the data frame
(ISO/IEC 3309)
TxCRCEn
if set, a CRC is appended to the data stream
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Table 133.ꢀTransmitter CRC preset value configuration
TXPresetVal[6...4]
CRC16
0000h
6363h
A671h
FFFEh
-
CRC8
CRC5
0h
1h
2h
3h
4h
5h
6h
7h
00h
00h
12h
12h
BFh
-
FDh
-
-
-
-
-
-
User defined
FFFFh
User defined
FFh
User defined
1Fh
Remark: User defined CRC preset values can be configured by EEprom (see Section
7.7.2.1, Table 29 "Configuration area (Page 0)").
8.10.2 RxCrcCon
Table 134.ꢀRxCrcCon register (address 2Dh)
Bit
7
RxForceCRCWrite
r/w
6
5
4
3
2
1
RxCRCInvert
r/w
0
Symbol
RXPresetVal
r/w
RXCRCtype
r/w
RxCRCEn
r/w
Access
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Table 135.ꢀRxCrcCon bits
Bit
Symbol
Description
7
RxForceCrc
Write
If set, the received CRC byte(s) are copied to the FIFO.
If cleared CRC Bytes are only checked, but not copied to the FIFO.
This bit has to be always set in case of a not byte aligned CRC (e.g.
ISO/IEC 18000-3 mode 3/ EPC Class-1HF)
6 to 4
3 to 2
RXPresetVal
RxCRCtype
Defines the CRC preset value (Hex.) for transmission. (see Table
135).
Defines which type of CRC (CRC8/CRC16/CRC5) is calculated:
• 00h -- CRC5
• 01h -- CRC8
• 02h -- CRC16
• 03h -- RFU
1
0
RxCrcInvert
RxCrcEn
If set, the CRC check is done for the inverted CRC.
If set, the CRC is checked and in case of a wrong CRC an error flag is
set. Otherwise the CRC is calculated but the error flag is not modified.
Table 136.ꢀReceiver CRC preset value configuration
RXPresetVal[6...4]
CRC16
CRC8
CRC5
0h
0000h
00h
00h
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RXPresetVal[6...4]
CRC16
6363h
A671h
FFFEh
-
CRC8
CRC5
1h
2h
3h
4h
5h
6h
7h
12h
12h
BFh
-
FDh
-
-
-
-
-
-
User defined
FFFFh
User defined
FFh
User defined
1Fh
8.11 Transmitter configuration registers
8.11.1 TxDataNum
Table 137.ꢀTxDataNum register (address 2Eh)
Bit
7
6
5
4
KeepBitGrid
r/w
3
2
1
TxLastBits
r/w
0
Symbol
RFU
RFU-
RFU-
DataEn
r/w
Access
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Table 138.ꢀTxDataNum bits
Bit
7 to 5
4
Symbol
RFU
Description
-
KeepBitGrid
If set, the time between consecutive transmissions starts is a multiple
of one ETU. If cleared, consecutive transmissions can even start
within one ETU
3
DataEn
If cleared - it is possible to send a single symbol pattern.
If set - data is sent.
2 to 0
TxLastBits
Defines how many bits of the last data byte to be sent. If set to 000b
all bits of the last data byte are sent.
Note - bits are skipped at the end of the byte.
Example - Data byte B2h (sent LSB first).
TxLastBits = 011b (3h) => 010b (LSB first) is sent
TxLastBits = 110b (6h) => 010011b (LSB first) is sent
8.11.2 TxDATAModWidth
Transmitter data modulation width register
Table 139.ꢀTxDataModWidth register (address 2Fh)
Bit
7
6
5
4
3
2
1
0
Symbol
DModWidth
r/w
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Table 140.ꢀTxDataModWidth bits
Bit
Symbol
Description
7 to 0
DModWidth
Specifies the length of a pulse for sending data with enabled pulse
modulation. The length is given by the number of carrier clocks + 1.
A pulse can never be longer than from the start of the pulse to the
end of the bit. The starting position of a pulse is given by the setting
of TxDataMod.DPulseType. Note: This register is only used if Miller
modulation (ISO/IEC 14443A PCD) is used. The settings are also
used for the modulation width of start and/or stop symbols.
8.11.3 TxSym10BurstLen
If a protocol requires a burst (an unmodulated subcarrier) the length can be defined with
this TxSymBurstLen, the value high or low can be defined by TxSym10BurstCtrl.
Table 141.ꢀTxSym10BurstLen register (address 30h)
Bit
7
RFU
-
6
5
4
3
RFU
-
2
1
Sym0Burst Len
r/w
0
Symbol
Sym1Burst Len
r/w
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Table 142.ꢀTxSym10BurstLen bits
Bit
7
Symbol
Description
RFU
-
6 to 4
Sym1BurstLen Specifies the number of bits issued for symbol 1 burst. The 3 bits
encodes a range from 8 to 256 bit:
00h - 8bit
01h - 16bit
02h - 32bit
04h - 48bit
05h - 64bit
06h - 96bit
07h - 128bit
08h - 256bit
3
RFU
-
2 to 0
Sym0BurstLen Specifies the number of bits issued for symbol 1 burst. The 3 bits
encodes a range from 8 to 256 bit:
00h - 8bit
01h - 16bit
02h - 32bit
03h - 48bit
04h - 64bit
05h - 96bit
06h - 128bit
07h - 256bit
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8.11.4 TxWaitCtrl
Table 143.ꢀTxWaitCtrl register (address 31h); reset value: C0h
Bit
7
TxWaitStart
r/w
6
5
4
TxWait High
r/w
3
2
1
TxStopBitLength
r/w
0
Symbol
TxWaitEtu
r/w
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Table 144.ꢀTXWaitCtrl bits
Bit
Symbol
Description
7
TxWaitStart
If cleared, the TxWait time is starting at the End of the send data
(TX).
If set, the TxWait time is starting at the End of the received data
(RX).
6
TxWaitEtu
If cleared, the TxWait time is TxWait × 16/13.56 MHz.
If set, the TxWait time is TxWait × 0.5 / DBFreq (DBFreq is the
frequency of the bit stream as defined by TxDataCon).
5 to 3
2 to 0
TxWait High
Bit extension of TxWaitLo. TxWaitCtrl bit 5 is MSB.
TxStopBitLength
Defines stop-bits and EGT (= stop-bit + extra guard time EGT) to
be send:
0h: no stop-bit, no EGT
1h: 1 stop-bit, no EGT
2h: 1 stop-bit + 1 EGT
3h: 1 stop-bit + 2 EGT
4h: 1 stop-bit + 3 EGT
5h: 1 stop-bit + 4 EGT
6h: 1 stop-bit + 5 EGT
7h: 1 stop-bit + 6 EGT
Note: This is only valid for ISO/IEC14443 Type B
8.11.5 TxWaitLo
Table 145.ꢀTxWaitLo register (address 32h)
Bit
7
6
5
4
3
2
1
0
Symbol
TxWaitLo
r/w
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Table 146.ꢀTxWaitLo bits
Bit
Symbol
Description
7 to 0
TxWaitLo
Defines the minimum time between receive and send or between two
send data streams
Note: TxWait is a 11bit register (additional 3 bits are in the TxWaitCtrl
register)!
See also TxWaitEtu and TxWaitStart.
8.12 FrameCon
Table 147.ꢀFrameCon register (address 33h)
Bit
7
TxParityEn
r/w
6
RxParityEn
r/w
5
-
4
-
3
2
1
0
Symbol
StopSym
r/w
StartSym
r/w
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RFU
RFU
Table 148.ꢀFrameCon bits
Bit
Symbol
Description
7
TxParityEn
If set, a parity bit is calculated and appended to each byte
transmitted.
6
RxParityEn
If set, the parity calculation is enabled. The parity is not transferred to
the FIFO.
5 to 4
3 to 2
-
RFU
StopSym
Defines which symbol is sent as stop-symbol:
• 0h: No symbol is sent
• 1h: Symbol0 is sent
• 2 h symbol1 is sent
• 3h Symbol2 is sent
1 to 0
StartSym
Defines which symbol is sent as start-symbol:
• 0h: No Symbol is sent
• 1h: Symbol0 is sent
• 2 h: Symbol1 is sent
• 3h: Symbol2 is sent
8.13 Receiver configuration registers
8.13.1 RxSofD
Table 149.ꢀRxSofD register (address 34h)
Bit
7
6
5
4
SOFDetected
dy
3
RFU
-
2
1
SubC_Detected
dy
0
Symbol
RFU
-
SOF_En
r/w
SubC_En
r/w
SubC_Present
r
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Table 150.ꢀRxSofD bits
Bit Symbol
7 to 6 RFU
Description
-
5
4
3
2
1
0
SOF_En
If set and a SOF is detected an RxSOFIRQ is raised.
Shows that a SOF is or was detected. Can be cleared by SW.
-
SOF_Detected
RFU
SubC_En
If set and a subcarrier is detected an RxSOFIRQ is raised.
Shows that a subcarrier is or was detected. Can be cleared by SW.
Shows that a subcarrier is currently detected.
SubC_Detected
SubC_Present
8.13.2 RxCtrl
Table 151.ꢀRxCtrl register (address 35h)
Bit
7
RxAllowBits
r/w
6
RxMultiple
r/w
5
RxEOFType
r/w
4
EGT_Check
r/w
3
2
1
0
Symbol
EMD_Sup
r/w
Baudrate
r/w
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Table 152.ꢀRxCtrl bits
Bit
Symbol
Description
7
RxAllowBits
If set, data is written into FIFO even if CRC is enabled, and no
complete byte has been received.
6
5
RxMultiple
If set, RxMultiple is activated and the receiver will not terminate
automatically (refer Section 7.10.3.5 "Receive command").
If set to logic 1, at the end of a received data stream an error byte is
added to the FIFO. The error byte is a copy of the Error register.
RxEOFType
0: EOF as defined in the RxEOFSymbolReg is expected.
1: ISO/IEC14443B EOF is expected.
Note: Clearing this bit to 0 and clearing bit 0 and bit 1 in the
RxEOFSymbolReg disables the EOF check.
4
3
EGT_Check
EMD_Sup
If set to 1, the EGT is checked and if it is too long
a protocol error is set. (This is only valid for ISO/IEC14443 Type B).
Enables the EMD suppression according ISO/IEC14443. If an error
occurs within the first three bytes, these three bytes are assumed to
be EMD, ignored and the FIFO is reset. A collision is treated as an
error as well If a valid SOF was received, the EMD_Sup is set and a
frame of less than 3 bytes had been received. RX_IRQ is not set in
this EMD error cases. If RxForceCRCWrite is set, the FIFO should not
be read out before three bytes are written into.
2 to 0
Baudrate
Defines the baud rate of the receiving signal.
4h: 106 kBd
5h: 212 kBd
6h: 424 kBd
7h: 847 kBd
all remaining values are RFU
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8.13.3 RxWait
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Selects internal receiver settings.
Table 153.ꢀRxWait register (address 36h)
Bit
7
RxWaitEtu
r/w
6
5
4
3
2
1
0
Symbol
RxWait
r/w
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Table 154.ꢀRxWait bits
Bit
Symbol
Description
7
RXWaitEtu
If set to 0, the RxWait time is RxWait × 16/13.56 MHz.
If set to 1, the RxWait time is RxWait × (0.5/DBFreq).
6 to 0
RxWait
Defines the time after sending, where every input is ignored.
8.13.4 RxThreshold
Selects minimum threshold level for the bit decoder.
Table 155.ꢀRxThreshold register (address 37h)
Bit
7
6
5
4
3
2
1
0
Symbol
MinLevel
r/w
MinLevelP
r/w
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Table 156.ꢀRxThreshold bits
Bit
Symbol
Description
Defines the MinLevel of the reception.
Note: The MinLevel should be higher than the noise level in the system.
MinLevelP Defines the MinLevel of the phase shift detector unit.
7 to 4
MinLevel
3 to 0
8.13.5 Rcv
Table 157.ꢀRcv register (address 38h)
Bit
7
Rcv_Rx_single
r/w
6
Rx_ADCmode
r/w
5
4
3
2
1
0
Symbol
SigInSel
r/w
RFU
-
CollLevel
r/w
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Table 158.ꢀRcv bits
Bit
Symbol
Description
7
Rcv_Rx_single
Single RXP Input Pin Mode;
0: Fully Differential
1: Quasi-Differential
6
Rx_ADCmode
SigInSel
Defines the operation mode of the Analog Digital Converter (ADC)
0: normal reception mode for ADC
1: LPCD mode for ADC
5 to 4
Defines input for the signal processing unit:
0h - idle
1h - internal analog block (RX)
2h - signal in over envelope (ISO/IEC14443A)
3h - signal in over s3c-generic
3 to 2
1 to 0
RFU
-
CollLevel
Defines the strength of a signal to be interpreted as a collision:
0h - Collision has at least 1/8 of signal strength
1h - Collision has at least 1/4 of signal strength
2h - Collision has at least 1/2 of signal strength
3h - Collision detection is switched off
8.13.6 RxAna
This register allows to set the gain (rcv_gain) and high pass corner frequencies
(rcv_hpcf).
Table 159.ꢀRxAna register (address 39h)
Bit
7
6
5
4
3
2
1
0
Symbol
VMid_r_sel
r/w
RFU
-
rcv_hpcf
r/w
rcv_gain
r/w
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Table 160.ꢀRxAna bits
Bit
Symbol
VMid_r_sel
RFU
Description
Factory trim value, needs to be 0.
7, 6
5, 4
3, 2
rcv_hpcf
The rcv_hpcf [1:0] signals allow 4 different settings of the base band
amplifier high pass cut-off frequency from ~40 kHz to ~300 kHz.
1 to 0
rcv_gain
With rcv_gain[1:0] four different gain settings from 30 dB and 60
dB can be configured (differential output voltage/differential input
voltage).
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Table 161.ꢀEffect of gain and highpass corner register settings
rcv_gain
(Hex.)
rcv_hpcf
(Hex.)
fl (kHz)
fU (MHz)
gain (dB20)
bandwith
(MHz)
03
03
03
03
02
02
02
02
01
01
01
01
00
00
00
00
00
01
02
03
00
01
02
03
00
01
02
03
00
01
02
03
38
2,3
2,4
2,6
2,9
2,3
2,4
2,6
3,0
2,6
2,7
2,9
3,3
2,6
2,7
2,9
3,4
60
59
58
55
51
50
49
41
43
42
41
39
35
34
33
30
2,3
2,3
2,5
2,6
2,3
2,3
2,4
2,7
2,6
2,6
2,7
3,0
2,6
2,6
2,7
3,1
79
150
264
41
83
157
272
42
84
157
273
43
85
159
276
8.14 Clock configuration
8.14.1 SerialSpeed
This register allows to set speed of the RS232 interface. The default speed is set to
115.2 kbit/s. The transmission speed of the interface can be changed by modifying
the entries for BR_T0 and BR_T1. The transfer speed can be calculated by using the
following formulas:
BR_T0 = 0: transfer speed = 27.12 MHz / (BR_T1 + 1)
BR_T0 > 0: transfer speed = 27.12 MHz / (BR_T1 + 33) / 2^(BR_T0 - 1)
The framing is implemented with 1 startbit, 8 databits and 1 stop bit. A parity bit is not
used. Transfer speeds above 1228,8 kbit/s are not supported.
Table 162.ꢀSerialSpeed register (address3Bh); reset value: 7Ah
Bit
7
6
5
4
3
2
BR_T1
r/w
1
0
Symbol
BR_T0
r/w
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Table 163.ꢀSerialSpeed bits
Bit
Symbol
Description
7 to 5 BR_T0
BR_T0 = 0: transfer speed = 27.12 MHz / (BR_T1 + 1)
BR_T0 > 0: transfer speed = 27.12 MHz / (BR_T1 + 33) / 2^(BR_T0 - 1)
4 to 0 BR_T1
BR_T0 = 0: transfer speed = 27.12 MHz / (BR_T1 + 1)
BR_T0 > 0: transfer speed = 27.12 MHz / (BR_T1 + 33) / 2^(BR_T0 - 1)
Table 164.ꢀRS232 speed settings
Transfer speed (kbit/s)
SerialSpeed register content (Hex.)
7,2
FA
9,6
EB
DA
CB
AB
9A
7A
74
14,4
19,2
38,4
57,6
115,2
128,0
230,4
460,8
921,6
1228,8
5A
3A
1C
15
8.14.2 LFO_Trimm
Table 165.ꢀLFO_Trim register (address 3Ch)
Bit
7
6
5
4
3
2
1
0
Symbol
LFO_trimm
r/w
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Table 166.ꢀLFO_Trim bits
Bit
Symbol
Description
7 to 0
LFO_trimm
Trimm value. Refer to Section 7.8.3
Note: If the trimm value is increased, the frequency of the oscillator
decreases.
8.14.3 PLL_Ctrl Register
The PLL_Ctrl register implements the control register for the IntegerN PLL. Two stages
exist to create the ClkOut signal from the 27,12MHz input. In the first stage the 27,12Mhz
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input signal is multiplied by the value defined in PLLDiv_FB and divided by two, and the
second stage divides this frequency by the value defined by PLLDIV_Out.
Table 167.ꢀPLL_Ctrl register (address3Dh)
Bit
7
6
5
4
3
ClkOut_En
r/w
2
1
0
Symbol
ClkOutSel
r/w
PLL_PD
r/w
PLLDiv_FB
r/w
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Table 168.ꢀPLL_Ctrl register bits
Bit
Symbol
Description
7 to 4
CLkOutSel
• 0h - pin CLKOUT is used as I/O
• 1h - pin CLKOUT shows the output of the analog PLL
• 2h - pin CLKOUT is hold on 0
• 3h - pin CLKOUT is hold on 1
• 4h - pin CLKOUT shows 27.12 MHz from the crystal
• 5h - pin CLKOUT shows 13.56 MHz derived from the crystal
• 6h - pin CLKOUT shows 6.78 MHz derived from the crystal
• 7h - pin CLKOUT shows 3.39 MHz derived from the crystal
• 8h - pin CLKOUT is toggled by the Timer0 overflow
• 9h - pin CLKOUT is toggled by the Timer1 overflow
• Ah - pin CLKOUT is toggled by the Timer2 overflow
• Bh - pin CLKOUT is toggled by the Timer3 overflow
• Ch...Fh - RFU
3
ClkOut_En
PLL_PD
Enables the clock at Pin CLKOUT
PLL power down
2
1-0
PLLDiv_FB
PLL feedback divider (see table 174)
Table 169.ꢀSetting of feedback divider PLLDiv_FB [1:0]
Bit 1
Bit 0
Division
0
0
1
1
0
1
0
1
23 (VCO frequency 312Mhz)
27 (VCO frequency 366MHz)
28 (VCO frequency 380Mhz)
23 (VCO frequency 312Mhz)
8.14.4 PLLDiv_Out
Table 170.ꢀPLLDiv_Out register (address 3Eh)
Bit
7
6
5
4
3
2
1
0
Symbol
PLLDiv_Out
r/w
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Table 171.ꢀPLLDiv_Out bits
Bit
Symbol
Description
7 to 0
PLLDiv_Out
PLL output divider factor; Refer to Section 7.8.2
Table 172.ꢀSetting for the output divider ratio PLLDiv_Out [7:0]
Value
Division
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
8
0
1
2
3
4
5
6
7
8
9
9
10
...
253
254
10
...
253
254
8.15 Low-power card detection configuration registers
The LPCD registers contain the settings for the low-power card detection. The setting
for LPCD_IMax (6 bits) is done by the two highest bits (bit 7, bit 6) of the registers
LPCD_QMin, LPCD_QMax and LPCD_IMin each.
8.15.1 LPCD_QMin
Table 173.ꢀLPCD_QMin register (address 3Fh)
Bit
7
LPCD_IMax.5
r/w
6
LPCD_IMax.4
r/w
5
4
3
2
1
0
Symbol
LPCD_QMin
r/w
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Table 174.ꢀLPCD_QMin bits
Bit
Symbol
Description
7, 6
LPCD_IMax
Defines the highest two bits of the higher border for the LPCD. If the
measurement value of the I channel is higher than LPCD_IMax, a
LPCD interrupt request is indicated by bit IRQ0.LPCDIRQ.
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Bit
Symbol
Description
5 to 0
LPCD_QMin
Defines the lower border for the LPCD. If the measurement value of
the Q channel is higher than LPCD_QMin, a LPCDinterrupt request is
indicated by bit IRQ0.LPCDIRQ.
8.15.2 LPCD_QMax
Table 175.ꢀLPCD_QMax register (address 40h)
Bit
7
LPCD_IMax.3
r/w
6
LPCD_IMax.2
r/w
5
4
3
2
1
0
Symbol
LPCD_QMax
r/w
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Table 176.ꢀLPCD_QMax bits
Bit
Symbol
Description
7
LPCD_IMax.3
Defines the bit 3 of the high border for the LPCD. If the
measurement value of the I channel is higher than LPCD IMax, a
LPCD IRQ is raised.
6
LPCD_IMax.2
LPCD_QMax
Defines the bit 2 of the high border for the LPCD. If the
measurement value of the I channel is higher than LPCD IMax, a
LPCD IRQ is raised.
5 to 0
Defines the high border for the LPCD. If the measurement value of
the Q channel is higher than LPCD QMax, a LPCD IRQ is raised.
8.15.3 LPCD_IMin
Table 177.ꢀLPCD_IMin register (address 41h)
Bit
7
LPCD_IMax.1
r/w
6
5
4
3
2
1
0
Symbol
LPCD_IMax.0 LPCD_IMin
r/w
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Table 178.ꢀLPCD_IMin bits
Bit
Symbol
Description
7 to 6
LPCD_IMax
Defines lowest two bits of the higher border for the low-power card
detection (LPCD). If the measurement value of the I channel is higher
than LPCD IMax, a LPCD IRQ is raised.
5 to 0
LPCD_IMin
Defines the lower border for the ow power card detection. If the
measurement value of the I channel is lower than LPCD IMin, a LPCD
IRQ is raised.
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8.15.4 LPCD_Result_I
Table 179.ꢀLPCD_Result_I register (address 42h)
Bit
7
RFU-
-
6
RFU-
-
5
4
3
2
1
0
Symbol
LPCD_Result_I
r
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Table 180.ꢀLPCD_I_Result bits
Bit
Symbol
Description
7 to 6
5 to 0
RFU
-
LPCD_Result_I Shows the result of the last low-power card detection (I-Channel).
8.15.5 LPCD_Result_Q
Table 181.ꢀLPCD_Result_Q register (address 43h)
Bit
7
6
5
4
3
2
1
0
Symbol
RFU
LPCD_I
RQ_Clr
LPCD_Reslult_Q
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r
Table 182.ꢀLPCD_Q_Result bits
Bit
7
Symbol
Description
RFU
-
6
LPCD_IRQ_Clr
If set no LPCD IRQ is raised any more until the next low-power
card detection procedure. Can be used by software to clear the
interrupt source.
5 to 0
LPCD_Result_Q
Shows the result of the last ow power card detection (Q-Channel).
8.15.6 LPCD_Options
This register is available on the CLRC63103 only. For silicon version CLRC63102 this
register on address 3AH is RFU.
Table 183.ꢀLPCD_Options register (address 3Ah)
Bit
7
6
5
4
3
2
1
0
Symbol
RFU
-
LPCD_TX_HIGH
LPCD_FILTER
LPCD_Q_
LPCD_I_UNSTABLE
UNSTABLE
Access
rights
r/w
r/w
r
r
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Table 184.ꢀLPCD_Options
Bit
7 to 4
3
Symbol
Description
RFU
-
LPCD_TX_HIGH
If set, the TX-driver will be the same as VTVDD during LPCD. This will allow for
a better LPCD detection range (higher transmitter output voltage) at the cost of
a higher current consumption. If this bit is cleared, the output voltage at the TX
drivers will be = TVDD- 0.4V. If this bit is set, the output voltage at the TX drivers
will be = VTVDD
.
2
LPCD_FILTER
If set, The LPCD decision is based on the result of a filter which allows
to remove noise from the evaluated signal in I and Q channel. Enabling
LPCD_FILTER allows compensating for noisy conditions at the cost of a longer
RF-ON time required for sampling. The total maximum LPCD sampling time is
4.72us.
1
0
LPCD_Q_UNSTABLE
LPCD_I_UNSTABLE
If bit 2 of this register is set, bit 1 indicates that the Q-channel ADC value was
changing during the LPCD measuring time. Note: Only valid if LPCD_FILTER
(bit 2) = 1. This information can be used by the host application for configuration
of e.g. the threshold LPCD_QMax or inverting the TX drivers.
If bit 2 of this register is set, bit 0 Indicates that the I-channel ADC value was
changing during the LPCD measuring time. Note: Only valid if LPCD_FILTER
(bit2) = 1. This information can be used by the host application for configuration
of e.g. the threshold LPCD_IMax or inverting the TX drivers.
8.16 Pin configuration
8.16.1 PinEn
Table 185.ꢀPinEn register (address 44h)
Bit
7
6
5
IFSEL1_EN
r/w
4
IFSEL0_EN
r/w
3
2
1
0
Symbol
SIGIN_EN CLKOUT_EN
r/w r/w
TCK_EN
r/w
TMS_EN
r/w
TDI_EN TMDO_EN
r/w r/w
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Table 186.ꢀPinEn bits
Bit
Symbol
Description
7
SIGIN_EN
Enables the output functionality on SIGIN (pin 5). The pin is then used
as I/O.
6
5
4
3
CLKOUT_EN Enables the output functionality of the CLKOUT (pin 22). The pin is
then used as I/O. The CLKOUT function is switched off.
IFSEL1_EN
IFSEL0_EN
TCK_EN
Enables the output functionality of the IFSEL1 (pin 27). The pin is then
used as I/O.
Enables the output functionality of the IFSEL0 (pin 26). The pin is then
used as I/O.
Enables the output functionality of the TCK (pin 4) of the boundary
scan interface. The pin is then used as I/O. If the boundary scan is
activated in EEPROM, this bit has no function.
MFRC631
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Bit
Symbol
Description
2
TMS_EN
Enables the output functionality of the TMS (pin 2) of the boundary
scan interface. The pin is then used as I/O. If the boundary scan is
activated in EEPROM, this bit has no function.
1
0
TDI_EN
Enables the output functionality of the TDI (pin 1) of the boundary
scan interface. The pin is then used as I/O. If the boundary scan is
activated in EEPROM, this bit has no function.
TDO_EN
Enables the output functionality of the TDO(pin 3) of the boundary
scan interface. The pin is then used as I/O. If the boundary scan is
activated in EEPROM, this bit has no function.
8.16.2 PinOut
Table 187.ꢀPinOut register (address 45h)
Bit
Symbol SIGIN_OUT CLKOUT_OUT IFSEL1_OUT IFSEL0_OUT TCK_OUT TMS_OUT TDI_OUT TDO_OUT
7
6
5
4
3
2
1
0
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r/w
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r/w
r/w
r/w
Table 188.ꢀPinOut bits
Bit
7
Symbol
Description
SIGIN_OUT
Output buffer of the SIGIN pin
6
CLKOUT_OUT Output buffer of the CLKOUT pin
5
IFSEL1_OUT
IFSEL0_OUT
TCK_OUT
TMS_OUT
TDI_OUT
Output buffer of the IFSEL1 pin
Output buffer of the IFSEL0 pin
Output buffer of the TCK pin
Output buffer of the TMS pin
Output buffer of the TDI pin
Output buffer of the TDO pin
4
3
2
1
0
TDO_OUT
8.16.3 PinIn
Table 189.ꢀPinIn register (address 46h)
Bit
7
6
5
4
3
2
1
TDI_IN
r
0
Symbol
SIGIN_IN CLKOUT_IN IFSEL1_IN IFSEL0_IN
TCK_IN
r
TMS_IN
r
TDO_IN
r
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r
r
r
Table 190.ꢀPinIn bits
Bit
Symbol
Description
7
SIGIN_IN
Input buffer of the SIGIN pin
MFRC631
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Bit
6
Symbol
Description
CLKOUT_IN
IFSEL1_IN
IFSEL0_IN
TCK_IN
Input buffer of the CLKOUT pin
Input buffer of the IFSEL1 pin
Input buffer of the IFSEL0 pin
Input buffer of the TCK pin
Input buffer of the TMS pin
Input buffer of the TDI pin
Input buffer of the TDO pin
5
4
3
2
TMS_IN
1
TDI_IN
0
TDO_IN
8.16.4 SigOut
Table 191.ꢀSigOut register (address 47h)
Bit
7
6
5
4
3
2
1
0
Symbol
Pad
RFU
SigOutSel
Speed
Access
rights
r/w
-
r/w
Table 192.ꢀSigOut bits
Bit
Symbol
Description
7
PadSpeed
If set, the I/O pins are supporting a fast switching mode.The fast mode
for the I/O’s will increase the peak current consumption of the device,
especially if multiple I/Os are switching at the same time. The power
supply needs to be designed to deliver this peak currents.
6 to 4
3 to 0
RFU
-
SIGOutSel
0h, 1h - The pin SIGOUT is 3-state
2h - The pin SIGOUT is 0
3h - The pin SIGOUT is 1
4h - The pin SIGOUT shows the TX-envelope
5h - The pin SIGOUT shows the TX-active signal
6h - The pin SIGOUT shows the S3C (generic) signal
7h - The pin SIGOUT shows the RX-envelope
(only valid for ISO/IEC 14443A, 106 kBd)
8h - The pin SIGOUT shows the RX-active signal
9h - The pin SIGOUT shows the RX-bit signal
8.17 Version register
8.17.1 Version
Table 193.ꢀVersion register (address 7Fh)
Bit
7
6
5
4
3
2
1
0
Symbol
MFRC631
Version
SubVersion
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Bit
7
6
5
4
3
2
1
0
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Table 194.ꢀVersion bits
Bit
Symbol
Description
7 to 4
Version
Includes the version of the MFRC631 silicon.
MFRC63102: 0x1
MFRC63103: 0x1
3 to 0
SubVersion
Includes the subversion of the MFRC631 silicon.
MFRC63102: 0x8
MFRC63103: 0xA
MFRC631
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9 Limiting values
Table 195.ꢀLimiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDD
Parameter
Conditions
Min
-0.5
-0.5
-0.5
-
Max
+ 6.0
+ 6.0
+ 6.0
250
Unit
V
supply voltage
VDD(PVDD)
VDD(TVDD)
IDD(TVDD)
PVDD supply voltage
TVDD supply voltage
TVDD supply current
V
V
MFRC63102
MFRC63103
mA
-
500
Vi(RXP)
Vi(RXN)
Ptot
input voltage on pin RXP
input voltage on pin RXN
total power dissipation
-0.5
-0.5
-
+ 2.0
+ 2.0
1125
2000
V
V
per package
mW
V
VESD(HBM)
electrostatic discharge voltage Human Body Model (HBM);
-2000
1500 Ω, 100 pF; JESD22-A114-
B
VESD(CDM)
Tj(max)
electrostatic discharge voltage Charge Device Model (CDM);
-500
-
500
125
V
maximum junction
temperature
°C
Tstg
storage temperature
no supply voltage applied
-55
+150
°C
MFRC631
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10 Recommended operating conditions
Exposure of the device to other conditions than specified in the Recommended Operating
Conditions section for extended periods may affect device reliability.
Electrical parameters (minimum, typical and maximum) of the device are guaranteed only
when it is used within the recommended operating conditions.
Table 196.ꢀOperating conditions MFRC63102HN
Symbol
Parameter
Conditions
Min
3.0
3.0
3.0
-25
Typ
5.0
5.0
5.0
+25
Max Unit
VDD
supply voltage
5.5
5.5
5.5
+85
V
[1]
VDD(TVDD) TVDD supply voltage
VDD(PVDD) PVDD supply voltage
V
V
Tamb
operating ambient
temperature
in still air with exposed pin soldered on a 4
layer JEDEC PCB
°C
Tstg
storage temperature
no supply voltage applied, relative humidity
45...75%
-40
+25
+125 °C
[1] VDD(PVDD) must always be the same or lower than VDD
.
Table 197.ꢀOperating conditions MFRC63103HN
Symbol
Parameter
Conditions
Min
2.5
2.5
2.5
3.0
-40
Typ
5.0
5.0
5.0
5.0
+25
Max Unit
VDD
supply voltage
5.5
5.5
5.5
5.5
V
V
V
V
[1]
VDD(TVDD) TVDD supply voltage
VDD(PVDD) PVDD supply voltage
all host interfaces except I2C interface
all host interfaces incl. I2C interface
Tamb
Tstg
operating ambient
temperature
in still air with exposed pin soldered on a 4
layer JEDEC PCB
+105 °C
storage temperature
no supply voltage applied, relative humidity
45...75%
-45
+25
+125 °C
[1] VDD(PVDD) must always be the same or lower than VDD
.
MFRC631
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High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
11 Thermal characteristics
Table 198.ꢀThermal characteristics
Symbol
Parameter
Conditions
Package Typ Unit
HVQFN32 40 K/W
Rth(j-a)
thermal resistance from junction to
ambient
in still air with exposed pin soldered on a 4
layer JEDEC PCB
MFRC631
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12 Characteristics
Table 199.ꢀCharacteristics
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Current consumption
IDD
supply current
IDD = AVDD+DVDD; modem
on (transmitter and
-
17
20
mA
receiver are switched on)
IDD = AVDD+DVDD; modem
off (transmitter and
receiver are switched off)
-
-
0.45
0.5
0.5
5
mA
μA
IDD(PVDD) PVDD supply current
IDD(TVDD) TVDD supply current
no load on digital pins,
leakage current only
MFRC63102HN
-
-
100
250
250
350
mA
mA
MFRC63103HN
Ipd
power-down current
All OUTx pins floating
ambient temp = +25 °C
-
-
40
400
2.1
nA
μA
ambient temp = -40°C...
+85°C
1.5
MFRC63103: ambient
temp = +105 °C
-
3.5
5.2
μA
μA
Istby
standby current
All OUTx pins floating
ambient temp = 25 °C,
IVDD+ITVDD+ IPVDD
-
-
3
6
ambient temp = -40°C...
5.25
26
+105°C, Istby = IVDD+ITVDD
+
IPVDD
ILPCD(sleep) LPCD sleep current
ILPCD(averageL)PCD average current
All OUTx pins floating
[1]
LFO active, no RF field on,
ambient temp = 25 °C
-
3.3
6.3
μA
All OUTx pins floating,
TxLoad = 50 ohms.
LPCD_FILTER = 0; Rfon
duration = 10 us, RF-off
duration 300ms; VTVDD
=
3.0V; Tamb = 25°C; ILPCD
IVDD+ITVDD+ IPVDD
=
LPCD_TX_HIGH = 0,
LPCD_TX_HIGH = 1
-
-
-
12
23
10
-
-
-
μA
μs
tRFON
RF-on time during LPCD LPCD_TX_HIGH = 0;
TVDD=5.0 V
T=25C;
LPCD_TX_HIGH = 1;
TVDD=5.0 V; T=25C
-
50
-
-
μs
nF
Buffer capacitors on AVDD,DVDD
CL
external buffer capacitor AVDD
220
470
MFRC631
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Symbol Parameter
Conditions
Min
Typ
Max
Unit
CL
external buffer capacitor DVDD
220
470
-
nF
I/O pin characteristics SIGIN/OUT7, SIGOUT, CLKOUT/OUT6,
IFSEL0/OUT4, IFSEL1/OUT5, TCK/OUT3, TMS/OUT2, TDI/
OUT1, TDO/OUT0, IRQ, IF0, IF1, IF2, SCL2, SDA2
ILI
input leakage current
low-level input voltage
high-level input voltage
output disabled
0.0
50
-
500
nA
V
VIL
VIH
-0.5
0.3 x VDD(PVDD)
0.7 x
VDD(PVDD) DD(PVDD)
V
+ 0.5
V
VDD(PVDD)
VOL
VOH
low-level output voltage
0.0
0.0 0.4
V
V
high-level output voltage If pins are used as output
OUTx, IOH = 4 mA driving
VDD(PVDD)-0.4 VDD(PVDDV) DD(PVDD)
current for each pin
Ci
input capacitance
0.0
2.5
0.0
4.5
pF
Pin characteristics PDOWN
VIL
VIH
low-level input voltage
high-level input voltage
0.0
0.4
V
V
0.6 x VPVDD
VDD(PVDDV) DD(PVDD)
Pull-up resistance for TCK, TMS, TDI, IF2
Rpu pull-up resistance
Pin characteristics AUX 1, AUX 2
50
72
120
KΩ
Vo
CL
output voltage
0.0
0.0
-
-
1.8
V
load capacitance
400
pF
Pin characteristics RXP, RXN
Vpp
input voltage
0
2
-
1.65
3.5
1.8
5
V
Ci
input capacitance
modulation voltage
pF
mV
Vmod(pp)
Vmod(pp) = Vi(pp)(max) - Vi(pp)
2.5
-
(min)
Pins TX1 and TX2
Vo
Ro
output voltage
output resistance
Vss(TVSS)
-
-
VDD(TVDD)
-
V
MFRC63102: T=25°C,
VDD(TVDD) = 5.0V
1.5
Ω
MFRC63103: T=25°C,
VDD(TVDD) = 5.0V
-
1.2
-
Ω
Clock frequency Pin CLKOUT
fclk
clock frequency
clock duty cycle
configured to 27.12 MHz
-
-
27.12
50
-
-
MHz
%
δclk
Crystal connection XTAL1, XTAL2
Vo(p-p)
peak-to-peak output
voltage
pin XTAL1
-
1.0
-
V
Vi
Ci
input voltage
pin XTAL1
pin XTAL1
0.0
-
-
1.8
-
V
input capacitance
3
pF
MFRC631
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Symbol Parameter
Crystal requirements
Conditions
Min
Typ
Max
Unit
fxtal
crystal frequency
ISO/IEC14443 compliancy
27.12-14kHz 27.12 27.12+14kHz
MHz
Ω
ESR
equivalent series
resistance
-
50
100
CL
load capacitance
-
-
10
50
-
pF
Pxtal
crystal power dissipation
100
μW
Input characteristics I/O Pin Characteristics IF3-SDA in I2C configuration
ILI
input leakage current
LOW-level input voltage
HIGH-level input voltage
output disabled
-
2
-
100
nA
V
VIL
VIH
VOL
IOL
-0.5
+0.3 VDD(PVDD)
0.7 VDD(PVDD)
-
VDD(PVDD) + 0.5
V
LOW-level output voltage IOL = 3 mA
-
-
0.3
-
V
LOW-level output current VOL = 0.4 V; Standard
mode, Fast mode
4
-
mA
VOL = 0.6 V; Standard
mode, Fast mode
6
-
-
-
-
mA
ns
tf(o)
output fall time
Standard mode, Fast
mode, CL < 400 pF
250
Fast mode +; CL < 550 pF
-
-
-
120
50
ns
ns
tSP
pulse width of spikes that
must be suppressed by
the input filter
0
Ci
input capacitance
load capacitance
-
3.5
5
pF
CL
Standard mode
Fast mode
-
-
-
-
400
550
-
pF
-
pF
tEER
EEPROM data retention Tamb = +55 °C
time
10
year
NEEC
EEPROM endurance
under all operating
5 x 105
-
-
cycle
(number of programming conditions
cycles)
[1] Ipd is the total current for all supplies.
V
mod
V
V
i(p-p)(min)
i(p-p)(max)
VMID
13.56 MHz
carrier
0 V
001aak012
Figure 31.ꢀPin RX input voltage
MFRC631
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High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
12.1 Timing characteristics
Table 200.ꢀSPI timing characteristics
Symbol
tSCKL
Parameter
Conditions
Min Typ Max Unit
SCK LOW time
SCK HIGH time
50
50
25
-
-
-
-
-
-
ns
ns
ns
tSCKH
th(SCKH-D)
SCK HIGH to data input
hold time
SCK to changing MOSI
tsu(D-SCKH)
th(SCKL-Q)
data input to SCK HIGH set- changing MOSI to SCK
up time
25
-
-
-
-
-
-
ns
ns
ns
ns
SCK LOW to data output
hold time
SCK to changing MISO
25
-
t(SCKL-NSSH) SCK LOW to NSS HIGH
time
0
tNSSH
NSS HIGH time
before communication
50
-
Remark: To send more bytes in one data stream the NSS signal must be LOW during
the send process. To send more than one data stream the NSS signal must be HIGH
between each data stream.
Table 201.ꢀI2C-bus timing in fast mode and fast mode plus
Symbol
Parameter
Conditions
Fast mode Fast mode Unit
Plus
Min Max Min Max
fSCL
SCL clock frequency
0
400
-
0
1000 kHz
tHD;STA
hold time (repeated) START
condition
after this period,
the first clock
pulse is generated
600
260
-
-
ns
tSU;STA
set-up time for a repeated
START condition
600
600
-
-
260
ns
tSU;STO
tLOW
tHIGH
tHD;DAT
tSU;DAT
tr
set-up time for STOP condition
LOW period of the SCL clock
HIGH period of the SCL clock
data hold time
260
-
-
-
ns
ns
ns
1300 -
500
600
0
-
260
900
-
-
-
-
-
-
450 ns
- ns
data set-up time
100
20
20
20
rise time
SCL signal
SCL signal
300
300
300
120 ns
120 ns
120 ns
tf
fall time
tr
rise time
SDA and SCL
signals
tf
fall time
SDA and SCL
signals
20
300
-
-
120 ns
tBUF
bus free time between a STOP
and START condition
1.3
0.5
-
μs
MFRC631
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High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
SDA
SCL
t
t
t
t
r
f
SU;DAT
SP
t
t
t
t
BUF
LOW
f
HD;STA
t
t
t
SU;STO
r
HIGH
t
t
SU;STA
HD;STA
t
HD;DAT
S
Sr
P
S
001aaj635
Figure 32.ꢀTiming for fast and standard mode devices on the I2C-bus
MFRC631
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High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
13 Application information
A typical application diagram using a complementary antenna connection to the
MFRC631 is shown in Figure 33.
The antenna tuning and RF part matching is described in the application note [1] and [2].
VDD
PVDD
25
TVDD
18
8
C
C
RXN
AVDD
RXN
9
13
14
17
16
R1
vmid
VMID
TX1
R2
PDOWN
21
C1
C1
L0
Ra
C2
host
interface
antenna
Lant
READER IC
C0
C0
MICRO-
PROCESSOR
28-31
32
TVSS
TX2
IRQ
C2
Ra
L0
15
14
12
DVDD
7
RXP
R3
R4
33
19
20
XTAL2
C
RXP
VSS XTAL1
27.12 MHz
001aam269
Figure 33.ꢀTypical application antenna circuit diagram
13.1 Antenna design description
The matching circuit for the antenna consists of an EMC low pass filter (L0 and C0), a
matching circuitry (C1 and C2), and a receiving circuits (R1 = R3, R2 = R4, C3 = C5
and C4 = C6;), and the antenna itself. The receiving circuit component values needs to
be designed for operation with the MFRC631. A reuse of dedicated antenna designs
done for other products without adaptation of component values will result in degraded
performance.
13.1.1 EMC low pass filter
The MIFARE product-based system operates at a frequency of 13.56 MHz. This
frequency is derived from a quartz oscillator to clock the MFRC631 and is also the
basis for driving the antenna with the 13.56 MHz energy carrier. This will not only
cause emitted power at 13.56 MHz but will also emit power at higher harmonics. The
international EMC regulations define the amplitude of the emitted power in a broad
frequency range. Thus, an appropriate filtering of the output signal is necessary to fulfil
these regulations.
Remark: The PCB layout has a major influence on the overall performance of the filter.
MFRC631
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High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
13.1.2 Antenna matching
Due to the impedance transformation of the given low pass filter, the antenna coil has to
be matched to a certain impedance. The matching elements C1 and C2 can be estimated
and have to be fine tuned depending on the design of the antenna coil.
The correct impedance matching is important to provide the optimum performance.
The overall quality factor has to be considered to guarantee a proper ISO/IEC 14443
communication scheme. Environmental influences have to be considered as well as
common EMC design rules.
For details refer to the NXP application notes.
13.1.3 Receiving circuit
The internal receiving concept of the MFRC631 makes use both side-bands of the sub-
carrier load modulation of the card response via a differential receiving concept (RXP,
RXN). No external filtering is required.
It is recommended to use the internally generated VMID potential as the input potential
of pin RX. This DC voltage level of VMID has to be coupled to the Rx-pins via R2 and
R4. To provide a stable DC reference voltage capacitances C4, C6 has to be connected
between VMID and ground. Refer to Figure 33
Considering the (AC) voltage limits at the Rx-pins the AC voltage divider of R1 + C3 and
R2 as well as R3 + C5 and R4 has to be designed. Depending on the antenna coil design
and the impedance matching the voltage at the antenna coil varies from antenna design
to antenna design. Therefore the recommended way to design the receiving circuit is to
use the given values for R1(= R3), R2 (= R4), and C3 (= C5) from the above mentioned
application note, and adjust the voltage at the RX-pins by varying R1(= R3) within the
given limits.
Remark: R2 and R4 are AC-wise connected to ground (via C4 and C6).
13.1.4 Antenna coil
The precise calculation of the antenna coils’ inductance is not practicable but the
inductance can be estimated using the following formula. We recommend designing an
antenna either with a circular or rectangular shape.
(4)
• I1 - Length in cm of one turn of the conductor loop
• D1 - Diameter of the wire or width of the PCB conductor respectively
• K - Antenna shape factor (K = 1,07 for circular antennas and K = 1,47 for square
antennas)
• L1 - Inductance in nH
• N1 - Number of turns
• Ln: Natural logarithm function
The actual values of the antenna inductance, resistance, and capacitance at 13.56
MHz depend on various parameters such as:
MFRC631
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• antenna construction (Type of PCB)
• thickness of conductor
• distance between the windings
• shielding layer
• metal or ferrite in the near environment
Therefore a measurement of those parameters under real life conditions, or at least a
rough measurement and a tuning procedure is highly recommended to guarantee a
reasonable performance. For details refer to the above mentioned application notes.
MFRC631
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14 Package outline
HVQFN32: plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5 x 5 x 0.85 mm
SOT617-1
B
A
D
terminal 1
index area
A
A
1
E
c
detail X
C
e
1
y
y
e
1/2 e
v
M
b
C
C
A B
C
1
w M
9
16
L
17
8
e
e
2
E
h
1/2 e
1
24
terminal 1
index area
32
25
X
D
h
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
1
c
e
y
b
E
h
e
e
2
D
D
E
L
v
w
y
1
1
h
max.
0.05 0.30
0.00 0.18
5.1
4.9
3.25
2.95
5.1
4.9
3.25
2.95
0.5
0.3
mm
0.05 0.1
1
0.2
0.5
3.5
3.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
01-08-08
02-10-18
SOT617-1
- - -
MO-220
- - -
Figure 34.ꢀPackage outline SOT617-1 (HVQFN32)
MFRC631
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Detailed package information can be found at http://www.nxp.com/package/
SOT617-1.html.
MFRC631
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15 Handling information
Moisture Sensitivity Level (MSL) evaluation has been performed according to SNW-
FQ-225B rev.04/07/07 (JEDEC J-STD-020C). MSL for this package is level 2 which
means 260 °C convection reflow temperature.
For MSL2:
• Dry pack is required.
• 1 year out-of-pack floor life at maximum ambient temperature 30 °C/ 85 % RH.
For MSL1:
• No dry pack is required.
• No out-of-pack floor live spec. required.
MFRC631
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16 Packing information
strap 46 mm from corner
The straps around the package of
stacked trays inside the plano-box
have sufficient pre-tension to avoid
loosening of the trays.
tray
ESD warning preprinted
barcode label (permanent)
barcode label (peel-off)
chamfer
PIN 1
chamfer
PIN 1
QA seal
Hyatt patent preprinted
In the traystack (2 trays)
only ONE tray type* allowed
printed plano box
*one supplier and one revision number.
001aaj740
Figure 35.ꢀPacking information 1 tray
MFRC631
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strap 46 mm from the corner
PQ-label (permanent)
bag
dry-agent
relative humidity indicator
preprinted:
tray
recycling symbol
moisture caution label
ESD warning
manufacturer bag info
chamfer
ESD warning preprinted
PQ-label (permanent)
PIN 1
PLCC52
dry-pack ID preprinted
strap
chamfer
PIN 1
QA seal
chamfer
PIN 1
printed plano box
aaa-004952
Figure 36.ꢀPacking information 5 tray
MFRC631
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BC
BA
BB
BA
BD
BD
section BC-BC
scale 4:1
BC
BB
C
A B
0.50
16.60±0.08+7°/S SQ.
13.85±0.08+12°/S SQ.
(14.40+5°/S SQ.)
vacuum cell
end lock
side lock
AN
AJ
AJ
AK
12.80-5°/S SQ.
AM
AM
AL
AL
AR
AR
14.20±0.08+10°/S SQ.
C
A B
0.50
section BA-BA
scale 4:1
AK
AN
section AK-AK
scale 5:1
section AN-AN
scale 4:1
detail AC
section AJ-AJ
scale 2:1
scale 20:1
section AM-AM
scale 4:1
section AL-AL
scale 5:1
section AR-AR
scale 2:1
section BD-BD
scale 4:1
aaa-004949
Figure 37.ꢀTray details
MFRC631
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ASSY REEL + LABELS
tape
see: ASSY REEL + LABELS
(see: HOW TO SECURE)
Ø 330x12/16/24/32 (hub 7'')
guard band
label side
embossed
ESD logo
tape
circular sprocket holes
opposite the label side of reel
(see: HOW TO SECURE)
printed plano-box
Ø 330x16/24/32/44 (hub 4'')
Ø 330x44 (hub 6'')
cover tape
embossed
ESD logo
carrier tape
Ø 180x12/16/24
enlongated
product orientation ONLY for turned
products with 12nc ending 128
HOW TO SECURE LEADER END TO THE GUARD BAND,
HOW TO SECURE GUARD BAND
PIN1 has to be
in quadrant 1
circular
PIN1
SO
PIN1
PIN1
PIN1
PIN1
PIN1
product orientation
in carrier tape
trailer : lenght of trailer shall be 160 mm min.
1
3
2
4
1
3
2
4
tapeslot
QFP
PLCC
SO
PIN1
for SOT765
ending 125
QFP
and covered with cover tape
PIN1
for SOT505-2
BGA
BGA
bare die
PIN1
bare die
ending 125
leader : lenght of trailer shall be 400 mm min.
and covered with cover tape
unreeling direction
label side
trailer
(HV)QFN
(HV)SON
(H)BCC
(HV)QFN
(HV)SON
(H)BCC
enlongated
circular sprocket hole side
guard band
leader
QA seal
tape
(with pull tabs on both ends)
preprinted ESD warning
lape double-backed
onto itself on both ends
PQ-label
(permanent)
dry-pack ID preprinted
guard band
aaa-004950
Figure 38.ꢀPacking information Reel
MFRC631
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MFRC631
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17 Appendix
17.1 LoadProtocol command register initialization
The RF configuration is loaded with the command Load Protocol. The tables below
show the register configuration as performed by this command for each of the protocols.
Antenna specific configurations are not covered by this register settings.
The MFRC63102 is not initialized for any antenna configuration. For this products the
antenna configuration needs to be done by firmware.
The MFRC63103 antenna configuration in the user EEPROM is described in the
Section 17.2.
Table 202.ꢀProtocol Number 00: ISO/IEC14443-A 106 / MIFARE Classic
Value for register
TxBitMod
Value (hex)
20
RFU
00
TxDataCon
TxDataMod
TxSymFreq
TxSym0H
04
50
40
00
TxSym0L
00
TxSym1H
00
TxSym1L
00
TxSym2
00
TxSym3
00
TxSym10Len
TxSym32Len
TxSym10BurstCtrl
TxSym10Mod
TxSym32Mod
RxBitMod
00
00
00
00
50
02
RxEofSym
RxSyncValH
RxSyncValL
RxSyncMod
RxMod
00
00
01
00
08
RxCorr
80
FabCal
B2
MFRC631
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High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
Table 203.ꢀProtocol Number 01: ISO/IEC14443-A 212/ MIFARE Classic
Value for register
TxBitMod
Value (hex)
20
RFU
00
TxDataCon
TxDataMod
TxSymFreq
TxSym0H
05
50
50
00
TxSym0L
00
TxSym1H
00
TxSym1L
00
TxSym2
00
TxSym3
00
TxSym10Len
TxSym32Len
TxSym10BurstCtrl
TxSym10Mod
TxSym32Mod
RxBitMod
00
00
00
00
50
22
RxEofSym
RxSyncValH
RxSyncValL
RxSyncMod
RxMod
00
00
00
00
0D
80
RxCorr
FabCal
B2
Table 204.ꢀProtocol Number 02: ISO/IEC14443-A 424/ MIFARE Classic
Value for register
TxBitMod
Value (hex)
20
00
06
50
60
00
00
00
00
RFU
TxDataCon
TxDataMod
TxSymFreq
TxSym0H
TxSym0L
TxSym1H
TxSym1L
MFRC631
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High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
Value for register
TxSym2
Value (hex)
00
00
00
00
00
00
50
22
00
00
00
00
0D
80
B2
TxSym3
TxSym10Len
TxSym32Len
TxSym10BurstCtrl
TxSym10Mod
TxSym32Mod
RxBitMod
RxEofSym
RxSyncValH
RxSyncValL
RxSyncMod
RxMod
RxCorr
FabCal
Table 205.ꢀProtocol Number 03: ISO/IEC14443-A 848/ MIFARE Classic
Value for register
TxBitMod
Value (hex)
20
00
07
50
70
00
00
00
00
00
00
00
00
00
00
50
22
00
RFU
TxDataCon
TxDataMod
TxSymFreq
TxSym0H
TxSym0L
TxSym1H
TxSym1L
TxSym2
TxSym3
TxSym10Len
TxSym32Len
TxSym10BurstCtrl
TxSym10Mod
TxSym32Mod
RxBitMod
RxEofSym
MFRC631
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High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
Value for register
RxSyncValH
Value (hex)
00
00
00
0D
80
B2
RxSyncValL
RxSyncMod
RxMod
RxCorr
FabCal
Table 206.ꢀProtocol Number 04: ISO/IEC14443-B 106
Value for register
TxBitMod
Value (hex)
09
RFU
00
TxDataCon
TxDataMod
TxSymFreq
TxSym0H
04
08
04
00
TxSym0L
03
TxSym1H
00
TxSym1L
01
TxSym2
00
TxSym3
00
TxSym10Len
TxSym32Len
TxSym10BurstCtrl
TxSym10Mod
TxSym32Mod
RxBitMod
AB
00
00
08
00
04
RxEofSym
RxSyncValH
RxSyncValL
RxSyncMod
RxMod
00
00
00
02
MFRC63102: 1D
MFRC63103: 0D
RxCorr
FabCal
80
B2
MFRC631
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High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
Table 207.ꢀProtocol Number 05: ISO/IEC14443-B 212
Value for register
TxBitMod
Value (hex)
09
RFU
00
TxDataCon
TxDataMod
TxSymFreq
TxSym0H
05
08
05
00
TxSym0L
03
TxSym1H
00
TxSym1L
01
TxSym2
00
TxSym3
00
TxSym10Len
TxSym32Len
TxSym10BurstCtrl
TxSym10Mod
TxSym32Mod
RxBitMod
AB
00
00
08
00
04
RxEofSym
RxSyncValH
RxSyncValL
RxSyncMod
RxMod
00
00
00
02
MFRC63102: 1D
MFRC63103: 0D
RxCorr
FabCal
80
B2
Table 208.ꢀProtocol Number 06: ISO/IEC14443-B 424
Value for register
TxBitMod
Value (hex)
09
00
06
08
06
00
03
00
RFU
TxDataCon
TxDataMod
TxSymFreq
TxSym0H
TxSym0L
TxSym1H
MFRC631
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High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
Value for register
TxSym1L
Value (hex)
01
TxSym2
00
TxSym3
00
TxSym10Len
TxSym32Len
TxSym10BurstCtrl
TxSym10Mod
TxSym32Mod
RxBitMod
AB
00
00
08
00
04
RxEofSym
00
RxSyncValH
RxSyncValL
RxSyncMod
RxMod
00
00
02
MFRC63102: 1D
MFRC63103: 0D
RxCorr
FabCal
80
B2
Table 209.ꢀProtocol Number 07: ISO/IEC14443-B 848
Value for register
TxBitMod
Value (hex)
09
00
07
08
07
00
03
00
01
00
00
AB
00
00
08
00
RFU
TxDataCon
TxDataMod
TxSymFreq
TxSym0H
TxSym0L
TxSym1H
TxSym1L
TxSym2
TxSym3
TxSym10Len
TxSym32Len
TxSym10BurstCtrl
TxSym10Mod
TxSym32Mod
MFRC631
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High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
Value for register
RxBitMod
Value (hex)
04
RxEofSym
RxSyncValH
RxSyncValL
RxSyncMod
RxMod
00
00
00
02
MFRC63102: 1D
MFRC63103: 0D
RxCorr
FabCal
80
B2
17.2 MFRC63103 EEPROM configuration
The MFRC63103 user EEPROM had been initalized with useful values for configuration
of the chip using a typical 65x65mm antenna. This values stored in EEPROM can be
used to configure the MFRC63103 with the command LoadReg.Typically, some of this
entries will be required to be modified compared to the preset values to achieve the best
RF performance for a specific antenna.
The registers 0x28...0x39 are relevant for configuration of the Antenna. For each
supported protocol, a dedicated preset configuration is available. To ensure compatibility
between products of the CLRC63103 family, all products use the same default settings
which are initialized in EEPROM, even if some of this protocols are not supported by the
MFRC63103 product (e.g.ISO/IEC14443-B) and cannot be used.
Alternatively, the registers can be initialized by individual register write commands.
Table 210.ꢀISO/IEC14443-A 106 / MIFARE Classic
Value for register
DrvMode
EEPROM address (hex)
Value (hex)
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
8E
12
39
0A
18
18
0F
21
00
C0
12
CF
00
04
TxAmp
DrvCon
TxI
TXCrcPreset
RXCrcPreset
TxDataNum
TxModWidth
TxSym10BurstLen
TxWaitCtrl
TxWaitLo
TxFrameCon
RxSofD
RxCtrl
MFRC631
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High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
Value for register
EEPROM address (hex)
Value (hex)
RxWait
RxTreshold
Rcv
CE
CF
D0
D1
90
5C
12
0A
RxAna
Table 211.ꢀISO/IEC14443-A 212/ MIFARE Classic
Value for register
DrvMode
EEPROM address (hex)
Value (hex)
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
8E
D2
11
0A
18
18
0F
10
00
C0
12
CF
00
05
90
3C
12
0B
TxAmp
DrvCon
TxI
TXCrcPreset
RXCrcPreset
TxDataNum
TxModWidth
TxSym10BurstLen
TxWaitCtrl
TxWaitLo
TxFrameCon
RxSofD
RxCtrl
RxWait
RxTreshold
Rcv
RxAna
Table 212.ꢀISO/IEC14443-A 424/ MIFARE Classic
Value for register
DrvMode
EEPROM address (hex)
Value (hex)
E8
E9
EA
EB
EC
ED
EE
EF
8F
DE
11
0F
18
18
0F
07
TxAmp
DrvCon
TxI
TXCrcPreset
RXCrcPreset
TxDataNum
TxModWidth
MFRC631
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MFRC631
High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
Value for register
EEPROM address (hex)
Value (hex)
TxSym10BurstLen
TxWaitCtrl
TxWaitLo
TxFrameCon
RxSofD
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
00
C0
12
CF
00
06
90
2B
12
0B
RxCtrl
RxWait
RxTreshold
Rcv
RxAna
Table 213.ꢀISO/IEC14443-A 848/ MIFARE Classic
Value for register
DrvMode
EEPROM address (hex)
Value (hex)
0100
0101
0102
0103
0104
0105
0106
0107
0108
0109
010A
010B
010C
010D
010E
010F
0110
0111
8F
DB
21
0F
18
18
0F
02
00
C0
12
CF
00
07
90
3A
12
0B
TxAmp
DrvCon
TxI
TXCrcPreset
RXCrcPreset
TxDataNum
TxModWidth
TxSym10BurstLen
TxWaitCtrl
TxWaitLo
TxFrameCon
RxSofD
RxCtrl
RxWait
RxTreshold
Rcv
RxAna
Table 214.ꢀISO/IEC14443-B 106
Value for register
EEPROM address (hex)
Value (hex)
DrvMode
TxAmp
0114
0115
8F
0E
MFRC631
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MFRC631
High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
Value for register
EEPROM address (hex)
Value (hex)
DrvCon
0116
0117
0118
0119
011A
011B
011C
011D
011E
011F
0120
0121
0112
0113
0114
0115
09
0A
7B
7B
08
00
00
01
00
05
00
34
90
6F
12
03
TxI
TXCrcPreset
RXCrcPreset
TxDataNum
TxModWidth
TxSym10BurstLen
TxWaitCtrl
TxWaitLo
TxFrameCon
RxSofD
RxCtrl
RxWait
RxTreshold
Rcv
RxAna
Table 215.ꢀISO/IEC14443-B 212
Value for register
EEPROM address (hex)
Value (hex)
DrvMode
TxAmp
0128
0129
012A
012B
012C
012D
012E
012F
0130
0131
0132
0133
0134
0135
0136
0137
0138
8F
0E
09
0A
7B
7B
08
00
00
01
00
05
00
35
90
3F
12
DrvCon
TxI
TXCrcPreset
RXCrcPreset
TxDataNum
TxModWidth
TxSym10BurstLen
TxWaitCtrl
TxWaitLo
TxFrameCon
RxSofD
RxCtrl
RxWait
RxTreshold
Rcv
MFRC631
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MFRC631
High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
Value for register
EEPROM address (hex)
Value (hex)
RxAna
0139
03
Table 216.ꢀISO/IEC14443-B 424
Value for register
EEPROM address (hex)
Value (hex)
DrvMode
TxAmp
0140
0141
0142
0143
0144
0145
0146
0147
0148
0149
014A
014B
014C
014D
014E
014F
0150
0151
8F
0F
09
0A
7B
7B
08
00
00
01
00
05
00
36
90
3F
12
03
DrvCon
TxI
TXCrcPreset
RXCrcPreset
TxDataNum
TxModWidth
TxSym10BurstLen
TxWaitCtrl
TxWaitLo
TxFrameCon
RxSofD
RxCtrl
RxWait
RxTreshold
Rcv
RxAna
Table 217.ꢀISO/IEC14443-B 848
Value for register
EEPROM address (hex)
Value (hex)
DrvMode
0154
0155
0156
0157
0158
0159
015A
015B
015C
015D
015E
8F
10
09
0A
7B
7B
08
00
00
01
00
TxAmp
DrvCon
TxI
TXCrcPreset
RXCrcPreset
TxDataNum
TxModWidth
TxSym10BurstLen
TxWaitCtrl
TxWaitLo
MFRC631
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MFRC631
High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
Value for register
EEPROM address (hex)
Value (hex)
TxFrameCon
RxSofD
RxCtrl
015F
0160
0161
0162
0163
0164
0165
05
00
37
90
3F
12
03
RxWait
RxTreshold
Rcv
RxAna
The following EEprom values for initializing the Receiver cannot be used on the
MFRC63103. They are provided for compatibility reasons between the products of the
CLRC66303 product family
Table 218.ꢀJIS X 6319-4 (FeliCa) 212
Value for register
DrvMode
EEPROM address (hex)
Value (hex)
0168
0169
016A
016B
016C
016D
016E
016F
0170
0171
0172
0173
0174
0175
0176
0177
0178
0179
8F
17
01
06
09
09
08
00
03
80
12
01
00
05
86
3F
12
02
TxAmp
DrvCon
TxI
TXCrcPreset
RXCrcPreset
TxDataNum
TxModWidth
TxSym10BurstLen
TxWaitCtrl
TxWaitLo
TxFrameCon
RxSofD
RxCtrl
RxWait
RxTreshold
Rcv
RxAna
Table 219.ꢀJIS X 6319-4 (FeliCa) 424
Value for register
DrvMode
EEPROM address (hex)
Value (hex)
0180
0181
0182
8F
17
01
TxAmp
DrvCon
MFRC631
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MFRC631
High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
Value for register
EEPROM address (hex)
Value (hex)
TxI
0183
0184
0185
0186
0187
0188
0189
018A
018B
018C
018D
018E
018F
0190
0191
06
09
09
08
00
03
80
12
01
00
06
86
3F
12
02
TXCrcPreset
RXCrcPreset
TxDataNum
TxModWidth
TxSym10BurstLen
TxWaitCtrl
TxWaitLo
TxFrameCon
RxSofD
RxCtrl
RxWait
RxTreshold
Rcv
RxAna
Table 220.ꢀISO/IEC15693 SLI 1/4 - SSC- 26
Value for register
DrvMode
EEPROM address (hex)
Value (hex)
0194
0195
0196
0197
0198
0199
019A
019B
019C
019D
019E
019F
01A0
01A1
01A2
01A3
01A4
01A5
89
10
09
0A
7B
7B
08
00
00
88
A9
0F
00
02
9C
74
12
07
TxAmp
DrvCon
TxI
TXCrcPreset
RXCrcPreset
TxDataNum
TxModWidth
TxSym10BurstLen
TxWaitCtrl
TxWaitLo
TxFrameCon
RxSofD
RxCtrl
RxWait
RxTreshold
Rcv
RxAna
MFRC631
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MFRC631
High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
Table 221.ꢀISO/IEC15693 SLI 1/4 - SSC-53
Value for register
DrvMode
EEPROM address (hex)
Value (hex)
01A8
01A9
01AA
01AB
01AC
01AD
01AE
016F
01B0
01B1
01B2
01B3
01B4
01B5
01B6
01B7
01B8
01B9
89
10
09
0A
7B
7B
08
00
00
88
A9
0F
00
03
9C
74
12
03
TxAmp
DrvCon
TxI
TXCrcPreset
RXCrcPreset
TxDataNum
TxModWidth
TxSym10BurstLen
TxWaitCtrl
TxWaitLo
TxFrameCon
RxSofD
RxCtrl
RxWait
RxTreshold
Rcv
RxAna
Table 222.ꢀISO/IEC15693 SLI 1/256 - DSC
Value for register
DrvMode
EEPROM address (hex)
Value (hex)
01C0
01C1
01C2
01C3
01C4
01C5
01C6
01C7
01C8
01C9
01CA
01CB
01CC
01CD
01CE
8E
10
01
06
7B
7B
08
00
00
88
A9
0F
00
02
10
TxAmp
DrvCon
TxI
TXCrcPreset
RXCrcPreset
TxDataNum
TxModWidth
TxSym10BurstLen
TxWaitCtrl
TxWaitLo
TxFrameCon
RxSofD
RxCtrl
RxWait
MFRC631
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MFRC631
High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
Value for register
EEPROM address (hex)
Value (hex)
RxTreshold
Rcv
01CF
01D0
01D1
44
12
06
RxAna
Table 223.ꢀEPC/UID - SSC -26
Value for register
EEPROM address (hex)
Value (hex)
DrvMode
TxAmp
01D4
01D5
01D6
01D7
01D8
01D9
01DA
01DB
01DC
01DD
01DE
01DF
01E0
01E1
01E2
01E3
01E4
01E5
8F
10
01
06
74
7B
18
00
00
50
5C
0F
00
03
10
4E
12
06
DrvCon
TxI
TXCrcPreset
RXCrcPreset
TxDataNum
TxModWidth
TxSym10BurstLen
TxWaitCtrl
TxWaitLo
TxFrameCon
RxSofD
RxCtrl
RxWait
RxTreshold
Rcv
RxAna
Table 224.ꢀEPC-V2 - 2/424
Value for register
EEPROM address (hex)
Value (hex)
DrvMode
01E8
01E9
01EA
01EB
01EC
01ED
01EE
01EF
01F0
8F
10
09
0A
11
91
09
00
00
TxAmp
DrvCon
TxI
TXCrcPreset
RXCrcPreset
TxDataNum
TxModWidth
TxSym10BurstLen
MFRC631
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MFRC631
High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
Value for register
EEPROM address (hex)
Value (hex)
TxWaitCtrl
TxWaitLo
TxFrameCon
RxSofD
RxCtrl
01F1
01F2
01F3
01F4
01F5
01F6
01F7
01F8
01F9
80
12
01
00
03
A0
56
12
0F
RxWait
RxTreshold
Rcv
RxAna
Table 225.ꢀEPC-V2 - 4/424
Value for register
EEPROM address (hex)
Value (hex)
DrvMode
TxAmp
0200
0201
0202
0203
0204
0205
0206
0207
0208
0209
020A
020B
020C
020D
020E
020F
0210
0211
8F
10
09
0A
11
91
09
00
00
80
12
01
00
03
A0
56
12
0F
DrvCon
TxI
TXCrcPreset
RXCrcPreset
TxDataNum
TxModWidth
TxSym10BurstLen
TxWaitCtrl
TxWaitLo
TxFrameCon
RxSofD
RxCtrl
RxWait
RxTreshold
Rcv
RxAna
Table 226.ꢀEPC-V2 - 2/848
Value for register
EEPROM address (hex)
Value (hex)
DrvMode
TxAmp
0214
0215
0216
8F
D0
01
DrvCon
MFRC631
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MFRC631
High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
Value for register
EEPROM address (hex)
Value (hex)
TxI
0217
0218
0219
021A
021B
021C
021D
021E
021F
0220
0221
0222
0223
0224
0225
0A
11
91
09
00
00
80
12
01
00
05
A0
26
12
0E
TXCrcPreset
RXCrcPreset
TxDataNum
TxModWidth
TxSym10BurstLen
TxWaitCtrl
TxWaitLo
TxFrameCon
RxSofD
RxCtrl
RxWait
RxTreshold
Rcv
RxAna
Table 227.ꢀEPC-V2 - 4/848
Value for register
EEPROM address (hex)
Value (hex)
DrvMode
TxAmp
0228
0229
022A
022B
022C
022D
022E
022F
0230
0231
0232
0233
0234
0235
0236
0237
0238
0239
8F
D0
01
0A
11
91
09
00
00
80
12
01
00
05
A0
26
12
0E
DrvCon
TxI
TXCrcPreset
RXCrcPreset
TxDataNum
TxModWidth
TxSym10BurstLen
TxWaitCtrl
TxWaitLo
TxFrameCon
RxSofD
RxCtrl
RxWait
RxTreshold
Rcv
RxAna
MFRC631
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MFRC631
High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
Table 228.ꢀJewel
Value for register
DrvMode
EEPROM address (hex)
Value (hex)
0240
0241
0242
0243
0244
0245
0246
0247
0248
0249
024A
024B
024C
024D
024E
024F
0250
0251
8E
15
11
06
18
18
0F
20
00
40
09
4F
00
04
8F
32
12
0A
TxAmp
DrvCon
TxI
TXCrcPreset
RXCrcPreset
TxDataNum
TxModWidth
TxSym10BurstLen
TxWaitCtrl
TxWaitLo
TxFrameCon
RxSofD
RxCtrl
RxWait
RxTreshold
Rcv
RxAna
Table 229.ꢀISO/IEC14443 - B 106 EMVCo Optimized
Value for register
DrvMode
EEPROM address (hex)
Value (hex)
0254
0255
0256
0257
0258
0259
025A
025B
025C
025D
025E
025F
0260
0261
0262
8F
0E
09
0A
7B
7B
08
00
00
01
00
05
00
34
90
TxAmp
DrvCon
TxI
TXCrcPreset
RXCrcPreset
TxDataNum
TxModWidth
TxSym10BurstLen
TxWaitCtrl
TxWaitLo
TxFrameCon
RxSofD
RxCtrl
RxWait
MFRC631
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NXP Semiconductors
MFRC631
High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
Value for register
EEPROM address (hex)
Value (hex)
RxTreshold
Rcv
0263
0264
0265
9F
12
03
RxAna
MFRC631
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MFRC631
High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
18 Abbreviations
Table 230.ꢀAbbreviations
Acronym
Description
ADC
BPSK
CRC
CW
Analog-to-Digital Converter
Binary Phase Shift Keying
Cyclic Redundancy Check
Continuous Wave
EGT
EMC
EMD
EOF
EPC
ETU
GPIO
HBM
I2C
Extra Guard Time
Electro Magnetic Compatibility
Electro Magnetic Disturbance
End Of Frame
Electronic Product Code
Elementary Time Unit
General Purpose Input/Output
Human Body Model
Inter-Integrated Circuit
Interrupt Request
IRQ
LFO
LPCD
LSB
MISO
MOSI
MSB
NRZ
NSS
PCD
PLL
Low Frequency Oscillator
Low-Power Card Detection
Least Significant Bit
Master In Slave Out
Master Out Slave In
Most Significant Bit
Not Return to Zero
Not Slave Select
Proximity Coupling Device
Phase-Locked Loop
Return To Zero
RZ
RX
Receiver
SAM
SOF
SPI
Secure Access Module
Start Of Frame
Serial Peripheral Interface
Software
SW
TTimer
TX
Timing of the clk period
Transmitter
UART
UID
Universal Asynchronous Receiver Transmitter
Unique IDentification
MFRC631
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MFRC631
High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
Acronym
Description
VCO
Voltage Controlled Oscillator
MFRC631
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MFRC631
High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
19 References
[1]
Application note AN11019
CLRC663, MFRC630, MFRC631, SLRC610 Antenna Design Guide
[2]
Application note AN11783
CLRC663 plus Low Power Card Detection
MFRC631
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MFRC631
High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
20 Revision history
Table 231.ꢀRevision history
Document ID
MFRC631 v.4.5
Modifications:
MFRC631 v.4.4
Modifications:
MFRC631 v.4.3
Modifications:
Release date
20180912
Data sheet status
Change notice
Supersedes
Product data sheet
-
MFRC631 v.4.4
• Description of Low frequency timer in Section 7.8.3 more detailed now
20180627
Product data sheet
Product data sheet
-
MFRC631 v.4.3
MFRC631 v.4.2
• Editorial updates
20171219
-
• Deleted references to MICORE Application notes
• Description for new product type MFRC63103 added
• Section 19 updated
MFRC631 v.4.2
Modifications:
MFRC631 v.4.1
Modifications:
20160427
• Descriptive title updated
20160211 Product data sheet
Product data sheet
-
MFRC631 v.4.1
MFRC631 v.4.0
-
• Table: Quick reference data: Table notes [3] and [4] removed
• Table: Characteristics: TVDD supply current value updated
MFRC631 v.4.0
Modifications:
20151029
Product data sheet
-
MFRC631 v.3.3
• Table: Characteristics:
– AVDD and DVDD min and max values added
– IDD(TVDD) max value updated to 250 mA
• Figure 10 "Connection to host with SPI": updated
• Figure 19 "Register read and write access": updated
MFRC631 v.3.3
Modifications:
20140204
Product data sheet
-
MFRC631 v.3.2
• PVDD, TVDD data updated
• Information on FIFO size corrected
• Typing error corrected in description for LPCD
• WaterLevel and FIFOLength updated in register overview description
• WaterLevel and FIFOLength updated in register FIFOControl
• Waterlevel Register updated
• FIFOLength Register updated
• Section 8.15.2 "PinOut": Pin Out register description corrected
MFRC631 v.3.2
Modifications:
20130312
Product data sheet
-
MFRC631 v.3.1
• Update of EEPROM content
• Descriptive title changed
• Table 184 "PinOut register (address 45h)": corrected
MFRC631 v.3.1
<tbd> Product data sheet
-
-
MFRC631
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MFRC631
High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
21 Legal information
21.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Product [short] data sheet
Qualification
Production
This document contains data from the preliminary specification.
This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
21.2 Definitions
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
Draft — The document is a draft version only. The content is still under
to result in personal injury, death or severe property or environmental
internal review and subject to formal approval, which may result in
damage. NXP Semiconductors and its suppliers accept no liability for
modifications or additions. NXP Semiconductors does not give any
inclusion and/or use of NXP Semiconductors products in such equipment or
representations or warranties as to the accuracy or completeness of
applications and therefore such inclusion and/or use is at the customer’s own
information included herein and shall have no liability for the consequences
risk.
of use of such information.
Applications — Applications that are described herein for any of these
Short data sheet — A short data sheet is an extract from a full data sheet
products are for illustrative purposes only. NXP Semiconductors makes
with the same product type number(s) and title. A short data sheet is
no representation or warranty that such applications will be suitable
intended for quick reference only and should not be relied upon to contain
for the specified use without further testing or modification. Customers
detailed and full information. For detailed and full information see the
are responsible for the design and operation of their applications and
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products using NXP Semiconductors products, and NXP Semiconductors
Semiconductors sales office. In case of any inconsistency or conflict with the
accepts no liability for any assistance with applications or customer product
short data sheet, the full data sheet shall prevail.
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications
Product specification — The information and data provided in a Product
and products planned, as well as for the planned application and use of
data sheet shall define the specification of the product as agreed between
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design and operating safeguards to minimize the risks associated with
customer have explicitly agreed otherwise in writing. In no event however,
their applications and products. NXP Semiconductors does not accept any
shall an agreement be valid in which the NXP Semiconductors product
liability related to any default, damage, costs or problem which is based
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
on any weakness or default in the customer’s applications or products, or
the application or use by customer’s third party customer(s). Customer is
responsible for doing all necessary testing for the customer’s applications
and products using NXP Semiconductors products in order to avoid a
default of the applications and the products or of the application or use by
21.3 Disclaimers
Limited warranty and liability — Information in this document is believed
customer’s third party customer(s). NXP does not accept any liability in this
respect.
to be accurate and reliable. However, NXP Semiconductors does not
Limiting values — Stress above one or more limiting values (as defined in
give any representations or warranties, expressed or implied, as to the
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
accuracy or completeness of such information and shall have no liability
damage to the device. Limiting values are stress ratings only and (proper)
for the consequences of use of such information. NXP Semiconductors
operation of the device at these or any other conditions above those
takes no responsibility for the content in this document if provided by an
given in the Recommended operating conditions section (if present) or the
information source outside of NXP Semiconductors. In no event shall NXP
Characteristics sections of this document is not warranted. Constant or
Semiconductors be liable for any indirect, incidental, punitive, special or
repeated exposure to limiting values will permanently and irreversibly affect
consequential damages (including - without limitation - lost profits, lost
the quality and reliability of the device.
savings, business interruption, costs related to the removal or replacement
of any products or rework charges) whether or not such damages are based
on tort (including negligence), warranty, breach of contract or any other
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
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any reason whatsoever, NXP Semiconductors’ aggregate and cumulative
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
liability towards customer for the products described herein shall be limited
in accordance with the Terms and conditions of commercial sale of NXP
agreement shall apply. NXP Semiconductors hereby expressly objects to
Semiconductors.
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or
notice. This document supersedes and replaces all information supplied prior
the grant, conveyance or implication of any license under any copyrights,
to the publication hereof.
patents or other industrial or intellectual property rights.
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High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
21.4 Licenses
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Purchase of NXP ICs with ISO/IEC 14443 type B functionality
This NXP Semiconductors IC is ISO/IEC
14443 Type B software enabled and is
licensed under Innovatron’s Contactless
Card patents license for ISO/IEC 14443 B.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor
tested in accordance with automotive testing or application requirements.
NXP Semiconductors accepts no liability for inclusion and/or use of non-
automotive qualified products in automotive equipment or applications. In
the event that customer uses the product for design-in and use in automotive
applications to automotive specifications and standards, customer (a) shall
use the product without NXP Semiconductors’ warranty of the product for
such automotive applications, use and specifications, and (b) whenever
customer uses the product for automotive applications beyond NXP
Semiconductors’ specifications such use shall be solely at customer’s own
risk, and (c) customer fully indemnifies NXP Semiconductors for any liability,
damages or failed product claims resulting from customer design and use
of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
The license includes the right to use the IC
in systems and/or end-user equipment.
RATP/Innovatron
Technology
Purchase of NXP ICs with NFC technology
Purchase of an NXP Semiconductors IC that complies with one of the
Near Field Communication (NFC) standards ISO/IEC 18092 and ISO/
IEC 21481 does not convey an implied license under any patent right
infringed by implementation of any of those standards. Purchase of NXP
Semiconductors IC does not include a license to any NXP patent (or other
IP right) covering combinations of those products with other products,
whether hardware or software.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
21.5 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
MIFARE — is a trademark of NXP B.V.
DESFire — is a trademark of NXP B.V.
ICODE and I-CODE — are trademarks of NXP B.V.
MIFARE Plus — is a trademark of NXP B.V.
MIFARE Ultralight — is a trademark of NXP B.V.
MIFARE Classic — is a trademark of NXP B.V.
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MFRC631
High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
Tables
Tab. 1.
Tab. 2.
Tab. 3.
Tab. 4.
Tab. 5.
Tab. 6.
Quick reference data MFRC63102HN ...............3
Quick reference data MFRC63103HN ...............3
Tab. 42. MFRC631 registers overview ..........................55
Tab. 43. Command register (address 00h) ....................57
Tab. 44. Command bits .................................................58
Tab. 45. HostCtrl register (address 01h); ...................... 58
Tab. 46. HostCtrl bits .....................................................58
Tab. 47. FIFOControl register (address 02h); ............... 59
Tab. 48. FIFOControl bits ..............................................59
Tab. 49. WaterLevel register (address 03h); .................59
Tab. 50. WaterLevel bits ............................................... 60
Tab. 51. FIFOLength register (address 04h); reset
value: 00h ........................................................60
Tab. 52. FIFOLength bits .............................................. 60
Tab. 53. FIFOData register (address 05h); ................... 60
Tab. 54. FIFOData bits ..................................................61
Tab. 55. IRQ0 register (address 06h); reset value:
00h .................................................................. 61
Ordering information ..........................................4
Pin description ...................................................6
Interrupt sources ............................................... 9
Read/write mode for ISO/IEC 14443 type A
and read/write mode for MIFARE Classic ....... 12
Communication overview for ISO/IEC 14443
B reader/writer .................................................14
Connection scheme for detecting the
different interface types ...................................15
Byte Order for MOSI and MISO ...................... 16
Tab. 7.
Tab. 8.
Tab. 9.
Tab. 10. Byte Order for MOSI and MISO ...................... 16
Tab. 11. Address byte 0 register; address MOSI ...........16
Tab. 12. Timing conditions SPI ..................................... 16
Tab. 13. Settings of BR_T0 and BR_T1 ........................17
Tab. 14. Selectable transfer speeds ..............................18
Tab. 15. UART framing ................................................. 18
Tab. 16. Byte Order to Read Data ................................ 18
Tab. 17. Byte Order to Write Data ................................ 19
Tab. 18. Timing parameter I2CL ................................... 24
Tab. 19. SPI SAM connection ....................................... 26
Tab. 20. Boundary scan command ............................... 26
Tab. 21. Boundary scan path of the MFRC631 .............29
Tab. 22. Settings for TX1 and TX2 ............................... 33
Tab. 23. Setting residual carrier and modulation
index by TXamp.set_residual_carrier ..............33
Tab. 24. Configuration for single or differential
receiver ............................................................36
Tab. 25. Register configuration of MFRC631 active
antenna concept (DIGITAL) ............................ 37
Tab. 26. Register configuration of MFRC631 active
antenna concept (Antenna) .............................37
Tab. 27. EEPROM memory organization ...................... 41
Tab. 28. Production area (Page 0) ................................41
Tab. 29. Product ID overview of CLRC663 family ......... 42
Tab. 30. Configuration area (Page 0) ............................42
Tab. 31. Interface byte .................................................. 42
Tab. 32. Interface bits ....................................................43
Tab. 33. Tx and Rx arrangements in the register set
protocol area ................................................... 43
Tab. 34. Register reset values (Hex.) (Page0) ..............43
Tab. 35. Register reset values (Hex.)(Page1 and
page 2) ............................................................44
Tab. 36. Crystal requirements recommendations ..........45
Tab. 37. Divider values for selected frequencies
using the integerN PLL ................................... 46
Tab. 56. IRQ0 bits ......................................................... 61
Tab. 57. IRQ1 register (address 07h) ............................62
Tab. 58. IRQ1 bits ......................................................... 62
Tab. 59. IRQ0En register (address 08h) ....................... 62
Tab. 60. IRQ0En bits .....................................................63
Tab. 61. IRQ1EN register (address 09h); ......................63
Tab. 62. IRQ1EN bits .................................................... 63
Tab. 63. Error register (address 0Ah) ............................64
Tab. 64. Error bits ..........................................................64
Tab. 65. Status register (address 0Bh) ......................... 65
Tab. 66. Status bits ....................................................... 65
Tab. 67. RxBitCtrl register (address 0Ch); .................... 66
Tab. 68. RxBitCtrl bits ................................................... 66
Tab. 69. RxColl register (address 0Dh); ........................66
Tab. 70. RxColl bits .......................................................67
Tab. 71. TControl register (address 0Eh) ......................67
Tab. 72. TControl bits ....................................................67
Tab. 73. T0Control register (address 0Fh); ................... 68
Tab. 74. T0Control bits ..................................................68
Tab. 75. T0ReloadHi register (address 10h); ................ 69
Tab. 76. T0ReloadHi bits ...............................................69
Tab. 77. T0ReloadLo register (address 11h); ................69
Tab. 78. T0ReloadLo bits .............................................. 69
Tab. 79. T0CounterValHi register (address 12h) ...........69
Tab. 80. T0CounterValHi bits ........................................ 70
Tab. 81. T0CounterValLo register (address 13h) .......... 70
Tab. 82. T0CounterValLo bits ........................................70
Tab. 83. T1Control register (address 14h); ................... 70
Tab. 84. T1Control bits ..................................................70
Tab. 85. T0ReloadHi register (address 15h) ................. 71
Tab. 86. T1ReloadHi bits ...............................................71
Tab. 87. T1ReloadLo register (address 16h) .................71
Tab. 88. T1ReloadValLo bits .........................................71
Tab. 89. T1CounterValHi register (address 17h) ...........72
Tab. 90. T1CounterValHi bits ........................................ 72
Tab. 91. T1CounterValLo register (address 18h) .......... 72
Tab. 92. T1CounterValLo bits ........................................72
Tab. 93. T2Control register (address 19h) .................... 72
Tab. 94. T2Control bits ..................................................72
Tab. 95. T2ReloadHi register (address 1Ah) .................73
Tab. 38. Command set ..................................................49
Tab. 39. Predefined protocol overview RXFor more
protocol details please refer to Section 7
"Functional description". ..................................52
Tab. 40. Predefined protocol overview TXFor more
protocol details please refer to Section 7
"Functional description". ..................................53
Tab. 41. Behavior of register bits and their
designation ...................................................... 55
MFRC631
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High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
Tab. 96. T2Reload bits ..................................................73
Tab. 97. T2ReloadLo register (address 1Bh) ................ 73
Tab. 98. T2ReloadLo bits .............................................. 74
Tab. 99. T2CounterValHi register (address 1Ch) .......... 74
Tab. 100. T2CounterValHi bits ........................................ 74
Tab. 101. T2CounterValLo register (address 1Dh) ..........74
Tab. 102. T2CounterValLo bits ........................................74
Tab. 103. T3Control register (address 1Eh) ....................74
Tab. 104. T3Control bits ..................................................75
Tab. 105. T3ReloadHi register (address 1Fh); ................ 75
Tab. 106. T3ReloadHi bits ...............................................75
Tab. 107. T3ReloadLo register (address 20h) .................75
Tab. 108. T3ReloadLo bits .............................................. 76
Tab. 109. T3CounterValHi register (address 21h) ...........76
Tab. 110. T3CounterValHi bits ........................................ 76
Tab. 111. T3CounterValLo register (address 22h) .......... 76
Tab. 112. T3CounterValLo bits ........................................76
Tab. 113. T4Control register (address 23h) .................... 77
Tab. 114. T4Control bits ..................................................77
Tab. 115. T4ReloadHi register (address 24h) ................. 78
Tab. 116. T4ReloadHi bits ...............................................78
Tab. 117. T4ReloadLo register (address 25h) .................78
Tab. 118. T4ReloadLo bits .............................................. 78
Tab. 119. T4CounterValHi register (address 26h) ...........78
Tab. 120. T4CounterValHi bits ........................................ 78
Tab. 121. T4CounterValLo register (address 27h) .......... 79
Tab. 122. T4CounterValLo bits ........................................79
Tab. 123. DrvMode register (address 28h) ......................79
Tab. 124. DrvMode bits ...................................................79
Tab. 125. TxAmp register (address 29h) .........................80
Tab. 126. TxAmp bits ...................................................... 80
Tab. 127. TxCon register (address 2Ah) .........................80
Tab. 128. TxCon bits .......................................................80
Tab. 129. Txl register (address 2Bh) ...............................81
Tab. 130. Txl bits .............................................................81
Tab. 131. TXCrcPreset register (address 2Ch) ............... 81
Tab. 132. TxCrcPreset bits ..............................................81
Tab. 133. Transmitter CRC preset value configuration ....82
Tab. 134. RxCrcCon register (address 2Dh) ...................82
Tab. 135. RxCrcCon bits .................................................82
Tab. 136. Receiver CRC preset value configuration ....... 82
Tab. 137. TxDataNum register (address 2Eh) .................83
Tab. 138. TxDataNum bits .............................................. 83
Tab. 139. TxDataModWidth register (address 2Fh) ........ 83
Tab. 140. TxDataModWidth bits ......................................84
Tab. 141. TxSym10BurstLen register (address 30h) .......84
Tab. 142. TxSym10BurstLen bits .................................... 84
Tab. 143. TxWaitCtrl register (address 31h); reset
value: C0h .......................................................85
Tab. 154. RxWait bits ......................................................88
Tab. 155. RxThreshold register (address 37h) ................88
Tab. 156. RxThreshold bits ............................................. 88
Tab. 157. Rcv register (address 38h) ..............................88
Tab. 158. Rcv bits ........................................................... 89
Tab. 159. RxAna register (address 39h) ......................... 89
Tab. 160. RxAna bits .......................................................89
Tab. 161. Effect of gain and highpass corner register
settings ............................................................ 90
Tab. 162. SerialSpeed register (address3Bh); reset
value: 7Ah ....................................................... 90
Tab. 163. SerialSpeed bits .............................................. 91
Tab. 164. RS232 speed settings .....................................91
Tab. 165. LFO_Trim register (address 3Ch) ................... 91
Tab. 166. LFO_Trim bits ................................................. 91
Tab. 167. PLL_Ctrl register (address3Dh) .......................92
Tab. 168. PLL_Ctrl register bits .......................................92
Tab. 169. Setting of feedback divider PLLDiv_FB [1:0] ....92
Tab. 170. PLLDiv_Out register (address 3Eh) ................ 92
Tab. 171. PLLDiv_Out bits .............................................. 93
Tab. 172. Setting for the output divider ratio
PLLDiv_Out [7:0] .............................................93
Tab. 173. LPCD_QMin register (address 3Fh) ................93
Tab. 174. LPCD_QMin bits ............................................. 93
Tab. 175. LPCD_QMax register (address 40h) ............... 94
Tab. 176. LPCD_QMax bits ............................................ 94
Tab. 177. LPCD_IMin register (address 41h) ..................94
Tab. 178. LPCD_IMin bits ............................................... 94
Tab. 179. LPCD_Result_I register (address 42h) ............95
Tab. 180. LPCD_I_Result bits .........................................95
Tab. 181. LPCD_Result_Q register (address 43h) ..........95
Tab. 182. LPCD_Q_Result bits ....................................... 95
Tab. 183. LPCD_Options register (address 3Ah) ............95
Tab. 184. LPCD_Options .................................................96
Tab. 185. PinEn register (address 44h) .......................... 96
Tab. 186. PinEn bits ........................................................96
Tab. 187. PinOut register (address 45h) .........................97
Tab. 188. PinOut bits .......................................................97
Tab. 189. PinIn register (address 46h) ............................97
Tab. 190. PinIn bits ......................................................... 97
Tab. 191. SigOut register (address 47h) .........................98
Tab. 192. SigOut bits .......................................................98
Tab. 193. Version register (address 7Fh) ........................98
Tab. 194. Version bits ..................................................... 99
Tab. 195. Limiting values .............................................. 100
Tab. 196. Operating conditions MFRC63102HN ...........101
Tab. 197. Operating conditions MFRC63103HN ...........101
Tab. 198. Thermal characteristics ................................. 102
Tab. 199. Characteristics ...............................................103
Tab. 200. SPI timing characteristics ..............................106
Tab. 201. I2C-bus timing in fast mode and fast mode
plus ................................................................106
Tab. 144. TXWaitCtrl bits ................................................ 85
Tab. 145. TxWaitLo register (address 32h) .....................85
Tab. 146. TxWaitLo bits .................................................. 86
Tab. 147. FrameCon register (address 33h) ................... 86
Tab. 148. FrameCon bits .................................................86
Tab. 149. RxSofD register (address 34h) ........................86
Tab. 150. RxSofD bits ..................................................... 87
Tab. 151. RxCtrl register (address 35h) ..........................87
Tab. 152. RxCtrl bits ........................................................87
Tab. 153. RxWait register (address 36h) ........................ 88
Tab. 202. Protocol Number 00: ISO/IEC14443-A 106 /
MIFARE Classic ............................................ 119
Tab. 203. Protocol Number 01: ISO/IEC14443-A 212/
MIFARE Classic ............................................ 120
Tab. 204. Protocol Number 02: ISO/IEC14443-A 424/
MIFARE Classic ............................................ 120
MFRC631
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MFRC631
High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
Tab. 205. Protocol Number 03: ISO/IEC14443-A 848/
MIFARE Classic ............................................ 121
Tab. 218. JIS X 6319-4 (FeliCa) 212 ............................ 130
Tab. 219. JIS X 6319-4 (FeliCa) 424 ............................ 130
Tab. 220. ISO/IEC15693 SLI 1/4 - SSC- 26 ..................131
Tab. 221. ISO/IEC15693 SLI 1/4 - SSC-53 ...................132
Tab. 222. ISO/IEC15693 SLI 1/256 - DSC ....................132
Tab. 223. EPC/UID - SSC -26 ...................................... 133
Tab. 224. EPC-V2 - 2/424 .............................................133
Tab. 225. EPC-V2 - 4/424 .............................................134
Tab. 226. EPC-V2 - 2/848 .............................................134
Tab. 227. EPC-V2 - 4/848 .............................................135
Tab. 228. Jewel ............................................................. 136
Tab. 229. ISO/IEC14443 - B 106 EMVCo Optimized .... 136
Tab. 230. Abbreviations .................................................138
Tab. 231. Revision history .............................................141
Tab. 206. Protocol Number 04: ISO/IEC14443-B 106 ... 122
Tab. 207. Protocol Number 05: ISO/IEC14443-B 212 ... 123
Tab. 208. Protocol Number 06: ISO/IEC14443-B 424 ... 123
Tab. 209. Protocol Number 07: ISO/IEC14443-B 848 ... 124
Tab. 210. ISO/IEC14443-A 106 / MIFARE Classic ........125
Tab. 211. ISO/IEC14443-A 212/ MIFARE Classic .........126
Tab. 212. ISO/IEC14443-A 424/ MIFARE Classic .........126
Tab. 213. ISO/IEC14443-A 848/ MIFARE Classic .........127
Tab. 214. ISO/IEC14443-B 106 .....................................127
Tab. 215. ISO/IEC14443-B 212 .....................................128
Tab. 216. ISO/IEC14443-B 424 .....................................129
Tab. 217. ISO/IEC14443-B 848 .....................................129
MFRC631
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MFRC631
High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
Figures
Fig. 1.
Fig. 2.
Simplified block diagram of the MFRC631 ........ 5
Pinning configuration HVQFN32
Fig. 20. I2C interface enables convenient MIFARE
SAM integration ...............................................26
Fig. 21. Boundary scan cell path structure ...................28
Fig. 22. General dependences of modulation .............. 32
Fig. 23. Example 1: overshoot_t1 = 2d; overhoot_t2
= 5d. ................................................................34
(SOT617-1) ........................................................6
Detailed block diagram of the MFRC631 ...........8
Read/write mode ............................................. 12
Read/write mode for ISO/IEC 14443 type A
and read/write mode for MIFARE Classic ....... 12
Data coding and framing according to ISO/
IEC 14443 A ................................................... 13
Read/write mode for ISO/IEC 14443 type A
and read/write mode for MIFARE Classic ....... 13
SOF and EOF according to ISO/IEC 14443
B ...................................................................... 14
Connection to host with SPI ............................15
Fig. 3.
Fig. 4.
Fig. 5.
Fig. 24. Example 2: overshoot_t1 = 0d; overhoot_t2
= 5d .................................................................35
Fig. 6.
Fig. 7.
Fig. 8.
Fig. 9.
Fig. 25. Block diagram of receiver circuitry .................. 36
Fig. 26. Block diagram of the active Antenna concept .. 37
Fig. 27. Overview SIGIN/SIGOUT Signal Routing ........39
Fig. 28. Sector arrangement of the EEPROM .............. 41
Fig. 29. Quartz connection ........................................... 45
Fig. 30. Internal PDown to voltage regulator logic ........49
Fig. 31. Pin RX input voltage ..................................... 105
Fig. 32. Timing for fast and standard mode devices
on the I2C-bus .............................................. 107
Fig. 33. Typical application antenna circuit diagram ... 108
Fig. 34. Package outline SOT617-1 (HVQFN32) ........111
Fig. 35. Packing information 1 tray .............................114
Fig. 36. Packing information 5 tray .............................115
Fig. 37. Tray details ....................................................116
Fig. 38. Packing information Reel .............................. 117
Fig. 10. Connection to host with SPI ............................17
Fig. 11. Example for UART Read ................................ 19
Fig. 12. Example diagram for a UART write .................19
Fig. 13. I2C-bus interface .............................................20
Fig. 14. Bit transfer on the I2C-bus. .............................20
Fig. 15. START and STOP conditions ......................... 21
Fig. 16. Acknowledge on the I2C- bus .........................22
Fig. 17. Data transfer on the I2C- bus ......................... 22
Fig. 18. First byte following the START procedure .......22
Fig. 19. Register read and write access .......................24
MFRC631
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MFRC631
High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
Contents
1
2
3
4
5
6
6.1
7
General description ............................................ 1
7.5
Buffer ............................................................... 30
Overview ..........................................................30
Accessing the FIFO buffer ...............................30
Controlling the FIFO buffer ..............................31
Status Information about the FIFO buffer ........ 31
Analog interface and contactless UART .......... 31
General ............................................................ 32
TX transmitter ..................................................32
Overshoot protection ....................................... 34
Bit generator ....................................................35
Receiver circuitry ............................................. 35
General ............................................................ 35
Block diagram ..................................................35
Active antenna concept ................................... 37
Symbol generator ............................................ 40
Memory ............................................................40
Memory overview .............................................40
EEPROM memory organization .......................40
Product information and configuration - Page
Features and benefits .........................................2
Quick reference data .......................................... 3
Ordering information .......................................... 4
Block diagram ..................................................... 5
Pinning information ............................................ 6
Pin description ...................................................6
Functional description ........................................8
Interrupt controller ............................................. 8
Timer module ...................................................10
Timer modes ....................................................10
Time-Out- and Watch-Dog-Counter .................11
Wake-up timer ................................................. 11
Stop watch .......................................................11
Programmable one-shot timer ......................... 11
Periodical trigger ..............................................11
Contactless interface unit ................................ 12
Communication mode for ISO/IEC14443
7.5.1
7.5.2
7.5.3
7.5.4
7.6
7.6.1
7.6.2
7.6.2.1
7.6.2.2
7.6.3
7.6.3.1
7.6.3.2
7.6.4
7.6.5
7.7
7.1
7.2
7.2.1
7.2.1.1
7.2.1.2
7.2.1.3
7.2.1.4
7.2.1.5
7.3
7.7.1
7.7.2
7.7.2.1
7.3.1
type A and for MIFARE Classic .......................12
ISO/IEC14443B functionality ........................... 13
Host interfaces .................................................14
Host interface configuration .............................14
SPI interface ....................................................15
General ............................................................ 15
Read data ........................................................15
Write data ........................................................ 16
Address byte ....................................................16
Timing Specification SPI ..................................16
RS232 interface ...............................................17
Selection of the transfer speeds ......................17
Framing ............................................................18
I2C-bus interface ............................................. 19
General ............................................................ 20
I2C Data validity .............................................. 20
I2C START and STOP conditions ................... 21
I2C byte format ................................................21
I2C Acknowledge .............................................21
I2C 7-bit addressing ........................................ 22
I2C-register write access .................................23
I2C-register read access ................................. 23
I2CL-bus interface ........................................... 24
SAM interface ..................................................25
SAM functionality .............................................25
SAM connection .............................................. 26
Boundary scan interface ..................................26
Interface signals .............................................. 27
Test Clock (TCK) .............................................27
Test Mode Select (TMS) ................................. 27
Test Data Input (TDI) ...................................... 28
Test Data Output (TDO) ..................................28
Data register ....................................................28
Boundary scan cell ..........................................28
Boundary scan path ........................................ 28
Boundary Scan Description Language
7.3.2
7.4
7.4.1
7.4.2
0 .......................................................................41
EEPROM initialization content LoadProtocol ... 43
Clock generation ..............................................45
Crystal oscillator .............................................. 45
IntegerN PLL clock line ................................... 46
Low Frequency Oscillator (LFO) ......................46
Power management .........................................47
Supply concept ................................................ 47
Power reduction mode .....................................47
Power-down .....................................................47
Standby mode ................................................. 48
Modem off mode ............................................. 48
Low-Power Card Detection (LPCD) .................48
Reset and start-up time ...................................48
Command set .................................................. 49
General ............................................................ 49
Command set overview ...................................49
Command functionality .................................... 50
7.7.3
7.8
7.8.1
7.8.2
7.8.3
7.9
7.9.1
7.9.2
7.9.2.1
7.9.2.2
7.9.2.3
7.9.3
7.9.4
7.10
7.4.2.1
7.4.2.2
7.4.2.3
7.4.2.4
7.4.2.5
7.4.3
7.4.3.1
7.4.3.2
7.4.4
7.4.4.1
7.4.4.2
7.4.4.3
7.4.4.4
7.4.4.5
7.4.4.6
7.4.4.7
7.4.4.8
7.4.4.9
7.4.5
7.10.1
7.10.2
7.10.3
7.10.3.1 Idle command ..................................................50
7.10.3.2 LPCD command .............................................. 50
7.10.3.3 Load key command ......................................... 50
7.10.3.4 MFAuthent command ...................................... 51
7.10.3.5 Receive command ...........................................51
7.10.3.6 Transmit command ..........................................51
7.10.3.7 Transceive command ...................................... 51
7.10.3.8 WriteE2 command ........................................... 52
7.10.3.9 WriteE2PAGE command ................................. 52
7.10.3.10 ReadE2 command ...........................................52
7.10.3.11 LoadReg command ......................................... 52
7.10.3.12 LoadProtocol command ...................................52
7.10.3.13 LoadKeyE2 command ..................................... 53
7.10.3.14 StoreKeyE2 command .....................................53
7.10.3.15 GetRNR command .......................................... 54
7.10.3.16 SoftReset command ........................................ 54
7.4.5.1
7.4.5.2
7.4.6
7.4.6.1
7.4.6.2
7.4.6.3
7.4.6.4
7.4.6.5
7.4.6.6
7.4.6.7
7.4.6.8
7.4.6.9
8
8.1
8.2
MFRC631 registers ............................................55
Register bit behavior ....................................... 55
MFRC631 registers overview .......................... 55
(BSDL) ............................................................. 29
7.4.6.10 Non-IEEE1149.1 commands ........................... 30
MFRC631
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 4.5 — 12 September 2018
227445
148 / 149
NXP Semiconductors
MFRC631
High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus
8.3
8.3.1
8.4
8.4.1
8.5
Command configuration ...................................57
8.11.2
8.11.3
8.11.4
8.11.5
8.12
TxDATAModWidth ........................................... 83
TxSym10BurstLen ........................................... 84
TxWaitCtrl ........................................................ 85
TxWaitLo ..........................................................85
FrameCon ........................................................86
Receiver configuration registers ...................... 86
RxSofD .............................................................86
RxCtrl ...............................................................87
RxWait ............................................................. 88
RxThreshold .....................................................88
Rcv ...................................................................88
RxAna .............................................................. 89
Clock configuration .......................................... 90
SerialSpeed ..................................................... 90
LFO_Trimm ......................................................91
PLL_Ctrl Register ............................................ 91
PLLDiv_Out ......................................................92
Low-power card detection configuration
registers ........................................................... 93
LPCD_QMin .....................................................93
LPCD_QMax ....................................................94
LPCD_IMin .......................................................94
LPCD_Result_I ................................................ 95
LPCD_Result_Q .............................................. 95
LPCD_Options .................................................95
Pin configuration ..............................................96
PinEn ............................................................... 96
PinOut ..............................................................97
PinIn .................................................................97
SigOut ..............................................................98
Version register ............................................... 98
Version .............................................................98
Limiting values ................................................100
Recommended operating conditions ............ 101
Thermal characteristics ..................................102
Characteristics ................................................ 103
Timing characteristics ....................................106
Application information ..................................108
Antenna design description ........................... 108
EMC low pass filter ....................................... 108
Antenna matching ..........................................109
Receiving circuit .............................................109
Antenna coil ...................................................109
Package outline ...............................................111
Handling information ...................................... 113
Packing information ........................................114
Appendix ..........................................................119
LoadProtocol command register initialization . 119
MFRC63103 EEPROM configuration ............ 125
Abbreviations .................................................. 138
References .......................................................140
Revision history .............................................. 141
Legal information ............................................142
Command ........................................................ 57
SAM configuration register .............................. 58
HostCtrl ............................................................58
FIFO configuration register ..............................59
FIFOControl ..................................................... 59
WaterLevel .......................................................59
FIFOLength ......................................................60
FIFOData ......................................................... 60
Interrupt configuration registers .......................61
IRQ0 register ................................................... 61
IRQ1 register ................................................... 62
IRQ0En register ...............................................62
IRQ1En ............................................................ 63
Contactless interface configuration registers ... 64
Error .................................................................64
Status ...............................................................65
RxBitCtrl ...........................................................66
RxColl .............................................................. 66
Timer configuration registers ........................... 67
TControl ........................................................... 67
T0Control ......................................................... 68
T0ReloadHi ......................................................69
T0ReloadLo ..................................................... 69
T0CounterValHi ............................................... 69
T0CounterValLo ...............................................70
T1Control ......................................................... 70
T1ReloadHi ......................................................71
T1ReloadLo ..................................................... 71
T1CounterValHi ............................................... 71
T1CounterValLo ...............................................72
8.5.1
8.5.2
8.5.3
8.5.4
8.6
8.6.1
8.6.2
8.6.3
8.6.4
8.7
8.7.1
8.7.2
8.7.3
8.7.4
8.8
8.8.1
8.8.2
8.8.2.1
8.8.2.2
8.8.2.3
8.8.2.4
8.8.2.5
8.8.2.6
8.8.2.7
8.8.2.8
8.8.2.9
8.13
8.13.1
8.13.2
8.13.3
8.13.4
8.13.5
8.13.6
8.14
8.14.1
8.14.2
8.14.3
8.14.4
8.15
8.15.1
8.15.2
8.15.3
8.15.4
8.15.5
8.15.6
8.16
8.16.1
8.16.2
8.16.3
8.16.4
8.17
8.17.1
9
10
11
12
12.1
13
13.1
13.1.1
13.1.2
13.1.3
13.1.4
14
8.8.2.10 T2Control ......................................................... 72
8.8.2.11 T2ReloadHi ......................................................73
8.8.2.12 T2ReloadLo ..................................................... 73
8.8.2.13 T2CounterValHi ............................................... 74
8.8.2.14 T2CounterValLoReg ........................................ 74
8.8.2.15 T3Control ......................................................... 74
8.8.2.16 T3ReloadHi ......................................................75
8.8.2.17 T3ReloadLo ..................................................... 75
8.8.2.18 T3CounterValHi ............................................... 76
8.8.2.19 T3CounterValLo ...............................................76
8.8.2.20 T4Control ......................................................... 77
8.8.2.21 T4ReloadHi ......................................................77
8.8.2.22 T4ReloadLo ..................................................... 78
8.8.2.23 T4CounterValHi ............................................... 78
8.8.2.24 T4CounterValLo ...............................................79
15
16
17
17.1
17.2
18
19
20
8.9
Transmitter configuration registers .................. 79
TxMode ............................................................79
TxAmp ..............................................................79
TxCon .............................................................. 80
Txl .................................................................... 81
CRC configuration registers .............................81
TxCrcPreset .....................................................81
RxCrcCon ........................................................ 82
Transmitter configuration registers .................. 83
TxDataNum ......................................................83
8.9.1
8.9.2
8.9.3
8.9.4
8.10
8.10.1
8.10.2
8.11
21
8.11.1
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© NXP B.V. 2018.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 12 September 2018
Document identifier: MFRC631
Document number: 227445
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