MCZ33905CD5EK,574 [NXP]
Power Supply Management Circuit, Adjustable, 1 Channel, MOS, PDSO54;
| 型号： | MCZ33905CD5EK,574 |
| 厂家： | 
NXP |
| 描述： | Power Supply Management Circuit, Adjustable, 1 Channel, MOS, PDSO54 光电二极管 |
| 文件： | 总107页 (文件大小：2814K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MC33903_4_5
Rev. 14.0, 2/2018
NXP Semiconductors
Data Sheet: Advance Information
SBC Gen2 with CAN high speed and
LIN interface
33903/4/5
The 33903/4/5 is the second generation family of the System Basis Chip (SBC).
It combines several features and enhances present module designs. The device
works as an advanced power management unit for the MCU with additional
integrated circuits such as sensors and CAN transceivers. It has a built-in
enhanced high-speed CAN interface (ISO11898-2 and -5) with local and bus
failure diagnostics, protection, and fail-safe operation modes. The SBC may
include zero, one or two LIN 2.1 interfaces with LIN output pin switches. It
includes up to four wake-up input pins that can also be configured as output
drivers for flexibility. This device is powered by SMARTMOS technology.
SYSTEM BASIS CHIP
This device implements multiple Low-power (LP) modes, with very low-current
consumption. In addition, the device is part of a family concept where pin
compatibility adds versatility to module design.
EK Suffix (Pb-free)
98ASA10506D
54-PIN SOIC
EK Suffix (Pb-free)
98ASA10556D
32-PIN SOIC
The 33903/4/5 also implements an innovative and advanced fail-safe state
machine and concept solution.
Applications
• Aircraft and marine systems
• Automotive and robotic systems
• Farm equipment
Features
• Voltage regulator for MCU, 5.0 or 3.3 V, part number selectable, with
possibility of usage external PNP to extend current capability and share power
dissipation
• Voltage, current, and temperature protection
• Industrial actuator controls
• Extremely low quiescent current in LP modes
• Lamp and inductive load controls
• DC motor control applications requiring diagnostics
• Applications where high-side switch control is
required
• Fully-protected embedded 5.0 V regulator for the CAN driver
• Multiple undervoltage detections to address various MCU specifications and
system operation modes (i.e. cranking)
• Auxiliary 5.0 or 3.3 V SPI configurable regulator, for additional ICs, with
overcurrent detection and undervoltage protection
• MUX output pin for device internal analog signal monitoring and power supply
monitoring
• Advanced SPI, MCU, ECU power supply, and critical pins diagnostics and
monitoring.
• Multiple wake-up sources in LP modes: CAN or LIN bus, I/O transition,
automatic timer, SPI message, and VDD overcurrent detection.
• ISO11898-5 high-speed CAN interface compatibility for baud rates of 40 kb/s
to 1.0 Mb/s
• Scalable product family of devices ranging from 0 to 2 LINs which are
compatible to J2602-2 and LIN 2.1
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© NXP B.V. 2018.
Table of Contents
1. Simplified application diagrams ..................................................................................................................................................... 3
2. Orderable part ................................................................................................................................................................................ 7
3. Internal block diagrams .................................................................................................................................................................. 9
4. Pin Connections ........................................................................................................................................................................... 11
4.1. Pinout diagram ....................................................................................................................................................................... 11
5. Electrical characteristics .............................................................................................................................................................. 16
5.1. Maximum ratings .................................................................................................................................................................... 16
5.2. Static electrical characteristics ............................................................................................................................................... 18
5.3. Dynamic electrical characteristics .......................................................................................................................................... 26
5.4. Timing diagrams .................................................................................................................................................................... 29
6. Functional description .................................................................................................................................................................. 32
6.1. Introduction ............................................................................................................................................................................ 32
6.2. Functional pin description ...................................................................................................................................................... 32
7. Functional device operation ......................................................................................................................................................... 36
7.1. Mode and state description .................................................................................................................................................... 36
7.2. LP modes ............................................................................................................................................................................... 37
7.3. State diagram ......................................................................................................................................................................... 39
7.4. Mode change ......................................................................................................................................................................... 40
7.5. Watchdog operation ............................................................................................................................................................... 40
7.6. Functional block operation versus mode ............................................................................................................................... 43
7.7. Illustration of device mode transitions .................................................................................................................................... 44
7.8. Cyclic sense operation during LP modes ............................................................................................................................... 45
7.9. Cyclic INT operation during LP VDD on mode ....................................................................................................................... 47
7.10. Behavior at power up and power down ................................................................................................................................ 48
7.11. Fail-safe operation ............................................................................................................................................................... 51
8. CAN interface .............................................................................................................................................................................. 55
8.1. CAN interface description ...................................................................................................................................................... 55
8.2. CAN bus fault diagnostic ........................................................................................................................................................ 58
9. LIN block ...................................................................................................................................................................................... 62
9.1. LIN interface description ........................................................................................................................................................ 62
9.2. LIN operational modes ........................................................................................................................................................... 63
10. Serial peripheral interface .......................................................................................................................................................... 64
10.1. High level overview .............................................................................................................................................................. 64
10.2. Detail operation .................................................................................................................................................................... 64
10.3. Detail of control bits and register mapping ........................................................................................................................... 68
10.4. Flags and device status ....................................................................................................................................................... 84
11. Typical applications ................................................................................................................................................................... 92
12. Packaging ................................................................................................................................................................................ 100
12.1. SOIC 32 package dimensions ........................................................................................................................................... 100
12.2. SOIC 54 package dimensions ........................................................................................................................................... 103
13. Revision history ....................................................................................................................................................................... 106
33903/4/5
2
NXP Semiconductors
SIMPLIFIED APPLICATION DIAGRAMS
1
Simplified application diagrams
* = Optional
33905D
VBAT
(5.0 V/3.3 V)
Q1*
D1
Q2
VCAUX VAUX
VSUP1 VE VB
V
BAUX
SUP2
VDD
VDD
V
RST
INT
SAFE
DBG
GND
MOSI
SCLK
MISO
VSENSE
SPI
MCU
I/O-0
CS
A/D
MUX-OUT
I/O-1
5V-CAN
TXD
CANH
SPLIT
RXD
TXD-L1
RXD-L1
TXD-L2
RXD-L2
CAN Bus
LIN Bus
LIN Bus
CANL
LIN-TERM 1
LIN-1
LIN-TERM 2
LIN-2
Figure 1. 33905D simplified application diagram
* = Optional
33905S
VBAT
(5.0 V/3.3 V)
D1
Q2
Q1*
VSUP1
VE VB
VAUX
V
V
BAUX
SUP2
VCAUX
VDD
DD
V
RST
INT
SAFE
DBG
GND
MOSI
SCLK
MISO
VSENSE
SPI
MCU
I/O-0
CS
A/D
MUX-OUT
I/O-1
5V-CAN
TXD
CANH
SPLIT
RXD
TXD-L
RXD-L
CAN Bus
LIN Bus
CANL
LIN-T
VBAT
LIN
I/O-3
Figure 2. 33905S simplified application diagram
33903/4/5
NXP Semiconductors
3
SIMPLIFIED APPLICATION DIAGRAMS
33904
VBAT
* = Optional
(5.0 V/3.3 V)
Q1*
D1
Q2
VCAUX VAUX
VSUP1 VE VB
V
BAUX
SUP2
VDD
VDD
V
RST
INT
SAFE
DBG
GND
MOSI
SCLK
MISO
VSENSE
SPI
MCU
I/O-0
CS
A/D
MUX-OUT
5V-CAN
I/O-1
CANH
TXD
SPLIT
CANL
VBAT
RXD
CAN Bus
I/O-2
I/O-3
Figure 3. 33904 simplified application diagram
33903
VBAT
D1
VDD
VDD
VSUP1 VSUP2
DBG
RST
INT
SAFE
GND
MOSI
SCLK
MISO
CS
SPI
MCU
I/O-0
5V-CAN
CANH
SPLIT
CANL
TXD
CAN Bus
RXD
Figure 4. 33903 simplified application diagram
33903/4/5
4
NXP Semiconductors
SIMPLIFIED APPLICATION DIAGRAMS
33903D
VBAT
D1
* = Optional
Q1*
VSUP
VE VB
VDD
VDD
RST
INT
SAFE
DBG
GND
MOSI
SCLK
MISO
VSENSE
SPI
MCU
IO-0
CS
A/D
MUX-OUT
CANH
SPLIT
5V-CAN
TXD
CANL
RXD
TXD-L1
RXD-L1
TXD-L2
RXD-L2
LIN-T1/I/O-2
CAN Bus
LIN Bus
LIN-1
LIN-T2/IO-3
LIN Bus
LIN-2
Figure 5. 33903D simplified application diagram
33903S
VBAT
D1
* = Optional
VDD
Q1*
VSUP
VE VB
VDD
RST
INT
SAFE
DBG
GND
MOSI
SCLK
MISO
VSENSE
SPI
MCU
IO-0
CS
A/D
MUX-OUT
CANH
SPLIT
5V-CAN
TXD
CANL
RXD
TXD-L1
RXD-L1
LIN-T1/I/O-2
VBAT
CAN Bus
LIN Bus
LIN-1
I/O-3
Figure 6. 33903S simplified application diagram
33903/4/5
NXP Semiconductors
5
SIMPLIFIED APPLICATION DIAGRAMS
33903P
VBAT
D1
* = Optional
VDD
Q1*
VSUP
VE VB
VDD
RST
INT
SAFE
DBG
GND
MOSI
SCLK
MISO
VSENSE
SPI
MCU
IO-0
CS
A/D
MUX-OUT
5V-CAN
CANH
SPLIT
CANL
CAN Bus
VBAT
TXD
RXD
VBAT
I/O-2
I/O-3
Figure 7. 33903P simplified application diagram
33903/4/5
6
NXP Semiconductors
ORDERABLE PART
2
Orderable part
Table 1. MC33905 orderable part variations - (all devices rated at TA = -40 °C TO 125 °C)
Version
(1), (2), (3)
VDD output
voltage
LIN
interface(s)
Wake-up input / LIN master
termination
VAUX VSENSE
NXP part number
Package
MUX
MC33905D (Dual LIN)
MCZ33905BD3EK/R2
MCZ33905CD3EK/R2
MCZ33905DD3EK/R2
MCZ33905D5EK/R2
MCZ33905BD5EK/R2
MCZ33905CD5EK/R2
MCZ33905DD5EK/R2
MC33905S (Single LIN)
MCZ33905BS3EK/R2
MCZ33905CS3EK/R2
MCZ33905DS3EK/R2
MCZ33905S5EK/R2
MCZ33905BS5EK/R2
MCZ33905CS5EK/R2
MCZ33905DS5EK/R2
B
C
D
3.3 V
5.0 V
2 Wake-up + 2 LIN terms
or
SOIC 54-pin
exposed pad
2
3 Wake-up + 1 LIN terms
or
4 Wake-up + no LIN terms
Yes
Yes
Yes
B
C
D
B
C
D
3.3 V
5.0 V
3 Wake-up + 1 LIN terms
SOIC 32-pin
exposed pad
1
Yes
Yes
Yes
or
4 Wake-up + no LIN terms
B
C
D
Notes
1. Design changes in the ‘B’ version resolved V
slow ramp up issues, enhanced device current consumption and improved oscillator stability. ‘B’
SUP
version has an errata linked to the SPI operation.
2. Design changes in the ‘C’ version resolve the SPI deviation of all prior versions, and does not have the RxD short to ground detection feature.
3. ’C’ versions are no longer recommended for new design.
’D’ versions are recommended for new design, and include quality improvement, and has no electrical parameters specification changes.
Table 2. MC33904 orderable part variations - (all devices rated at TA = -40 °C TO 125 °C)
Version
(4), (5), (6)
VDD output
voltage
LIN
interface(s)
Wake-up input / LIN master
termination
VAUX VSENSE
NXP part number
MC33904
Package
MUX
MCZ33904B3EK/R2
MCZ33904C3EK/R2
MCZ33904D3EK/R2
MCZ33904A5EK/R2
MCZ33904B5EK/R2
MCZ33904C5EK/R2
MCZ33904D5EK/R2
B
C
D
A
B
C
D
3.3 V
5.0 V
SOIC 32 pin
exposed pad
0
4 Wake-up
Yes
Yes
Yes
Notes
4. Design changes in the “B” version resolved V
slow ramp up issues, enhanced device current consumption and improved oscillator stability.
SUP
‘B’ version has an errata linked to the SPI operation.
5. Design changes in the “C” version resolve the SPI deviation of all prior versions, and does not have the RxD short to ground detection feature.
6. ’C’ versions are no longer recommended for new design.
’D’ versions are recommended for new design, and include quality improvement, and has no electrical parameters specification changes.
33903/4/5
NXP Semiconductors
7
ORDERABLE PART
Table 3. MC33903 orderable part variations - (all devices rated at TA = -40 °C TO 125 °C)
Version
(8), (9), (10)
VDD output
voltage
LIN
interface(s)
Wake-up input / LIN master
termination
VAUX VSENSE
NXP part number
MC33903
Package
MUX
MCZ33903B3EK/R2
MCZ33903C3EK/R2
MCZ33903D3EK/R2
MCZ33903B5EK/R2
MCZ33903C5EK/R2
MCZ33903D5EK/R2
MC33903D (Dual LIN)
MCZ33903BD3EK/R2
MCZ33903CD3EK/R2
MCZ33903DD3EK/R2
MCZ33903BD5EK/R2
MCZ33903CD5EK/R2
MCZ33903DD5EK/R2
MC33903S (Single LIN)
MCZ33903BS3EK/R2
MCZ33903CS3EK/R2
MCZ33903DS3EK/R2
MCZ33903BS5EK/R2
MCZ33903CS5EK/R2
MCZ33903DS5EK/R2
MC33903P
B
C
D
B
C
D
3.3 V(7)
5.0 V(7)
SOIC 32 pin
exposed pad
0
1 Wake-up
No
No
No
B
C
D
B
C
D
3.3 V
5.0 V
1 Wake-up + 2 LIN terms
or
SOIC 32 pin
exposed pad
2
2 Wake-up + 1 LIN terms
or
3 Wake-up + no LIN terms
No
Yes
Yes
B
C
D
B
C
D
3.3 V
5.0 V
2 Wake-up + 1 LIN terms
or
3 Wake-up + no LIN terms
SOIC 32 pin
exposed pad
1
No
Yes
Yes
Yes
Yes
MCZ33903CP5EK/R2
MCZ33903DP5EK/R2
MCZ33903CP3EK/R2
MCZ33903DP3EK/R2
C
D
C
D
5.0 V
3.3 V
SOIC 32 pin
exposed pad
0
3 Wake-up
No
Notes
7. VDD does not allow usage of an external PNP on the 33903.
8. Design changes in the ‘B’ version resolved V slow ramp up issues, enhanced device current consumption and improved oscillator stability. ‘B’
SUP
version has an errata linked to the SPI operation.
9. Design changes in the “C” version resolve the SPI deviation of all prior versions, and does not have the RxD short to ground detection feature.
10. ’C’ versions are no longer recommended for new design.
’D’ versions are recommended for new design, and include quality improvement, and has no electrical parameters specification changes.
33903/4/5
8
NXP Semiconductors
INTERNAL BLOCK DIAGRAMS
3
Internal block diagrams
VBAUX VCAUX
VSUP1
VBAUX VCAUX
VSUP1
VAUX
VE
VB
VAUX
VE
VB
5 V Auxiliary
Regulator
5 V Auxiliary
Regulator
VSUP2
SAFE
VDD
VSUP2
VDD
VDD Regulator
VDD Regulator
V
S2-INT
V
S2-INT
RST
INT
RST
INT
SAFE
Fail-safe
Fail-safe
Power Management
State Machine
Power Management
State Machine
DBG
GND
DBG
GND
MOSI
SCLK
MOSI
SCLK
Oscillator
Oscillator
SPI
SPI
MISO
CS
MISO
CS
VSENSE
VSENSE
Analog Monitoring
Analog Monitoring
Signals Condition & Analog MUX
MUX-OUT
5 V-CAN
Signals Condition & Analog MUX
MUX-OUT
5 V-CAN
V
V
S2-INT
S2-INT
I/O-0
I/O-1
I/O-3
I/O-0
I/O-1
Configurable
5 V-CAN
Input-Output
Regulator
5 V-CAN
Configurable
Regulator
Input-Output
CANH
SPLIT
CANL
CANH
SPLIT
CANL
Enhanced High Speed CAN
Physical Interface
TXD
Enhanced High Speed CAN
Physical Interface
TXD
RXD
RXD
V
V
S2-INT
S2-INT
TXD-L1
RXD-L1
TXD-L
RXD-L
LIN Term #1
LIN Term #1
LIN-T1
LIN1
LIN 2.1 Interface - #1
LIN 2.1 Interface - #2
LIN-T
LIN
LIN 2.1 Interface - #1
V
S2-INT
TXD-L2
RXD-L2
33905S
LIN Term #2
LIN-T2
LIN2
33905D
Figure 8. 33905 internal block diagram
VBAUX VCAUX
VSUP1
VAUX
VE
VB
5 V Auxiliary
Regulator
VDD
VDD Regulator
VSUP2
SAFE
V
S2-INT
RST
INT
Fail-safe
Power Management
State Machine
DBG
GND
MOSI
SCLK
Oscillator
SPI
MISO
CS
VSENSE
Analog Monitoring
Signals Condition & Analog MUX
MUX-OUT
5 V-CAN
V
I/O-0
I/O-1
I/O-2
I/O-3
S2-INT
Configurable
Input-Output
5 V-CAN
Regulator
CANH
SPLIT
CANL
Enhanced High Speed CAN
Physical Interface
TXD
RXD
Figure 9. 33904 internal block diagram
33903/4/5
NXP Semiconductors
9
INTERNAL BLOCK DIAGRAMS
VSUP
VE
VB
VSUP1
VDD Regulator
VDD
VSUP2
SAFE
VDD
VDD Regulator
V
S-INT
V
RST
INT
S2-INT
RST
INT
SAFE
Fail-safe
Power Management
State Machine
MOSI
SCLK
Power Management
State Machine
DBG
GND
MOSI
SCLK
DBG
GND
SPI
MISO
CS
Oscillator
SPI
Oscillator
MISO
CS
V
VSENSE
S2-INT
Analog Monitoring
Signals Condition & Analog MUX
Configurable
Input-Output
5 V-CAN
5 V-CAN
I/O-0
Regulator
MUX-OUT
5 V-CAN
CANH
SPLIT
CANL
V
S-INT
Enhanced High Speed CAN
Physical Interface
TXD
I/O-0
I/O-2
5 V-CAN
Regulator
RXD
Configurable
Input-Output
I/O-3
33903
CANH
SPLIT
CANL
Enhanced High Speed CAN
Physical Interface
TXD
RXD
VSUP
VE
VB
33903P
VDD
VSUP
VE
VDD Regulator
Fail-safe
VB
V
S-INT
RST
INT
SAFE
VDD
VDD Regulator
V
S-INT
Power Management
State Machine
DBG
GND
MOSI
SCLK
RST
INT
SAFE
Oscillator
SPI
Fail-safe
MISO
CS
Power Management
State Machine
DBG
GND
VSENSE
MOSI
SCLK
Analog Monitoring
Signals Condition & Analog MUX
Oscillator
SPI
MUX-OUT
5 V-CAN
MISO
CS
VSENSE
Analog Monitoring
Signals Condition & Analog MUX
V
S-INT
Configurable
Input-Output
5 V-CAN
Regulator
IO-0
MUX-OUT
5 V-CAN
V
S-INT
CANH
SPLIT
CANL
I/O-0
I/O-3
Enhanced High-speed CAN
Physical Interface
TXD
5 V-CAN
Regulator
Configurable
Input-Output
RXD
V
S-INT
CANH
SPLIT
CANL
TXD-L1
RXD-L1
Enhanced High Speed CAN
Physical Interface
TXD
LIN Term #1
LIN Term #2
LIN-T1
LIN1
LIN 2.1 Interface - #1
LIN 2.1 Interface - #2
RXD
V
S-INT
V
S-INT
TXD-L2
RXD-L2
TXD-L
LIN-T2
LIN2
LIN Term #1
LIN-T
LIN
LIN 2.1 Interface - #1
RXD-L
33903D
33903S
Figure 10. 33903 internal block diagram
33903/4/5
10
NXP Semiconductors
PIN CONNECTIONS
4
Pin Connections
Pinout diagram
MC33905D
4.1
MC33905S
1
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
1
32
NC
NC
NC
NC
NC
VB
VE
VSUP1
2
2
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSUP2
I/O-3
LIN-T/I/O-2
3
3
RXD
TXD
VDD
MISO
NC
VB
VE
4
4
VSUP1
5
5
SAFE
5V-CAN
CANH
VSUP2
LIN-T2/I/O-3
LIN-T1/I/O-2
6
6
RXD
7
7
TXD
VDD
MISO
MOSI
SCLK
CS
MOSI
SCLK
CS
INT
RST
8
CANL
8
SAFE
5V-CAN
CANH
GROUND
9
9
GND CAN
SPLIT
V-BAUX
V-CAUX
10
11
12
13
14
15
16
17
18
19
20
21
22
10
11
12
13
14
15
16
CANL
GND CAN
SPLIT
V-BAUX
V-CAUX
I/O-1
V-AUX
MUX-OUT
INT
VSENSE
RXD-L
TXD-L
LIN
GROUND
RST
I/O-0
DBG
I/O-1
V-AUX
MUX-OUT
VSENSE
RXD-L1
TXD-L1
LIN-1
NC
38
37
GND - LEAD FRAME
32 pin exposed package
I/O-0
DBG
NC
36
35
34
33
32
31
30
29
28
NC
NC
NC
NC
NC
TXD-L2
GND
RXD-L2
LIN-2
NC
23
24
GND
25
26
27
NC
NC
NC
GND - LEAD FRAME
54 pin exposed package
MC33904
MC33903
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VB
VE
VSUP1
VSUP1
VSUP2
NC
NC
NC
RXD
TXD
VDD
MISO
2
2
VSUP2
I/O-3
I/O-2
SAFE
5V-CAN
CANH
3
3
RXD
TXD
VDD
MISO
4
4
NC
5
5
SAFE
5V-CAN
CANH
6
6
7
7
MOSI
SCLK
CS
INT
RST
I/O-1
MOSI
SCLK
CS
INT
RST
NC
CANL
8
CANL
8
GROUND
GROUND
9
9
GND CAN
SPLIT
V-BAUX
V-CAUX
GND CAN
SPLIT
10
11
12
13
14
15
16
10
11
12
13
14
15
16
NC
NC
NC
NC
I/O-0
DBG
V-AUX
MUX-OUT
I/O-0
NC
VSENSE
NC
NC
NC
NC
NC
DBG
NC
GND - LEAD FRAME
32 pin exposed package
GND - LEAD FRAME
32 pin exposed package
Note: MC33905D, MC33905S, MC33904 and MC33903 are footprint compatible,
Figure 11. 33905D, MC33905S, MC33904 and MC33903 pin connections
33903/4/5
NXP Semiconductors
11
PIN CONNECTIONS
MC33903D
MC33903S
VE
VE
1
32
1
32
VB
VSUP
VB
VSUP
2
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
2
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
RXD
TXD
VDD
MISO
RXD
TXD
VDD
MISO
3
3
LIN-T2 / I/O-3
LIN-T1 / I/O-2
I/O-3
LIN-T / I/O-2
4
4
5
5
SAFE
5V-CAN
CANH
SAFE
5V-CAN
CANH
6
6
MOSI
SCLK
CS
INT
RST
VSENSE
RXD-L1
TXD-L1
LIN1
MOSI
SCLK
CS
INT
RST
VSENSE
RXD-L
TXD-L
LIN
7
7
CANL
8
CANL
8
GROUND
GROUND
9
9
GND CAN
SPLIT
GND CAN
SPLIT
10
11
12
13
14
15
16
10
11
12
13
14
15
16
MUX-OUT
IO-0
MUX-OUT
I/O-0
DBG
NC
DBG
TXD-L2
GND
GND
GND
GND
NC
LIN2
NC
RXD-L2
GND - LEAD FRAME
32 pin exposed package
GND - LEAD FRAME
32 pin exposed package
MC33903P
VE
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VB
VSUP
I/O-3
2
RXD
TXD
VDD
MISO
3
4
I/O-2
5
SAFE
5V-CAN
CANH
6
MOSI
SCLK
CS
INT
RST
7
CANL
8
GROUND
9
GND CAN
SPLIT
10
11
12
13
14
15
16
VSENSE
N/C
MUX-OUT
I/O-0
DBG
NC
N/C
N/C
GND
NC
GND
NC
GND - LEAD FRAME
32 pin exposed package
Note: MC33903D, MC33903S, and MC33903P are footprint compatible.
Figure 12. 33905D, MC33905S, MC33904 and MC33903 pin connections
33903/4/5
12
NXP Semiconductors
PIN CONNECTIONS
4.2
Pin definitions
A functional description of each pin can be found in the Functional pin description section beginning on page 32.
Table 4. 33903/4/5 pin definitions
54 Pin 32 Pin 32 Pin 32 Pin 32 Pin 32 Pin 32 Pin
33905D 33905S 33904 33903 33903D 33903S 33903P
Pin
Function
Formal
Name
Pin Name
Definition
1-3, 20-
22, 27-
30, 32-
35, 52-
54
3-4,11-
17, 18, 14, 17-
No
Connect
N/A
N/A
1
N/A
N/A
2
N/A
N/A
N/C
-
Connect to GND.
19
21, 31,
32
14, 16,
17, 19-
21
14, 16,
17
No
Connect
Do NOT connect the N/C pins to GND. Leave
these pins Open.
N/A
N/A
N/A
1
N/C
Supply input for the device internal supplies,
power on reset circuitry and the VDD regulator.
VSUP and VSUP1 supplies are internally
connected on part number MC33903BDEK and
MC33903BSEK
Battery
Voltage
Supply 1
4
1
2
2
2
VSUP/1
Power
Power
Supply input for 5 V-CAN regulator, VAUX
regulator, I/O and LIN pins. VSUP1 and VSUP2
supplies are internally connected on part
number MC33903BDEK and MC33903BSEK
Battery
Voltage
Supply 2
5
2
2
N/A
N/A
N/A
VSUP2
33903D and 33905D - Output pin for the LIN2
master node termination resistor.
or
33903P, 33903S, 33903D, 33904, 33905S and
33905D - Configurable pin as an input or HS
output, for connection to external circuitry
(switched or small load). The input can be used
LIN
Termination 2
Output
or
Input/
LIN-T2
or
I/O-3
6
3
3
N/A
3
3
3
or
Input/Output as a programmable Wake-up input in (LP)
Output
3
mode. When used as a HS, no
overtemperature protection is implemented. A
basic short to GND protection function, based
on switch drain-source overvoltage detection, is
available.
33905D - Output pin for the LIN1 master node
termination resistor.
or
LIN-T1
or
33903P, 33903S, 33903D, 33904, 33905S and
33905D - Configurable pin as an input or HS
output, for connection to external circuitry
(switched or small load). The input can be used
as a programmable Wake-up input in (LP)
mode. When used as a HS, no
overtemperature protection is implemented. A
basic short to GND protection function, based
on switch drain-source overvoltage detection, is
available.
LIN
Termination
Output
or
LIN-T
or
1
or
7
4
4
N/A
4
4
4
Input/
Output
Input/Output
2
I/O-2
Output of the safe circuitry. The pin is asserted
Safe Output LOW if a fault event occurs (e.g.: software
(Active LOW) watchdog is not triggered, VDD low, issue on the
RST pin, etc.). Open drain structure.
8
9
5
6
5
6
5
6
5
6
5
6
5
6
SAFE
Output
Output
Output voltage for the embedded CAN
5 V-CAN
5V-CAN
interface. A capacitor must be connected to this
pin.
10
11
12
7
8
9
7
8
9
7
8
9
7
8
9
7
8
9
7
8
9
CANH
CANL
Output
Output
CAN High
CAN Low
GND-CAN
CAN high output.
CAN low output.
GND-CAN Ground
SPLIT Output SPLIT Output
Power GND of the embedded CAN interface
Output pin for connection to the middle point of
the split CAN termination
13
10
10
10
10
10
10
33903/4/5
NXP Semiconductors
13
PIN CONNECTIONS
Table 4. 33903/4/5 pin definitions (continued)
54 Pin 32 Pin 32 Pin 32 Pin 32 Pin 32 Pin 32 Pin
33905D 33905S 33904 33903 33903D 33903S 33903P
Pin
Function
Formal
Name
Pin Name
Definition
Output pin for external path PNP transistor
base
14
15
16
11
12
13
11
12
13
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
VBAUX
VCAUX
VAUX
Output
Output
Output
VB Auxiliary
VCOLLECT Output pin for external path PNP transistor
OR Auxiliary collector
VOUT
Output pin for the auxiliary voltage.
Auxiliary
Multiplexed output to be connected to an MCU
A/D input. Selection of the analog parameter
Multiplex
Output
available at MUX-OUT is done via the SPI. A
switchable internal pull-down resistor is
integrated for VDD current sense
measurements.
17
14
14
N/A
11
12
11
12
11
12
MUX-OUT
Output
Configurable pin as an input or output, for
connection to external circuitry (switched or
small load). The voltage level can be read by
Input/
Output
Input/Output the SPI and via the MUX output pin. The input
18
19
15
16
15
16
15
16
I/O-0
DBG
0
can be used as a programmable Wake-up input
in LP mode. In LP, when used as an output, the
High-side (HS) or Low-side (LS) can be
activated for a cyclic sense function.
Input to activate the Debug mode. In Debug
mode, no watchdog refresh is necessary.
Outside of Debug mode, connection of a
resistor between DBG and GND allows the
selection of Safe mode functionality.
13
14
13
13
Input
Debug
LIN Transmit LIN bus transmit data input. Includes an internal
23
24,31
25
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
TXD-L2
GND
Input
Ground
Output
Data 2
pull-up resistor to VDD.
15, 18 15, 18 15, 18
Ground
Ground of the IC.
LIN Receive
Data
16
17
N/A
N/A
N/A
N/A
RXD-L2
LIN bus receive data output.
Input/
Output
26
36
N/A
17
N/A
N/A
N/A
N/A
LIN2
LIN bus
LIN bus input output connected to the LIN bus.
33903D/5D
LIN-1
33903S/5S Output
LIN
Input/
19
20
19
20
N/A
N/A
LIN bus
LIN bus input output connected to the LIN bus.
33903D/5D
TXD-L11
33903S/5S
LIN Transmit LIN bus transmit data input. Includes an internal
37
18
N/A
N/A
Input
Data
pull-up resistor to VDD.
TXD-L
33903D/5D
RXD-L1
33903S/5S
RXD-L
LIN Receive
Data
38
39
19
20
N/A
20
N/A
N/A
21
22
21
22
N/A
22
Output
LIN bus receive data output.
Direct battery voltage input sense. A serial
VSENSE
Input
Sense input resistor is required to limit the input current
during high voltage transients.
Configurable pin as an input or output, for
connection to external circuitry (switched or
small load). The voltage level can be read by
the SPI and the MUX output pin. The input can
be used as a programmable Wake-up input in
Input/
Output
Input Output
40
21
21
N/A
N/A
N/A
N/A
I/O-1
1
(LP) mode. It can be used in association with
I/O-0 for a cyclic sense function in (LP) mode.
33903/4/5
14
NXP Semiconductors
PIN CONNECTIONS
Table 4. 33903/4/5 pin definitions (continued)
54 Pin 32 Pin 32 Pin 32 Pin 32 Pin 32 Pin 32 Pin
33905D 33905S 33904 33903 33903D 33903S 33903P
Pin
Function
Formal
Name
Pin Name
Definition
This is the device reset output whose main
function is to reset the MCU. This pin has an
internal pull-up to VDD. The reset input voltage
is also monitored in order to detect external
reset and safe conditions.
Reset Output
(Active LOW)
41
22
22
22
23
23
23
RST
Output
This output is asserted low when an enabled
interrupt condition occurs. This pin is an open
drain structure with an internal pull up resistor
to VDD.
Interrupt
Output
(Active LOW)
42
43
23
24
23
24
23
24
24
25
24
25
24
25
INT
CS
Output
Input
Chip select pin for the SPI. When the CS is low,
the device is selected. In (LP) mode with VDD
ON, a transition on CS is a Wake-up condition
Chip Select
(Active LOW)
Serial Data
Clock
Clock input for the Serial Peripheral Interface
(SPI) of the device
44
45
46
47
25
26
27
28
25
26
27
28
25
26
27
28
26
27
28
29
26
27
28
29
26
27
28
29
SCLK
MOSI
MISO
VDD
Input
Input
Master Out/
Slave In
SPI data received by the device
Master In/
Slave Out
SPI data sent to the MCU. When the CS is high,
MISO is high-impedance
Output
Output
Input
Voltage
5.0 or 3.3 V output pin of the main regulator for
Digital Drain the Microcontroller supply.
Transmit
Data
CAN bus transmit data input. Internal pull-up to
VDD
48
49
29
30
29
30
29
30
30
31
30
31
30
31
TXD
RXD
Output Receive Data CAN bus receive data output
Connection to the external PNP path transistor.
This is an intermediate current supply source
for the VDD regulator
Voltage
Emitter
50
51
31
32
31
32
N/A
N/A
32
1
32
1
32
1
VE
Base output pin for connection to the external
PNP pass transistor
VB
Output Voltage Base
EX PAD EX PAD EX PAD EX PAD EX PAD EX PAD EX PAD
GND
Ground
Ground
Ground
33903/4/5
NXP Semiconductors
15
ELECTRICAL CHARACTERISTICS
5
Electrical characteristics
5.1
Maximum ratings
Table 5. Maximum ratings
All voltages are referenced to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage
to the device.
Symbol
Ratings
Value
Unit
Notes
Electrical ratings(11)
Supply Voltage at VSUP/1 and VSUP2
V
Normal Operation (DC)
Transient Conditions (Load Dump)
-0.3 to 28
-0.3 to 40
V
V
V
V
V
SUP1/2
V
SUP1/2TR
DC voltage on LIN/1 and LIN2
Normal Operation (DC)
VBUSLIN
VBUSLINTR
-28 to 28
-28 to 40
Transient Conditions (Load Dump)
DC voltage on CANL, CANH, SPLIT
Normal Operation (DC)
VBUS
VBUSTR
-28 to 28
-32 to 40
Transient Conditions (Load Dump)
DC Voltage at SAFE
VSAFE
VSAFETR
Normal Operation (DC)
Transient Conditions (Load Dump)
-0.3 to 28
-0.3 to 40
DC Voltage at I/O-0, I/O-1, I/O-2, I/O-3 (LIN-T Pins)
Normal Operation (DC)
VI/O
-0.3 to 28
-0.3 to 40
VI/OTR
Transient Conditions (Load Dump)
VDIGLIN
VDIG
DC voltage on TXD-L, TXD-L1 TXD-L2, RXD-L, RXD-L1, RXD-L2
DC voltage on TXD, RXD
-0.3 to VDD +0.3
-0.3 to VDD +0.3
-0.3 to 10
V
V
(13)
VINT
DC Voltage at INT
V
VRST
VRST
VMUX
VDBG
ILH
DC Voltage at RST
-0.3 to VDD +0.3
-0.3 to VDD +0.3
-0.3 to VDD +0.3
-0.3 to 10
V
DC Voltage at MOSI, MSIO, SCLK and CS
DC Voltage at MUX-OUT
V
V
DC Voltage at DBG
V
Continuous current on CANH and CANL
DC voltage at VDD, 5V-CAN, VAUX, VCAUX
DC voltage at VBASE and VBAUX
DC voltage at VE
200
mA
V
VREG
VREG
VE
-0.3 to 5.5
(12)
(13)
-0.3 to 40
V
-0.3 to 40
V
VSENSE
DC voltage at VSENSE
-28 to 40
V
Notes
11. The voltage on non-VSUP pins should never exceed the VSUP voltage at any time or permanent damage to the device may occur.
12. If the voltage delta between VSUP/1/2 and VBASE is greater than 6.0 V, the external V ballast current sharing functionality may be damaged.
DD
13. Potential Electrical Over Stress (EOS) damage may occur if RXD is in contact with VE while the device is ON.
33903/4/5
16
NXP Semiconductors
ELECTRICAL CHARACTERISTICS
Table 5. Maximum ratings (continued)
All voltages are referenced to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage
to the device.
Symbol
Ratings
Value
Unit
Notes
ESD Capability
AECQ100(14)
Human Body Model - JESD22/A114 (C
= 100 pF, R
= 1500 Ω)
ZAP
ZAP
8000
2000
V
V
CANH and CANL. LIN1 and LIN2, Pins versus all GND pins
all other Pins including CANH and CANL
ESD1-1
ESD1-2
Charge Device Model - JESD22/C101 (C
= 4.0 pF)
ZAP
750
500
V
V
ESD2-1
ESD2-2
Corner Pins (Pins 1, 16, 17, and 32)
All other Pins (Pins 2-15, 18-31)
Tested per IEC 61000-4-2 (C
= 150 pF, R
ZAP
= 330 Ω)
V
ZAP
V
V
V
15000
15000
15000
ESD3-1
ESD3-2
ESD3-3
Device unpowered, CANH and CANL pin without capacitor, versus GND
Device unpowered, LIN, LIN1 and LIN2 pin, versus GND
Device unpowered, VS1/VS2 (100 nF to GND), versus GND
Tested per specific OEM EMC requirements for CAN and LIN with
additional capacitor on VSUP/1/2 pins (See Typical applications on page
92)
V
V
V
9000
12000
7000
ESD4-1
ESD4-2
ESD4-3
CANH, CANL without bus filter
LIN, LIN1 and LIN2 with and without bus filter
I/O with external components (22 k - 10 nF)
Thermal ratings
TJ
Junction temperature
Ambient temperature
Storage temperature
150
°C
°C
°C
TA
-40 to 125
-50 to 150
TST
Thermal resistance
RθJA
(17)
Thermal resistance junction to ambient
50
°C/W
°C
(15), (16)
TPPRT
Peak package reflow temperature during reflow
Note 16
Notes
14. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), the Charge Device Model (CDM),
and Robotic (CZAP = 4.0 pF).
15. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause
malfunction or permanent damage to the device.
16. NXP’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and
Moisture Sensitivity Levels (MSL), go to www.nxp.com, search by part number (remove prefixes/suffixes) and enter the core ID to view all
orderable parts, and review parametrics.
17. This parameter was measured according to Figure 13:
PCB 100mm x 100mm
Top side, 300 sq. mm
(20mmx15mm)
Bottom view
Bottom side
20mm x 40mm
Figure 13. PCB with top and bottom layer dissipation area (dual layer)
33903/4/5
NXP Semiconductors
17
ELECTRICAL CHARACTERISTICS
5.2
Static electrical characteristics
Table 6. Static electrical characteristics
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 28 V, -40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical values noted reflect
the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
Power input
VSUP1/VSUP2
VSUP1/VSUP2
(18)
(19)
Nominal DC Voltage Range
5.5
4.0
-
-
28
V
V
Extended DC Low Voltage Range
5.5
Undervoltage Detector Thresholds, at the VSUP/1 pin,
5.5
-
0.22
6.0
-
0.35
6.5
6.6
0.5
Low threshold (VSUP/1 ramp down)
High threshold (VSUP/1 ramp up)
Hysteresis
VS1_LOW
V
Note: function not active in LP mode
Undervoltage Detector Thresholds, at the VSUP2 pin:
5.5
-
0.22
6.0
-
0.35
6.5
6.6
0.5
Low threshold (VSUP2 ramp down)
High threshold (VSUP2 ramp up)
Hysteresis
VS2_LOW
V
V
Note: function not active in LP modes
VSUP Overvoltage Detector Thresholds, at the VSUP/1 pin:
Not active in LP modes
VS_HIGH
16.5
17
18.5
BATFAIL
VSUP-TH1
Battery loss detection threshold, at the VSUP/1 pin.
VSUP/1 to turn VDD ON, VSUP/1 rising
VSUP/1 to turn VDD ON, hysteresis (Guaranteed by design)
Supply current
2.0
-
2.8
4.1
180
4.0
4.5
V
V
VSUP-TH1HYST
150
mV
(20), (21)
ISUP1
- from VSUP/1
- from VSUP2, (5V-CAN VAUX, I/O OFF)
-
-
mA
mA
2.0
0.05
4.0
0.85
Supply current, ISUP1 + ISUP2, Normal mode, VDD ON
- 5 V-CAN OFF, VAUX OFF
-
-
-
-
2.8
4.5
5.0
5.5
8.0
- 5 V-CAN ON, CAN interface in Sleep mode, VAUX OFF
- 5 V-CAN OFF, Vaux ON
- 5 V-CAN ON, CAN interface in TXD/RXD mode, VAUX OFF, I/O-x
disabled
ISUP1+2
-
-
-
LP mode VDD OFF. Wake-up from CAN, I/O-x inputs
VSUP ≤ 18 V, -40 to 25 °C
ILPM_OFF
μA
μA
-
-
15
-
35
50
VSUP ≤ 18 V, 125 °C
LP mode VDD ON (5.0 V) with VDD undervoltage and VDD
overcurrent monitoring, Wake-up from CAN, I/O-x inputs
-
-
VSUP ≤ 18 V, -40 to 25 °C, IDD = 1.0 μA
VSUP ≤ 18 V, -40 to 25 °C, IDD = 100 μA
VSUP ≤ 18 V, 125 °C, IDD = 100 μA
ILPM_ON
20
40
-
-
65
85
LP mode, additional current for oscillator (used for: cyclic sense,
forced Wake-up, and in LP V
watchdog)
ON mode cyclic interruption and
DD
IOSC
μA
-
5.0
-
9.0
10
VSUP ≤ 18 V, -40 to 125 °C
VDBG
Notes
Debug mode DBG voltage range
8.0
V
18. All parameters in spec (ex: VDD regulator tolerance).
19. Device functional, some parameters could be out of spec. VDD is active, device is not in Reset mode if the lowest VDD undervoltage reset threshold
is selected (approx. 3.4 V). CAN and I/Os are not operational.
20. In Run mode, CAN interface in Sleep mode, 5 V-CAN and VAUX turned OFF. IOUT at VDD < 50 mA. Ballast: turned OFF or not connected.
21. VSUP1 and VSUP2 supplies are internally connected on part number MC33903BDEK and MC33903BSEK. Therefore, I
be measured individually.
and I
cannot
SUP2
SUP1
33903/4/5
18
NXP Semiconductors
ELECTRICAL CHARACTERISTICS
Table 6. Static electrical characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 28 V, -40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical values noted reflect
the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
VDD Voltage regulator, VDD pin
Output Voltage
VDD = 5.0 V, VSUP 5.5 to 28 V, IOUT 0 to 150 mA
VDD = 5.0 V, under EMC immunity test condition
VDD = 3.3 V, VSUP 5.5 to 28 V, IOUT 0 to 150 mA
VOUT-5.0
VOUT-5.0-EMC
VOUT-3.3
4.9
4.9
3.234
5.0
5.0
3.3
5.1
5.15
3.4
V
(22)
Drop voltage without external PNP pass transistor
(23)
(23)
VDD = 5.0 V, IOUT = 100 mA
VDD = 5.0 V, IOUT = 150 mA
VDROP
-
-
330
-
450
500
mV
mV
V
Drop voltage with external transistor
VDROP-B
-
350
500
IOUT = 200 mA (I_BALLAST + I_INTERNAL
)
VSUP/1 to maintain V within V
specified voltage range
OUT-3.3
DD
VDD = 3.3 V, IOUT = 150 mA
VDD = 3.3 V, IOUT = 200 mA, external transistor implemented
VSUP1-3.3
4.0
4.0
-
-
-
-
External ballast versus internal current ratio (I_BALLAST = K x Internal
current)
K
1.5
2.0
2.5
ILIM
TPW
TSD
Output Current limitation, without external transistor
Temperature pre-warning (Guaranteed by design)
Thermal shutdown (Guaranteed by design)
150
-
350
550
mA
°C
°C
μF
140
-
-
160
4.7
-
-
(24)
CEXT
Range of decoupling capacitor (Guaranteed by design)
LP mode VDD ON, IOUT ≤ 50 mA (time limited)
100
VDD = 5.0 V, 5.6 V ≤ V
VDD = 3.3 V, 5.6 V ≤ V
≤ 28 V
≤ 28 V
VDDLP
4.75
3.135
5.0
3.3
5.25
3.465
V
SUP
SUP
LP mode VDD ON, dynamic output current capability (Limited duration.
Ref. to device description).
LP-IOUTDC
-
-
50
mA
mA
mV
LP VDD ON mode:
LP-ITH
Overcurrent Wake-up threshold.
Hysteresis
1.0
0.1
3.0
1.0
-
-
LP mode VDD ON, drop voltage, at IOUT = 30 mA (Limited duration.
Ref. to device description)
(23)
LP-VDROP
-
200
400
LP mode VDD ON, min VSUP operation (Below this value, a VDD
undervoltage reset may occur)
,
LP-MINVS
VDD_OFF
5.5
-
-
-
-
-
0.3
-
V
V
V
VDD when VSUP < VSUP-TH1, at I_VDD ≤ 10 μA (Guaranteed by design)
VDD when VSUP ≥ VSUP-TH1, at I_VDD ≤ 40 mA (Guaranteed with
VDD_START UP
3.0
parameter VSUP-TH1
Notes
22. Guaranteed by design. During immunity tests, according to IEC62132-4, with RF injection applied to CAN or LIN pins. No filter components on
CAN or LIN pins. When immunity tests are performed with a CAN filter component (common mode choke) or LIN filter component (capacitor), the
V
DD specification is 5.0 V 2%.
23. For 3.3 V VDD devices, the drop-out voltage test condition leads to a VSUP below the min VSUP threshold (4.0 V). As a result, the dropout voltage
parameter cannot be specified.
24. The regulator is stable without an external capacitor. Usage of an external capacitor is recommended for AC performance.
33903/4/5
NXP Semiconductors
19
ELECTRICAL CHARACTERISTICS
Table 6. Static electrical characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 28 V, -40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical values noted reflect
the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
Voltage regulator for CAN interface supply, 5.0 V-CAN pin
Output voltage, VSUP/2 = 5.5 to 40 V
5V-C OUT
4.75
5.0
5.25
V
IOUT 0 to 160 mA
(25)
5V-C ILIM
5V-C UV
5V-CTS
Output Current limitation
160
4.1
160
1.0
280
-
4.7
-
mA
V
Undervoltage threshold
4.5
Thermal shutdown (Guaranteed by design)
External capacitance (Guaranteed by design)
-
-
°C
μF
CEXT-CAN
100
V auxiliary output, 5.0 and 3.3 V selectable pin VB-Aux, VC-Aux, Vaux
VAUX output voltage
VAUX = 5.0 V, VSUP = VSUP2 5.5 to 40 V, IOUT 0 to 150 mA
VAUX = 3.3 V, VSUP = VSUP2 5.5 to 40 V, IOUT 0 to 150 mA
VAUX
4.75
3.135
5.0
3.3
5.25
3.465
V
V
VAUX undervoltage detector (VAUX configured to 5.0 V)
Low Threshold
Hysteresis
4.2
0.06
2.75
4.5
-
3.0
4.70
0.12
3.135
VAUX-UVTH
VAUX undervoltage detector (VAUX configured to 3.3 V, default
value)
VAUX overcurrent threshold detector
VAUX set to 3.3 V
VAUX-ILIM
VAUX CAP
250
230
360
330
450
430
mA
VAUX set to 5.0 V
External capacitance (Guaranteed by design)
2.2
-
100
μF
Undervoltage reset and reset function, RST pin
(26), (28)
(26), (28)
VDD undervoltage threshold down - 90% VDD (VDD 5.0 V)
4.5
4.65
4.85
4.90
3.135
3.135
VDD undervoltage threshold up - 90% VDD (VDD 5.0 V)
VDD undervoltage threshold down - 90% VDD (VDD 3.3 V)
VDD undervoltage threshold up - 90% VDD (VDD 3.3 V)
-
2.75
-
-
3.0
-
VRST-TH1
V
V
(27), (28)
VRST-TH2-5
VDD undervoltage reset threshold down - 70% VDD (VDD 5.0 V)
2.95
3.2
3.45
Hysteresis
for threshold 90% VDD, 5.0 V device
20
10
-
-
150
150
for threshold 70% VDD, 5.0 V device
VRST-HYST
mV
Hysteresis 3.3 V VDD
10
-
150
for threshold 90% VDD, 3.3 V device
VDD undervoltage reset threshold down - LP VDD ON mode
(Note: device change to Normal Request mode). VDD 5.0 V
VRST-LP
4.0
2.75
4.5
3.0
4.85
3.135
V
(Note: device change to Normal Request mode). VDD 3.3 V
VOL
Reset VOL @ 1.5 mA, VSUP 5.5 to 28 V
Current limitation, Reset activated, VRESET = 0.9 x VDD
Pull-up resistor (to VDD pin)
-
300
7.0
11
500
10
mV
mA
kΩ
IRESET LOW
RPULL-UP
Notes
2.5
8.0
15
25. Current limitation will be reported by setting a flag.
26. Generate a Reset or an INT. SPI programmable
27. Generate a Reset
28. In Non-LP modes
33903/4/5
20
NXP Semiconductors
ELECTRICAL CHARACTERISTICS
Table 6. Static electrical characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 28 V, -40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical values noted reflect
the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
Undervoltage reset and reset function, RST PIN (continued)
(29)
VSUP-RSTL
VRST-VTH
VHYST
VSUP to guaranteed reset low level
2.5
-
-
V
Reset input threshold
Low threshold, VDD = 5.0 V
1.5
-
-
-
-
-
3.5
-
High threshold, VDD = 5.0 V
Low threshold, VDD = 3.3 V
High threshold, VDD = 3.3 V
-
0.99
-
V
V
2.31
Reset input hysteresis
0.5
1.0
1.5
I/O pins when function selected is output
VI/O-0 HSDRP
VI/O-2-3 HSDRP
VI/O-1 HSDRP
VI/O-01 LSDRP
II/O_LEAK
I/O-0 HS switch drop @ I = -12 mA, VSUP = 10.5 V
-
-
-
-
-
0.5
0.5
0.4
0.4
0.1
1.4
1.4
1.4
1.4
3.0
V
V
I/O-2 and I/O-3 HS switch drop @ I = -20 mA, VSUP = 10.5 V
I/O-1, HS switch drop @ I = -400 μA, VSUP = 10.5 V
I/O-0, I/O-1 LS switch drop @ I = 400 μA, VSUP = 10.5 V
Leakage current, I/O-x ≤ VSUP
V
V
μA
I/O pins when function selected is input
VI/O_NTH
VI/O_PTH
VI/O_HYST
II/O_IN
Negative threshold
Positive threshold
Hysteresis
1.4
2.1
0.2
-5.0
2.0
3.0
1.0
1.0
2.9
3.8
1.4
5.0
V
V
V
Input current, I/O ≤ VSUP/2
μA
I/O-0 and I/O-1 input resistor. I/O-0 (or I/O-1) selected in
register, 2.0 V < VI/O-X <16 V (Guaranteed by design).
RI/O-X
-
100
-
kΩ
VSENSE input
VSENSE undervoltage threshold (Not active in LP modes)
Low Threshold
High threshold
Hysteresis
8.1
-
0.1
8.6
-
0.25
9.0
9.1
0.5
VSENSE_TH
V
Input resistor to GND. In all modes except in LP modes. (Guaranteed
by design).
RVSENSE
-
125
-
kΩ
Notes
29. Reset must be kept low
33903/4/5
NXP Semiconductors
21
ELECTRICAL CHARACTERISTICS
Table 6. Static electrical characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 28 V, -40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical values noted reflect
the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
Analog MUX output
VOUT_MAX
RMI
Output Voltage Range, with external resistor to GND >2.0 kΩ
Internal pull-down resistor for regulator output current sense
External capacitor at MUX OUTPUT (Guaranteed by design)
0.0
0.8
-
-
1.9
-
VDD - 0.5
2.8
V
kΩ
nF
(30)
CMUX
1.0
Chip temperature sensor coefficient (Guaranteed by design and
device characterization)
TEMP-COEFF
mv/°C
V
VDD = 5.0 V
VDD = 3.3 V
20
13.2
21
13.9
22
14.6
Chip temperature: MUX-OUT voltage
VDD = 5.0 V, TA = 125 °C
VTEMP
3.6
2.45
3.75
2.58
3.9
2.65
VDD = 3.3 V, TA = 125 °C
Chip temperature: MUX-OUT voltage (guaranteed by design and
characterization)
TA = -40 °C, VDD = 5.0 V
TA = 25 °C, VDD = 5.0 V
TA = -40 °C, VDD = 3.3 V
TA = 25 °C, VDD = 3.3 V
0.12
1.5
0.07
1.08
0.30
1.65
0.19
1.14
0.48
1.8
0.3
VTEMP(GD)
V
1.2
Gain for VSENSE, with external 1.0 k 1% resistor
VDD = 5.0 V
VSENSE GAIN
5.42
8.1
5.48
8.2
5.54
8.3
VDD = 3.3 V
VSENSE OFFSET Offset for VSENSE, with external 1.0 k 1% resistor
Divider ratio for VSUP/1
-20
-
20
mV
VDD = 5.0 V
VSUP/1 RATIO
5.335
7.95
5.5
8.18
5.665
8.45
VDD = 3.3 V
Attenuation/Gain ratio for I/O-0 and I/O-1 actual voltage:
VDD = 5.0 V, I/O = 16 V (Attenuation, MUX-OUT register bit 3 set to
1)
3.8
-
5.6
-
4.0
2.0
5.8
1.3
4.2
-
6.2
-
VDD = 5.0 V, (Gain, MUX-OUT register bit 3 set to 0)
VI/O RATIO
VDD = 3.3 V, I/O = 16 V (Attenuation, MUX-OUT register bit 3 set to
1)
VDD = 3.3 V, (Gain, MUX-OUT register bit 3 set to 0)
Internal reference voltage
VDD = 5.0 V
VREF
2.45
1.64
2.5
1.67
2.55
1.7
V
VDD = 3.3 V
Current ratio between VDD output & IOUT at MUX-OUT
(IOUT at MUX-OUT = IDD out / IDD_RATIO
At IOUT = 50 mA
)
IDD_RATIO
80
62.5
97
97
115
117
I_OUT from 25 to 150 mA
SAFE output
VOL
SAFE low level, at I = 500 μA
0.0
-
0.2
0.0
1.0
1.0
V
Safe leakage current (VDD low, or device unpowered). VSAFE 0 to
28 V.
ISAFE-IN
μA
Notes
30. When C is higher than CMUX, a serial resistor must be inserted
33903/4/5
22
NXP Semiconductors
ELECTRICAL CHARACTERISTICS
Table 6. Static electrical characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 28 V, -40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical values noted reflect
the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Interrupt
Characteristic
Min.
Typ.
Max.
Unit
Notes
V
kΩ
V
VOL
RPU
Output low voltage, IOUT = 1.5 mA
-
0.2
10
1.0
14
Pull-up resistor
6.5
3.9
VOH-LPVDDON
Output high level in LP V
ON mode (Guaranteed by design)
4.3
DD
Leakage current INT voltage = 10 V (to allow high-voltage on MCU
INT pin)
μA
VMAX
-
35
100
10
mA
I SINK
Sink current, VINT > 5.0 V, INT low state
2.5
6.0
MISO, MOSI, SCLK, CS pins
VOL
VOH
VIL
Output low voltage, IOUT = 1.5 mA (MISO)
-
VDD -0.9
-
-
1.0
V
V
Output high voltage, IOUT = -0.25 mA (MISO)
Input low voltage (MOSI, SCLK,CS)
Input high voltage (MOSI, SCLK,CS)
Tri-state leakage current (MISO)
Pull-up current (CS)
-
-
0.3 x VDD
V
VIH
IHZ
0.7 x VDD
-2.0
-
-
-
V
2.0
500
μA
μA
IPU
200
370
CAN logic input pins (TXD)
VIH
VIL
High Level Input Voltage
0.7 x VDD
-0.3
-
-
VDD + 0.3
0.3 x VDD
V
V
Low Level Input Voltage
Pull-up Current, TXD, VIN = 0 V
VDD = 5.0 V
IPDWN
-850
-500
-650
-250
-200
-175
µA
VDD = 3.3 V
CAN data output pins (RXD)
Low Level Output Voltage
VOUTLOW
VOUTHIGH
IOUTHIGH
IOUTLOW
V
V
IRXD = 5.0 mA
0.0
0.7 x VDD
2.5
-
0.3 x VDD
VDD
High Level Output Voltage
IRX = -3.0 mA
-
High Level Output Current
mA
mA
VRXD = V
- 0.4 V
5.0
5.0
9.0
DD
Low Level Input Current
VRXD = 0.4 V
2.5
9.0
33903/4/5
NXP Semiconductors
23
ELECTRICAL CHARACTERISTICS
Table 6. Static electrical characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 28 V, -40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical values noted reflect
the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
CAN output pins (CANH, CANL)
VCOM
Bus pins common mode voltage for full functionality
Differential input voltage threshold
Differential input hysteresis
-12
500
50
-
12
900
-
V
VCANH-VCANL
VDIFF-HYST
-
mV
mV
kΩ
kΩ
%
-
-
RIN
Input resistance
5.0
10
50
RIN-DIFF
RIN-MATCH
Differential input resistance
-
100
3.0
Input resistance matching
-3.0
0.0
CANH output voltage (45 Ω < RBUS < 65 Ω)
TXD dominant state
VCANH
2.75
2.0
3.5
2.5
4.5
3.0
V
V
V
TXD recessive state
CANL output voltage (45 Ω < RBUS < 65 Ω)
TXD dominant state
VCANL
0.5
2.0
1.5
2.5
2.25
3.0
TXD recessive state
Differential output voltage (45 Ω < RBUS < 65 Ω)
TXD dominant state
VOH-VOL
1.5
-0.5
2.0
0.0
3.0
0.05
TXD recessive state
ICANH
ICANL
ICANL-OC
ICANH-OC
CAN H output current capability - Dominant state
CAN L output current capability - Dominant state
CANL overcurrent detection - Error reported in register
CANH overcurrent detection - Error reported in register
-
-
-30
-
mA
mA
mA
mA
30
-
75
120
-120
195
-75
-195
CANH, CANL input resistance to GND, device supplied, CAN in Sleep
mode, V_CANH, V_CANL from 0 to 5.0 V
RINSLEEP
VCANLP
5.0
-0.1
-
-
50
0.1
10
kΩ
V
CANL, CANH output voltage in LP V
OFF and LP V
ON modes
DD
0.0
3.0
DD
CANH, CANL input current, VCANH, VCANL = 0 to 5.0 V, device
unpowered (VSUP, VDD, 5V-CAN: open).
(31)
(31)
ICAN-UN_SUP1
µA
CANH, CANL input current, VCANH, VCANL = -2.0 to 7.0 V, device
unpowered (VSUP, VDD, 5V-CAN: open).
ICAN-UN_SUP2
-
-
250
µA
(32)
(32)
VDIFF-R-LP
VDIFF-D-LP
Differential voltage for recessive bit detection in LP mode
Differential voltage for dominant bit detection in LP mode
-
-
-
0.4
-
V
V
1.15
CANH and CANL diagnostic information
VLG
VHG
VLVB
VHVB
VL5
CANL to GND detection threshold
1.6
1.6
-
1.75
2.0
V
V
V
V
V
V
CANH to GND detection threshold
1.75
2.0
CANL to VBAT detection threshold, VSUP/1 and VSUP2 > 8.0 V
CANH to VBAT detection threshold, VSUP/1 and VSUP2 > 8.0 V
CANL to VDD detection threshold
VSUP -2.0
VSUP -2.0
VDD -0.43
VDD -0.43
-
-
-
-
-
4.0
4.0
VH5
CANH to VDD detection threshold
Notes
31. VSUP, VDD, 5V-CAN: shorted to GND, or connected to GND via a 47 k resistor instances are guaranteed by design and device characterization.
32. Guaranteed by design and device characterization.
33903/4/5
24
NXP Semiconductors
ELECTRICAL CHARACTERISTICS
Table 6. Static electrical characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 28 V, -40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical values noted reflect
the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
SPLIT
Characteristic
Min.
Typ.
Max.
Unit
Notes
Output voltage
Loaded condition ISPLIT = ±500 µA
VSPLIT
0.3 x VDD 0.5 x VDD 0.7 x VDD
0.45 x VDD 0.5 x VDD 0.55 x VDD
V
Unloaded condition Rmeasure > 1.0 MΩ
Leakage current
-12 V < VSPLIT < +12 V
ILSPLIT
-
-
0.0
-
5.0
200
µA
-22 to -12 V < VSPLIT < +12 to +35 V
LIN terminals (LIN-T/1, LIN-T2)
VLT_HSDRP LIN-T1, LIN-T2, HS switch drop @ I = -20 mA, V
> 10.5 V
-
1.0
1.4
V
SUP
LIN1 & LIN2 33903D/5D pin - LIN 33903S/5S pin (parameters guaranteed for VSUP/1, VSUP2 7.0 V ≤ VSUP ≤ 18 V)
VBAT
Operating Voltage Range
8.0
-
18
18
V
V
VSUP
Supply Voltage Range
7.0
-
Current Limitation for Driver Dominant State
Driver ON, VBUS = 18 V
IBUS_LIM
40
-1.0
-
90
-
200
-
mA
Input Leakage Current at the receiver
Driver off; VBUS = 0 V; VBAT = 12 V
IBUS_PAS_DOM
mA
µA
Leakage Output Current to GND
IBUS_PAS_REC
-
20
Driver Off; 8.0 V < VBAT < 18 V; 8.0 V < VBUS < 18 V; VBUS ≥ VBAT
Control unit disconnected from ground (Loss of local ground must not
affect communication in the residual network)
IBUS_NO_GND
-1.0
-
-
1.0
mA
µA
GNDDEVICE = VSUP; VBAT = 12 V; 0 < V
design)
< 18 V (Guaranteed by
BUS
V
Disconnected; VSUP_DEVICE = GND; 0 < V
< 18 V (Node has
BUS
BAT
IBUSNO_BAT
to sustain the current that can flow under this condition. Bus must
remain operational under this condition). (Guaranteed by design)
-
100
VBUSDOM
VBUSREC
Receiver Dominant State
Receiver Recessive State
-
-
-
0.4
-
VSUP
VSUP
0.6
Receiver Threshold Center
(VTH_DOM + VTH_REC)/2
VBUS_CNT
VHYS
0.475
-
0.5
-
0.525
0.175
VSUP
VSUP
Receiver Threshold Hysteresis
(VTH_REC - VTH_DOM
)
VBUSWU
RSLAVE
LIN Wake-up threshold from LP V
ON or LP V
OFF mode
DD
-
20
140
-
5.3
30
5.8
60
180
-
V
DD
LIN Pull-up Resistor to V
SUP
kΩ
°C
°C
TLINSD
Overtemperature Shutdown (Guaranteed by design)
Overtemperature Shutdown Hysteresis (Guaranteed by design)
160
10
TLINSD_HYS
33903/4/5
NXP Semiconductors
25
ELECTRICAL CHARACTERISTICS
5.3
Dynamic electrical characteristics
Table 7. Dynamic electrical characteristics
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 28 V, -40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
SPI timing
Characteristic
Min.
Typ.
Max.
Unit
Notes
FREQ
tPCLK
SPI Operation Frequency (MISO cap = 50 pF)
SCLK Clock Period
0.25
250
125
125
-
-
-
-
4.0
N/A
N/A
N/A
MHz
ns
tWSCLKH
tWSCLKL
SCLK Clock High Time
ns
SCLK Clock Low Time
ns
Falling Edge of CS to Rising Edge of SCLK
tLEAD
ns
‘C’ and ‘D’ versions
All others
30
550
-
-
N/A
N/A
Falling Edge of CS to Rising Edge of SCLK when CS_low flag is set to
‘1’
tLEAD
μs
‘C’ and ‘D’ versions
All others
0.030
0.55
-
-
2.5
2.5
tLAG
tSISU
tSIH
Falling Edge of SCLK to Rising Edge of CS
MOSI to Falling Edge of SCLK
Falling Edge of SCLK to MOSI
MISO Rise Time (CL = 50 pF)
MISO Fall Time (CL = 50 pF)
30
30
30
-
-
-
-
-
-
N/A
N/A
N/A
30
ns
ns
ns
ns
ns
tRSO
tFSO
tSOEN
tSODIS
-
30
Time from Falling to MISO Low-impedance
Time from Rising to MISO High-impedance
-
-
-
-
30
30
ns
ns
tVALID
tCSLOW
tCS-TO
Time from Rising Edge of SCLK to MISO Data Valid
-
-
30
Delay between falling and rising edge on CS
1.0
5.5
-
-
N/A
N/A
μs
‘C’ and ‘D’ versions
All others
CS Chip Select Low Timeout Detection
2.0
-
-
ms
Supply, voltage regulator, reset
tVS_LOW1/2_DGLT undervoltage detector threshold deglitcher
tRISE-ON
V
30
50
20
50
250
30
100
800
40
μs
μs
μs
SUP
Rise time at turn ON. VDD from 1.0 to 4.5 V. 2.2 μF at the VDD pin.
tRST-DGLT
Deglitcher time to set RST pin low
Reset pulse duration
VDD undervoltage (SPI selectable)
short, default at power on when BATFAIL bit set
0.9
4.0
8.5
17
1.0
5.0
10
1.4
6.0
12
tRST-PULSE
ms
medium
medium long
long
20
24
tRST-WD
I/O input
Watchdog reset
0.9
19
30
1.0
30
-
1.4
41
ms
μs
μs
tIODT
VSENSE input
tBFT
Deglitcher time (Guaranteed by design)
Undervoltage deglitcher time
100
33903/4/5
26
NXP Semiconductors
ELECTRICAL CHARACTERISTICS
Table 7. Dynamic electrical characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 28 V, -40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Interrupt
Characteristic
Min.
Typ.
Max.
Unit
Notes
INT pulse duration (refer to SPI for selection. Guaranteed by design)
short (25 to 125 °C)
20
25
35
tINT-PULSE
μs
short (-40 °C)
long (25 to 125 °C)
20
90
25
100
40
130
long (-40 °C)
90
100
140
State diagram timings
Delay for SPI Timer A, Timer B or Timer C write command after
entering Normal mode
tD_NM
(No command should occur within tD_NM
tD_NM delay definition: from CS rising edge of “Go to Normal mode (i.e.
0x5A00)” command to CS falling edge of “Timer write” command)
.
60
-
-
-
μs
Tolerance for: watchdog period in all modes, FWU delay, Cyclic sense
period and active time, Cyclic Interrupt period, LP mode overcurrent
(unless otherwise noted)
(36)
t
-10
10
%
TIMING-ACC
CAN dynamic characteristics
tDOUT TXD Dominant State Timeout
tDOM
300
300
600
600
1000
1000
µs
µs
Bus dominant clamping detection
Propagation loop delay TXD to RXD, recessive to dominant (Fast slew
rate)
tLRD
60
120
210
ns
tTRD
tRRD
Propagation delay TXD to CAN, recessive to dominant
Propagation delay CAN to RXD, recessive to dominant
-
-
70
45
110
140
ns
ns
Propagation loop delay TXD to RXD, dominant to recessive (Fast slew
rate)
tLDR
100
120
200
ns
tTDR
tRDR
Propagation delay TXD to CAN, dominant to recessive
Propagation delay CAN to RXD, dominant to recessive
-
-
75
50
150
140
ns
ns
Loop time TXD to RXD, Medium Slew Rate (Selected by SPI)
Recessive to Dominant
tLOOP-MSL
-
-
200
200
-
-
ns
ns
Dominant to Recessive
Loop time TXD to RXD, Slow Slew Rate (Selected by SPI)
Recessive to Dominant
tLOOP-SSL
-
-
300
300
-
-
Dominant to Recessive
CAN Wake-up filter time, single dominant pulse detection (See
Figure 35)
(33)
(34)
(35)
tCAN-WU1-F
tCAN-WU3-F
tCAN-WU3-TO
0.5
300
-
2.0
5.0
-
μs
ns
μs
CAN Wake-up filter time, 3 dominant pulses detection
-
-
CAN Wake-up filter time, 3 dominant pulses detection timeout (See
Figure 36)
120
Notes
33. No Wake-up for single pulse shorter than tCAN-WU1 min. Wake-up for single pulse longer than tCAN-WU1 max.
34. Each pulse should be greater than tCAN-WU3-F min. Guaranteed by design, and device characterization.
35. The 3 pulses should occur within tCAN-WU3-TO. Guaranteed by design, and device characterization.
36. Guaranteed by design.
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ELECTRICAL CHARACTERISTICS
Table 7. Dynamic electrical characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 28 V, -40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
LIN physical layer: driver characteristics for normal slew rate - 20.0 kBit/sec according to lin physical layer specification
Bus load RBUS and CBUS 1.0 nF / 1.0 kΩ, 6.8 nF / 660 Ω, 10 nF / 500 Ω. See Figure 18, page 30.
Duty Cycle 1:
THREC(MAX) = 0.744 * VSUP
D1
THDOM(MAX) = 0.581 * VSUP
0.396
-
-
-
D1 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 50 µs, 7.0 V ≤ VSUP ≤ 18 V
Duty Cycle 2:
THREC(MIN) = 0.422 * VSUP
D2
THDOM(MIN) = 0.284 * VSUP
-
0.581
D2 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 50 µs, 7.6 V ≤ VSUP ≤ 18 V
LIN physical layer: driver characteristics for slow slew rate - 10.4 kBit/sec according to lin physical layer specification
Bus load RBUS and CBUS 1.0 nF / 1.0 kΩ, 6.8 nF / 660 Ω, 10 nF / 500 Ω. Measurement thresholds. See Figure 19, page 31.
Duty Cycle 3:
THREC(MAX) = 0.778 * VSUP
D3
THDOM(MAX) = 0.616 * VSUP
0.417
-
-
D3 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 96 µs, 7.0 V ≤ VSUP ≤ 18 V
Duty Cycle 4:
THREC(MIN) = 0.389 * VSUP
D4
THDOM(MIN) = 0.251 * VSUP
-
-
-
0.590
-
D4 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 96 µs, 7.6 V ≤ VSUP ≤ 18 V
LIN physical layer: driver characteristics for fast slew rate
SR LIN Fast Slew Rate (Programming Mode)
20
V/μs
FAST
LIN physical layer: characteristics and wake-up timings. VSUP from 7.0 to 18 V, bus load RBUS and CBUS 1.0 nF / 1.0 kΩ, 6.8 nF / 660 Ω,
10 nF / 500 Ω. See Figure 18, page 30.
Propagation Delay and Symmetry (See Figure 18, page 30 and
Figure 19, page 31)
Propagation Delay of Receiver, tREC_PD = MAX (tREC_PDR
tREC_PDF
Symmetry of Receiver Propagation Delay, tREC_PDF - tREC_PDR
,
μs
μs
)
tREC_PD
tREC_SYM
-
4.2
-
6.0
2.0
-2.0
Bus Wake-up Deglitcher (LP V
OFF and LP V
OFF mode and Figure 21, page 31 for
ON modes) (See
DD
DD
tPROPWL
Figure 20, page 30 for LP V
42
70
95
DD
LP mode)
Bus Wake-up Event Reported
From LP V
OFF mode
tWAKE_LPVDDOFF
-
-
1500
DD
μs
tWAKE_LPVDDON
tTXDDOM
From LP V
ON mode
1.0
-
12
DD
TXD Permanent Dominant State Delay (Guaranteed by design)
0.65
1.0
1.35
s
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ELECTRICAL CHARACTERISTICS
5.4
Timing diagrams
t
PCLK
CS
t
WCLKH
t
LEAD
t
LAG
SCLK
t
WCLKL
t
t
SIH
SISU
MOSI
MISO
Undefined
Di 0
Don’t Care
Di n
Don’t Care
t
VALID
t
SODIS
t
SOEN
Do 0
Do n
t
CSLOW
Figure 14. SPI timing
t
LRD
TXD
0.3 x V
0.7 x V
DD
DD
t
LDR
0.7 x V
RXD
DD
0.3 x V
DD
Figure 15. CAN signal propagation loop delay TXD to RXD
t
TRD
TXD
0.3 x VDD
0.7 x V
DD
t
TDR
0.9 V
V
DIFF
0.5 V
t
RRD
t
RDR
0.7 x V
RXD
DD
0.3 x V
DD
Figure 16. CAN signal propagation delays TXD to CAN and CAN to RXD
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ELECTRICAL CHARACTERISTICS
.
12 V
10 μF
5 V_CAN
CANH
VSUP
TXD
22 μF
100 nF
Signal generator
RBUS
CBus
60 Ω
100 pF
CANL
SPLIT
RXD
All pins are not shown
GND
15 pF
Figure 17. Test circuit for CAN timing characteristics
TXD
tBIT
tBIT
t
t
BUS_REC
(MAX)
(MIN)
BUS_DOM
VLIN_REC
74.4% VSUP
Thresholds of
receiving node 1
TH
REC(MAX)
DOM(MAX)
58.1% V
SUP
TH
LIN
Thresholds of
receiving node 2
42.2% V
28.4% V
SUP
TH
REC(MIN)
SUP
TH
DOM(MIN)
t
BUS_DOM(MIN)
t
BUS_REC(MAX)
RXD
Output of receiving Node 1
t
REC_PDF(1)
t
REC_PDR(1)
RXD
Output of receiving Node 2
t
REC_PDF(2)
t
REC_PDR(2)
Figure 18. LIN timing measurements for normal slew rate
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ELECTRICAL CHARACTERISTICS
TXD
tBIT
tBIT
t
t
BUS_REC(MIN)
BUS_DOM(MAX)
VLIN_REC
77.8% VSUP
Thresholds of
receiving node 1
TH
REC(MAX)
DOM(MAX)
61.6% V
SUP
TH
LIN
Thresholds of
receiving node 2
38.9% V
25.1% V
SUP
TH
REC(MIN)
SUP
TH
DOM(MIN)
t
BUS_DOM(MIN)
t
BUS_REC(MAX)
RXD
Output of receiving Node 1
t
REC_PDF(1)
t
REC_PDR(1)
RXD
Output of receiving Node 2
t
REC_PDF(2)
t
REC_PDR(2)
Figure 19. LIN timing measurements for slow slew rate
V
REC
V
BUSWU
LIN
0.4 V
SUP
Dominant level
3V
VDD
T
T
WAKE
PROPWL
Figure 20. LIN wake-up LP VDD off mode timing
VLIN_REC
LIN
V
BUSWU
0.4 V
SUP
Dominant level
IRQ
T
T
WAKE
PROPWL
IRQ stays low until SPI reading command
Figure 21. LIN Wake-up LP VDD ON Mode Timing
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FUNCTIONAL DESCRIPTION
6
Functional description
6.1
Introduction
The MC33903_4_5 is the second generation of System Basis Chip, combining:
- Advanced power management unit for the MCU, the integrated CAN interface and for the additional ICs such as sensors, CAN
transceiver.
- Built in enhanced high speed CAN interface (ISO11898-2 and -5), with local and bus failure diagnostic, protection, and fail-safe operation
mode.
- Built in LIN interface, compliant to LIN 2.1 and J2602-2 specification, with local and bus failure diagnostic and protection.
- Innovative hardware configurable fail-safe state machine solution.
- Multiple LP modes, with low current consumption.
- Family concept with pin compatibility; with and without LIN interface devices.
6.2
Functional pin description
6.2.1 Power supply (VSUP/1 and VSUP2)
Note: VSUP1 and VSUP2 supplies are externally available on all devices except the 33903D, 33903S, and 33903P, where these are
connected internally.
VSUP1 is the input pin for the internal supply and the VDD regulator. VSUP2 is the input pin for the 5 V-CAN regulator, LIN’s interfaces
and I/O functions. The VSUP block includes over and undervoltage detections which can generate interrupt. The device includes a loss
of battery detector connected to VSUP/1.
Loss of battery is reported through a bit (called BATFAIL). This generates a POR (Power On Reset).
6.2.2 VDD voltage regulator (VDD)
The regulator has two main modes of operation (Normal mode and LP mode). It can operate with or without an external PNP transistor.
In Normal mode, without external PNP, the max DC capability is 150 mA. Current limitation, temperature pre-warning flag and
overtemperature shutdown features are included. When VDD is turned ON, rise time from 0 to 5.0 V is controlled. Output voltage is 5.0 V.
A 3.3 V option is available via dedicated part number.
If current higher than 150 mA is required, an external PNP transistor must be connected to VE (PNP emitter) and VB (PNP base) pins, in
order to increase total current capability and share the power dissipation between internal VDD transistor and the external transistor. See
External transistor Q1 (VE and VB). The PNP can be used even if current is less than 150 mA, depending upon ambient temperature,
maximum supply and thermal resistance. Typically, above 100-200 mA, an external ballast transistor is recommended.
6.2.3 VDD regulator in LP mode
When the device is set in LP VDD ON mode, the VDD regulator is able to supply the MCU with a DC current below typically 1.5 mA (LP-
ITH). Transient current can also be supplied up to a tenth of a mA. Current in excess of 1.5 mA is detected, and this event is managed by
the device logic (Wake-up detection, timer start for overcurrent duration monitoring or watchdog refresh).
6.2.4 External transistor Q1 (VE and VB)
The device has a dedicated circuit to allow usage of an external “P” type transistor, with the objective to share the power dissipation
between the internal transistor of the VDD regulator and the external transistor. The recommended bipolar PNP transistor is MJD42C or
BCP52-16.
When the external PNP is connected, the current is shared between the internal path transistor and the external PNP, with the following
typical ratio: 1/3 in the internal transistor and 2/3 in the external PNP. The PNP activation and control is done by SPI.
The device is able to operate without an external transistor. In this case, the VE and VB pins must remain open.
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FUNCTIONAL DESCRIPTION
6.2.5 5 V-CAN voltage regulator for CAN and analog MUX
This regulator is supplied from the VSUP/2 pin. A capacitor is required at 5 V-CAN pin. Analog MUX and part of the LIN interfaces are
supplied from 5 V-CAN. Consequently, the 5 V-CAN must be ON in order to have Analog MUX operating and to have the LIN interface
operating in TXD/RXD mode.
The 5 V-CAN regulator is OFF by default and must be turned ON by SPI. In Debug mode, the 5 V-CAN is ON by default.
6.2.6 V auxiliary output, 5.0 and 3.3 V selectable
(VB-Aux, VC-Aux, and VCaux) - Q2
The VAUX block is used to provide an auxiliary voltage output, 5.0 or 3.3 V, selectable by the SPI. It uses an external PNP pass transistor
for flexibility and power dissipation constraints. The external recommended bipolar transistors are MJD42C or BCP52-16.
An overcurrent and undervoltage detectors are provided.
VAUX is controlled via the SPI, and can be turned ON or OFF. VAUX low threshold detection and overcurrent information will disable VAUX
,
and are reported in the SPI and can generate INT. VAUX is OFF by default and must be turned ON by the SPI.
6.2.7 Undervoltage reset and reset function (RST)
The RST pin is an open drain structure with an internal pull-up resistor. The LS driver has limited current capability when asserted low, in
order to tolerate a short to 5.0 V. The RST pin voltage is monitored in order to detect failure (e.g. RST pin shorted to 5.0 V or GND).
The RST pin reports an undervoltage condition to the MCU at the VDD pin, as a RST failure in the watchdog refresh operation. VDD
undervoltage reset also operates in LP VDD ON mode.
Two VDD undervoltage thresholds are included. The upper (typically 4.65 V, RST-TH1-5) can lead to a Reset or an Interrupt. This is selected
by the SPI. When “RST-TH2-5“is selected, in Normal mode, an INT is asserted when VDD falls below “RST-TH1-5“, then, when VDD falls
below “RST-TH2-5” a Reset will occur. This will allow the MCU to operate in a degraded mode (i.e., with 4.0 V VDD).
6.2.8 I/O pins (I/O-0: I/O-3)
I/Os are configurable input/output pins. They can be used for small loads or to drive external transistors. When used as output drivers, the
I/Os are either a HS or LS type. They can also be set to high-impedance. I/Os are controlled by the SPI and at power on, the I/Os are set
as inputs. They include overload protection by temperature or excess of a voltage drop.
When I/O-0/-1/-2/-3 voltage is greater than VSUP/2 voltage, the leakage current (II/O_LEAK) parameter is not applicable
• I/O-0 and I/O-1 will have current flowing into the device through three diodes limited by an 80 kOhm resistor (in series).
• I/O-2 and I/O-3 will have unlimited current flowing into the device through one diode.
In LP mode, the state of the I/O can be turned ON or OFF, with extremely low power consumption (except when there is a load). Protection
is disabled in LP mode. When cyclic sense is used, I/O-0 is the HS/LS switch, I/O-1, -2 and -3 are the wake inputs. I/O-2 and I/O-3 pins
share the LIN Master pin function.
6.2.9 VSENSE input (VSENSE)
This pin can be connected to the battery line (before the reverse battery protection diode), via a serial resistor and a capacitor to GND. It
incorporates a threshold detector to sense the battery voltage and provide a battery early warning. It also includes a resistor divider to
measure the VSENSE voltage via the MUX-OUT pin.
6.2.10 MUX-output (MUXOUT)
The MUX-OUT pin (Figure 22) delivers an analog voltage to the MCU A/D input. The voltage to be delivered to MUX-OUT is selected via
the SPI, from one of the following functions: VSUP/1, VSENSE, I/O-0, I/O-1, Internal 2.5 V reference, die temperature sensor, VDD current
copy.
Voltage divider or amplifier is inserted in the chain, as shown in Figure 22.
For the VDD current copy, a resistor must be added to the MUX-OUT pin, to convert current into voltage. Device includes an internal 2.0 k
resistor selectable by the SPI.
Voltage range at MUX-OUT is from GND to VDD. It is automatically limited to VDD (max 3.3 V for 3.3 V part numbers).
The MUX-OUT buffer is supplied from 5 V-CAN regulator, so the 5 V-CAN regulator must be ON in order to have:
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FUNCTIONAL DESCRIPTION
1) MUX-OUT functionality and
2) SPI selection of the analog function.
If the 5 V-CAN is OFF, the MUX-OUT voltage is near GND and the SPI command that selects one of the analog inputs is ignored.
Delay must be respected between SPI commands for 5 V-CAN turned ON and SPI to select MUX-OUT function. The delay depends
mainly upon the 5 V-CAN capacitor and load on 5 V-CAN.
The delay can be estimated using the following formula: delay = C(5 V-CAN) x U (5.0 V) / I_lim 5 V-CAN.
C = cap at 5 V-CAN regulator, U = 5.0 V,
I_LIM 5 V-CAN = min current limit of 5 V-CAN regulator (parameter 5 V-C ILIM).
Note:
As there is no link between 5VCAN and VDD, the 5VCAN can starts after both the VDD and RSTB are released. To ensure the MCU can
use MUXOUT output information, it must verify the presence of the 5VCAN. This can be done for instance by checking the 5VCAN
undervoltage flag (bit4 of the 0xDF00 SPI command).
VBAT
D1
S_in
VDD-I_COPY
Multiplexer
VSUP/1
VSENSE
S_iddc
5 V-CAN
S_in
S_in
5 V-CAN
R
1.0 k
SENSE
MCU
MUX-OUT
buffer
S_g3.3
A/D in
I/O-0
I/O-1
RM(*)
RMI
S_ir
S_g5
S_I/O_att
S_in
(*)Optional
All swicthes and resistor are configured and controlled via the SPI
R : internal resistor connected when V current monitor is used
Temp
VREF: 2.5 V
M
REG
S_g3.3 and S_g5 for 5.0 V or 3.3 V VDD versions
S_iddc to select V regulator current copy
DD
S_in1 for LP mode resistor bridge disconnection
S_ir to switch on/off of the internal R resistor
S_I/O_att for I/O-0 and I/O-1 attenuation selection
MI
S_I/O_att
Figure 22. Analog multiplexer block diagram
6.2.11 DGB (DGB) and debug mode
6.2.11.1 Primary function
It is an input used to set the device in Debug mode. This is achieved by applying a voltage between 8.0 and 10 V at the DEBUG pin and
then, powering up the device (See State diagram). When the device leaves the INIT Reset mode and enters into INIT mode, it detects the
voltage at the DEBUG pin to be between a range of 8.0 to 10 V, and activates the Debug mode.
When Debug mode is detected, no Watchdog SPI refresh commands are necessary. This allows an easy debug of the hardware and
software routines (i.e. SPI commands).
When the device is in Debug mode it is reported by the SPI flag. While in Debug mode, and the voltage at DBG pin falls below the 8.0 to
10 V range, the Debug mode is left, and the device starts the watchdog operation, and expects the proper watchdog refresh. The Debug
mode can be left by SPI. This is recommended to avoid staying in Debug mode when an unwanted Debug mode selection (FMEA pin) is
present. The SPI command has a higher priority than providing 8.0 to 10 V at the DEBUG pin.
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FUNCTIONAL DESCRIPTION
6.2.11.2 Secondary function
The resistor connected between the DBG pin and the GND selects the Fail-Safe mode operation. DBG pin can also be connected directly
to GND (this prevents the usage of Debug mode).
Flexibility is provided to select SAFE output operation via a resistor at the DBG pin or via a SPI command. The SPI command has higher
priority than the hardware selection via Debug resistor. When the Debug mode is selected, the SAFE modes cannot be configured via the
resistor connected at DBG pin.
6.2.12 SAFE
6.2.12.1 Safe output pin
This pin is an output and is asserted low when a fault event occurs. The objective is to drive electrical safe circuitry and set the ECU in a
known state, independent of the MCU and SBC, once a failure has been detected. The SAFE output structure is an open drain, without
a pull-up.
6.2.13 Interrupt (INT)
The INT output pin is asserted low or generates a low pulse when an interrupt condition occurs. The INT condition is enabled in the INT
register. The selection of low level or pulse and pulse duration are selected by SPI.
No current will flow inside the INT structure when VDD is low, and the device is in LP VDD OFF mode. This allows the connection of an
external pull-up resistor and connection of an INT pin from other ICs without extra consumption in unpowered mode.
INT has an internal pull-up structure to VDD. In LP VDD ON mode, a diode is inserted in series with the pull-up, so the high level is slightly
lower than in other modes.
6.2.14 CANH, CANL, SPLIT, RXD, TXD
These are the pins of the high speed CAN physical interface, between the CAN bus and the micro controller. A detail description is
provided in the document.
6.2.15 LIN, LIN-T, TXDL and RXDL
These are the pins of the LIN physical interface. Device contains zero, one or two LIN interfaces.
The MC33903, MC33903P, and MC33904 do not have a LIN interface. However, the MC33903S/5S (S = Single) and MC33903D/5D
(D=Dual) contain 1 and 2 LIN interfaces, respectively.
LIN, LIN1 and LIN2 pins are the connection to the LIN sub buses. LIN interfaces are connected to the MCU via the TXD, TXD-L1 and
TXD-L2 and RXD, RXD-L1 and RXD-L2 pins.
The device also includes one or two HS switches to VSUP/2 pin which can be used as a LIN master termination switch. Pins LINT, LINT-
1 and LINT-2 pins are the same as I/O-2 and I/O-3.
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FUNCTIONAL DEVICE OPERATION
7
Functional device operation
7.1
Mode and state description
The device has several operation modes. The transitions and conditions to enter or leave each mode are illustrated in the state diagram.
7.1.1 INIT reset
This mode is automatically entered after the device is “powered on”. In this mode, the RST pin is asserted low, for a duration of typically
1.0 ms. Control bits and flags are ‘set’ to their default reset condition. The BATFAIL is set to indicate the device is coming from an
unpowered condition, and all previous device configurations are lost and “reset” the default value. The duration of the INIT reset is typically
1.0 ms.
INIT reset mode is also entered from INIT mode if the expected SPI command does not occur in due time (Ref. INIT mode), and if the
device is not in the debug mode.
7.1.2 INIT
This mode is automatically entered from the INIT Reset mode. In this mode, the device must be configured via SPI within a time of 256 ms
max. Four registers called INIT Wdog, INIT REG, INIT LIN I/O and INIT MISC must be, and can only be configured during INIT mode.
Other registers can be written in this and other modes.
Once the INIT register configuration is done, a SPI Watchdog Refresh command must be sent in order to set the device into Normal mode.
If the SPI watchdog refresh does not occur within the 256 ms period, the device will return into INIT Reset mode for typically 1.0 ms, and
then re enter into INIT mode.
Register read operation is allowed in INIT mode to collect device status or to read back the INIT register configuration.
When INIT mode is left by a SPI watchdog refresh command, it is only possible to re-enter the INIT mode using a secured SPI command.
In INIT mode, the CAN, LIN1, LIN2, VAUX, I/O_x and Analog MUX functions are not operating. The 5 V-CAN is also not operating, except
if the Debug mode is detected.
7.1.3 Reset
In this mode, the RST pin is asserted low. Reset mode is entered from Normal mode, Normal Request mode, LP VDD on mode and from
the Flash mode when the watchdog is not triggered, or if a VDD low condition is detected.
The duration of reset is typically 1.0 ms by default. You can define a longer Reset pulse activation only when the Reset mode is entered
following a VDD low condition. Reset pulse is always 1.0 ms, when reset mode is entered due to wrong watchdog refresh command.
Reset mode can be entered via the secured SPI command.
7.1.4 Normal request
This mode is automatically entered after RESET mode, or after a Wake-up from LP VDD ON mode.
A watchdog refresh SPI command is necessary to transition to NORMAL mode. The duration of the Normal request mode is 256 ms when
Normal Request mode is entered after RESET mode. Different durations can be selected by SPI when normal request is entered from LP
VDD ON mode.
If the watchdog refresh SPI command does not occur within the 256 ms (or the shorter user defined time out), then the device will enter
into RESET mode for a duration of typically 1.0 ms.
Note: in init reset, init, reset and normal request modes as well as in LP modes, the VDD external PNP is disabled.
7.1.5 Normal
In this mode, all device functions are available. This mode is entered by a SPI watchdog refresh command from Normal Request mode,
or from INIT mode.
During Normal mode, the device watchdog function is operating, and a periodic watchdog refresh must occur. When an incorrect or
missing watchdog refresh command is initiated, the device will enter into Reset mode.
While in Normal mode, the device can be set to LP modes (LP VDD ON or LP VDD OFF) using the SPI command. Dedicated, secured SPI
commands must be used to enter from Normal mode to Reset mode, INIT mode or Flash mode.
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FUNCTIONAL DEVICE OPERATION
7.1.6 Flash
In this mode, the software watchdog period is extended up to typically 32 seconds. This allow programming of the MCU flash memory
while minimizing the software over head to refresh the watchdog. The flash mode is entered by Secured SPI command and is left by SPI
command. Device will enter into Reset mode. When an incorrect or missing watchdog refresh command device will enter into Reset mode.
An interrupt can be generated at 50% of the watchdog period.
CAN interface operates in Flash mode to allow flash via CAN bus, inside the vehicle.
7.1.7 Debug
Debug is a special operation mode of the device which allows for easy software and hardware debugging. The debug operation is detected
after power up if the DBG pin is set to 8.0 to 10 V range.
When debug is detected, all the software watchdog operations are disabled: 256 ms of INIT mode, watchdog refresh of Normal mode and
Flash mode, Normal Request time out (256 ms or user defined value) are not operating and will not lead to transition into INIT reset or
Reset mode.
When the device is in Debug mode, the SPI command can be sent without any time constraints with respect to the watchdog operation
and the MCU program can be “halted” or “paused” to verify proper operation.
Debug can be left by removing 8 to 10 V from the DEBUG pin, or by the SPI command (Ref. to MODE register).
The 5 V-CAN regulator is ON by default in Debug mode.
7.2
LP modes
The device has two main LP modes: LP mode with VDD OFF, and LP mode with VDD ON.
Prior to entering into LP mode, I/O and CAN Wake-up flags must be cleared (Ref. to mode register). If the Wake-up flags are not cleared,
the device will not enter into LP mode. In addition, the CAN failure flags (i.e. CAN_F and CAN_UF) must be cleared, in order to meet the
LP current consumption specification.
7.2.1 LP - VDD off
In this mode, VDD is turned OFF and the MCU connected to VDD is unsupplied. This mode is entered using SPI. It can also be entered
by an automatic transition due to fail-safe management. 5 V-CAN and VAUX regulators are also turned OFF.
When the device is in LP VDD OFF mode, it monitors external events to Wake-up and leave the LP mode. The Wake-up events can occur
from:
• CAN
• LIN interface, depending upon device part number
• Expiration of an internal timer
• I/O-0, and I/O-1 inputs, and depending upon device part number and configuration, I/O-2 and/or -3 input
• Cyclic sense of I/O-1 input, associated by I/O-0 activation, and depending upon device part number and configuration, cyclic sense
of I/O-2 and -3 input, associated by I/O-0 activation
When a Wake-up event is detected, the device enters into Reset mode and then into Normal Request mode. The Wake-up sources are
reported to the device SPI registers. In summary, a Wake-up event from LP VDD OFF leads to the VDD regulator turned ON, and the MCU
operation restart.
7.2.2 LP - VDD ON
In this mode, the voltage at the VDD pin remains at 5.0 V (or 3.3 V, depending upon device part number). The objective is to maintain the
MCU powered, with reduced consumption. In such mode, the DC output current is expected to be limited to 100 μA or a few mA, as the
ECU is in reduced power operation mode.
During this mode, the 5 V-CAN and VAUX regulators are OFF. The optional external PNP at VDD will also be automatically disabled when
entering this mode.
The same Wake-up events as in LP VDD OFF mode (CAN, LIN, I/O, timer, cyclic sense) are available in LP VDD on mode. In addition, two
additional Wake-up conditions are available.
• Dedicated SPI command. When device is in LP VDD ON mode, the Wake-up by SPI command uses a write to “Normal Request
mode”, 0x5C10.
• Output current from VDD exceeding LP-ITH threshold.
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FUNCTIONAL DEVICE OPERATION
In LP VDD ON mode, the device is able to source several tenths of mA DC. The current source capability can be time limited, by a
selectable internal timer. Timer duration is up to 32 ms, and is triggered when the output current exceed the output current threshold
typically 1.5 mA.
This allows for instance, a periodic activation of the MCU, while the device remains in LP VDD on mode. If the duration exceed the selected
time (ex 32 ms), the device will detect a Wake-up.
Wake-up events are reported to the MCU via a low level pulse at INT pulse. The MCU will detect the INT pulse and resume operation.
7.2.2.1
Watchdog function in LP V on mode
DD
It is possible to enable the watchdog function in LP VDD ON mode. In this case, the principle is timeout.
Refresh of the watchdog is done either by:
• a dedicated SPI command (different from any other SPI command or simple CS activation which would Wake-up - Ref. to the
previous paragraph)
• or by a temporary (less than 32 ms max) VDD over current Wake-up (IDD > 1.5 mA typically).
As long as the watchdog refresh occurs, the device remains in LP VDD on mode.
7.2.2.2
Mode transitions
Mode transitions are either done automatically (i.e. after a timeout expired or voltage conditions), or via a SPI command, or by an external
event such as a Wake-up. Some mode changes are performed using the Secured SPI commands.
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FUNCTIONAL DEVICE OPERATION
7.3
State diagram
V
rise > V
SUP/1
SUP-TH1
DD_UVTH
V
fall
INIT Reset
& V > V
SUP
DD
start T_
Debug
mode
detection
IR
POWER DOWN
(T_ = 1.0 ms)
IR
T_
expired
INIT
V
fall
SUP
or V <V
_
DD
DD UVTH
watchdog refresh
by SPI
T_ expired
IR
INIT
start T_
FLASH
INIT
start T_
WDF
(T_
= 256ms)
INIT
(config)
SPI secured (3)
SPI secured (3)
Ext reset
SPI secured
or T_ expired
SPI write (0x5A00)
WDF
(watchdog refresh)
or V <V
_
DD
DD UVTH
NORMAL (4)
RESET
watchdog refresh
by SPI
start T_
WDN
start T_
R
(1.0 ms or config)
V
<V
_
or T_
expired
WD
DD
DD UVTH
(T_
= config)
WDN
or watchdog failure (1) or SPI secured
or VDD T
Wake-up
SD
SPI write (0x5A00)
(watchdog refresh)
T_ expired
NR
T_ expired
R
& V >V
_
DD
DD UVTH
NORMAL
REQUEST
SPI
start T_
(256 ms or config)
if enable
watchdog refresh
by SPI
NR
LP
VDD ON
Wake-up (5)
start T_
(2)
T_ expired
OC
WDL
or Wake-up
I- <I
DD OC
(1.5 mA)
I- >I
(1.5 mA)
DD OC
LP VDDON
IDD > 1.5 mA
V
<V
_
DD UVTHLP
start T_ time
DD
OC
T_
expired or V <V
DD
_
DD UVTHLP
WDL
SPI
LP
VDD OFF
FAIL-SAFE DETECTED
(1) watchdog refresh in closed window or enhanced watchdog refresh failure
(2) If enable by SPI, prior to enter LP V ON mode
DD
(3) Ref. to “SPI secure” description
(4) V external PNP is disable in all mode except Normal and Flash modes.
DD
(5) Wake-up from LP V ON mode by SPI command is done by a SPI mode change: 0X5C10
DD
Figure 23. State diagram
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FUNCTIONAL DEVICE OPERATION
7.4
Mode change
7.4.1 ‘Secured SPI’ description
A request is done by a SPI command, the device provide on MISO an unpredictable ‘random code’. Software must perform a logical
change on the code and return it to the device with the new SPI command to perform the desired action.
The ‘random code’ is different at every exercise of the secured procedure and can be read back at any time.
The secured SPI uses the Special MODE register for the following transitions:
- from Normal mode to INT mode
- from Normal mode to Flash mode
- from Normal mode to Reset mode (reset request).
“Random code” is also used when the ‘advance watchdog’ is selected.
7.4.2 Changing of device critical parameters
Some critical parameters are configured one time at device power on only, while the batfail flag is set in the INIT mode. If a change is
required while device is no longer in INIT mode, device must be set back in INIT mode using the “SPI secure” procedure.
7.5
Watchdog operation
7.5.1 In normal request mode
In Normal Request mode, the device expects to receive a watchdog configuration before the end of the normal request time out period.
This period is reset to a long (256 ms) after power on and when BATFAIL is set.
The device can be configured to a different (shorter) time out period which can be used after Wake-up from LP VDD on mode.
After a software watchdog reset, the value is restored to 256 ms, in order to allow for a complete software initialization, similar to a device
power up. In Normal Request mode the watchdog operation is “timeout” only and can be triggered/observed any time within the period.
7.5.2 Watchdog type selection
Three types of watchdog operation can be used:
- Window watchdog (default)
- Timeout operation
- Advanced
The selection of watchdog is performed in INIT mode. This is done after device power up and when the BATFAIL flag is set. The Watchdog
configuration is done via the SPI, then the Watchdog mode selection content is locked and can be changed only via a secured SPI
procedure.
7.5.2.1
Window watchdog operation
The window watchdog is available in Normal mode only. The watchdog period selection can be kept (SPI is selectable in INIT mode),
while the device enters into LP VDD ON mode. The watchdog period is reset to the default long period after BATFAIL.
The period and the refresh of watchdog are done by the SPI. A refresh must be done in the open window of the period, which starts at
50% of the selected period and ends at the end of the period.
If the watchdog is triggered before 50%, or not triggered before end of period, a reset has occurred. The device enters into Reset mode.
7.5.2.2
Watchdog in debug mode
When the device is in Debug mode (entered via the DBG pin), the watchdog continues to operate but does not affect the device operation
by asserting a reset. For the user, operation appears without the watchdog.
When Debug mode is left by software (SPI mode reg), the watchdog period starts at the end of the SPI command.
When Debug mode is left by hardware (DBG pin below 8-10 V), the device enters into Reset mode.
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FUNCTIONAL DEVICE OPERATION
7.5.2.3
Watchdog in flash mode
During Flash mode, watchdog can be set to a long timeout period. Watchdog is timeout only and an INT pulse can be generated at 50%
of the time window.
7.5.2.4
Advance watchdog operation
When the Advance watchdog is selected (at INIT mode), the refresh of the watchdog must be done using a random number and with 1,
2, or 4 SPI commands. The number for the SPI command is selected in INIT mode.
The software must read a random byte from the device, and then must return the random byte inverted to clear the watchdog. The random
byte write can be performed in 1, 2, or 4 different SPI commands.
If one command is selected, all eight bits are written at once.
If two commands are selected, the first write command must include four of the eight bits of the inverted random byte. The second
command must include the next four bits. This completes the watchdog refresh.
If four commands are selected, the first write command must include two of the eight bits of the inverted random byte. The second
command must include the next two bits, the 3rd command must include the next two, and the last command, must include the last two.
This completes the watchdog refresh. When multiple writes are used, the most significant bits are sent first. The latest SPI command
needs to be done inside the open window time frame, if window watchdog is selected.
7.5.3 Detail SPI operation and SPI commands for all watchdog types.
All SPI commands and examples do not use parity functions.
In INIT mode, the watchdog type (window, timeout, advance and number of SPI commands) is selected using the register Init watchdog,
bits 1, 2 and 3. The watchdog period is selected using the TIM_A register. The watchdog period selection can also be done in Normal
mode or in Normal Request mode.
Transition from INIT mode to Normal mode or from Normal Request mode to Normal mode is done using a single watchdog refresh
command (SPI 0x 5A00).
While in Normal mode, the Watchdog Refresh Command depends upon the watchdog type selected in INIT mode. They are detailed in
the paragraph below:
7.5.3.1
Simple watchdog
The Refresh command is 0x5A00. It can be send any time within the watchdog period, if the timeout watchdog operation is selected (INIT-
watchdog register, bit 1 WD N/Win = 0). It must be send in the open window (second half of the period) if the Window Watchdog operation
was selected (INIT-watchdog register, bit 1 WD N/Win = 1).
7.5.3.2
Advance watchdog
The first time the device enters into Normal mode (entry on Normal mode using the 0x5A00 command), Random (RNDM) code must be
read using the SPI command, 0x1B00. The device returns on MISO second byte the RNDM code. The full 16 bits MISO is called 0x XXRD.
RD is the complement of the RD byte.
7.5.3.3
Advance watchdog, refresh by 1 SPI command
The refresh command is 0x5ARD. During each refresh command, the device will return on MISO, a new Random Code. This new Random
Code must be inverted and send along with the next refresh command. It must be done in an open window, if the Window operation was
selected.
7.5.3.4
Advance watchdog, refresh by two SPI commands
The refresh command is split in two SPI commands.
The first partial refresh command is 0x5Aw1, and the second is 0x5Aw2. Byte w1 contains the first four inverted bits of the RD byte plus
the last four bits equal to zero. Byte w2 contains four bits equal to zero plus the last four inverted bits of the RD byte.
During this second refresh command the device returns on MISO a new Random Code. This new random code must be inverted and send
along with the next two refresh commands and so on. The second command must be done in an open window if the Window operation
was selected.
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FUNCTIONAL DEVICE OPERATION
7.5.3.5
Advance watchdog, refresh by four SPI commands
The refresh command is split into four SPI commands.
The first partial refresh command is 0x5Aw1, the second is 0x5Aw2, the third is 0x5Aw3, and the last is 0x5Aw4.
Byte w1 contains the first two inverted bits of the RD byte, plus the last six bits equal to zero.
Byte w2 contains two bits equal to zero, plus the next two inverted bits of the RD byte, plus four bits equal to zero.
Byte w3 contains four bits equal to zero, plus the next two inverted bits of the RD byte, plus two bits equal to zero.
Byte w4 contains six bits equal to zero, plus the next two inverted bits of the RD byte.
During this fourth refresh command, the device will return, on MISO, a new Random Code. This new Random Code must be inverted and
send along with the next four refresh commands.
The fourth command must be done in an open window if the Window operation was selected.
7.5.4 Proper response to INT
During a device detect upon an INT, the software handles the INT in a timely manner: Access of the INT register is done within two
watchdog periods. This feature must be enabled by SPI using the INIT watchdog register bit 7.
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NXP Semiconductors
FUNCTIONAL DEVICE OPERATION
7.6
Functional block operation versus mode
Table 8. Device block operation for each state
State
VDD
5 V-CAN
I/O-X
VAUX
CAN
LIN1/2
Power down
OFF
OFF
OFF
OFF
High-impedance
High-impedance
OFF:
internal 30 k pull-up
active. Transmitter:
receiver / Wake-up OFF.
OFF:
HS/LS off
Wake-up disable
CAN termination 25 k to GND
Transmitter / receiver /Wake-up
OFF
Init Reset
ON
OFF
OFF
LIN term OFF
INIT
Reset
ON
ON
ON
OFF (38)
OFF
OFF
OFF
OFF
OFF
OFF
OFF
WU disable
(39)(40)(41)
Keep SPI
config
OFF
OFF
WU disable
(39)(40)(41)
Keep SPI
config
Normal Request
WU disable
(39)(40)(41)
SPI config
WU SPI config
Normal
ON
OFF
SPI config
OFF
SPI config
OFF
SPI config
SPI config
user defined
WU SPI config
LP VDD OFF
LP VDD ON
OFF + Wake-up en/dis
OFF + Wake-up en/dis
OFF + Wake-up en/dis
OFF + Wake-up en/dis
user defined
WU SPI config
ON(37)
OFF
OFF
safe case
A:ON
safe case B:
OFF
HS/LS off
Wake-up by
change state
SAFE output low:
Safe case A
A: Keep SPI
config, B: OFF
OFF
OFF
OFF + Wake-up enable
SPI config
OFF + Wake-up enable
OFF
FLASH
ON
SPI config
SPI config
Notes
37. With limited current capability
38. 5 V-CAN is ON in Debug mode.
39. I/O-0 and I/O-1, configured as an output high-side switch and ON in Normal mode will remain ON in RESET, INIT or Normal Request.
40. I/O-0, configured as an output low-side switch and ON in Normal mode will turn OFF when entering Reset mode, resume operation in Normal
mode.
41. I/O-1, configured as an output low-side switch and ON in Normal mode will remain ON in RESET, INIT or Normal Request.
The 5 V-CAN default is ON when the device is powered-up and set in Debug mode. It is fully controllable via the SPI command.
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FUNCTIONAL DEVICE OPERATION
7.7
Illustration of device mode transitions
Normal to LP
ON Mode
Normal to LP
OFF Mode
Power up to Normal Mode
V
DD
A
V
D
B
C
B
B
DD
V
V
V
>4.0 V
SUP
SUP
SUP
V
V
(4.5 V typically)
DD-UV
DD-UV
V
V
V
DD
DD
DD
5V-CAN
VAUX
RST
5V-CAN
VAUX
5V-CAN
VAUX
RST
RST
INT
SPI
INT
SPI
INT
SPI
NORMAL
NORMAL
LP VDD OFF
LP VDD On
MODE
NORMAL
RESET
INIT
BATFAIL
s_2: go to LP V
OFF mode
s_1: go to Normal mode
s_11: write INT registers
s_3: go to LP mode
s_13: LP Mode configuration
DD
s_12: LP Mode configuration
legend:
Series of SPI
Single SPI
Figure 24. Power up normal and LP modes
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NXP Semiconductors
FUNCTIONAL DEVICE OPERATION
Wake-up from LP V ON Mode
Wake-up from LP V OFF Mode
DD
D
C
DD
V
V
SUP
SUP
V
(4.5 V typically)
DD-UV
V
V
DD
DD
Based on reg configuration
Based on reg configuration
Based on reg configuration
Based on reg configuration
5V-CAN
VAUX
5V-CAN
VAUX
RST
RST
INT
SPI
INT
SPI
NORMAL
REQUEST
NORMAL
REQUEST
LP V _OFF
DD
MODE
MODE
RESET
NORMAL
LP V ON
NORMAL
DD
CAN bus
LIN Bus
CAN bus
LIN Bus
CAN Wake-up
pattern
CAN Wake-up
pattern
LIN Wake-up filter
LIN Wake-up filter
I/O-x toggle
FWU timer
I/O-x toggle
FWU timer
.
Start
Stop
Start
FWU timer
FWU timer
duration (50-8192 ms)
SPI selectable
duration (50-8192 ms)
SPI selectable
I
current
SPI
I
(3.0 mA typically)
DD
DD-OC
Wake-up detected
I
deglitcher or timer (100 us typically, 3 -32 ms)
Wake-up detected
D OC
Figure 25. Wake-up from LP modes
7.8
Cyclic sense operation during LP modes
This function can be used in both LP modes: VDD OFF and VDD ON.
Cyclic sense is the periodic activation of I/O-0 to allow biasing of external contact switches. The contact switch state can be detected via
I/O-1, -2, and -3, and the device can Wake-up from either LP mode. Cyclic sense is optimized and designed primarily for closed contact
switch in order to minimize consumption via the contact pull-up resistor.
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FUNCTIONAL DEVICE OPERATION
7.8.1 Principle
A dedicated timer provides an opportunity to select a cyclic sense period from 3.0 to 512 ms (selection in timer B).
At the end of the period, the I/O-0 will be activated for a duration of T_CSON (SPI selectable in INIT register, to 200 μs, 400 μs, 800 μs, or
1.6 ms). The I/O-0 HS transistor or LS transistor can be activated. The selection is done by the state of I/O-0 prior to entering in LP mode.
During the T-CSON duration, the I/O-x’s are monitored. If one of them is high, the device will detect a Wake-up. (Figure 26).
Cyclic sense period is selected by the SPI configuration prior to entering LP mode. Upon entering LP mode, the I/O-0 should be activated.
The level of I/O-1 is sense during the I/O-0 active time, and is deglitched for a duration of typically 30 μs. This means that I/O-1 should be
in the expected state for a duration longer than the deglitch time. The diagram below (Figure 26) illustrates the cyclic sense operation,
with I/O-0 HS active and I/O-1 Wake-up at high level.
I/O-0 HS active in Normal mode
I/O-0 HS active during cyclic sense active time
I/O-0
Zoom
S1
S1 closed
S1 open
Cyclic sense active
time (ex 200 us)
I/O-1
I/O-0
I/O-1
I/O-1 high => Wake-up
Cyclic sense period
state of I/O-1 low => no Wake-up
I/O-1 deglitcher time
(typically 30 us)
Cyclic sense active time
Wake-up event detected
NORMAL MODE
LP MODE
RESET or NORMAL REQUEST MODE
Wake-up detected.
R
R
R
R
R
R
I/O-0
I/O-0
I/O-1
I/O-2
I/O-3
I/O-1
I/O-2
I/O-3
S1
S1
S2
S2
S3
S3
Upon entering in LP mode, all 3
contact switches are closed.
In LP mode, 1 contact switch is open.
High level is detected on I/O-x, and device wakes up.
Figure 26. Cyclic sense operation - switch to GND, wake-up by open switch
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FUNCTIONAL DEVICE OPERATION
7.9
Cyclic INT operation during LP VDD on mode
7.9.1 Principle
This function can be used only in LP VDD ON mode (LP VDD ON). When Cyclic INT is selected and device is in LP VDD ON mode, the
device will generate a periodic INT pulse.
Upon reception of the INT pulse, the MCU must acknowledge the INT by sending SPI commands before the end of the next INT period
in order to keep the process going.
When Cyclic INT is selected and operating, the device remains in LP VDD ON mode, assuming the SPI commands are issued properly.
When no/improper SPI commands are sent, the device will cease Cyclic INT operation and leave LP VDD ON mode by issuing a reset.
The device will then enter into Normal Request mode. VDD current capability and VDD regulator behavior is similar as in LP VDD ON
mode.
7.9.1.1
Operation
Cyclic INT period selection: register timer B
SPI command in hex 0x56xx [example; 0x560E for 512ms cyclic Interrupt period (SPI command without parity bit)].
This command must be send while the device is in Normal mode.
SPI commands to acknowledge INT: (2 commands)
- read the Random code via the watchdog register address using the following command: MOSI 0x1B00 device report on MISO second
byte the RNDM code (MISO bit 0-7).
- write watchdog refresh command using the random code inverted: 0x5A RNDb.
These commands can occur at any time within the period.
Initial entry in LP mode with Cyclic INT: after the device is set in LP VDD ON mode, with cyclic INT enable, no SPI command is necessary
until the first INT pulse occurs. The acknowledge process must start only after the 1st INT pulse.
Leave LP mode with Cyclic INT:
This is done by a SPI Wake-up command, similar to SPI Wake-up from LP VDD ON mode: 0x5C10. The device will enter into Normal
Request mode.
Improper SPI command while Cyclic INT operates:
When no/improper SPI commands are sent, while the device is in LP VDD ON mode with Cyclic INT enable, the device will cease Cyclic
INT operation and leave LP VDD ON mode by issuing a reset. The device will then enter into Normal Request mode.
Figure 27 describes the complete Cyclic Interrupt operation.
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FUNCTIONAL DEVICE OPERATION
Prepare LP V
with Cyclic INT
ON
Leave LP
ON Mode
DD
In LP V
DD
ON with Cyclic INT
V
DD
INT
LP V
ON mode
DD
SPI
Timer B
Cyclic INT period
1st period
Cyclic INT period
3rd period
Cyclic INT period
2nd period
Cyclic INT period
NORMAL
REQUEST
MODE
NORMAL MODE
LP V
ON MODE
DD
Legend for SPI commands
Write Timer B, select Cyclic INT period (ex: 512 ms, 0x560E)
Leave LP V
ON and Cyclic INT due to improper operation
DD
INT
Write Device mode: LP V
ON with Cyclic INT enable (example: 0x5C90)
DD
Improper or no
acknowledge SPI command
Read RNDM code
SPI
Write RNDM code inv.
SPI Wake-up: 0x5C10
RST
Cyclic INT period
RESET and
NORMAL
REQUEST
MODE
LP V
ON MODE
DD
Figure 27. Cyclic interrupt operation
7.10 Behavior at power up and power down
7.10.1 Device power up
This section describe the device behavior during ramp up, and ramp down of VSUP/1, and the flexibility offered mainly by the Crank bit and
the two VDD undervoltage reset thresholds.
The figures below illustrate the device behavior during VSUP/1 ramp up. As the Crank bit is by default set to 0, VDD is enabled when
VSUP/1 is above VSUP TH 1 parameters.
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FUNCTIONAL DEVICE OPERATION
V
(ex 12 V)
SUP_NOMINAL
V
(ex 5.0 V)
DD NOMINAL
V
slew rate
SUP
VBAT
V
(typically 4.65 V)
DD_UV TH
D1
V
VSUP/1
VDD
SUP_TH1
3390X
V
DD_START UP
90% V
I_VDD
DD_START UP
VSUP/1
Gnd
10% V
DD_OFF
DD_START UP
VDD
RST
V
1.0 ms
Figure 28. VDD start-up versus VSUP/1 tramp
7.10.2 Device power down
The figures below illustrate the device behavior during VSUP/1 ramp down, based on Crank bit configuration, and VDD undervoltage reset
selection.
7.10.2.1 Crank bit reset (INIT watchdog register, Bit 0 =0)
Bit 0 = 0 is the default state for this bit.
During VSUP/1 ramp down, VDD remain ON until device enters in Reset mode due to a VDD undervoltage condition (VDD < 4.6 V or VDD
3.2 V typically, threshold selected by the SPI). When device is in Reset, if VSUP/1 is below “VSUP_TH1”, VDD is turned OFF.
<
7.10.2.2 Crank bit set (INIT watchdog register, Bit 0 =1)
The bit 0 is set by SPI write. During VSUP/1 ramp down, VDD remains ON until device detects a POR and set BATFAIL. This occurs for a
VSUP/1 approx 3.0 V.
V
BAT
V
BAT
V
SUP_NOMINAL
(ex 12 V)
V
SUP_NOMINAL
(ex 12 V)
V
(4.1V)
SUP_TH1
V
(4.1V)
VSUP1
SUP_TH1
VSUP1
minV
(2.8 V)
SUP
VDD
V
(3.3 V)
DD
VDD
V
(3.3 V)
DD
V
(typ 3.0 V)
DD_UV TH
V
(typ 3.0 V)
DD_UV TH
RESET
RESET
Case 1: VDD 3.3V, “VDD UV TH 3.0 V”,
with bit Crank =0 (default value)
Case 2: VDD 3.3V, “VDD UV TH 3.0 V”, with bit Crank =1
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FUNCTIONAL DEVICE OPERATION
V
V
BAT
BAT
V
V
SUP_NOMINAL
(ex 12 V)
SUP_NOMINAL
(ex 12 V)
VSUP/1
VSUP/1
V
(5.0 V)
V
(5.0 V)
DD
DD
V
(4.1 V)
SUP_TH1
V
(typically 4.65 V)
V
(typically 4.65 V)
DD_UV TH
DD_UV TH
BATFAIL (3.0 V)
VDD
VDD
RST
RST
Case 3: “VDD UV TH 4.6V”, with bit Crank = 0 (default value)
Case 4: “VDD UV 4.6V”, with bit Crank = 1
V
V
BAT
BAT
V
V
SUP_NOMINAL
(ex 12 V)
SUP_NOMINAL
(ex 12 V)
VSUP/1
VSUP/1
V
(4.1 V)
SUP_TH1
V
(5.0 V)
V
(5.0 V)
DD
DD
V
(typically 4.65 V)
V
(typically 4.65 V)
BATFAIL (3.0 V)
DD_UV TH
DD_UV TH
VDD
VDD
V
(typically 3.2 V)
V
(typically 3.2 V)
DD_UV TH2
DD_UV TH2
(2)
INT
INT
RST
RST
(1)
(1) reset then (2) V turn OFF
DD
Case 6: “VDD UV 3.2V”, with bit Crank = 1
Case 5: “VDD UV TH 3.2V”, with bit Crank = 0 (default value)
Figure 29. VDD behavior during VSUP/1 ramp down
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FUNCTIONAL DEVICE OPERATION
7.11 Fail-safe operation
7.11.1 Overview
Fail-safe mode is entered when specific fail conditions occur. The ‘Safe state’ condition is defined by the resistor connected at the DGB
pin. Safe mode is entered after additional event or conditions are met: time out for CAN communication and state at I/O-1 pin.
Exiting the safe state is always possible by a Wake-up event: in the safe state, the device can automatically be awakened by CAN and
I/O (if configured as inputs). Upon Wake-up, the device operation is resumed: enter in Reset mode.
7.11.2 Fail-safe functionality
Upon dedicated event or issue detected at a device pin (i.e. RST short to VDD), the Safe mode can be entered. In this mode, the SAFE
pin is active low.
7.11.2.1 Description
Upon activation of the SAFE pin, and if the failure condition that make the SAFE pin activated have not recovered, the device can help
to reduce ECU consumption, assuming that the MCU is not able to set the whole ECU in LP mode. Two main cases are available:
7.11.2.2 Mode A
Upon SAFE activation, the MCU remains powered (VDD stays ON), until the failure condition recovers (i.e. S/W is able to properly
control the device and properly refresh the watchdog).
7.11.2.3 Modes B1, B2 and B3
Upon SAFE activation, the system continues to monitor external event, and disable the MCU supply (turn VDD OFF). The external
events monitored are: CAN traffic, I/O-1 low level or both of them. 3 sub cases exist, B1, B2 and B3.
Note: no CAN traffic indicates that the ECU of the vehicle are no longer active, thus that the car is being parked and stopped. The I/O low
level detection can also indicate that the vehicle is being shutdown, if the I/O-1 pin is connected for instance to a switched battery signal
(ignition key on/off signal).
The selection of the monitored events is done by hardware, via the resistor connected at DBG pin, but can be over written by software,
via a specific SPI command.
By default, after power up the device detect the resistor value at DBG pin (upon transition from INIT to Normal mode), and, if no specific
SPI command related to Debug resistor change is send, operates according to the detected resistor.
The INIT MISC register allow you to verify and change the device behavior, to either confirm or change the hardware selected behavior.
Device will then operate according to the SAFE mode configured by the SPI.
Table 9 illustrates the complete options available:
Table 9. Fail-safe options
Resistor at
DBG pin
SPI coding - register INIT MISC bits [2,1,0]
(higher priority that Resistor coding)
Safe mode
code
V
status
DD
bits [2,1,0) = [111]: verification enable: resistor at DBG pin is
typically 0 kohm (RA) - Selection of SAFE mode A
<6.0 k
A
remains ON
bits [2,1,0) = [110]: verification enable: resistor at DBG pin is
typically 15 kohm (RB1) - Selection of SAFE mode B1
Turn OFF 8.0 s after CAN traffic bus idle
detection.
typically 15 k
typically 33 k
typically 68 k
B1
B2
B3
bits [2,1,0) = [101]: verification enable: resistor at DBG pin is
typically 33 kohm (RB2 - Selection of SAFE mode B2
Turn OFF when I/O-1 low level detected.
bits [2,1,0) = [100]: verification enable: resistor at DBG pin is
typically 68 kohm (RB3) - Selection of SAFE mode B3
Turn OFF 8.0 s after CAN traffic bus idle
detection AND when I/O-1 low level detected.
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FUNCTIONAL DEVICE OPERATION
7.11.2.4 Exit of safe mode
Exit of the safe state with VDD OFF is always possible by a Wake-up event: in this safe state the device can automatically awakened by
CAN and I/O (if I/O Wake-up was enable by the SPI prior to enter into SAFE mode). Upon Wake-up, the device operation is resumed, and
device enters in Reset mode. The SAFE pin remains active, until there is a proper read and clear of the SPI flags reporting the SAFE
conditions.
.
SAFE Operation Flow Chart
Legend:
Failure events
Device state:
RESET
NR
RESET
detection of 2nd
bit 4, INIT watchdog = 1 (1)
bit 4, INIT watchdog = 0 (1)
consecutive watchdog failure
SAFE high
SAFE low
Reset: 1.0 ms pulse
Reset: 1.0 ms pulse
(6)
SAFE low
8 consecutive watchdog failure (5
- SAFE low
- V ON
- Reset: 1.0 ms
periodic pulse
DD
State A: R
watchdog failure
<6.0 k AND
DBG
SAFE pin release
(SAFE high)
a) Evaluation of
watchdog failure
State A: R <6.0 k AND
Resistor detected
at DBG pin during
power up, or SPI
DBG
- SAFE low
(V low or R s/c GND) failure
DD
ST
- V ON
DD
SPI (3)
- Reset low
V
low:
<V
DD
State B1: R
= 15 k AND
DBG
register content
V
_
Bus idle timeout expired
DD
DD UVTH
INIT,
Normal Request
Normal, FLASH
State B2:
b) ECU external signal
monitoring (7):
- Reset low
- SAFE low
- Reset low
- V OFF
DD
R
= 33 k AND I/O-1 low
DBG
- SAFE low
- bus idle time out
- I/O-1 monitoring
State B3:
- V ON
DD
R
=
DBG 47 k AND I/O-1 low
Rst s/c GND:
Rst <2.5 V, t >100 ms
AND Bus idle time out expired
Wake-up (2), V ON, SAFE pin remains low
DD
RESET
failure recovery, SAFE pin remains low
1) bit 4 of INIT Watchdog register
2) Wake-up event: CAN, LIN or I/O-1 high level (if I/O-1 Wake-up previously enabled)
3) SPI commands: 0x1D80 or 0xDD80 to release SAFE pin
4) Recovery: reset low condition released, V low condition released, correct SPI watchdog refresh
DD
5) detection of 8 consecutive watchdog failures: no correct SPI watchdog refresh command occurred for duration of 8 x 256 ms.
6) Dynamic behavior: 1.0 ms reset pulse every 256 ms, due to no watchdog refresh SPI command, and device state transition
between RESET and NORMAL REQUEST mode, or INIT RESET and INIT modes.
7) 8 second timer for bus idle timeout. I/O-1 high to low transition.
Figure 30. Safe operation flow chart
7.11.2.5 Conditions to set SAFE pin active low
Watchdog refresh issue: SAFE activated at 1st reset pulse or at the second consecutive reset pulse (selected by bit 4, INIT watchdog
register).
VDD low: VDD < RST-TH. SAFE pin is set low at the same time as the RST pin is set low. The RST pin is monitored to verify that reset is not
clamped to a low level preventing the MCU to operate. If this is the case, the Safe mode is entered.
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FUNCTIONAL DEVICE OPERATION
7.11.2.6 SAFE mode A illustration
Figure 31 illustrates the event and consequences when SAFE mode A is selected via the appropriate debug resistor or SPI configuration.
Behavior Illustration for Safe State A (R < 6.0 kohm), or Selection by the SPI
DG
step 2: Consequence on
step 1: Failure illustration
V
, RST and SAFE
DD
V
DD
V
DD
failure event, i.e. watchdog
8th
2nd
1st
RST
SAFE
RST
SAFE
ON state
OFF state
8 x 256 ms delay time to enter in SAFE mode
to evaluate resistor at DBG pin
and monitor ECU external events
failure event, V low
DD
V
DD_UV TH
V
V
V
<
DD
DD_UV TH
DD
V
DD
GND
GND
RST
RST
SAFE
ON state
OFF state
SAFE
100ms
100 ms delay time to enter in SAFE mode
to evaluate resistor at DBG pin
and monitor ECU external events
failure event, Reset s/c GND
V
DD
V
DD
RST
2.5 V
RST
SAFE
ON state
OFF state
SAFE
100ms
100 ms deglitcher time to activate SAFE and
enter in SAFE mode to evaluate resistor at the DBG pin
and monitor ECU external events
Figure 31. SAFE mode A behavior illustration
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53
FUNCTIONAL DEVICE OPERATION
7.11.2.7 SAFE mode B1, B2 and B3 illustration
Figure 32 illustrates the event, and consequences when SAFE mode B1, B2, or B3 is selected via the appropriate debug resistor or SPI
configuration.
Behavior illustration for the safe state B (RDG > 10 kohm)
CAN bus
DBG resistor => safe state B1
step 2:
CAN bus idle time
Exclusive detection of
ECU external event to
disable VDD based on
I/O-1
I/O-1 high to low transition
DBG resistor => safe state B2
RDBG resistor or
SPI configuration
CAN bus
DBG resistor => safe state B3
CAN bus idle time
I/O-1
I/O-1 high to low transition
step 1: Failure illustration
Consequences for V
step 3:
DD
VDD
VDD
failure event, i.e. watchdog
8th
2nd
1st
RST
RST
SAFE
ON state
OFF state
SAFE
8 x 256 ms delay time to enter in SAFE mode
to evaluate resistor at the DBG pin
and monitor ECU external events
failure event, VDD low
If VDD failure recovered
VDD
GND
VDD < VDD_UV TH
VDD_UV TH
VDD
GND
VDD OFF
RST
RST
SAFE
SAFE
ON state
OFF state
100 ms
100 ms delay time to enter in SAFE mode
to evaluate resistor at DBG pin
and monitor ECU external events
If Reset s/c GND recovered
VDD OFF
failure event, Reset s/c GND
VDD
VDD
2.5 V
RST
RST
SAFE
ON state
OFF state
SAFE
100 ms
100 ms deglitcher time to activate SAFE and
enter in SAFE mode to evaluate resistor at DBG pin
and monitor ECU external events
Figure 32. SAFE modes B1, B2, or B3 behavior illustration
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CAN INTERFACE
8
CAN interface
8.1
CAN interface description
The figure below is a high level schematic of the CAN interface. It exist in a LS driver between CANL and GND, and a HS driver from
CANH to 5 V-CAN. Two differential receivers are connected between CANH and CANL to detect a bus state and to Wake-up from CAN
Sleep mode. An internal 2.5 V reference provides the 2.5 V recessive levels via the matched RIN resistors. The resistors can be switched
to GND in CAN Sleep mode. A dedicated split buffer provides a low-impedance 2.5 V to the SPLIT pin, for recessive level stabilization.
VSUP/2
Pattern
Wake-up
Receiver
SPI & State machine
Detection
5 V-CAN
Driver
QH
R
R
IN
2.5 V
CANH
CANL
Differential
Receiver
RXD
TXD
IN
5 V-CAN
Driver
QL
Thermal
SPI & State machine
SPI & State machine
5 V-CAN
Failure Detection
& Management
Buffer
SPLIT
Figure 33. CAN interface block diagram
8.1.1 Can interface supply
The supply voltage for the CAN driver is the 5 V-CAN pin. The CAN interface also has a supply pass from the battery line through the
VSUP/2 pin. This pass is used in CAN Sleep mode to allow Wake-up detection.
During CAN communication (transmission and reception), the CAN interface current is sourced from the 5 V-CAN pin. During CAN LP
mode, the current is sourced from the VSUP/2 pin.
8.1.2 TXD/RXD mode
In TXD/RXD mode, both the CAN driver and the receiver are ON. In this mode, the CAN lines are controlled by the TXD pin level and the
CAN bus state is reported on the RXD pin.
The 5 V-CAN regulator must be ON. It supplies the CAN driver and receiver.The SPLIT pin is active and a 2.5 V biasing is provided on
the SPLIT output pin.
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CAN INTERFACE
8.1.2.1
Receive only mode
This mode is used to disable the CAN driver, but leave the CAN receiver active. In this mode, the device is only able to report the CAN
state on the RXD pin. The TXD pin has no effect on CAN bus lines. The 5 V-CAN regulator must be ON. The SPLIT pin is active and a
2.5 V biasing is provided on the SPLIT output pin.
8.1.2.2
Operation in TXD/RXD mode
The CAN driver will be enabled as soon as the device is in Normal mode and the TXD pin is recessive.
When the CAN interface is in Normal mode, the driver has two states: recessive or dominant. The driver state is controlled by the TXD
pin. The bus state is reported through the RXD pin.
When TXD is high, the driver is set in the recessive state, and CANH and CANL lines are biased to the voltage set with 5 V-CAN divided
by 2, or approx. 2.5 V.
When TXD is low, the bus is set into the dominant state, and CANL and CANH drivers are active. CANL is pulled low and CANH is pulled
high.
The RXD pin reports the bus state: CANH minus the CANL voltage is compared versus an internal threshold (a few hundred mV).
If “CANH minus CANL” is below the threshold, the bus is recessive and RXD is set high.
If “CANH minus CANL” is above the threshold, the bus is dominant and RXD is set low.
The SPLIT pin is active and provides a 2.5 V biasing to the SPLIT output.
8.1.2.3
TXD/RXD mode and slew rate selection
The CAN signal slew rate selection is done via the SPI. By default and if no SPI is used, the device is in the fastest slew rate. Three slew
rates are available. The slew rate controls the recessive to dominant, and dominant to recessive transitions. This also affects the delay
time from the TXD pin to the bus and from the bus to the RXD. The loop time is thus affected by the slew rate selection.
8.1.2.4
Minimum baud rate
The minimum baud rate is determined by the shortest TXD permanent dominant timing detection. The maximum number of consecutive
dominant bits in a frame is 12 (6 bits of active error flag and its echo error flag).
The shortest TXD dominant detection time of 300 μs lead to a single bit time of: 300 μs / 12 = 25 μs.
So the minimum Baud rate is 1 / 25 μs = 40 kBaud.
8.1.2.5
Sleep mode
Sleep mode is a reduced current consumption mode. CANH and CANL drivers are disabled and CANH and CANL lines are terminated
to GND via the RIN resistor, the SPLIT pin is high-impedance. In order to monitor bus activities, the CAN Wake-up receiver can be enabled.
It is supplied internally from VSUP/2
.
Wake-up events occurring on the CAN bus pin are reporting by dedicated flags in SPI and by INT pulse, and results in a device Wake-up
if the device was in LP mode. When the device is set back into Normal mode, CANH and CANL are set back into the recessive level. This
is illustrated in Figure 34.
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CAN INTERFACE
.
TXD
Dominant state
CANH-DOM
Recessive state
CANH
CANL
CANL/CANH-REC
CANH-CANL
2.5 V
CANL-DOM
High ohmic termination (50 kohm) to GND
RXD
2.5 V
SPLIT
High-impedance
Go to sleep,
Bus Driver
Receiver
(bus dominant set by other IC)
Normal or Listen Only mode
Sleep or Stand-by mode
Normal or Listen Only mode
Figure 34. Bus signal in TXD/RXD and LP mode
8.1.2.6
Wake-up
When the CAN interface is in Sleep mode with Wake-up enabled, the CAN bus traffic is detected. The CAN bus Wake-up is a pattern
Wake-up. The Wake-up by the CAN is enabled or disabled via the SPI.
CAN
bus
CANH
Dominant
Pulse # 2
Dominant
Pulse # 1
CANL
Internal differential Wake-up receiver signal
Internal Wake-up signal
Can Wake-up detected
t
CAN WU1-F
Figure 35. Single dominant pulse wake-up
8.1.2.7
Pattern wake-up
In order to Wake-up the CAN interface, the Wake-up receiver must receive a series of three consecutive valid dominant pulses, by
default when the CANWU bit is low. CANWU bit can be set high by SPI and the Wake-up will occur after a single pulse duration of 2.0 μs
(typically). A valid dominant pulse should be longer than 500 ns. The three pulses should occur in a time frame of 120 μs, to be considered
valid. When three pulses meet these conditions, the wake signal is detected. This is illustrated by the following figure.
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57
CAN INTERFACE
.
CAN
bus
CANH
CANL
Dominant
Pulse # 3
Dominant
Pulse # 2
Dominant
Pulse # 4
Dominant
Pulse # 1
Internal differential Wake-up receiver signal
Internal Wake-up signal
Can Wake-up detected
t
t
t
CAN WU3-F
CAN WU3-F
CAN WU3-F
t
CAN WU3-TO
Dominant Pulse # n: duration 1 or multiple dominant bits
Figure 36. Pattern wake-up - multiple dominant detection
8.1.3 BUS termination
The device supports the two main types of bus terminations:
• Differential termination resistors between CANH and CANL lines.
• SPLIT termination concept, with the mid point of the differential termination connected to GND through a capacitor and to the SPLIT pin.
• In application, the device can also be used without termination.
• Figure 37 illustrates some of the most common terminations.
CANH
SPLIT
CANL
CANH
SPLIT
CANL
No
connect
No
connect
120
CAN bus
CAN bus
ECU connector
ECU connector
No termination
Standard termination
CANH
SPLIT
CANL
60
60
CAN bus
ECU connector
Figure 37. Bus termination options
8.2
CAN bus fault diagnostic
The device includes diagnostic of bus short-circuit to GND, VBAT, and internal ECU 5.0 V. Several comparators are implemented on
CANH and CANL lines. These comparators monitor the bus level in the recessive and dominant states. The information is then managed
by a logic circuitry to properly determine the failure and report it.
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CAN INTERFACE
Vr5
H5
Hb
V
(12-14 V)
-2.0 V)
BAT
Vrvb
V
DD
V
(V
RVB SUP
Vrg
TXD
Diag
Hg
Lg
CANH
CANL
V
(5.0 V)
DD
Logic
V
(V -.43 V)
R5 DD
CANH dominant level (3.6 V)
Vrg
Lb
Recessive level (2.5 V)
Vrvb
V
(1.75 V)
RG
L5
CANL dominant level (1.4 V)
GND (0.0 V)
Vr5
Figure 38. CAN bus simplified structure truth table for failure detection
The following table indicates the state of the comparators when there is a bus failure, and depending upon the driver state.
Table 10. Failure detection truth table
Driver recessive state
Driver dominant state
Failure description
Lg (threshold 1.75 V)
Hg (threshold 1.75 V)
Lg (threshold 1.75 V)
Hg (threshold 1.75 V)
No failure
1
1
0
1
CANL to GND
CANH to GND
0
0
0
1
0
0
0
0
Lb (threshold VSUP -2.0 V)
Hb (threshold VSUP -2.0 V)
Lb (threshold VSUP -2.0 V)
Hb (threshold VSUP -2.0 V)
No failure
0
0
0
0
CANL to VBAT
CANH to VBAT
1
1
1
1
1
1
0
1
L5 (threshold VDD -0.43 V)
H5 (threshold VDD -0.43 V)
L5 (threshold VDD -0.43 V)
H5 (threshold VDD -0.43 V)
No failure
0
1
1
0
1
1
0
1
0
0
1
1
CANL to 5.0 V
CANH to 5.0 V
8.2.1 Detection principle
In the recessive state, if one of the two bus lines are shorted to GND, VDD (5.0 V), or VBAT, the voltage at the other line follows the shorted
line, due to the bus termination resistance. For example: if CANL is shorted to GND, the CANL voltage is zero, the CANH voltage
measured by the Hg comparator is also close to zero.
In the recessive state, the failure detection to GND or VBAT is possible. However, it is not possible with the above implementation to
distinguish which of the CANL or CANH lines are shorted to GND or VBAT. A complete diagnostic is possible once the driver is turned
on, and in the dominant state.
8.2.1.1
Number of samples for proper failure detection
The failure detector requires at least one cycle of the recessive and dominant states to properly recognize the bus failure. The error will
be fully detected after five cycles of the recessive-dominant states. As long as the failure detection circuitry has not detected the same
error for five recessive-dominant cycles, the error is not reported.
8.2.2 Bus clamping detection
If the bus is detected to be in dominant for a time longer than (TDOM), the bus failure flag is set and the error is reported in the SPI.
This condition could occur when the CANH line is shorted to a high-voltage. In this case, current will flow from the high-voltage short-
circuit, through the bus termination resistors (60 Ω), into the SPLIT pin (if used), and into the device CANH and CANL input resistors,
which are terminated to internal 2.5 V biasing or to GND (Sleep mode).
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CAN INTERFACE
Depending upon the high-voltage short-circuit, the number of nodes, usage of the SPLIT pin, RIN actual resistor and mode state (Sleep
or Active) the voltage across the bus termination can be sufficient to create a positive dominant voltage between CANH and CANL, and
the RXD pin will be low. This would prevent start of any CAN communication and thus, proper failure identification requires five pulses on
TXD. The bus dominant clamp circuit will help to determine such failure situation.
8.2.3 RXD permanent recessive failure (does not apply to ‘C’ and ‘D’ versions)
The aim of this detection is to diagnose an external hardware failure at the RXD output pin and ensure that a permanent failure at RXD
does not disturb the network communication. If RXD is shorted to a logic high signal, the CAN protocol module within the MCU will not
recognize any incoming message. In addition, it will not be able to easily distinguish the bus idle state and can start communication at any
time. In order to prevent this, RXD failure detection is necessary. When a failure is detected, the RXD high flag is set and CAN switches
to receive only mode.
TXD
CANL&H
Diag
TXD driver
Logic
Diff output
V
/2
DD
Sampling
Sampling
V
DD
Rxsense
V
DD
RXD short to V
RXD output
DD
RXD
CANH
CANL
RXD flag latched
60
RXD driver Diff
RXD flag
Prop delay
The RXD flag is not the RXPR bit in the LPC register, and neither is the CANF in the INTR register.
Figure 39. RXD path simplified schematic, RXD short to VDD detection
8.2.3.1
Implementation for detection
The implementation senses the RXD output voltage at each low to high transition of the differential receiver. Excluding the internal
propagation delay, the RXD output should be low when the differential receiver is low. When an external short to VDD at the RXD output,
RXD will be tied to a high level and can be detected at the next low to high transition of the differential receiver.
As soon as the RXD permanent recessive is detected, the RXD driver is deactivated.
Once the error is detected the driver is disabled and the error is reported via SPI in CAN register.
8.2.3.2
Recovery condition
The internal recovery is done by sampling a correct low level at TXD as shown in the following illustration.
CANL&H
Diff output
Sampling
Sampling
RXD short to V
DD
RXD output
RXD flag
RXD no longer shorted to V
DD
RXD flag latched
The RXD flag is not the RXPR bit in the LPC register, and neither is the CANF in the INTR register.
Figure 40. RXD path simplified schematic, RXD short to VDD detection
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CAN INTERFACE
8.2.4 TXD permanent dominant
8.2.4.1
Principle
If the TXD is set to a permanent low level, the CAN bus is set into dominant level, and no communication is possible. The device has a
TXD permanent timeout detector. After the timeout (TDOUT), the bus driver is disabled and the bus is released into a recessive state. The
TXD permanent flag is set.
8.2.4.2
Recovery
The TXD permanent dominant is used and activated when there is a TXD short to RXD. The recovery condition for a TXD permanent
dominant (recovery means the re-activation of the CAN drivers) is done by entering into a Normal mode controlled by the MCU or when
TXD is recessive while RXD change from recessive to dominant.
8.2.5 TXD to RXD short-circuit
8.2.5.1
Principle
When TXD is shorted to RXD during incoming dominant information, RXD is set to low. Consequently, the TXD pin is low and drives CANH
and CANL into a dominant state. Thus the bus is stuck in dominant. No further communication is possible.
8.2.5.2
Detection and recovery
The TXD permanent dominant timeout will be activated and release the CANL and CANH drivers. However, at the next incoming dominant
bit, the bus will then be stuck in dominant again. The recovery condition is same as the TXD dominant failure
8.2.6 Important information for bus driver reactivation
The driver stays disabled until the failure is/are removed (TXD and/or RXD is no longer permanent dominant or recessive state or shorted)
and the failure flags cleared (read). The CAN driver must be set by SPI in TXD/RXD mode in order to re enable the CAN bus driver.
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LIN BLOCK
9
LIN block
9.1
LIN interface description
The physical interface is dedicated to automotive LIN sub-bus applications.
The interface has 20 kbps and 10 kbps baud rates, and includes as well as a fast baud rate for test and programming modes. It has
excellent ESD robustness and immunity against disturbance, and radiated emission performance. It has safe behavior when a LIN bus
short-to-ground, or a LIN bus leakage during LP mode. Digital inputs are related to the device VDD pin.
9.1.1 Power supply pin (VSUP/2)
The VSUP/2 pin is the supply pin for the LIN interface. To avoid a false bus message, an undervoltage on VSUP/2 disables the
transmission path (from TXD to LIN) when
VSUP/2 falls below 6.1 V.
9.1.2 Ground pin (GND)
When there is a ground disconnection at the module level, the LIN interface do not have significant current consumption on the LIN bus
pin when in the recessive state.
9.1.3 LIN bus pin (LIN, lin1, lin2)
The LIN pin represents the single-wire bus transmitter and receiver. It is suited for automotive bus systems, and is compliant to the LIN
bus specification 2.1 and SAEJ2602-2. The LIN interface is only active during Normal mode.
9.1.3.1
Driver characteristics
The LIN driver is a LS MOSFET with internal overcurrent thermal shutdown. An internal pull-up resistor with a serial diode structure is
integrated so no external pull-up components are required for the application in a slave node. An additional pull-up resistor of 1.0 kΩ must
be added when the device is used in the master node. The 1.0 kΩ pull-up resistor can be connected to the LIN pin or to the ECU battery
supply.
The LIN pin exhibits no reverse current from the LIN bus line to VSUP/2, even in the event of a GND shift or VSUP/2 disconnection. The
transmitter has a 20 kbps, 10 kbps and fast baud rate, which are selected by SPI.
9.1.3.2
Receiver characteristics
The receiver thresholds are ratiometric with the device VSUP/2 voltage.
If the VSUP/2 voltage goes below typically 6.1 V, the LIN bus enters into a recessive state even if communication is sent on TXD.
If LIN driver temperature reaches the overtemperature threshold, the transceiver and receiver are disabled. When the temperature falls
below the overtemperature threshold, LIN driver and receiver will be automatically enabled.
9.1.4 Data input pin (TXD-L, TXD-L1, TXD-L2)
The TXD-L,TXD-L1 and TXD-L2 input pin is the MCU interface to control the state of the LIN output. When TXD-L is LOW (dominant),
LIN output is LOW. When TXD-L is HIGH (recessive), the LIN output transistor is turned OFF.
This pin has an internal pull-up current source to VDD to force the recessive state if the input pin is left floating.
If the pin stays low (dominant sate) more than tTXDDOM, the LIN transmitter goes automatically in recessive state. This is reported by flag
in LIN register.
9.1.5 Data output pin (RXD-L, RXD-L1, RXD-L2)
This output pin is the MCU interface, which reports the state of the LIN bus voltage. LIN HIGH (recessive) is reported by a high voltage
on RXD, LIN LOW (dominant) is reported by a low voltage on RXD.
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9.2
LIN operational modes
The LIN interface have two operational modes, Transmit receiver and LIN disable modes.
9.2.1 Transmit receive
In the TXD/RXD mode, the LIN bus can transmit and receive information.
When the 20 kbps baud rate is selected, the slew rate and timing are compatible with LIN protocol specification 2.1.
When the 10 kbps baud rate is selected, the slew rate and timing are compatible with J2602-2.
When the fast baud rate is selected, the slew rate and timing are much faster than the above specification and allow fast data transition.
The LIN interface can be set by the SPI command in TXD/RXD mode, only when TXD-L is at a high level. When the SPI command is send
while TXD-L is low, the command is ignored.
9.2.2 Sleep mode
This mode is selected by SPI, and the transmission path is disabled. Supply current for LIN block from VSUP/2 is very low (typically 3.0 μA).
LIN bus is monitor to detect Wake-up event. In the Sleep mode, the internal 725 kOhm pull-up resistor is connected and the 30 kOhm
disconnected. The LIN block can be awakened from Sleep mode by detection of LIN bus activity.
9.2.2.1
LIN bus activity detection
The LIN bus Wake-up is recognized by a recessive to dominant transition, followed by a dominant level with a duration greater than 70 μs,
followed by a dominant to recessive transition. This is illustrated in Figures 20 and 21. Once the Wake-up is detected, the event is reported
to the device state machine. An INT is generated if the device is in LP VDD ON mode, or VDD will restart if the device was in LP VDDOFF
mode. The Wake-up can be enable or disable by the SPI.
Fail-safe Features
Table 11 describes the LIN block behavior when there is a failure.
Table 11. LIN block failure
Functionnal
Fault
Condition
Consequence
Recovery
mode
LIN supply Undervoltage
LIN supply voltage < 6.0 V (typically)
TXD pin low for more than tTXDDOM
LIN transmitter in recessive State
LIN transmitter in recessive State
Condition gone
Condition gone
TXD RXD
TXD Pin Permanent
Dominant
LIN transmitter and receiver
disabled
LIN driver temperature > 160 °C
(typically)
LIN Thermal Shutdown
TXD RXD
Condition gone
HS turned off
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10 Serial peripheral interface
10.1 High level overview
The device uses a 16 bits SPI, with the following arrangements:
MOSI, Master Out Slave In bits:
• bits 15 and 14 (called C1 and C0) are control bits to select the SPI operation mode (write control bit to device register, read back of
the control bits, read of device flag).
• bit 13 to 9 (A4 to A0) to select the register address.
• bit 8 (P/N) has two functions: parity bit in write mode (optional, = 0 if not used), Next bit ( = 1) in read mode.
• bit 7 to 0 (D7 to D0): control bits
MISO, Master In Slave Out bits:
• bits 15 to 8 (S15 to S8) are device status bits
• bits 7 to 0 (Do7 to Do0) are either extended device status bits, device internal control register content or device flags.
The SPI implementation does not support daisy chain capability.
Figure 41 is an overview of the SPI implementation.
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
D7 D6 D5 D4 D3 D2 D1 D0
MOSI C1
C0
A4
A2
A3
A1
P/N
A0
register address
Parity (optional) or
Next bit = 1
control bits
data
MISO S15 S14
S13
S11
S9
S8
S12
S10
Do7 Do6 Do5 Do4
Do3 Do2 Do1 Do0
Extended Device Status, Register Control bits or Device Flags
Device Status
CS active low. Must rise at end of 16 clocks,
for write commands, MOSI bits [15, 14] = [0, 1]
CS
SCLK
SCLK signal is low outside of CS active
MOSI and MISO data changed at SCLK rising edge
and sampled at falling edge. Msb first.
MOSI Don’t Care
Don’t Care
Tri-state
C1
C0
D0
Do0
MISO tri-state outside of CS active
MISO
Tri-state
S15
S14
SPI Wave Form, and Signals Polarity
Figure 41. SPI overview
10.2 Detail operation
The SPI operation deviation (does not apply to ‘C’ and ‘D’ versions).
In some cases, the SPI write command is not properly interpreted by the device. This results in either a ‘non received SPI command’ or
a ‘corrupted SPI command’. Important: Due to this, the tLEAD and tCSLOW parameters must be carefully acknowledged.
Only SPI write commands (starting with bits 15,14 = 01) are affected. The SPI read commands (starting with bits 15,14 = 00 or 11) are
not affected.
The occurrence of this issue is extremely low and is caused by the synchronization between internal and external signals. In order to
guarantee proper operation, the following steps must be taken.
1. Ensure the duration of the Chip Select Low (tCSLOW) state is >5.5 μs.
Note: In data sheet revisions prior to 7.0, this parameter is not specified and is indirectly defined by the sum of 3 parameters, tLEAD + 16
x tPCLK + tLAG (sum = 4.06 μs).
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2. Ensure SPI timing parameter tLEAD is a min. of 550 ns.
Note: In data sheet revisions prior to 7.0, the tLEAD parameter is a min of 30 ns.
3. Make sure to include a SPI read command after a SPI write command.
In case a series of SPI write commands is used, only one additional SPI read is necessary. The recommended SPI read command is
“device ID read: 0x2580” so device operation is not affected (ex: clear flag). Other SPI read commands may also be used.
When the previous steps are implemented, the device will operate as follows:
For a given SPI write command (named SPI write ‘n’):
• In case the SPI write command ‘n’ is not accepted, the following SPI command (named SPI ‘n+1’) will finish the write process of the
SPI write ‘n’, thanks to step 2 (tLAG > 550 ns) and step 3 (which is the additional SPI command ‘n+1’).
• By applying steps 1, 2, and 3, no SPI command is ignored. Worst case, the SPI write ‘n’ is executed at the time the SPI ‘n+1’ is sent.
This will lead to a delay in device operation (delay between SPI command ‘n’ and ‘n+1’).
Note: Occurrence of an incorrect command is reduced, thanks to step 1 (extension of tCSLOW duration to >5.5 μs).
Sequence examples:
Example 1:
• 0x60C0 (CAN interface control) – in case this command is missed, next write command will complete it
• 0x66C0 (LIN interface control) – in case this command is missed, next read command will complete it
• 0x2580 (read device ID) – Additional command to complete previous LIN command, in case it was missed
Example 2:
• 0x60C0 (CAN interface control) - in case this command is missed, next write command will complete it
• 0x66C0 (LIN interface control) - in case this command is missed, next read command will complete it
• 0x2100 (read CAN register content) – this command will complete previous one, in case it was missed
• 0x2700 (read LIN register content)
SPI Operation if the CSB low flag is set to '1' (All product versions)
When the ‘CSB low’ flag is set (Bit 4 = '1' using the 0xE300 SPI command), the next SPI write commands are executed by the device only
if the SPI tLEAD time is between 30 ns and 2.5 µs maximum for the ‘C’ and ‘D’ versions, and 550 ns and 2.5 µs maximum for others
versions.
The occurrence of the CSB flag set to ‘1’ is extremely low and is directly linked to an intermittent short to ground on the board trace or a
CSB driven low by the MCU. In both cases, the CSB pin must be asserted low for more than 2.0 ms to set the flag.
The tLEAD time is represented in the SPI timing diagram (Figure 14) and corresponds to the time between CSB high to low transition and
first SCLK signal.
Note:
If the flag is cleared by a read command and the fault is no longer present, the 2.5 µs maximum of tLEAD time does not apply, but can also
be respected. This means if all the SPI write commands use a maximum tLEAD time of 2.5 µs, they are all interpreted by the device,
whatever the indication of the ‘CSB low’ flag.
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10.2.1 Bits 15, 14, and 8 functions
Table 12 summarizes the various SPI operation, depending upon bit 15, 14, and 8.
Table 12. SPI operations (bits 8, 14, & 15)
Parity/Next
MOSI[8] P/N
Control Bits MOSI[15-14], C1-C0
Type of Command
Note for Bit 8 P/N
Read back of register
content and block (CAN,
I/O, INT, LINs) real time
state. See Table 39.
Bit 8 must be set to 1, independently of the parity function
selected or not selected.
00
1
If bit 8 is set to “0”: means parity not selected OR
parity is selected AND parity = 0
Write to register
address, to control the
device operation
0
1
01
if bit 8 is set to “1”: means parity is selected AND parity = 1
10
11
Reserved
Read of device flags
form a register address
Bit 8 must be set to 1, independently of the parity function
selected or not selected.
1
10.2.2 Bits 13-9 functions
The device contains several registers coded on five bits (bits 13 to 9).
Each register controls or reports part of the device’s function. Data can be written to the register to control the device operation or to set
the default value or behavior. Every register can also be read back in order to ensure that it’s content (default setting or value previously
written) is correct. In addition, some of the registers are used to report device flags.
10.2.2.1 Device status on MISO
When a write operation is performed to store data or control bits into the device, the MISO pin reports a 16 bit fixed device status composed
of 2 bytes: Device Fixed Status (bits 15 to 8) + extended Device Status (bits 7 to 0). In a read operation, MISO will report the Fixed device
status (bits 15 to 8) and the next eight bits will be the content of the selected register.
10.2.3 Register adress table
Table 13 is a list of device registers and addresses, coded with bits 13 to 9.
Table 13. Device registers with corresponding address
Address
MOSI[13-9]
A4...A0
Quick Ref.
Name
Description
Functionality
1) Write ‘device control bits’ to register address.
2) Read back register ‘control bits’
0_0000
Analog Multiplexer
MUX
0_0001
0_0010
0_0011
0_0100
0_0101
Memory byte A
Memory byte B
RAM_A
RAM_B
RAM_C
RAM_D
Init REG
1) Write ‘data byte’ to register address.
2) Read back ‘data byte’ from register address
Memory byte C
Memory byte D
Initialization Regulators
Init
watchdog
0_0110
Initialization Watchdog
1) Write ‘device initialization control bits’ to register address.
2) Read back ‘initialization control bits’ from register address
0_0111
0_1000
Initialization LIN and I/O
Init LIN I/O
Init MISC
Initialization Miscellaneous functions
1) Write to register to select device Specific mode, using
‘Inverted Random Code’
SPE_MOD
E
0_1001
Specific modes
2) Read ‘Random Code’
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Table 13. Device registers with corresponding address (continued)
0_1010
0_1011
0_1100
0_1101
Timer_A: watchdog & LP MCU consumption
Timer_B: Cyclic Sense & Cyclic Interrupt
Timer_C: watchdog LP & Forced Wake-up
Watchdog Refresh
TIM_A
TIM_B
1) Write ‘timing values’ to register address
2) Read back register ‘timing values’
TIM_C
watchdog
Watchdog Refresh Commands
1) Write to register to select LP mode, with optional “Inverted
Random code” and select Wake-up functionality
2) Read operations:
Read back device ‘Current mode’
Read ‘Random Code’,
0_1110
Mode register
MODE
Leave ‘Debug mode’
0_1111
1_0000
1_0001
1_0010
1_0011
1_0100
Regulator Control
CAN interface control
Input Output control
Interrupt Control
REG
CAN
1) Write ‘device control bits’ to register address, to select device
operation.
2) Read back register ‘control bits’.
3) Read device flags from each of the register addresses.
I/O
Interrupt
LIN1
LIN1 interface control
LIN2 interface control
LIN2
10.2.4 Complete SPI operation
Table 14 is a compiled view of all the SPI capabilities and options. Both MOSI and MISO information are described.
Table 14. SPI capabilities with options
MOSI/
MISO
Control bits
[15-14]
Address
[13-9]
Parity/Next
bits [8]
Type of Command
Bit 7
Bits [6-0]
MOSI
MISO
MOSI
MISO
MOSI
00
address
1
0
000 0000
Register control bits content
000 0000
Read back of “device control bits” (MOSI bit
7 = 0)
Device Fixed Status (8 bits)
00 address
Device Fixed Status (8 bits)
01 address (note)
OR
1
1
Read specific device information (MOSI bit
7 = 1)
Device ID and I/Os state
Control bits
Write device control bit to address selected
by bits (13-9).
MISO
Device Fixed Status (8 bits)
10
Device Extended Status (8 bits)
Reserved
MISO return 16 bits device status
MOSI
MISO
Reserved
Reserved
Reserved 0
Read of device flags form a register
address, and sub address LOW (bit 7)
MISO
MOSI
MISO
MOSI
11
Device Fixed Status (8 bits)
11 address
Device Fixed Status (8 bits)
address
Read device flags and Wake-up flags, from
register address (bit 13-9), and sub address
(bit 7).
MISO return fixed device status (bit 15-8) +
flags from the selected address and sub-
address.
Flags
Read of device flags form a register
address, and sub address HIGH (bit 7)
1
1
Flags
Note: P = 0 if parity bit is not selected or parity = 0. P = 1 if parity is selected and parity = 1.
10.2.5 Parity bit 8
10.2.5.1 Calculation
The parity is used for the write-to-register command (bit 15,14 = 01). It is calculated based on the number of logic one contained in bits
15-9,7-0 sequence (this is the entire 16 bits of the write command except bit 8).
Bit 8 must be set to 0 if the number of 1 is odd. Bit 8 must be set to 1if the number of 1 is even.
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10.2.5.2 Examples 1:
MOSI [bit 15-0] = 01 00 011 P 01101001, P should be 0, because the command contains 7 bits with logic 1. Thus the Exact command will
then be: MOSI [bit 15-0] = 01 00 011 0 01101001
10.2.5.3 Examples 2:
MOSI [bit 15-0] = 01 00 011 P 0100 0000, P should be 1, because the command contains 4 bits with logic 1. Thus the Exact command
will then be: MOSI [bit 15-0] = 01 00 011 1 0100 0000
10.2.5.4 Parity function selection
All SPI commands and examples do not use parity functions. The parity function is optional. It is selected by bit 6 in INIT MISC register.
If parity function is not selected (bit 6 of INIT MISC = 0), then Parity bits in all SPI commands (bit 8) must be ‘0’.
10.3 Detail of control bits and register mapping
The following tables contain register bit meaning arranged by register address, from address 0_000 to address 1_0100
10.3.1 MUX and RAM registers
Table 15. MUX Register(42)
MOSI Second Byte, bits 7-0
MOSI First Byte [15-8]
[b_15 b_14] 0_0000 [P/N]
bit 7
MUX_2
0
bit 6
MUX_1
0
bit 5
MUX_0
0
bit 4
Int 2K
0
bit 3
I/O-att
0
bit 2
0
bit 1
0
bit 0
0
01 00 _ 000 P
Default state
0
0
0
Condition for default
POR, 5 V-CAN off, any mode different from Normal
Bits
Description
b7 b6 b5
000
MUX_2, MUX_1, MUX_0 - Selection of external input signal or internal signal to be measured at MUX-OUT pin
All functions disable. No output voltage at MUX-OUT pin
001
VDD regulator current recopy. Ratio is approx 1/97. Requires an external resistor or selection of Internal 2.0 K (bit 3)
Device internal voltage reference (approx 2.5 V)
010
011
Device internal temperature sensor voltage
100
Voltage at I/O-0. Attenuation or gain is selected by bit 3.
101
Voltage at I/O-1. Attenuation or gain is selected by bit 3.
110
Voltage at VSUP/1 pin. Refer to electrical table for attenuation ratio (approx 5)
Voltage at VSENSE pin. Refer to electrical table for attenuation ratio (approx 5)
111
INT 2k - Select device internal 2.0 kohm resistor between AMUX and GND. This resistor allows the measurement of a voltage proportional
to the VDD output current.
b4
0
1
Internal 2.0 kohm resistor disable. An external resistor must be connected between AMUX and GND.
Internal 2.0 kohm resistor enable.
I/O-att - When I/O-0 (or I/O-1) is selected with b7,b6,b5 = 100 (or 101), b3 selects attenuation or gain
between I/O-0 (or I/O-1) and MUX-OUT pin
b3
0
Gain is approx 2 for device with VDD = 5.0 V (Ref. to electrical table for exact gain value)
Gain is approx 1.3 for device with VDD = 3.3 V (Ref. to electrical table for exact gain value)
Attenuation is approx 4 for device with VDD = 5.0 V (Ref. to electrical table for exact attenuation value)
Attenuation is approx 6 for device with VDD = 3.3 V (Ref. to electrical table for exact attenuation value)
1
Notes
42. The MUX register can be written and read only when the 5V-CAN regulator is ON. If the MUX register is written or read while 5V-CAN is OFF, the
command is ignored, and the MXU register content is reset to default state (all control bits = 0).
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Table 16. Internal memory registers A, B, C, and D, RAM_A, RAM_B, RAM_C, and RAM_D
MOSI Second Byte, bits 7-0
MOSI First Byte [15-8]
[b_15 b_14] 0_0xxx [P/N]
Bit 7
Ram a7
0
Bit 6
Ram a6
0
Bit 5
Ram a5
0
Bit 4
Ram a4
0
Bit 3
Ram a3
0
Bit 2
Ram a2
0
Bit 1
Ram a1
0
Bit 0
Ram a0
0
01 00 _ 001 P
Default state
Condition for default
01 00 _ 010 P
POR
Ram b7
0
Ram b6
0
Ram b5
0
Ram b4
0
Ram b3
0
Ram b2
0
Ram b1
0
Ram b0
0
Default state
Condition for default
01 00 _ 011 P
POR
Ram c7
0
Ram c6
0
Ram c5
0
Ram c4
0
Ram c3
0
Ram c2
0
Ram c1
0
Ram c0
0
Default state
Condition for default
01 00 _ 100 P
POR
Ram d7
0
Ram d6
0
Ram d5
0
Ram d4
0
Ram d3
0
Ram d2
0
Ram d1
0
Ram d0
0
Default state
Condition for default
POR
10.3.2 INIT registers
Note: these registers can be written only in INIT mode
Table 17. Initialization regulator registers, INIT REG (note: register can be written only in INIT mode)
MOSI Second Byte, bits 7-0
MOSI First Byte [15-8]
[b_15 b_14] 0_0101 [P/N]
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
VAUX5/3
0
bit 1
bit 0
01 00 _ 101 P
Default state
I/O-x sync VDDL rst[1] VDDL rst[0] VDD rstD[1] VDD rstD[0]
Cyclic on[1] Cyclic on[0]
1
0
0
0
0
0
0
Condition for default
POR
Bit
Description
b7
0
I/O-x sync - Determine if I/O-1 is sensed during I/O-0 activation, when cyclic sense function is selected
I/O-1 sense anytime
1
I/O-1 sense during I/O-0 activation
b6, b5
00
VDDL RST[1] VDDL RST[0] - Select the VDD undervoltage threshold, to activate RST pin and/or INT
Reset at approx 0.9 VDD
.
01
INT at approx 0.9 VDD, Reset at approx 0.7 VDD
Reset at approx 0.7 VDD
10
11
Reset at approx 0.9 VDD.
b4, b3
00
VDD RSTD[1] VDD RSTD[0] - Select the RST pin low lev duration, after VDD rises above the VDD undervoltage threshold
1.0 ms
5.0 ms
10 ms
20 ms
01
10
11
b2
0
[VAUX 5/3] - Select Vauxilary output voltage
VAUX = 3.3 V
1
VAUX = 5.0 V
b1, b0
Cyclic on[1] Cyclic on[0] - Determine I/O-0 activation time, when cyclic sense function is selected
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Bit
Description
00
01
10
11
200 μs (typical value. Ref. to dynamic parameters for exact value)
400 μs (typical value. Ref. to dynamic parameters for exact value)
800 μs (typical value. Ref. to dynamic parameters for exact value)
1600 μs (typical value. Ref. to dynamic parameters for exact value)
Table 18. Initialization watchdog registers, INIT watchdog (note: register can be written only in INIT mode)
MOSI Second Byte, bits 7-0
MOSI First Byte [15-8]
[b_15 b_14] 0_0110 [P/N]
bit 7
WD2INT
0
bit 6
MCU_OC
1
bit 5
OC-TIM
0
bit 4
bit 3
WD_spi[1]
0
bit 2
WD_spi[0]
0
bit 1
WD N/Win
1
bit 0
Crank
0
01 00 _ 110 P
Default state
WD Safe
Condition for default
POR
Bit
Description
b7
0
WD2INT - Select the maximum time delay between INT occurrence and INT source read SPI command
Function disable. No constraint between INT occurrence and INT source read.
1
INT source read must occur before the remaining of the current watchdog period plus 2 complete watchdog periods.
MCU_OC, OC-TIM - In LP VDD ON, select watchdog refresh and VDD current monitoring functionality. VDD_OC_LP threshold
is defined in device electrical parameters (approx 1.5 mA)
b6, b5
In LP mode, when watchdog is not selected
no
watchdog + In LP VDD ON mode, VDD overcurrent has no effect
00
no
watchdog + In LP VDD ON mode, VDD overcurrent has no effect
01
no
watchdog + In LP VDD ON mode, VDD current > VDD_OC_LP threshold for a time > 100 μs (typically) is a wake-up event
10
no
In LP VDD ON mode, VDD current > VDD_OC_LP threshold for a time > I_mcu_OC is a wake-up event. I_mcu_OC time is
watchdog +
selected in Timer register (selection range from 3.0 to 32 ms)
11
In LP mode when watchdog is selected
watchdog +
In LP VDD ON mode, VDD current > VDD_OC_LP threshold has no effect. watchdog refresh must occur by SPI command.
00
watchdog +
In LP VDD ON mode, VDD current > VDD_OC_LP threshold has no effect. watchdog refresh must occur by SPI command.
01
watchdog +
In LP VDD ON mode, VDD overcurrent for a time > 100 μs (typically) is a wake-up event.
10
In LP VDD ON mode, VDD current > VDD_OC_LP threshold for a time < I_mcu_OC is a watchdog refresh condition. VDD current
> VDD_OC_LP threshold for a time > I_mcu_OC is a wake-up event. I_mcu_OC time is selected in Timer register (selection
range from 3.0 to 32 ms)
watchdog +
11
b4
0
WD Safe - Select the activation of the SAFE pin low, at first or second consecutive RESET pulse
SAFE pin is set low at the time of the RST pin low activation
1
SAFE pin is set low at the second consecutive time RST pulse
b3, b2
00
WD_spi[1] WD_spi[0] - Select the Watchdog (watchdog) Operation
Simple Watchdog selection: watchdog refresh done by a 8 bits or 16 bits SPI
Enhanced 1: Refresh is done using the Random Code, and by a single 16 bits.
Enhanced 2: Refresh is done using the Random Code, and by two 16 bits command.
01
10
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Bit
Description
11
Enhanced 4: Refresh is done using the Random Code, and by four 16 bits command.
b1
0
WD N/Win - Select the Watchdog (watchdog) Window or Timeout operation
Watchdog operation is TIMEOUT, watchdog refresh can occur anytime in the period
1
Watchdog operation is WINDOW, watchdog refresh must occur in the open window (second half of period)
b0
0
Crank - Select the VSUP/1 threshold to disable VDD, while VSUP1 is falling toward GND
VDD disable when VSUP/1 is below typically 4.0 V (parameter VSUP-TH1), and device in Reset mode
1
VDD kept ON when VSUP/1 is below typically 4.0 V (parameter VSUP_TH1)
Table 19. Initialization LIN and I/O registers, INIT LIN I/O (note: register can be written only in INIT mode)
MOSI Second Byte, bits 7-0
MOSI First Byte [15-8]
[b_15 b_14] 0_0111 [P/N]
bit 7
bit 6
bit 5
bit 4
bit 3
LIN_T/1[0]
0
bit 2
bit 1
bit 0
Cyc_Inv
0
01 00 _ 111 P
Default state
I/O-1 ovoff LIN_T2[1] LIN_T2[0] LIN_T/1[1]
I/O-1 out-en I/O-0 out-en
0
0
0
0
0
Condition for default
POR
Bit
Description
b7
0
I/O-1 ovoff - Select the deactivation of I/O-1 when VDD or VAUX overvoltage condition is detected
Disable I/O-1 turn off.
1
Enable I/O-1 turn off, when VDD or VAUX overvoltage condition is detected.
b6, b5
00
LIN_T2[1], LIN_T2[0] - Select pin operation as LIN Master pin switch or I/O
pin is OFF
01
pin operation as LIN Master pin switch
pin operation as I/O: HS switch and Wake-up input
N/A
10
11
b4, b3
00
LIN_T/1[1], LIN_T/1[0] - Select pin operation as LIN Master pin switch or I/O
pin is OFF
01
pin operation as LIN Master pin switch
pin operation as I/O: HS switch and Wake-up input
N/A
10
11
b2
0
I/O-1 out-en- Select the operation of the I/O-1 as output driver (HS, LS)
Disable HS and LS drivers of pin I/O-1. I/O-1 can only be used as input.
Enable HS and LS drivers of pin I/O-1. Pin can be used as input and output driver.
1
b1
0
I/O-0 out-en - Select the operation of the I/O-0 as output driver (HS, LS)
Disable HS and LS drivers of I/O-0 can only be used as input.
1
Enable HS and LS drivers of the I/O-0 pin. Pin can be used as input and output drivers.
b0
Cyc_Inv - Select I/O-0 operation in device LP mode, when cyclic sense is selected
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Bit
Description
During cyclic sense active time, I/O is set to the same state prior to entering in to LP mode. During cyclic sense off time, I/O-0
is disable (HS and LS drivers OFF).
0
1
During cyclic sense active time, I/O is set to the same state prior to entering in to LP mode. During cyclic sense off time, the
opposite driver of I/O_0 is actively set. Example: If I/0_0 HS is ON during active time, then I/O_O LS is turned ON at expiration
of the active time, for the duration of the cyclic sense period.
Table 20. Initialization Miscellaneous Functions, INIT MISC (Note: Register can be written only in INIT mode)
MOSI Second Byte, bits 7-0
MOSI First Byte [15-8]
[b_15 b_14] 0_1000 [P/N]
bit 7
bit 6
SPI parity
0
bit 5
INT pulse
0
bit 4
bit 3
INT flash
0
bit 2
bit 1
bit 0
LPM w
RNDM
01 01_ 000 P
INT width
Dbg Res[2] Dbg Res[1] Dbg Res[0]
Default state
0
0
0
0
Condition for default
POR
Bit
Description
LPM w RNDM - This enables the usage of random bits 2, 1 and 0 of the MODE register to enter into LP VDD OFF or LP VDD
ON.
b7
0
1
Function disable: the LP mode can be entered without usage of Random Code
Function enabled: the LP mode is entered using the Random Code
b6
0
SPI parity - Select usage of the parity bit in SPI write operation
Function disable: the parity is not used. The parity bit must always set to logic 0.
Function enable: the parity is used, and parity must be calculated.
1
b5
0
INT pulse -Select INT pin operation: low level pulse or low level
INT pin will assert a low level pulse, duration selected by bit [b4]
INT pin assert a permanent low level (no pulse)
1
b4
0
INT width - Select the INT pulse duration
INT pulse duration is typically 100 μs. Ref. to dynamic parameter table for exact value.
INT pulse duration is typically 25 μs. Ref. to dynamic parameter table for exact value.
1
b3
INT flash - Select INT pulse generation at 50% of the Watchdog Period in Flash mode
Function disable
Function enable: an INT pulse will occur at 50% of the Watchdog Period when device in Flash mode.
Dbg Res[2], Dbg Res[1], Dbg Res[0] - Allow verification of the external resistor connected at DBG pin. Ref. to parametric
b2, b1, b0
table for resistor range value.(43)
0xx
100
101
110
111
Function disable
100 verification enable: resistor at DBG pin is typically 68 kohm (RB3) - Selection of SAFE mode B3
101 verification enable: resistor at DBG pin is typically 33 kohm (RB2 - Selection of SAFE mode B2
110 verification enable: resistor at DBG pin is typically 15 kohm (RB1) - Selection of SAFE mode B1
111 verification enable: resistor at DBG pin is typically 0 kohm (RA) - Selection of SAFE mode A
Notes
43. Bits b2,1 and 0 allow the following operation:
First, check the resistor device has detected at the DEBUG pin. If the resistor is different, bit 5 (Debug resistor) is set in INTerrupt
register (Ref. to device flag table).
Second, over write the resistor decoded by device, to set the SAFE mode operation by SPI. Once this function is selected by bit 2 = 1,
this selection has higher priority than ‘hardware’, and device will behave according to b2,b1 and b0 setting
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10.3.3 Specific mode register
Table 21. Specific mode register, SPE_MODE
MOSI Second Byte, bits 7-0
MOSI First Byte [15-8]
[b_15 b_14] 01_001 [P/N]
bit 7
bit 6
bit 5
bit 4
bit 3
Rnd_C3b
0
bit 2
Rnd_C2b
0
bit 1
Rnd_C1b
0
bit 0
Rnd_C0b
0
01 01_ 001 P
Default state
Sel_Mod[1] Sel_Mod[0] Rnd_C5b
Rnd_C4b
0
0
0
Condition for default
POR
Bit
Description
Sel_Mod[1], Sel_Mod[0] - Mode selection: these 2 bits are used to select which mode the device will enter upon a SPI
command.
b7, b6
00
01
10
11
RESET mode
INIT mode
FLASH mode
N/A
[Rnd_C4b... Rnd_C0b] - Random Code inverted, these six bits are the inverted bits obtained from the SPE MODE Register
read command.
b5....b0
10.3.3.1 The SPE mode register is used for the following operation
- Set the device in RESET mode, to exercise or test the RESET functions.
- Go to INIT mode, using the Secure SPi command.
- Go to FLASH mode (in this mode the watchdog timer can be extended up to 32 s).
- Activate the SAFE pin by S/W.
This mode (called Special mode) is accessible from the secured SPI command, which consist of 2 commands:
1) reading a random code and
2) then write the inverted random code plus mode selection or SAFE pin activation:
Return to INIT mode is done as follow (this is done from Normal mode only):
1) Read random code:
MOSI : 0001 0011 0000 0000 [Hex:0x 13 00]
MISO report 16 bits, random code are bits (5-0)
miso = xxxx xxxx xxR5 R4 R3 R2 R1 R0 (RXD = 6 bits random code)
2) Write INIT mode + random code inverted
MOSI : 0101 0010 01 Ri5 Ri4 Ri3 Ri2 Ri1 Ri0 [Hex 0x 52 HH] (RIX = random code inverted)
MISO : xxxx xxxx xxxx xxxx (don’t care)
SAFE pin activation: SAFE pin can be set low, only in INIT mode, with following commands:
1) Read random code:
MOSI : 0001 0011 0000 0000 [Hex:0x 13 00]
MISO report 16 bits, random code are bits (5-0)
miso = xxxx xxxx xxR5 R4 R3 R2 R1 R0 (RXD = 6 bits random code)
2) Write INIT mode + random code bits 5:4 not inverted and random code bits 3:0 inverted
MOSI : 0101 0010 01 R5 R4 Ri3 Ri2 Ri1 Ri0 [Hex 0x 52 HH] (RIX = random code inverted)
MISO : xxxx xxxx xxxx xxxx (don’t care)
Return to Reset or Flash mode is done similarly to the go to INIT mode, except that the b7 and b6 are set according to the table above
(b7, b6 = 00 - go to reset, b7, b6 = 10 - go to Flash).
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10.3.4 Timer registers
Table 22. Timer register A, LP VDD overcurrent & watchdog period normal mode, TIM_A
MOSI Second Byte, bits 7-0
MOSI First Byte [15-8]
[b_15 b_14] 01_010 [P/N]
bit 7
I_mcu[2]
0
bit 6
I_mcu[1]
0
bit 5
I_mcu[1]
0
bit 4
bit 3
W/D_N[4]
1
bit 2
W/D_Nor[3]
1
bit 1
W/D_N[2]
1
bit 0
W/D_Nor[0]
0
watchdog
Nor[4]
01 01_ 010 P
Default state
1
Condition for default
POR
LP VDD overcurrent (ms)
b6, b5
b7
00
3 (def)
4
01
6
10
12
16
11
0
1
24
32
8
Watchdog period in device normal mode (ms)
b2, b1, b0
b4, b3
000
2.5
3
001
5
010
10
12
14
16
011
20
24
28
32
100
40
101
80
110
160
111
320
384
448
512
00
01
10
11
6
48
96
192
3.5
4
7
56
112
128
224
8
64
256 (def)
Table 23. Timer register B, cyclic sense and cyclic INT, in device LP mode, TIM_B
MOSI Second Byte, bits 7-0
MOSI First Byte [15-8]
[b_15 b_14] 01_011 [P/N]
bit 7
bit 6
bit 5
bit 4
bit 3
Cyc-int[3]
0
bit 2
Cyc-int[2]
0
bit 1
bit 0
01 01_ 011 P
Default state
Cyc-sen[3] Cyc-sen[2] Cyc-sen[1] Cyc-sen[0]
Cyc-int[1]
Cyc-int[0]
0
0
0
0
0
0
Condition for default
POR
Cyclic sense (ms)
b6, b5, b4
b7
000
001
6
010
12
011
24
100
48
101
96
110
111
384
512
0
1
3
4
192
256
8
16
32
64
128
Cyclic interrupt (ms)
b2, b1, b0
b3
000
6 (def)
8
001
12
010
24
011
48
100
96
101
192
258
110
384
512
111
768
0
1
16
32
64
128
1024
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Table 24. Timer register C, watchdog LP mode or flash mode and forced wake-up timer, TIM_C
MOSI Second Byte, bits 7-0
MOSI First Byte [15-8]
[b_15 b_14] 01_100 [P/N]
bit 7
bit 6
bit 5
bit 4
bit 3
FWU[3]
0
bit 2
FWU[2]
0
bit 1
FWU[1]
0
bit 0
FWU[0]
0
01 01_ 100 P
Default state
WD-LP-F[3] WD-LP-F[2] WD-LP-F[1] WD-LP-F[0]
0
0
0
0
Condition for default
POR
Table 25. Typical timing values
Watchdog in LP VDD ON mode (ms)
b6, b5, b4
b7
000
12
001
24
010
48
011
96
100
192
256
101
384
512
110
768
111
0
1
1536
2048
16
32
64
128
1024
Watchdog in flash mode (ms)
b6, b5, b4
b7
000
48 (def)
256
001
96
010
192
011
384
100
768
101
1536
8192
110
111
0
1
3072
6144
32768
512
1024
2048
4096
16384
Forced wake-up (ms)
b2, b1, b0
b3
000
48 (def)
64
001
96
010
192
258
011
384
512
100
101
1536
2048
110
111
0
1
768
3072
4096
6144
8192
128
1024
10.3.5 Watchdog and mode registers
Table 26. Watchdog refresh register, watchdog(44)
MOSI Second Byte, bits 7-0
MOSI First Byte [15-8]
[b_15 b_14] 01_101 [P/N]
bit 7
0
bit 6
0
bit 5
0
bit 4
0
bit 3
0
bit 2
0
bit 1
0
bit 0
0
01 01_ 101 P
Default state
0
0
0
0
0
0
0
0
Condition for default
POR
Notes
44. The Simple Watchdog Refresh command is in hexadecimal: 5A00. This command is used to refresh the watchdog and also to
transition from INIT mode to Normal mode, and from Normal Request mode to Normal mode (after a wake-up of a reset)
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.
Table 27. MODE register, mode
MOSI Second Byte, bits 7-0
MOSI First Byte [15-8]
[b_15 b_14] 01_110 [P/N]
bit 7
bit 6
mode[3]
N/A
bit 5
mode[2]
N/A
bit 4
mode[1]
N/A
bit 3
mode[0]
N/A
bit 2
Rnd_b[2]
N/A
bit 1
Rnd_b[1]
N/A
bit 0
Rnd_b[0]
N/A
01 01_ 110 P
Default state
mode[4]
N/A
Table 28. LP VDD off selection and FWU / cyclic sense selection
b7, b6, b5, b4, b3
0 1100
FWU
Cyclic Sense
OFF
OFF
OFF
ON
0 1101
ON
0 1110
OFF
0 1111
ON
ON
Table 29. LP VDD on selection and operation mode
b7, b6, b5, b4, b3
1 0000
1 0001
1 0010
1 0011
1 0100
1 0101
1 0110
1 0111
FWU
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
Cyclic Sense
OFF
OFF
OFF
OFF
ON
Cyclic INT
Watchdog
OFF
OFF
ON
OFF
ON
OFF
ON
ON
OFF
OFF
ON
OFF
ON
ON
ON
OFF
ON
ON
ON
1 1000
1 1001
1 1010
1 1011
1 1100
1 1101
1 1110
OFF
OFF
OFF
OFF
ON
OFF
OFF
ON
OFF
ON
ON
ON
OFF
ON
ON
ON
ON
OFF
OFF
ON
OFF
ON
ON
ON
ON
ON
OFF
ON
1 1111
ON
ON
ON
Random Code inverted, these 3bits are the inverted bits obtained from the previous SPI command.
The usage of these bits are optional and must be previously selected in the INIT MISC register [See
bit 7 (LPM w RNDM) in Table 20]
b2, b1, b0
Prior to enter in LP VDD ON or LP VDD OFF, the Wake-up flags must be cleared or read.
This is done by the following SPI commands (See Table 39, Device flag, I/O real time and device identification):
0xE100 for CAN Wake-up clear
0xE380 for I/O Wake-up clear
0xE700 for LIN1 Wake-up clear
0xE900 for LIN2 Wake-up clear
If Wake-up flags are not cleared, the device will enter into the selected LP mode and immediately Wake-up. In addition, the CAN failure
flags (i.e. CAN_F and CAN_UF) must be cleared in order to meet the low power current consumption specification. This is done by the
following SPI command:
0xE180 (read CAN failure flags)
When the device is in LP VDD ON mode, the Wake-up by a SPI command uses a write to ‘Normal Request mode’, 0x5C10.
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10.3.5.1 Mode register features
The mode register includes specific functions and a ‘global SPI command’ that allow the following:
- read device current mode
- read device Debug status
- read state of SAFE pin
- leave Debug state
- release or turn off SAFE pin
- read a 3 bit Random Code to enter in LP mode
These global commands are built using the MODE register address bit [13-9], along with several combinations of bit [15-14] and bit [7].
Note, bit [8] is always set to 1.
10.3.5.2 Entering into LP mode using random code
- LP mode using Random Code must be selected in INIT mode via bit 7 of the INIT MISC register.
- In Normal mode, read the Random Code using 0x1D00 or 0x1D80 command. The 3 Random Code bits are available on MISO bits 2,1 and 0.
- Write LP mode by inverting the 3 random bits.
Example - Select LP VDD OFF without cyclic sense and FWU:
1. in hex: 0x5C60 to enter in LP VDD OFF mode without using the 3 random code bits.
2. if Random Code is selected, the commands are:
- Read Random Code: 0x1D00 or 0x1D80,
MISO report in binary: bits 15-8, bits 7-3, Rnd_[2], Rnd_[1], Rnd_[0].
- Write LP VDD OFF mode, using Random Code inverted:
in binary: 0101 1100 0110 0 Rnd_b[2], Rnd_b[1], Rnd_b[0].
Table 30 summarizes these commands
Table 30. Device modes
Global commands and effects
MOSI bits 15-14
bits 13-9
bit 8
bit 7
bits 6-0
000 0000
bit 2-0
Read device current mode, Leave debug mode.
Keep SAFE pin as is.
00
01 110
1
0
MISO
bit 15-8
bit 7-3
device current mode
MOSI in hexadecimal: 1D 00
Fix Status
Random code
bits 6-0
MOSI bits 15-14
bits 13-9
bit 8
bit 7
Read device current mode
Release SAFE pin (turn OFF).
MOSI in hexadecimal: 1D 80
00
01 110
1
1
000 0000
bit 2-0
MISO
bit 15-8
bit 7-3
device current mode
Fix Status
Random code
bits 6-0
MOSI bits 15-14
bits 13-9
bit 8
bit 7
Read device current mode, Leave debug mode.
Keep SAFE pin as is.
MOSI in hexadecimal: DD 00
MISO reports Debug and SAFE state (bits 1,0)
11
01 110
1
0
000 0000
bit 1
MISO
bit 15-8
bit 7-3
device current mode
bit 2
X
bit 0
Fix Status
SAFE
DEBUG
MOSI bits 15-14
bits 13-9
bit 8
bit 7
bits 6-0
Read device current mode, Keep DEBUG mode
Release SAFE pin (turn OFF).
MOSI in hexadecimal: DD 80
MISO reports Debug and SAFE state (bits 1,0)
11
01 110
1
1
000 0000
bit 1
MISO
bit 15-8
bit 7-3
device current mode
bit 2
X
bit 0
Fix Status
SAFE
DEBUG
Table 31 describes MISO bits 7-0, used to decode the device’s current mode.
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Table 31. MISO bits 7-3
Device current mode, any of the above commands
b7, b6, b5, b4, b3
0 0000
MODE
INIT
0 0001
FLASH
0 0010
Normal Request
Normal mode
Low Power mode (Table 29)
0 0011
1 XXXX
Table 32 describes the SAFE and DEBUG bit decoding.
Table 32. SAFE and DEBUG status
SAFE and DEBUG bits
b1
0
description
SAFE pin ON, driver activated
SAFE pin OFF, not activated
description
1
b0
0
Debug mode OFF
1
Debug mode Active
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10.3.6 Regulator, CAN, I/O, INT and lin registers
Table 33. Regulator register
MOSI Second Byte, bits 7-0
MOSI First Byte [15-8]
[b_15 b_14] 01_111 [P/N]
bit 7
VAUX[1]
0
bit 6
VAUX[0]
0
bit 5
-
bit 4
5V-can[1]
0
bit 3
5V-can[0]
0
bit 2
bit 1
bit 0
01 01_ 111 P
Default state
VDD bal en VDD bal auto VDD OFF en
N/A N/A N/A
N/A
Condition for default
POR
POR
Bits
Description
b7 b6
VAUX[1], VAUX[0] - Vauxilary regulator control
00
Regulator OFF
Regulator ON. undervoltage (UV) and Overcurrent (OC) monitoring flags not reported. VAUX is disabled when UV or OC
detected after 1.0 ms blanking time.
01
10
11
Regulator ON. undervoltage (UV) and overcurrent (OC) monitoring flags active. VAUX is disabled when UV or OC detected after
1.0 ms blanking time.
Regulator ON. undervoltage (UV) and overcurrent (OC) monitoring flags active. VAUX is disabled when UV or OC detected after
25 μs blanking time.
b4 b3
00
5 V-can[1], 5 V-can[0] - 5V-CAN regulator control
Regulator OFF
Regulator ON. Thermal protection active. undervoltage (UV) and overcurrent (OC) monitoring flags not reported. 1.0 ms
blanking time for UV and OC detection. Note: by default when in Debug mode
01
10
11
Regulator ON. Thermal protection active. undervoltage (UV) and overcurrent (OC) monitoring flags active. 1.0 ms blanking time
for UV and OC detection.
Regulator ON. Thermal protection active. undervoltage (UV) and overcurrent (OC) monitoring flags active after 25 μs blanking
time.
b2
0
VDD bal en - Control bit to Enable the VDD external ballast transistor
External VDD ballast disable
1
External VDD ballast Enable
b1
0
VDD bal auto - Control bit to automatically Enable the VDD external ballast transistor, if VDD is > typically 60 mA
Disable the automatic activation of the external ballast
Enable the automatic activation of the external ballast, if VDD > typically 60 mA
VDD OFF en - Control bit to allow transition into LP VDD OFF mode (to prevent VDD turn OFF)
Disable Usage of LP VDD OFF mode
1
b0
0
1
Enable Usage of LP VDD OFF mode
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Table 34. CAN register(45)
MOSI Second Byte, bits 7-0
MOSI First byte [15-8]
[b_15 b_14] 10_000 [P/N]
bit 7
bit 6
bit 5
Slew[1]
0
bit 4
Slew[0]
0
bit 3
Wake-up 1/3
0
bit 2
bit 1
bit 0
CAN int
0
01 10_ 000P
Default state
CAN mod[1] CAN mod[0]
-
-
-
-
1
0
Condition for default
note
POR
POR
POR
Bits
Description
b7 b6
00
CAN mod[1], CAN mod[0] - CAN interface mode control, Wake-up enable / disable
CAN interface in Sleep mode, CAN Wake-up disable.
01
CAN interface in receive only mode, CAN driver disable.
CAN interface is in Sleep mode, CAN Wake-up enable. In device LP mode,
CAN Wake-up is reported by device Wake-up. In device Normal mode, CAN Wake-up reported by INT.
10
11
b5 b4
00/11
01
10
b3
0
CAN interface in transmit and receive mode.
Slew[1] Slew[0] - CAN driver slew rate selection
FAST
MEDIUM
SLOW
Wake-up 1/3 - Selection of CAN Wake-up mechanism
3 dominant pulses Wake-up mechanism
1
Single dominant pulse Wake-up mechanism
b0
0
CAN INT - Select the CAN failure detection reporting
Select INT generation when a bus failure is fully identified and decoded (i.e. after 5 dominant pulses on TxCAN)
Select INT generation as soon as a bus failure is detected, event if not fully identified
1
Notes
45. The first time the device is set to Normal mode, the CAN is in Sleep Wake-up enabled (bit7 = 1, bit 6 =0). The next time the device is
set in Normal mode, the CAN state is controlled by bits 7 and 6.
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Table 35. I/O register
MOSI Second Byte, bits 7-0
MOSI First byte [15-8]
[b_15 b_14] 10_001 [P/N]
bit 7
I/O-3 [1]
0
bit 6
I/O-3 [0]
0
bit 5
I/O-2 [1]
0
bit 4
I/O-2 [0]
0
bit 3
I/O-1 [1]
0
bit 2
I/O-1 [0]
0
bit 1
I/O-0 [1]
0
bit 0
I/O-0 [0]
0
01 10_ 001P
Default state
Condition for default
POR
Bits
Description
b7 b6
00
I/O-3 [1], I/O-3 [0] - I/O-3 pin operation
I/O-3 driver disable, Wake-up capability disable
I/O-3 driver disable, Wake-up capability enable.
I/O-3 HS driver enable.
01
10
11
I/O-3 HS driver enable.
b5 b4
00
I/O-2 [1], I/O-2 [0] - I/O-2 pin operation
I/O-2 driver disable, Wake-up capability disable
I/O-2 driver disable, Wake-up capability enable.
I/O-2 HS driver enable.
01
10
11
I/O-2 HS driver enable.
b3 b2
00
I/O-1 [1], I/O-1 [0] - I/O-1 pin operation
I/O-1 driver disable, Wake-up capability disable
I/O-1 driver disable, Wake-up capability enable.
I/O-1 LS driver enable.
01
10
11
I/O-1 HS driver enable.
b1 b0
00
I/O-0 [1], I/O-0 [0] - I/O-0 pin operation
I/O-0 driver disable, Wake-up capability disable
I/O-0 driver disable, Wake-up capability enable.
I/O-0 LS driver enable.
01
10
11
I/O-0 HS driver enable.
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Table 36. INT register
MOSI Second Byte, bits 7-0
MOSI First byte [15-8]
[b_15 b_14] 10_010 [P/N]
bit 7
bit 6
bit 5
LIN2 fail
0
bit 4
LIN1fail
0
bit 3
I/O
0
bit 2
SAFE
0
bit 1
bit 0
Vmon
0
01 10_ 010P
Default state
CAN failure MCU req
-
0
0
0
Condition for default
POR
Bits
Description
CAN failure - control bit for CAN failure INT (CANH/L to GND, VDD or VSUP, CAN overcurrent, Driver Overtemp, TXD-PD,
RXD-PR, RX2HIGH, and CANBUS Dominate clamp)
b7
0
1
INT disable
INT enable.
b6
0
MCU req - Control bit to request an INT. INT will occur once when the bit is enable
INT disable
1
INT enable.
b5
0
LIN2 fail - Control bit to enable INT when of failure on LIN2 interface
INT disable
1
INT enable.
b4
0
LIN/1 fail - Control bit to enable INT when of failure on LIN1 interface
INT disable
1
INT enable.
b3
0
I/O - Bit to control I/O interruption: I/O failure
INT disable
INT enable.
1
SAFE - Bit to enable INT when of: Vaux overvoltage, VDD overvoltage, VDD Temp pre-warning, VDD undervoltage(46), SAFE
b2
resistor mismatch, RST terminal short to VDD, MCU request INT.(47)
0
1
INT disable
INT enable.
VMON - enable interruption by voltage monitoring of one of the voltage regulator: VAUX, 5 V-CAN, VDD (IDD Overcurrent, VSUV
SOV, VSENSELOW, 5V-CAN low or thermal shutdown, VAUX low or VAUX overcurrent
,
b0
V
0
1
INT disable
INT enable.
Notes
46. If VDD undervoltage is set to 70% of VDD, see bits b6 and b5 in Table 15 on page 69.
47. Bit 2 is used in conjunction with bit 6. Both bit 6 and bit 2 must be set to 1 to activate the MCU INT request.
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Table 37. LIN/1 Register(49)
MOSI Second Byte, bits 7-0
MOSI First byte [15-8]
[b_15 b_14] 10_010 [P/N]
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
LIN T/1 on
0
bit 1
bit 0
VSUP ext
0
01 10_ 011P
Default state
LIN mode[1] LIN mode[0] Slew rate[1] Slew rate[0]
-
-
0
0
0
0
0
0
Condition for default
POR
Bits
Description
b7 b6
00
LIN mode [1], LIN mode [0] - LIN/1 interface mode control, Wake-up enable / disable
LIN/1 disable, Wake-up capability disable
not used
01
10
LIN/1 disable, Wake-up capability enable
LIN/1 Transmit Receive mode(48)
11
b5 b4
00
Slew rate[1], Slew rate[0] LIN/1 slew rate selection
Slew rate for 20 kbit/s baud rate
Slew rate for 10 kbit/s baud rate
Slew rate for fast baud rate
01
10
11
Slew rate for fast baud rate
b2
0
LIN T/1 on
LIN/1 termination OFF
LIN/1 termination ON
1
b0
0
VSUP ext
LIN goes recessive when device VSUP/2 is below typically 6.0 V. This is to meet J2602 specification
LIN continues operation below VSUP/2 6.0 V, until 5 V-CAN is disabled.
1
Notes
48. The LIN interface can be set in TXD/RXD mode only when the TXD-L input signal is in recessive state. An attempt to set TXD/RXD
mode, while TXD-L is low, will be ignored and the LIN interface remains disabled.
49. In order to use the LIN interface, the 5V-CAN regulator must be set to ON.
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Table 38. LIN2 register(51)
MOSI Second Byte, bits 7-0
MOSI First byte [15-8]
[b_15 b_14] 10_010 [P/N]
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
LIN T2 on
0
bit 1
bit 0
VSUP ext
0
01 10_ 100P
Default state
LIN mode[1] LIN mode[0] Slew rate[1] Slew rate[0]
-
-
0
0
0
0
0
0
Condition for default
POR
Bits
Description
b7 b6
00
LIN mode [1], LIN mode [0] - LIN 2 interface mode control, Wake-up enable / disable
LIN2 disable, Wake-up capability disable
not used
01
10
LIN2 disable, Wake-up capability enable
LIN2 Transmit Receive mode(50)
11
b5 b4
00
01
10
11
b2
0
Slew rate[1], Slew rate[0] LIN 2slew rate selection
Slew rate for 20 kbit/s baud rate
Slew rate for 10 kbit/s baud rate
Slew rate for fast baud rate
Slew rate for fast baud rate
LIN T2 on
LIN 2 termination OFF
1
LIN 2 termination ON
b0
0
VSUP ext
LIN goes recessive when device VSUP/2 is below typically 6.0 V. This is to meet J2602 specification
LIN continues operation below VSUP/2 6.0 V, until 5 V-CAN is disabled.
1
Notes
50. The LIN interface can be set in TXD/RXD mode only when the TXD-L input signal is in a recessive state. An attempt to set TXD/RXD
mode while TXD-L is low, will be ignored and the LIN interface will remain disabled.
51. In order to use the LIN interface, the 5V-CAN regulator must be set to ON.
10.4 Flags and device status
10.4.1 Description
The table below is a summary of the device flags, I/O real time level, device Identification, and includes examples of SPI commands (SPI
commands do not use parity functions). They are obtained using the following commands.
This command is composed of the following:
bits 15 and 14:
• [1 1] for failure flags
• - [0 0] for I/O real time status, device identification and CAN LIN driver receiver real time state.
• bit 13 to 9 are the register address from which the flags is to be read.
• bit 8 = 1 (this is not parity bit function, as this is a read command).
When a failure event occurs, the respective flag is set and remains latched until it is cleared by a read command (provided the failure
event has recovered).
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Table 39. Device flag, I/O real time and device identification
Bits
15-14
13-9
8
7
6
5
4
3
2
1
0
MOSI bits 15-7
MOSI
Next 7 MOSI bits (bits 6.0) should be “000_0000”
bits [15, Address
14] [13-9]
bit
7
bit 8
MISO bits [7-0], device response on MISO pin
8 Bits Device Fixed Status
(bits 15...8)
MISO
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
5V-CAN_
5V-CAN_
overCURR
ENT
VSUP_
underVOLT
AGE
IDD-OC-
0_1111
REG
5V-CAN_
UV
VSENSE_
LOW
VAUX_overCU
THERMAL
SHUTDO
WN
11
1
0
1
VAUX_LOW
NORMAL
MODE
RRENT
REG
VDD_
IDD-OC-LP
VDDON
RST_LOW
VSUP_
(<100 ms) BATFAIL
THERMAL
SHUTDOW
N
11
-
-
-
MODE
Hexa SPI commands to get Vreg Flags: MOSI 0x DF 00, and MOSI Ox DF 80
CAN
Overcurren
t
CAN
Wake-up
CAN
Overtemp
Bus Dom
clamp
0
1
-
RXD low(52) Rxd high TXD dom
1_0000
CAN
11
00
1
1
CANL
to VBAT
CANL to
VDD
CANL to
GND
CANH to
VBAT
CANH to
VDD
CANH to
GND
CAN_UF
CAN_F
CAN
Hexa SPI commands to get CAN Flags: MOSI 0x E1 00, and MOSI 0x E1 80
CAN
Receiver
State
1_0000
CAN
CAN Driver
State
CAN WU
en/dis
1
-
-
-
-
-
Hexa SPI commands to get CAN real time status: MOSI 0x 21 80
watchdog
flash mode
50%
HS3 short HS2 short to SPI parity CSB low
I/O_O
thermal
0
1
V
V
SUP/2-UV SUP/1-OV
to GND
GND
error
>2.0 ms
FWU
1_0001
I/O
11
00
11
00
1
Hardware
Leave
Debug
I/O_1-3
Wake-up
I/O_0-2
Wake-up
SPI Wake-
up
INTservice LP VDD
Timeout OFF
Reset
request
I/O
Hexa SPI commands to get I/O Flags and I/O Wake-up: MOSI 0x E3 00, and MOSI 0x E3 80
1_0001
I/O
I/O_3
state
I/O_2
state
1
1
1
1
I/O_1 state
I/O_0 state
Hexa SPI commands to get I/O real time level: MOSI 0x 23 80
VDD
INT
request
DBG
VDD temp
VAUX_overVO
0
1
RST high
-
VDD UV Overvoltag
e
-
resistor Pre-warning
LTAGE
1_0010
SAFE
watchdog
refresh
failure
VDD low
>100 ms
VDD low
RST
RST low
>100 ms
multiple
Resets
-
-
SAFE
Hexa SPI commands to get INT and RST Flags: MOSI 0x E5 00, and MOSI 0x E5 80
1_0010
SAFE
device
p/n 1
device
p/n 0
VDD (5.0 V
or 3.3 V)
1
id4
id3
id2
id1
id0
Hexa SPI commands to get device Identification: MOSI 0x 2580
example: MISO bit [7-0] = 1011 0100: MC33904, 5.0 V version, silicon Rev. C and D
LIN1 Term
short to
GND
1_0011
LIN 1
LIN1
Wake-up
LIN 1
Overtemp
LIN1 bus
dom clamp
11
00
1
1
0
1
-
RXD1 low RXD1 high TXD1 dom
LIN/1
Hexa SPI commands to get LIN 2 Flags: MOSI 0x E7 00
1_0011
LIN 1
LIN1 WU
en/dis
LIN1 State
-
-
-
-
-
-
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Table 39. Device flag, I/O real time and device identification
Hexa SPI commands to get LIN1 real time status: MOSI 0x 27 80
LIN2 Term
short to
GND
1_0100
LIN 2
LIN2
Wake-up
LIN 2
Overtemp
LIN2 bus
dom clamp
11
00
1
1
0
1
-
RXD2 low RXD2 high TXD2 dom
LIN2
Hexa SPI commands to get LIN 2 Flags: MOSI 0x E9 00
LIN2 WU
1_0100
LIN 2
LIN2 State
-
-
-
-
-
-
en/dis
Hexa SPI commands to get LIN2 real time status: MOSI 0x 29 80
Notes
52. Not available on ‘C’ and ‘D’ versions
Table 40. Flag descriptions
Flag
Description
REG
Description
VAUX_LOW
Reports that VAUX regulator output voltage is lower than the VAUX
_
UV threshold.
Set / Reset condition
Set: VAUX below threshold for t >100 μs typically. Reset: VAUX above threshold and flag read (SPI)
Report that current out of VAUX regulator is above VAUX_OC threshold.
Description
VAUX_overCUR
RENT
Set / Reset condition
Description
Set: Current above threshold for t >100 μs. Reset: Current below threshold and flag read by SPI.
Report that the 5 V-CAN regulator has reached overtemperature threshold.
5 V-CAN_
THERMAL
SHUTDOWN
Set: 5 V-CAN thermal sensor above threshold. Reset: thermal sensor below threshold and flag read
(SPI)
Set / Reset condition
Description
Reports that 5 V-CAN regulator output voltage is lower than the 5 V-CAN UV threshold.
Set: 5V-CAN below 5V-CAN UV for t >100 μs typically. Reset: 5V-CAN > threshold and flag read (SPI)
Report that the CAN driver output current is above threshold.
5V-CAN_UV
Set / Reset condition
Description
5V-can_
overcurrent
Set: 5V-CAN current above threshold for t>100 μs. Reset: 5V-CAN current below threshold and flag
read (SPI)
Set / Reset condition
Description
Reports that VSENSE pin is lower than the VSENSE LOW threshold.
VSENSE_
LOW
Set: VSENSE below threshold for t >100 μs typically. Reset: VSENSE above threshold and flag read
(SPI)
Set / Reset condition
VSUP_
Description
Reports that VSUP/1 pin is lower than the VS1_LOW threshold.
UNDERVOLTAG
E
Set / Reset condition
Description
Set: VSUP/1 below threshold for t >100 μs typically. Reset: VSUP/1 above threshold and flag read (SPI)
Report that current out of VDD pin is higher that IDD-OC threshold, while device is in Normal mode.
Set: current above threshold for t>100 μs typically. Reset; current below threshold and flag read (SPI)
Report that the VDD has reached overtemperature threshold, and was turned off.
IDD-OC-
NORMAL MODE Set / Reset condition
VDD_
Description
THERMAL
SHUTDOWN
Set / Reset condition
Set: VDD OFF due to thermal condition. Reset: VDD recover and flag read (SPI)
Description
Report that the RST pin has detected a low level, shorter than 100 ms
RST_LOW
(<100 ms)
Set / Reset condition
Description
Set: after detection of reset low pulse. Reset: Reset pulse terminated and flag read (SPI)
Report that the device voltage at VSUP/1 pin was below BATFAIL threshold.
Set: VSUP/1 below BATFAIL. Reset: VSUP/1 above threshold, and flag read (SPI)
VSUP_
BATFAIL
Set / Reset condition
Report that current out of VDD pin is higher that IDD-OC threshold LP, while device is in LP V
mode.
ON
DD
Description
IDD-OC-LP
V
DDON mode
Set / Reset condition
Set: current above threshold for t>100 μs typically. Reset; current below threshold and flag read (SPI)
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Table 40. Flag descriptions
Flag
Description
CAN
Description
CAN driver
Report real time CAN bus driver state: 1 if Driver is enable, 0 if driver disable
Set: CAN driver is enable. Reset: CAN driver is disable. Driver can be disable by SPI command (ex
CAN set in RXD only mode) or following a failure event (ex: TXD Dominant). Flag read SPI command
(0x2180) do not clear the flag, as it is “real time” information.
state
Set / Reset condition
Description
Report real time CAN bus receiver state: 1 if Enable, 0 if disable
CAN receiver
state
Set: CAN bus receiver is enable. Reset: CAN bus receiver is disable. Receiver disable by SPI
command (ex: CAN set in sleep mode). Flag read SPI command (0x2180) do not clear the flag, as it
is “real time” information.
Set / Reset condition
Description
Report real time CAN bus Wake-up receiver state: 1 if WU receiver is enable, 0 if disable
CAN WU
enable
Set: CAN Wake-up receiver is enable. Reset: CAN Wake-up receiver is disable. Wake-up receiver is
controlled by SPI, and is active by default after device Power ON. SPI command (0x2180) do not
change flag state.
Set / Reset condition
Description
Report that Wake-up source is CAN
CAN
Wake-up
Set / Reset condition
Description
Set: after CAN wake detected. Reset: Flag read (SPI)
Report that the CAN interface has reach overtemperature threshold.
Set: CAN thermal sensor above threshold. Reset: thermal sensor below threshold and flag read (SPI)
Report that RXD pin is shorted to GND.
CAN
Overtemp
Set / Reset condition
Description
RXD low(53)
Rxd high
Set / Reset condition
Description
Set: RXD low failure detected. Reset: failure recovered and flag read (SPI)
Report that RXD pin is shorted to recessive voltage.
Set / Reset condition
Description
Set: RXD high failure detected. Reset: failure recovered and flag read (SPI)
Report that TXD pin is shorted to GND.
TXD dom
Set / Reset condition
Description
Set: TXD low failure detected. Reset: failure recovered and flag read (SPI)
Report that the CAN bus is dominant for a time longer than tDOM
Set: Bus dominant clamp failure detected. Reset: failure recovered and flag read (SPI)
Report that the CAN current is above CAN overcurrent threshold.
Set: CAN current above threshold. Reset: current below threshold and flag read (SPI)
Report that the CAN failure detection has not yet identified the bus failure
Set: bus failure pre detection. Reset: CAN bus failure recovered and flag read
Report that the CAN failure detection has identified the bus failure
Set: bus failure complete detetction.Reset: CAN bus failure recovered and flag read
Report CAN L short to VBAT failure
Bus Dom
clamp
Set / Reset condition
Description
CAN
Overcurrent
Set / Reset condition
Description
CAN_UF
CAN_F
Set / Reset condition
Description
Set / Reset condition
Description
CANL
to VBAT
Set / Reset condition
Description
Set: failure detected. Reset failure recovered and flag read (SPI)
Report CANL short to VDD
CANL to VDD
CANL to GND
Set / Reset condition
Description
Set: failure detected. Reset failure recovered and flag read (SPI)
Report CAN L short to GND failure
Set / Reset condition
Description
Set: failure detected. Reset failure recovered and flag read (SPI)
Report CAN H short to VBAT failure
CANH
to VBAT
Set / Reset condition
Description
Set: failure detected. Reset failure recovered and flag read (SPI)
Report CANH short to VDD
CANH to VDD
Set / Reset condition
Description
Set: failure detected. Reset failure recovered and flag read (SPI)
Report CAN H short to GND failure
CANH to
GND
Set / Reset condition
Set: failure detected. Reset failure recovered and flag read (SPI)
Notes
53. Not available on ‘C’ and ‘D’ versions
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Table 40. Flag descriptions
Flag
Description
I/O
Description
Report I/O-3 HS switch short to GND failure
HS3 short to
GND
Set / Reset condition
Description
Set: failure detected. Reset failure recovered and flag read (SPI)
Report I/O-2 HS switch short to GND failure
HS2 short to
GND
Set / Reset condition
Description
Set: failure detected. Reset failure recovered and flag read (SPI)
Report SPI parity error was detected.
SPI parity
error
Set / Reset condition
Description
Set: failure detected. Reset: flag read (SPI)
Report SPI CSB was low for a time longer than typically 2.0 ms
Set: failure detected. Reset: flag read (SPI)
CSB low
>2.0 ms
Set / Reset condition
Description
Report that V
is below V
threshold.
S2_LOW
SUP/2
V
SUP/2-UV
Set / Reset condition
Description
Set V
SUP/2
below V
thresh. Reset V
> V
thresh and flag read (SPI)
S2_LOW
S2_LOW
SUP/2
Report that V
is above V
threshold.
S_HIGH
SUP/1
V
SUP/1-OV
Set / Reset condition
Description
Set V
SUP/1
above V
threshold. Reset V
< V
thresh and flag read (SPI)
S_HIGH
S_HIGH
SUP/1
Report that the I/O-0 HS switch has reach overtemperature threshold.
I/O-0 thermal
Set: I/O-0 HS switch thermal sensor above threshold. Reset: thermal sensor below threshold and flag
read (SPI)
Set / Reset condition
watchdog
flash mode
50%
Description
Report that the watchdog period has reach 50% of its value, while device is in Flash mode.
Set: watchdog period > 50%. Reset: flag read
Set / Reset condition
Description
Report that Wake-up source is I/O-1 or I/O-3
I/O-1-3 Wake-
up
Set / Reset condition
Description
Set: after I/O-1 or I/O-3 wake detected. Reset: Flag read (SPI)
Report that Wake-up source is I/O-0 or I/O-2
I/O-0-2 Wake-
up
Set / Reset condition
Description
Set: after I/O-0 or I/O-2 wake detected. Reset: Flag read (SPI)
Report that Wake-up source is SPI command, in LP V
ON mode.
DD
SPI Wake-up
FWU
Set / Reset condition
Description
Set: after SPI Wake-up detected. Reset: Flag read (SPI)
Report that Wake-up source is forced Wake-up
Set / Reset condition
Description
Set: after Forced Wake-up detected. Reset: Flag read (SPI)
Report that INT timeout error detected.
INT service
Timeout
Set / Reset condition
Description
Set: INT service timeout expired. Reset: flag read.
Report that LP V OFF mode was selected, prior Wake-up occurred.
DD
LP VDD OFF
Set / Reset condition
Description
Set: LP V
OFF selected. Reset: Flag read (SPI)
DD
Report that RST source is an request from a SPI command (go to RST mode).
Set: After reset occurred due to SPI request. Reset: flag read (SPI)
Reset request
Set / Reset condition
Report that the device left the Debug mode due to hardware cause (voltage at DBG pin lower than
typically 8.0 V).
Description
Hardware
Leave Debug
Set / Reset condition
Set: device leave debug mode due to hardware cause. Reset: flag read.
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Table 40. Flag descriptions
Flag
Description
INT
Description
INT request
Report that INT source is an INT request from a SPI command.
Set: INT occurred. Reset: flag read (SPI)
Set / Reset condition
Description
Report that RST pin is shorted to high voltage.
Set: RST failure detection. Reset: flag read.
RST high
Set / Reset condition
Description
Report that the resistor at DBG pin is different from expected (different from SPI register content).
Set: failure detected. Reset: correct resistor and flag read (SPI).
DBG resistor
Set / Reset condition
Description
Report that the VDD has reached overtemperature pre-warning threshold.
VDD TEMP PRE-
Set: VDD thermal sensor above threshold. Reset: VDD thermal sensor below threshold and flag read
(SPI)
WARNING
Set / Reset condition
Description
Reports that VDD pin is lower than the VDDUV threshold.
VDD UV
Set / Reset condition
Set: VDD below threshold for t >100 μs typically. Reset: VDD above threshold and flag read (SPI)
Reports that VDD pin is higher than the typically VDD + 0.6 V threshold. I/O-1 can be turned OFF if
this function is selected in INIT register.
Description
VDD
overVOLTAGE
Set / Reset condition
Description
Set: VDD above threshold for t >100 μs typically. Reset: VDD below threshold and flag read (SPI)
Reports that VAUX pin is higher than the typically VAUX + 0.6 V threshold. I/O-1 can be turned OFF if
this function is selected in INIT register.
VAUX_overVOL
TAGE
Set / Reset condition
Description
Set: VAUX above threshold for t >100 μs typically. Reset: VAUX below threshold and flag read (SPI)
Reports that VDD pin is lower than the VDDUV threshold for a time longer than 100 ms
Set: VDD below threshold for t >100 ms typically. Reset: VDD above threshold and flag read (SPI)
Report that VDD is below VDD undervoltage threshold.
VDD LOW
>100 ms
Set / Reset condition
Description
VDD LOW
Set / Reset condition
Set: VDD below threshold. Reset: fag read (SPI)
0: mean 3.3 V VDD version
1: mean 5.0 V VDD version
Description
VDD (5.0 V or
3.3 V)
Set / Reset condition
N/A
Describe the device part number:
00: MC33903
Description
01: MC33904
10: MC33905S
Device P/N1
and 0
11: MC333905D
Set / Reset condition
Description
N/A
Describe the silicon revision number
10010: silicon revision A (Pass 3.1)
10011: silicon revision B (Pass 3.2)
10100: silicon revision C and D
Device id 4 to
0
Set / Reset condition
Description
N/A
Report that the RST pin has detected a low level, longer than 100 ms (Reset permanent low)
Set: after detection of reset low pulse. Reset: Reset pulse terminated and flag read (SPI)
RST low
>100 ms
Set / Reset condition
Report that the more than 8 consecutive reset pulses occurred, due to missing or wrong watchdog
refresh.
Description
Multiple
Resets
Set / Reset condition
Description
Set: after detection of multiple reset pulses. Reset: flag read (SPI)
Report that a wrong or missing watchdog failure occurred.
Set: failure detected. reset: flag read (SPI)
watchdog
refresh failure
Set / Reset condition
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Table 40. Flag descriptions
Flag
Description
LIN/1/2
Description
Report that the LIN/1/2 bus is dominant for a time longer than tDOM
LIN/1/2 bus
dom clamp
Set / Reset condition
Set: Bus dominant clamp failure detected. Reset: failure recovered and flag read (SPI)
Report real time LIN interface TXD/RXD mode. 1 if LIN is in TXD/RXD mode. 0 is LIN is not in TXD/
RXD mode.
Description
LIN/1/2 State
LIN/1/2 WU
Set: LIN in TXD RXD mode. Reset: LIN not in TXD/RXD mode. LIN not in TXD/RXD mode by SPI
command (ex LIN set in Sleep mode) or following a failure event (ex: TxL Dominant). Flag read SPI
command (0x2780 or 0x2980) do not clear it, as it is ‘real time’ flag.
Set / Reset condition
Description
Report real time LIN Wake-up receiver state. 1 if LIN Wake-up is enable, 0 if LIN Wake-up is disable
(means LIN signal will not be detected and will not Wake-up the device).
Set: LIN WU enable (LIN interface set in Sleep mode Wake-up enable). Reset: LIN Wake-up disable
(LIN interface set in Sleep mode Wake-up disable). Flag read SPI command (0x2780 or 0x2980) do
not clear the flag, as it is ‘real time’ information.
Set / Reset condition
Description
Report that Wake-up source is LIN/1/2
LIN/1/2
Wake-up
Set / Reset condition
Description
Set: after LIN/1/2 wake detected. Reset: Flag read (SPI)
Report LIN/1/2 short to GND failure
LIN/1/2 Term
short to GND
Set / Reset condition
Description
Set: failure detected. Reset failure recovered and flag read (SPI)
Report that the LIN/1/2 interface has reach overtemperature threshold.
Set: LIN/1/2 thermal sensor above threshold. Reset: sensor below threshold and flag read (SPI)
Report that RXD/1/2 pin is shorted to GND.
LIN/1/2
overtemp
Set / Reset condition
Description
RXD-L/1/2
low
Set / Reset condition
Description
Set: RXD low failure detected. Reset: failure recovered and flag read (SPI)
Report that RXD/1/2pin is shorted to recessive voltage.
Set: RXD high failure detected. Reset: failure recovered and flag read (SPI)
Report that TXD/1/2 pin is shorted to GND.
RXD-L/1/2
high
Set / Reset condition
Description
TXD-L/1/2
dom
Set / Reset condition
Set: TXD low failure detected. Reset: failure recovered and flag read (SPI)
10.4.2 Fix and extended device status
For every SPI command, the device response on MISO is fixed status information. This information is either:
Two Bytes
Fix Status + Extended Status: when a device write command is used (MOSI bits 15-14, bits C1 C0 = 01)
One Byte
Fix Status: when a device read operation is performed (MOSI bits 15-14, bits C1 C0 = 00 or 11).
Table 41. Status bits description
Bits
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CAN-
G
SAFE- VREG-
CAN-
BUS
CAN-
LOC
VREG-
1
MISO
INT WU
RST
LIN-G I/O-G
LIN2 LIN1 I/O-1 I/O-0
VREG-0
G
G
Bits
Description
INT
Indicates that an INT has occurred and that INT flags are pending to be read.
Indicates that a Wake-up has occurred and that Wake-up flags are pending to be read.
WU
RST
CAN-G
LIN-G
Indicates that a reset has occurred and that the flags that report the reset source are pending to be read.
The INT, WU, or RST source is CAN interface. CAN local or CAN bus source.
The INT, WU, or RST source is LIN2 or LIN1 interface
I/O-G
The INT, WU, or RST source is I/O interfaces.
SAFE-G
VREG-G
CAN-LOC
CAN-BUS
The INT, WU, or RST source is from a SAFE condition
The INT, WU, or RST source is from a Regulator event, or voltage monitoring event
The INT, WU, or RST source is CAN interface. CAN local source.
The INT, WU, or RST source is CAN interface. CAN bus source.
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NXP Semiconductors
SERIAL PERIPHERAL INTERFACE
Bits
Description
LIN2
LIN/LIN1
I/O-0
The INT, WU, or RST source is LIN2 interface
The INT, WU, or RST source is LIN1 interface
The INT, WU, or RST source is I/O interface, flag from I/O sub adress Low (bit 7 = 0)
The INT, WU, or RST source is I/O interface, flag from I/O sub adress High (bit 7 = 1)
I/O-1
VREG-1
VREG-0
The INT, WU, or RST source is from a Regulator event, flag from REG register sub adress high (bit 7 = 1)
The INT, WU, or RST source is from a Regulator event, flag from REG register sub adress low (bit 7 = 0)
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91
TYPICAL APPLICATIONS
11 Typical applications
* Optional
5.0 V (3.3 V)
>2.2
Q2
RF module
Switch Detection Interface
eSwitch
μF
<10 k
V
BAT
Safing Micro Controller
CAN xcvr
*
Q1
V
BAUX VAUX
VCAUX
D1
VE
V
SUP
V
SUP2
SUP1
V
B
22 μF
100 nF
V
(54)
V
V
DD
DD
DBG
5V-CAN
>4.7 μF
>1.0 μF
1.0 k
22 k
RST
RST
INT
A/D
V
BAT
INT
V
SENSE
MUX
100 nF
100 nF
4.7 k *
I/O-0
V
MOSI
SCLK
MISO
CS
SUP
MCU
SPI
I/O-1
CANH
TXD
60
60
CAN
LIN1
RXD
SPLIT
CANL
4.7 nF
TXD-L1
RXD-L1
CAN BUS
VSUP1/2
LIN TERM1
TXD-L2
RXD-L2
LIN2
1.0 k
1.0 k
LIN BUS 1
VSUP1/2
LIN1
option 2
option 1
N/C
LIN TERM2
1.0 k
1.0 k
LIN BUS 1
LIN2
option 2
option 1
GND
SAFE
V
SUP
V
SUP
Safe Circuitry
Notes
54. Tested per specific OEM EMC requirements for CAN and LIN with additional
capacitor > 10 μF on VSUP1/VSUP2 pins
Figure 42. 33905D typical application schematic
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NXP Semiconductors
TYPICAL APPLICATIONS
5.0 V (3.3 V)
Q2
RF module
Switch Detection Interface
eSwitch
Safing Micro Controller
CAN xcvr
>2.2 μF
<10 k
V
BAT
Q1*
VBAUX VCAUX VAUX
D1
VE
V
VSUP2
VSUP1
DBG
SUP
VB
22 μF
100 nF
(55)
VDD
VDD
>4.7 μF
>1.0 μF
5V-CAN
RST
INT
A/D
1.0 k
RST
V
BAT
INT
VSENSE
I/O-0
22 k
100 nF
100 nF
MUX
V
SUP
4.7 k *
MOSI
SCLK
MISO
CS
MCU
I/O-1
SPI
V
SUP
TXD
CAN
LIN1
I/O-3
RXD
CANH
TXD-L1
RXD-L1
60
60
SPLIT
CANL
4.7 nF
CAN BUS
LIN TERM1
VSUP1/2
1.0 k
option 1
1.0 k
option 2
LIN BUS 1
LIN1
GND
SAFE
V
SUP
V
SUP
Safe Circuitry
Notes
55. Tested per specific OEM EMC requirements for CAN and LIN with additional
capacitor > 10 μF on VSUP1/VSUP2 pins
Figure 43. 33905S typical application schematic
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93
TYPICAL APPLICATIONS
* Optional
5V (3.3 V)
Q2
RF module
Switch Detection Interface
>2.2 μF
<10 k
V
eSwitch
BAT
Q1*
>4.7 μF
4.7 k *
Safing Micro Controller
CAN xcvr
VBAUX VCAUX VAUX VE
D1
V
SUP
VSUP2
VSUP1
VB
22 μF
100 nF
(56)
VDD
VDD
DBG
>1.0 μF
1.0 k
RST
RST
INT
A/D
5V-CAN
V
BAT
INT
VSENSE
I/O-0
MUX
100nF
22 k
MCU
MOSI
SCLK
MISO
CS
V
SUP
100 nF
SPI
I/O-1
V
BAT
22 k
TXD
CAN
I/O-2
V
RXD
SUP
100 nF
I/O-3
N/C
CANH
60
60
SPLIT
CANL
4.7 nF
CAN BUS
GND
SAFE
V
V
SUP
SUP
OR
function
Safe Circuitry
Notes
56. Tested per specific OEM EMC requirements for CAN and LIN with additional
capacitor > 10 μF on VSUP1/VSUP2 pins
Figure 44. 33904 typical application schematic
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NXP Semiconductors
TYPICAL APPLICATIONS
V
BAT
D1
V
SUP
VSUP1
22 μF
100 nF
VSUP2
DBG
VDD
VDD
(57)
>4.7 μF
>1.0 μF
RST
INT
RST
INT
5V-CAN
V
BAT
MOSI
SCLK
MISO
CS
MCU
I/O-0
SPI
22 k
100 nF
CANH
TXD
60
60
CAN
SPLIT
CANL
RXD
4.7 nF
N/C
CAN BUS
GND
SAFE
V
V
SUP
SUP
OR
function
Safe Circuitry
Notes
57. Tested per specific OEM EMC requirements for CAN and LIN with additional
capacitor > 10 μF on VSUP1/VSUP2 pins
Figure 45. 33903 typical application schematic
33903/4/5
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95
TYPICAL APPLICATIONS
V
BAT
*
Q1
* = Optional
D1
V
SUP
VSUP
VB
VE
22 μF
100 nF
VDD
VDD
DBG
>4.7 μF
>1.0 μF
5V-CAN
1.0 k
22 k
V
RST
RST
INT
A/D
BAT
INT
VSENSE
100 nF
100 nF
MUX
IO-0
4.7 k (optional)
MOSI
SCLK
MISO
CS
CANH
SPLIT
CANL
LIN-T1
LIN1
SPI
MCU
60
60
4.7 nF
TXD
CAN BUS
CAN
LIN1
RXD
TXD-L1
RXD-L1
VSUP
LIN BUS 1
1.0 k
option1
1.0 k
TXD-L2
RXD-L2
option2
LIN2
LIN-T2
LIN2
VSUP
LIN BUS 2
1.0 k
1.0 k
V
SUP
V
SUP
GND
SAFE
option1
option2
Safe Circuitry
Notes
58. Tested per specific OEM EMC requirements for CAN and LIN with additional
capacitor > 10 μF on VSUP pin
Figure 46. 33903D typical application schematic
33903/4/5
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NXP Semiconductors
TYPICAL APPLICATIONS
V
BAT
*
Q1
* = Optional
D1
V
SUP
VSUP
VE VB
VDD
22 μF
100 nF
VDD
DBG
>4.7 μF
>1.0 μF
5V-CAN
1.0 k
22 k
V
RST
RST
INT
A/D
BAT
INT
VSENSE
IO-0
100 nF
100 nF
MUX
V
SUP
4.7 k (optional)
MOSI
SCLK
MISO
CS
IO-3
SPI
MCU
CANH
SPLIT
CANL
LIN-T
LIN
TXD
CAN
LIN
RXD
60
60
TXD-L
RXD-L
4.7 nF
CAN BUS
VSUP
LIN BUS
1.0 k
option1
N/C
1.0 k
option2
V
SUP
V
SUP
GND
SAFE
Safe Circuitry
Notes
59. Tested per specific OEM EMC requirements for CAN and LIN with additional
capacitor > 10 μF on VSUP pin
60. Leave N/C pins open.
Figure 47. 33903S typical application schematic
33903/4/5
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97
TYPICAL APPLICATIONS
V
BAT
*
Q1
* = Optional
D1
V
SUP
VSUP
VE VB
VDD
22 μF
100 nF
VDD
DBG
>4.7 μF
>1.0 μF
5V-CAN
1.0 k
22 k
V
RST
RST
INT
A/D
BAT
INT
VSENSE
IO-0
100 nF
100 nF
MUX
4.7 k (optional)
MOSI
SCLK
MISO
CS
V
BAT
SPI
MCU
22 k
100 nF
I/O-2
IO-3
V
SUP
TXD
CAN
RXD
CANH
SPLIT
CANL
60
60
4.7 nF
N/C
CAN BUS
V
SUP
V
SUP
GND
SAFE
Safe Circuitry
Notes
61. Tested per specific OEM EMC requirements for CAN and LIN with additional
capacitor > 10 μF on VSUP pin
62. Leave N/C pins open.
Figure 48. 33903P typical application schematic
33903/4/5
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NXP Semiconductors
TYPICAL APPLICATIONS
The following figure illustrates the application case where two reverse battery diodes can be used for optimization of the filtering and
buffering capacitor at the VDD pin. This allows using a minimum value capacitor at the VDD pin to guarantee reset-free operation of the
MCU during the cranking pulse and temporary (50 ms) loss of the V
supply.
BAT
Applications without an external ballast on V and without using the VAUX regulator are illustrated as well.
DD
Q2
Q2
VBAT
5.0 V/3.3 V
Q1
5.0 V/3.3 V
Q1
D2
C2
VBAT
VBAUX
VCAUX
VBAUX
VAUX
VCAUX VAUX
VE
D1
VSUP2
VSUP1
VSUP2
VSUP1
VE
VB
D1
C1
VB
VDD
VDD
Partial View
ex1: Single VSUP Supply
Partial View
ex2: Split V
Supply
SUP
Optimized solution for cranking pulses.
C1 is sized for MCU power supply buffer only.
Q2
5.0 V/3.3 V
VBAT
VBAT
VBAUX
VCAUX VAUX
VE
VAUX
VE
D1
VBAUX
VCAUX
D1
VSUP2
VSUP1
VSUP2
VSUP1
VB
VB
VDD
VDD
Partial View
Partial View
ex 4: No External Transistor - No VAUX
ex 3: No External Transistor, VDD ~100 mA Capability
delivered by internal path transistor.
Figure 49. Application options
33903/4/5
NXP Semiconductors
99
PACKAGING
12 Packaging
12.1 SOIC 32 package dimensions
For the most current package revision, visit www.NXP.com and perform a keyword search using the “98A” listed below.
33903/4/5
100
NXP Semiconductors
PACKAGING
33903/4/5
NXP Semiconductors
101
PACKAGING
33903/4/5
102
NXP Semiconductors
PACKAGING
12.2 SOIC 54 package dimensions
33903/4/5
NXP Semiconductors
103
PACKAGING
33903/4/5
104
NXP Semiconductors
PACKAGING
33903/4/5
NXP Semiconductors
105
REVISION HISTORY
13 Revision history
Revision
Date
9/2010
Description of changes
•
•
Initial Release - This document supersedes document MC33904_5.
Initial release of document includes the MC33903 part number, the VDD 3.3 V version description, and the silicon revision
rev. 3.2. Change details available upon request.
4.0
•
•
•
•
•
•
•
•
•
Added 7.9. Cyclic INT operation during LP VDD on mode 47
Changed VSUP pin to VSUP1 and pin 2 (NC) to VSUP2 for the 33903 device
Removed . Drop voltage without external PNP pass transistor 19 for V =3.3 V devices
Added VSUP1-3.3 to . VDD Voltage regulator, VDD pin 19.
DD
5.0
12/2010
Added . Pull-up Current, TXD, VIN = 0 V 23 for V =3.3 V devices
DD
Revised 10.3.1. MUX and RAM registers 68
Revised 41. Status bits description 90
Added 10.3.5.2. Entering into LP mode using random code 77.
Removed part numbers MCZ33905S3EK/R2, MCZ33904A3EK/R2 and MCZ33905D3EK/R2, and added part numbers
MCZ33903BD3EK/R2, MCZ33903BD5EK/R2, MCZ33903BS3EK/R2 and MCZ33903BS5EK/R2.
Voltage Supply was improved from 27V to 28V.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Changed Classification from Advance Information to Technical Data.
Updated Notes in Tables 8.
Revised Tables 8; Attenuation/Gain ratio for I/O-0 and I/O-1 actual voltage: to reflect a Typical value.
Corrected typographical errors throughout.
Added Chip temperature: MUX-OUT voltage (guaranteed by design and characterization) parameter to Tables 8.
Updated I/O pins (I/O-0: I/O-3) on page 33.
6.0
4/2011
Updated VOUT-5.0-EMC maximum
Updated tLEAD parameter
Added tCSLOW parameter
Updated the Detail operation section to reflect the importance of acknowledging tLEAD and tCSLOW
Corrected typographical error in Tables 34 CAN REGISTER for Slew Rate bits b5,b4
Added 12 PCZ devices to the ordering information
Bit label change on Table 39 from INT to SAFE
Revised notes on Table 1 to include “C” version
Split Falling Edge of CS to Rising Edge of SCLK to differentiate the “C” version
Added “C” version note to Table 39 and Table 40
Added device ID 10100 Rev C, Pass 3.3 to Device id 4 to 0
Added Debug mode DBG voltage range parameter. Already detailed in text.
Added the MC33903P device, making additions throughout the document, where applicable.
7.0
8.0
9/2011
1/2011
.
2/2012
4/2013
•
•
Changed all PC devices to MC devices.
9.0
No technical changes. Revised back page. Updated document properties. Added SMARTMOS sentence to first
paragraph.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Added package type in Table 1.
Added new parameter to Output Voltage on page 19 for VDD
Added (22)
Updated section 7.5.2.2. Watchdog in debug mode 40. Replaced “set” by “left”.
Changed tCS-TO in the Dynamic electrical characteristics from 2.5 to 2.0
Note added to MUX-output (MUXOUT) on page 33 of Functional pin description
Added a paragraph in the SPI Detail operation section for the maximum tLEAD time in case the ‘CSB low’ flag is set
Added maximum tLEAD time in case the ‘CSB low’ flag is set to 1 in the Dynamic electrical characteristics table
Updated as per CIN 201608012I
10.0
2/2014
8/2014
11.0
12.0
Added ‘D’ version orderable part numbers to Table 1, Table 2, and Table 3
Updated note (2), (5), (9)
8/2016
Added note (3), (6), (10) (‘C’ versions are no longer recommended for new design) to Table 1, Table 2, and Table 3
Added reference to ‘D’ version in the document where applicable
Updated flag description for device id 4 to 0 in Table 40
Updated to NXP document format and style
Updated Figure 29 to include 3.3 V information
Updated workflow step 3 in Figure 30 (SPI commands: changed 0xDD00 to 0x1D80)
Updated bit 1 description in Table 32
Updated note (7) (deleted “Output current limited to 100 mA”)
Updated values for VRST-VTH in Table 6 as per CIN 201712019I
13.0
14.0
5/2017
2/2018
•
•
•
•
•
•
Removed typ. and max. values for V
Removed min. and typ. values for V
Removed typ. and max. values for V
(Low threshold, V = 5.0 V)
(High threshold, V = 5.0 V)
DD
RST-VTH
RST-VTH
DD
(Low threshold, V = 3.3 V)
RST-VTH
RST-VTH
DD
Removed min. and typ. values for V
(High threshold, V = 3.3 V)
DD
33903/4/5
106
NXP Semiconductors
Information in this document is provided solely to enable system and software implementers to use NXP products.
There are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits
based on the information in this document. NXP reserves the right to make changes without further notice to any
products herein.
How to Reach Us:
Home Page:
NXP.com
Web Support:
http://www.nxp.com/support
NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular
purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation, consequential or incidental damages. "Typical"
parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications,
and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each
customer application by the customer's technical experts. NXP does not convey any license under its patent rights nor
the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the
following address:
http://www.nxp.com/terms-of-use.html.
NXP, the NXP logo, Freescale, the Freescale logo and SMARTMOS are trademarks of NXP B.V. All other product or
service names are the property of their respective owners. All rights reserved.
© NXP B.V. 2018.
Document Number: MC33903_4_5
Rev. 14.0
2/2018
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