MCIMX7D2DVM12SD [NXP]
i.MX 7Dual Family;型号: | MCIMX7D2DVM12SD |
厂家: | NXP |
描述: | i.MX 7Dual Family 外围集成电路 |
文件: | 总158页 (文件大小:1354K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Document Number: IMX7DCEC
Rev. 5, 07/2017
NXP Semiconductors
Data Sheet: Technical Data
MCIMX7DxDxxxxxD
MCIMX7DxExxxxxD
i.MX 7Dual Family of
Applications Processors
Datasheet
Package Information
Plastic Package
BGA 12 x 12 mm, 0.4 mm pitch
BGA 19 x 19 mm, 0.75 mm pitch
Ordering Information
See Table 1 on page 3
1
i.MX 7Solo introduction . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.1 Ordering information. . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.1 Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Modules list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.1 Special signal considerations . . . . . . . . . . . . . . . . .15
3.2 Recommended connections for unused analog
1 i.MX 7Dual introduction
The i.MX 7Dual family of processors represents NXP’s
latest achievement in high-performance processing for
low-power requirements with a high degree of functional
integration. These processors are targeted towards the
growing market of connected and portable devices.
2
3
interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . .19
4.1 Chip-level conditions . . . . . . . . . . . . . . . . . . . . . . .19
4.2 Integrated LDO voltage regulator parameters . . . .34
4.3 PLL electrical characteristics . . . . . . . . . . . . . . . . .36
4.4 On-chip oscillators . . . . . . . . . . . . . . . . . . . . . . . . .36
4.5 I/O DC parameters . . . . . . . . . . . . . . . . . . . . . . . . .37
4.6 I/O AC parameters . . . . . . . . . . . . . . . . . . . . . . . . .41
4.7 Output buffer impedance parameters. . . . . . . . . . .45
4.8 System modules timing . . . . . . . . . . . . . . . . . . . . .47
4.9 General-purpose media interface (GPMI) timing . .67
4.10 External peripheral interface parameters . . . . . . . .75
4.11 12-Bit A/D converter (ADC) . . . . . . . . . . . . . . . . .112
Boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . .113
5.1 Boot mode configuration pins. . . . . . . . . . . . . . . .113
5.2 Boot device interface allocation . . . . . . . . . . . . . .114
Package information and contact assignments . . . . . . .116
6.1 12 x 12 mm package information . . . . . . . . . . . . .116
6.2 19 x 19 mm package information . . . . . . . . . . . . .134
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
The i.MX 7Dual family of processors features advanced
®
®
implementation of the ARM Cortex -A7 core, which
operates at speeds of up to 1 GHz and 1.2 GHz,
depending on the part number. The i.MX 7Dual family
provides up to 32-bit
DDR3/DDR3L/LPDDR2/LPDDR3-1066 memory
interface and a number of other interfaces for connecting
peripherals, such as WLAN, Bluetooth, GPS, displays,
and camera sensors.
5
6
7
NXP reserves the right to change the detail specifications as may be required to permit improvements in the design of
its products.
© 2016–2017 NXP B.V.
i.MX 7Dual introduction
The i.MX 7Dual family of processors is specifically useful for applications such as:
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•
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Audio
Connected devices
Access control panels
Human-machine interfaces (HMI)
Portable medical and health care
IP phones
Smart appliances
Point of Sale
eReaders
Wearables
Home energy management systems
The features of the i.MX 7Dual family of processors include the following:
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•
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ARM Cortex-A7 plus ARM Cortex-M4—Heterogeneous Multicore Processing architecture
enables the device to run an open operating system like Linux/Android on the Cortex-A7 core and
an RTOS like FreeRTOS™ on the Cortex-M4 core.
Two ARM Cortex-A7 cores—The processor enhances the capabilities of portable, connected
applications by fulfilling the ever-increasing MIPS needs of operating systems and applications at
lowest power consumption levels per MHz.
Multilevel memory system—The multilevel Cortex-A7 memory system is based on the L1
instruction and data caches, L2 cache, and internal and external memory. The processor supports
many types of external memory devices, including DDR3, DDR3L, LPDDR2 and LPDDR3, NOR
Flash, NAND Flash (MLC and SLC), QSPI Flash, and managed NAND, including eMMC rev.
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Power efficiency—Power management implemented throughout the IC enables features and
peripherals to consume minimum power in both active and various low-power modes.
Multimedia—The multimedia performance is enhanced by a multilevel cache system, NEON™
MPE (Media Processor Engine) coprocessor, a programmable smart DMA (SDMA) controller.
Up to two Gigabit Ethernet with AVB—10/100/1000 Mbps Ethernet controllers supporting IEEE
Std 1588 time synchronization.
Electronic Paper Display Controller (EPDC)—The processor integrates an EPD controller that
supports E Ink color and monochrome panels with up to 2048 x 1536 resolution at 106 Hz refresh,
4096 x 4096 resolution at 20 Hz refresh, and 5-bit grayscale (32-levels per color channel).
•
•
Human-machine interface (HMI)—i.MX 7Dual processor provides up to two separate display
interfaces (parallel display and two-lane MIPI-DSI), CMOS sensor interface (two-lane MIPI-CSI
and parallel).
Interface flexibility—i.MX 7Dual processor supports connections to a variety of interfaces: two
high-speed USB on-the-go modules with PHY, High-Speed Inter-Chip USB, multiple expansion
card ports (high-speed MMC/SDIO host and other), two Gigabit Ethernet controllers with support
for Ethernet AVB, PCIe-II, two 12-bit ADCs with a total of 8 single-ended inputs, two CAN ports,
2
2
and a variety of other popular interfaces (such as UART, I C, and I S).
i.MX 7Dual Family of Applications Processors Datasheet, Rev. 5, 07/2017
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NXP Semiconductors
i.MX 7Dual introduction
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•
Advanced security—The processors deliver hardware-enabled security features that enable secure
e-commerce, digital rights management (DRM), information encryption, secure boot, and secure
software downloads. The security features are discussed in detail in the i.MX 7Dual security
reference manual.
Integrated power management—The processors integrate linear regulators and internally generate
voltage levels for different power domains. This significantly simplifies system power
management structure.
For a comprehensive list of the i.MX 7Dual features, see Section 1.2, “Features.”
1.1
Ordering information
Table 1 provides examples of orderable sample part numbers covered by this data sheet.
Table 1. Orderable parts
Cortex-A7 CPU
Speed Grade
Temperature
(Tj)
Part Number
Options
Qualification Tier
Package
MCIMX7D7DVK10SD
EPDC, CAN
2 x Gigabit Ethernet
4 tamper pins
1 x ADC
1 GHz
1 GHz
Consumer1
0 to +95°C
12x12 mm
0.4 mm pitch
BGA
MCIMX7D7DVM10SD
MCIMX7D5EVM10SD
MCIMX7D3DVK10SD
MCIMX7D3EVK10SD
MCIMX7D2DVK12SD
MCIMX7D2DVM12SD
EPDC, CAN
2 x Gigabit Ethernet
10 tamper pins
2 x ADC
Consumer1
Industrial2
Consumer1
Industrial2
Consumer
Consumer
0 to +95°C
19x19 mm
0.75 mm pitch
BGA
No EPDC, CAN
2 x Gigabit Ethernet
10 tamper pins
2 x ADC
1 GHz
-20 to 105°C 19x19 mm
0.75 mm pitch
BGA
No EPDC, No CAN
2 x Gigabit Ethernet
4 tamper pins
1 GHz
0 to +95°C
12x12 mm
0.4 mm pitch
BGA
1 x ADC
No EPDC, No CAN
2 x Gigabit Ethernet
4 tamper pins
1 GHz
–20 to +105°C 12x12 mm
0.4 mm pitch
BGA
1 x ADC
No EPDC, No CAN
2 x Gigabit Ethernet
4 tamper pins
1.2 GHz
1.2 GHz
0 to 85°C
0 to 85°C
12x12 mm
0.4 mm pitch
BGA
1x ADC
No EPDC, No CAN
2x Gigabit Ethernet
10 tamper pins
2x ADC
19x19mm
0.75 mm pitch
BGA
1
2
Consumer qualification grade assumes 5-year lifetime with 50% duty cycle.
Industrial qualification grade assumes 10-year lifetime with 100% duty cycle.
i.MX 7Dual Family of Applications Processors Datasheet, Rev. 5, 07/2017
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i.MX 7Dual introduction
Figure 1 describes the part number nomenclature so that the users can identify the characteristics of the
specific part number.
1
Restricted electrical specifications for parts with CPU maximum frequency of 1.2 GHz:
•
•
Temperature range 0 to 85 degrees C (see Table 1)
VDD_ARM requirements (see Table 9)
Figure 1. Part number nomenclature—i.MX 7Dual family of processors
1.2
Features
The i.MX 7Dual family of processors is based on ARM Cortex-A7 MPCore™ Platform, which has the
following features:
®
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Two ARM Cortex-A7 Cores (with TrustZone technology)
The core configuration is symmetric, where each core includes:
— 32 KByte L1 Instruction Cache
— 32 KByte L1 Data Cache
— Private Timer and Watchdog
— NEON MPE (media processing engine) coprocessor
The ARM Cortex-A7 Core complex shares:
•
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General interrupt controller (GIC) with 128 interrupt support
Global timer
Snoop control unit (SCU)
512 KB unified I/D L2 cache
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i.MX 7Dual introduction
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Two master AXI bus interfaces output of L2 cache
Frequency of the core (including NEON and L1 cache), as per Table 9.
NEON MPE coprocessor
— SIMD Media Processing Architecture
— NEON register file with 32x64-bit general-purpose registers
— NEON Integer execute pipeline (ALU, Shift, MAC)
— NEON dual, single-precision floating point execute pipeline (FADD, FMUL)
— NEON load/store and permute pipeline
The ARM Cortex-M4 platform:
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Cortex-M4 CPU core
MPU (memory protection unit)
FPU (floating-point unit)
16 KByte instruction cache
16 KByte data cache
64 KByte TCM (tightly-coupled memory)
The SoC-level memory system consists of the following additional components:
— Boot ROM, including HAB (96 KB)
— Internal multimedia / shared, fast access RAM (256 KB of total OCRAM)
— Secure/nonsecure RAM (32 KB)
•
External memory interfaces: The i.MX 7Dual family of processors supports the latest,
high-volume, cost effective DRAM, NOR, and NAND Flash memory standards.
— Up to 32-bit LP-DDR2-1066, DDR3-1066, DDR3L-1066, and LPDDR3-1066
— 8-bit NAND-Flash, including support for Raw MLC/SLC, 2 KB, 4 KB, and 8 KB page size,
BA-NAND, PBA-NAND, LBA-NAND, OneNAND™ and others. BCH ECC up to 62 bits.
— 16/32-bit NOR Flash. All EIMv2 pins are muxed on other interfaces.
Each i.MX 7Dual processor enables the following interfaces to external devices (some of them are muxed
and not available simultaneously):
•
Displays—Available interfaces.
— One parallel 24-bit display port
— One EPD port
— One MIPI DSI port
•
•
Camera sensors:
— One parallel Camera port (up to 24 bit and up to 133 MHz peak)
— One MIPI-CSI port
Expansion cards:
— Three MMC/SD/SDIO card ports all supporting the following. Moreover, the third port can
support HS400.
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i.MX 7Dual introduction
– 1-bit or 4-bit transfer mode specifications for SD and SDIO cards, up to 208 MHz
– 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 200 MHz in both
SDR and DDR modes, including HS200 and HS400 DDR modes
•
USB
:
— Two high-speed (HS) USB 2.0 OTG (Up to 480 Mbps), with integrated HS USB PHY
— One high-speed USB 2.0 (480 Mbps) host with integrated HSIC USB (high-speed inter-chip
USB) PHY
•
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Expansion PCI Express port (PCIe) v. 2.1 one lane
— PCI Express (Gen 2.0) dual mode complex, supporting root complex operations and endpoint
operations. Uses x1 PHY configuration.
Miscellaneous IPs and interfaces:
2
— Three instances of SAI supporting up to three I S and AC97 ports
— Seven UARTs, up to 4.0 Mbps:
– Providing RS232 interface
– Supporting 9-bit RS485 Multidrop mode
— Four eCSPI (Enhanced CSPI)
2
— Four I C, supporting 400 kbps
— Two 1-gigabit Ethernet controllers (designed to be compatible with IEEE Std 1588),
10/100/1000 Mbps with AVB support
— Four pulse width modulators (PWM)
— System JTAG controller (SJC)
— GPIO with interrupt capabilities
— 8x8 key pad port (KPP)
— One quad SPI
— Four watchdog timers (WDOG)
— One (12 x 12 mm) or two (19 x 19 mm) 2-channel, 12-bit analog-to-digital converters
(ADC)—effective number of bits (ENOB) can vary (typically 9–10 bits) depending on the
system implementation and the condition of the power/ground noise condition
The i.MX 7Dual family of processors integrates advanced power management unit and controllers:
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PMU (power-management unit), multiple LDO supplies, for on-chip resources
Temperature sensor for monitoring the die temperature
Software state retention and power gating for ARM and NEON
Support for various levels of system power modes
Flexible clock gating control scheme
The i.MX 7Dual family of processors uses dedicated hardware accelerators to meet the targeted
multimedia performance. The use of hardware accelerators is a key factor in obtaining high performance
at low power consumption numbers, while having the CPU core relatively free for performing other tasks.
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i.MX 7Dual introduction
The i.MX 7Dual family of processors incorporates the following hardware accelerators:
•
PXP—PiXel processing pipeline for imagine resize, rotation, overlay and CSC. Off loading key
pixel processing operations are required to support the LCD and EPDC display applications.
•
EPDC
Security functions are enabled and accelerated by the following hardware:
•
•
ARM TrustZone technology including separation of interrupts and memory mapping
SJC—System JTAG controller. Protecting JTAG from debug port attacks by regulating or blocking
the access to the system debug features.
•
CAAM—Cryptographic acceleration and assurance module, containing cryptographic and hash
engines supporting DPA (differential power analysis) protection, 32 KB secure RAM, and true and
pseudo random number generator (NIST certified).
•
•
SNVS—Secure non-volatile storage, including secure real time clock
CSU—Central security unit. Enhancement for the IC identification module (IIM). Configured
during boot and by eFuses and determines the security-level operation mode as well as the
TrustZone policy.
•
A-HAB—Advanced high-assurance boot—HABv4 with the new embedded enhancements:
SHA-256, 2048-bit RSA key, SRK revocation mechanism, warm boot, CSU, and TrustZone
initialization.
NOTE
The actual feature set depends on the part numbers as described in Table 1.
Functions, such as display and camera interfaces, connectivity interfaces,
may not be enabled for specific part numbers.
i.MX 7Dual Family of Applications Processors Datasheet, Rev. 5, 07/2017
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Architectural overview
2 Architectural overview
The following subsections provide an architectural overview of the i.MX 7Dual processor system.
2.1
Block diagram
Figure 2 shows the functional modules in the i.MX 7Dual processor system.
JTAG
(IEEE1149.6)
LPDDR2/LPDDR3
/DDR3/DDR3L
Crystal&
Clock Source
Battery Ctrl
Device
MMC/SD
ARM Cortex A7
MPCore Platform
CPU1
External Memory
DDR Controller
Debug
DAP
TPIU
CTIs
SJC
Clock & Reset
PLLs
eMMC/eSD
NAND FLASH
CCM
GPC
SRC
EIM
GPMI&BCH
CPU0
MMC/SD
SDXC
D$ 32KB
FPU
I$ 32KB
NEON
NOR Flash
(Parallel)
QSPI
SCU & Timer
L2 Cache 512KB
XTAL OSC
RC OSC
Internal Memory
OCRAM 320KB
ROM 96KB
Timers
WDOG(4)
GPT(4)
System Counter
Touch Panel
Control
ARM Cortex M4
Platform
Cortex-M4 Core
NOR FLASH
(Quad SPI)
AP Peripherals
uSDHC(3)
Security
OCOTP
Flex Timer(2)
Keypad
CAAM
I$ 16KB
MPU
D$ 16KB
FPU
USB 2.0
(32KB RAM)
Tamper
Host (1) / OTG (2)
Detection
CSU
OCOTP (eFuse)
Smart DMA
SDMA
TCM 64KB
AVB ENET(2)
PCIe v2.1
FlexCAN(2)
SIMv2(2)
I2C(4)
10/100/1000M
Ethernet x2
SNVS(SRTC)
Multi-Core Unit
RDC
SPBA
MU
Display Interface
LCDIF
Shared Peripherals
eCSPI(3)
SEMAPHORE
WLAN
Smart Card x2
CAN x2
LCD Panel
Camera
eCSPI(1)
PWM(4)
KPP
Image Processing
Pixel Processing
Pipeline(PXP)
MIPI DSI
SAI(3)
UART(3)
Camera Interface
CSI
Power Management
Temp Monitor
LDOs
UART(4)
GPIO(7)
IOMUX
MIPI CSI(2 lane)
EPD Controller
ADC (2)
USB OTG
(dev/host)
PCIe Bus
Sensors
EPD Panel
Modem IC
Figure 2. i.MX 7Dual System block diagram
i.MX 7Dual Family of Applications Processors Datasheet, Rev. 5, 07/2017
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Modules list
3 Modules list
The i.MX 7Dual family of processors contains a variety of digital and analog modules. Table 2 describes
these modules in alphabetical order.
Table 2. i.MX 7Dual modules list
Block Mnemonic
Block Name
Subsystem
Brief Description
ADC1
ADC2
Analog to Digital
Converter
The ADC is a 12-bit general purpose analog to digital
converter (ADC2 is not available in the 12x12 package).
ARM
ARM Platform
ARM
The ARM Core Platform includes two Cortex-A7
coresand 1x Cortex-M4. It also includes associated
sub-blocks, such as the Level 2 Cache Controller, SCU
(Snoop Control Unit), GIC (General Interrupt
Controller), private timers, watchdog, and CoreSight
debug modules.
BCH
Binary-BCH ECC
Processor
System control
peripherals
The BCH module provides up to 62-bit ECC
encryption/decryption for NAND Flash controller
(GPMI)
CAAM
Cryptographic
accelerator and
assurance module
Security
CAAM is a cryptographic accelerator and assurance
module. CAAM implements several encryption and
hashing functions, a run-time integrity checker, entropy
source generator, and a Pseudo Random Number
Generator (PRNG). The pseudo random number
generator is certifiable by Cryptographic Algorithm
Validation Program (CAVP) of National Institute of
Standards and Technology (NIST).
CAAM also implements a Secure Memory mechanism.
In i.MX 7Dual processors, the security memory
provided is 32 KB.
CCM
GPC
SRC
Clock Control Module,
General Power
Controller, System Reset
Controller
Clocks, resets, and These modules are responsible for clock and reset
power control
distribution in the system, and also for the system
power management.
CSI
Parallel CSI
Multimedia
peripherals
The CSI IP provides parallel CSI standard camera
interface port. The CSI parallel data ports are up to 24
bits. It is designed to support 24-bit RGB888/YUV444,
CCIR656 video interface, 8-bit YCbCr, YUV or RGB,
and 8-bit/10-bit/16-bit Bayer data input.
CSU
DAP
Central Security Unit
Debug Access Port
security
The Central Security Unit (CSU) is responsible for
setting comprehensive security policy within the i.MX
7Dual platform.
System control
peripherals
The DAP provides real-time access for the debugger
without halting the core to access:
• System memory and peripheral registers
• All debug configuration registers
The DAP also provides debugger access to JTAG scan
chains.
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Modules list
Table 2. i.MX 7Dual modules list(continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
eCSPI1
eCSPI2
eCSPI3
eCSPI4
Configurable SPI
Connectivity
Peripherals
Full-duplex enhanced Synchronous Serial Interface,
with data rate up to 52 Mbit/s. It is configurable to
support Master/Slave modes, four chip selects to
support multiple peripherals.
EIM
NOR-Flash /PSRAM
interface
Connectivity
Peripherals
The EIM NOR-FLASH / PSRAM provides:
• Support for 16-bit (in Muxed I/O mode only) PSRAM
memories (sync and async operating modes), at
slow frequency
• Support for 16-bit (in muxed and non-muxed I/O
modes) NOR-Flash memories, at slow frequency
• Multiple chip selects
ENET1
ENET2
Ethernet Controller
Connectivity
peripherals
The Ethernet Media Access Controller (MAC) is
designed to support 10/100/1000 Mbps Ethernet/IEEE
802.3 networks. An external transceiver interface and
transceiver function are required to complete the
interface to the media. The module has dedicated
hardware to support the IEEE 1588 standard. See the
ENET chapter of the i.MX 7Dual Application Processor
Reference Manual (IMX7DRM) for details.
EPDC
Electrophoretic
Display
Connectivity
peripherals
The EPDC is a feature-rich, low power, and
high-performance direct-drive, active matrix EPD
controller. It is specifically designed to drive E Ink™
EPD panels, supporting a wide variety of TFT
backplanes. Various levels of flexibility and
Controller
programmability have been introduced, as well as
hardware support for different E Ink image enhancing
algorithms, such as Regal D waveform support.
FLEXCAN1
FLEXCAN2
Flexible Controller Area
Network
Connectivity
peripherals
The CAN protocol was primarily, but not only, designed
to be used as a vehicle serial data bus, meeting the
specific requirements of this field: real-time processing,
reliable operation in the Electromagnetic interference
(EMI) environment of a vehicle, cost-effectiveness and
required bandwidth. The FlexCAN module is a full
implementation of the CAN protocol specification,
Version 2.0 B, which supports both standard and
extended message frames.
FLEXTIMER1
FLEXTIMER2
Flexible Timer Module
Timer Peripherals
Provide input signal capture and PWM support
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
General Purpose I/O
Modules
System control
peripherals
Used for general purpose input/output to external ICs.
Each GPIO module supports up to 32 bits of I/O.
GPMI
GeneralPurposeMemory
Interface
Connectivity
peripherals
The GPMI module supports up to 8x NAND devices and
62-bit ECC encryption/decryption for NAND Flash
Controller (GPMI2). GPMI supports separate DMA
channels for each NAND device.
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Modules list
Table 2. i.MX 7Dual modules list(continued)
Block Mnemonic
Block Name
General Purpose Timer
Subsystem
Brief Description
GPT
Timer peripherals
Each GPT is a 32-bit “free-running” or “set and forget”
mode timer with programmable prescaler and compare
and capture register. A timer counter value can be
captured using an external event and can be configured
to trigger a capture event on either the leading or trailing
edges of an input pulse. When the timer is configured to
operate in “set and forget” mode, it is capable of
providing precise interrupts at regular intervals with
minimal processor intervention. The counter has output
compare logic to provide the status and interrupt at
comparison. This timer can be configured to run either
on an external clock or on an internal clock.
I2C1
I2C2
I2C3
I2C4
I2C Interface
Connectivity
peripherals
I2C provide serial interface for external devices. Data
rates of up to 320 kbps are supported.
IOMUXC
IOMUX Control
Key Pad Port
System control
peripherals
This module enables flexible IO multiplexing. Each IO
pad has default and several alternate functions. The
alternate functions are software configurable.
KPP
Connectivity
peripherals
KPP Supports 8x8 external key pad matrix. KPP
features are:
• Open drain design
• Glitch suppression circuit design
• Multiple keys detection
• Standby key press detection
LCDIF
LCD interface
Multimedia
peripherals
The LCDIF is a general purpose display controller used
to drive a wide range of display devices varying in size
and capability. The LCDIF is designed to support dumb
(synchronous 24-bit Parallel RGB interface).
MIPI-CSI
(two-lane)
MIPI Camera Interface
MIPI Display Interface
DDR Controller
Multimedia
peripherals
This module provides a two-lane MIPI camera interface
operating up to a maximum bit rate of 1.5 Gbps.
MIPI DSI
(two-lane)
Connectivity
peripherals
This module provides a two-lane MIPI display interface
operating up to a maximum bit rate of 1.5 Gbps.
DDRC
MQS
Connectivity
peripherals
The DDR Controller has the following features:
• Supports 16/32-bit DDR3/DDR3L, LPDDR3, and
LPDDR2-1066
• Supports up to 2 Gbyte DDR memory space
Medium-quality sound
module
Multimedia
peripherals
MQS is used to generate 2-channel, medium-quality,
PWM-like audio, via two standard digital GPIO pins.
The electronic specification is the same as the GPIO
digital output.
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Modules list
Table 2. i.MX 7Dual modules list(continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
OCOTP_CTRL
OTP Controller
Security
The On-Chip OTP controller (OCOTP_CTRL) provides
an interface for reading, programming, and/or
overriding identification and control information stored
in on-chip fuse elements. The module supports
electrically-programmable poly fuses (eFUSEs). The
OCOTP_CTRL also provides a set of volatile
software-accessible signals that can be used for
software control of hardware elements, not requiring
non-volatility. The OCOTP_CTRL provides the primary
user-visible mechanism for interfacing with on-chip fuse
elements. Among the uses for the fuses are unique chip
identifiers, mask revision numbers, cryptographic keys,
JTAG secure mode, boot characteristics, and various
control signals, requiring permanent non-volatility.
OCRAM
On-Chip Memory
controller
Data path
The On-Chip Memory controller (OCRAM) module is
designed as an interface between system’s AXI bus
and internal (on-chip) SRAM memory module.
In i.MX 7Dual processors, the OCRAM is used for
controlling the 128 KB multimedia RAM through a 64-bit
AXI bus.
PCIe
PMU
PCI Express 2.0
Connectivity
peripherals
The PCIe IP provides PCI Express Gen 2.0
functionality.
Power Management Unit
Pulse Width Modulation
Data path
Integrated power management unit. Used to provide
power to various SoC domains.
PWM1
PWM2
PWM3
PWM4
Connectivity
peripherals
The pulse-width modulator (PWM) has a 16-bit counter
and is optimized to generate sound from stored sample
audio images and it can also generate tones. It uses
16-bit resolution and a 4x16 data FIFO to generate
sound.
PXP
PiXel Processing Pipeline Display peripherals A high-performance pixel processor capable of 1
pixel/clock performance for combined operations, such
as color-space conversion, alpha blending,
gamma-mapping, and rotation. The PXP is enhanced
with features specifically for gray scale applications. In
addition, the PXP supports traditional pixel/frame
processing paths for still-image and video processing
applications, allowing it to interface with the integrated
EPD.
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Modules list
Table 2. i.MX 7Dual modules list(continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
QSPI
Quad SPI
Connectivity
peripherals
Quad SPI module act as an interface to external serial
flash devices. This module contains the following
features:
• Flexible sequence engine to support various flash
vendor devices
• Single pad/Dual pad/Quad pad mode of operation
• Single Data Rate/Double Data Rate mode of
operation
• Parallel Flash mode
• DMA support
• Memory mapped read access to connected flash
devices
• Multi-master access with priority and flexible and
configurable buffer for each master
SAI1
SAI2
SAI3
Synchronous Audio
Interface
Connectivity
peripherals
The SAI module provides a synchronous audio
interface (SAI) that supports full duplex serial interfaces
with frame synchronization, such as I2S, AC97, TDM,
and codec/DSP interfaces.
SDMA
Smart Direct Memory
Access
System control
peripherals
The SDMA is a multichannel flexible DMA engine. It
helps in maximizing system performance by offloading
the various cores in dynamic data routing. It has the
following features:
• Powered by a 16-bit Instruction-Set micro-RISC
engine
• Multi-channel DMA supporting up to 32 time-division
multiplexed DMA channels
• 48 events with total flexibility to trigger any
combination of channels
• Memory accesses including linear, FIFO, and 2D
addressing
• Shared peripherals between ARM and SDMA
• Very fast Context-Switching with 2-level priority
based preemptive multi-tasking
• DMA units with auto-flush and prefetch capability
• Flexible address management for DMA transfers
(increment, decrement, and no address changes on
source and destination address)
• DMA ports can handle unidirectional and
bidirectional flows (Copy mode)
• Up to 8-word buffer for configurable burst transfers
for EMIv2.5
• Support of byte-swapping and CRC calculations
• Library of Scripts and API is available
SIMv2-1
SIMv2-2
Smart Card
Connectivity
peripherals
Smart card interface designed to be compatible with
ISO7816.
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Modules list
Table 2. i.MX 7Dual modules list(continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
SJC
System JTAG Controller
System control
peripherals
The SJC provides JTAG interface (designed to be
compatible with JTAG TAP standards) to internal logic.
The i.MX 7Dual family of processors uses JTAG port for
production, testing, and system debugging.
Additionally, the SJC provides BSR (Boundary Scan
Register) standard support, designed to be compatible
with IEEE 1149.1 and IEEE1149.6 standards.
The JTAG port must be accessible during platform
initial laboratory bring-up, for manufacturing tests and
troubleshooting, as well as for software debugging by
authorized entities. The i.MX 7Dual SJC incorporates
three security modes for protecting against
unauthorized accesses. Modes are selected through
eFUSE configuration.
SNVS
Secure Non-Volatile
Storage
Security
Secure Non-Volatile Storage, including Secure Real
Time Clock, Security State Machine, Master Key
Control, and Violation/Tamper Detection and reporting.
TEMPSENSOR
TZASC
Temperature Sensor
System control
peripherals
Temperature sensor
Trust-Zone Address
Space Controller
Security
The TZASC (TZC-380 by ARM) provides security
address region control functions required for intended
application. It is used on the path to the DRAM
controller.
UART1
UART2
UART3
UART4
UART5
UART6
UART7
UART Interface
Connectivity
peripherals
Each of the UARTv2 modules support the following
serial data transmit/receive protocols and
configurations:
• 7- or 8-bit data words, 1 or 2 stop bits, programmable
parity (even, odd or none)
• Programmable baud rates up to 4 Mbps. This is a
higher max baud rate relative to the 1.875 MHz,
which is stated by the TIA/EIA-232-F standard.
• 32-byte FIFO on Tx and 32 half-word FIFO on Rx
supporting auto-baud
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Modules list
Table 2. i.MX 7Dual modules list(continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
i.MX 7Dual SoC characteristics:
All the MMC/SD/SDIO controller IPs are based on the
uSDHC IP. They are designed to be:
• Fully compatible with MMC command/response sets
and Physical Layer as defined in the Multimedia
Card System Specification,
uSDHC1
uSDHC2
uSDHC3
SD/MMC and SDXC
Enhanced Multi-Media
Card / Secure Digital Host
Controller
Connectivity
peripherals
v5.0/v4.4/v4.41/v4.4/v4.3/v4.2.
• Fully compatible with SD command/response sets
and Physical Layer as defined in the SD Memory
Card Specifications v 3.0 including high-capacity
SDXC cards up to 2 TB.
• Fully compatible with SDIO command/response sets
and interrupt/Read-Wait mode as defined in the
SDIO Card Specification, Part E1, v. 3.0
All the ports support:
• 1-bit or 4-bit transfer mode specifications for SD and
SDIO cards up to UHS-I SDR104 mode (104 MB/s
max)
• 1-bit, 4-bit, or 8-bit transfer mode specifications for
MMC cards up to 200 MHz in both SDR and DDR
modes, including HS200 and HS400.
However, the SoC level integration and I/O muxing logic
restrict the functionality to the following:
• uSDHC1 and uSDHC2 are primarily intended to
serve as external slots or interfaces to on-board
SDIO devices. These ports are equipped with “Card
detection” and “Write Protection” pads and do not
support hardware reset.
• uSDHC3 is primarily intended to serve interfaces to
embedded MMC memory or interfaces to on-board
SDIO devices. These ports do not have “Card
detection” and “Write Protection” pads and do
support hardware reset.
• All ports can work with 1.8 V and 3.3 V cards. There
are two completely independent I/O power domains
for uSDHC1 and uSDHC2 in 4-bit configuration (SD
interface). uSDHC3 is placed in his own independent
power domain.
USBOTG2
2x USB 2.0 High Speed
OTG and HSIC USB
Connectivity
peripherals
USBOTG2 contains:
• Two high-speed OTG modules with integrated HS
USB PHYs
• One high-speed Host module connected to HSIC
USB port.
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Modules list
Table 2. i.MX 7Dual modules list(continued)
Block Mnemonic
Block Name
Subsystem
Brief Description
WDOG1
WDOG3
WDOG4
Watchdog
Timer peripherals
The Watch dog timer supports two comparison points
during each counting period. Each of the comparison
points is configurable to evoke an interrupt to the ARM
core, and a second point evokes an external event on
the WDOG line.
WDOG2
(TrustZone)
Watchdog (TrustZone
technology)
Timer peripherals
The TrustZone Watchdog (TZ WDOG) timer module
protects against TrustZone starvation by providing a
method of escaping Normal mode and forcing a switch
to the TZ mode. TZ starvation is a situation where the
normal OS prevents switching to the TZ mode. Such
situation is undesirable as it can compromise the
system’s security. Once the TZ WDOG module is
activated, it must be serviced by TZ software on a
periodic basis. If servicing does not take place, the
timer times out. Upon a time-out, the TZ WDOG asserts
a TZ mapped interrupt that forces switching to the TZ
mode. If it is still not served, the TZ WDOG asserts a
security violation signal to the CSU. The TZ WDOG
module cannot be programmed or deactivated by a
normal mode SW.
3.1
Special signal considerations
Table 3 lists special signal considerations for the i.MX 7Dual family of processors. The signal names are
listed in alphabetical order.
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Modules list
The package contact assignments can be found in Section 6, “Package information and contact
assignments.” Signal descriptions are provided in the i.MX 7Dual Application Processor Reference
Manual (IMX7DRM).
Table 3. Special signal considerations
Signal Name
Remarks
CCM_CLK1_P/
CCM_CLK1_N
CCM_CLK2
One general purpose differential high speed clock input/output and one single-ended clock input
are provided.
Either or both of them can be used:
• To feed an external reference clock to the PLLs and to the modules inside the SoC, for
example, as an alternate reference clock for PCIe, Video/Audio interfaces and so forth.
• To output the internal SoC clock to be used outside the SoC as either a reference clock or as
a functional clock for peripherals; for example, it can be used as an output of the PCIe master
clock (root complex use)
See the i.MX 7Dual Application Processor Reference Manual (IMX7DRM) for details on the
respective clock trees.
The CCM_CLK1_* inputs/outputs are an LVDS differential pair.
Alternatively, a single-ended signal may be used to drive CCM_CLK1_P input. In this case
corresponding CCM_CLK1_N input should be tied to the constant voltage level equal to 1/2 of the
input signal swing.
Termination should be provided in case of high frequency signals.
See the LVDS pad electrical specification for further details. CCM_CLK2 is a single-ended input
referenced to ground.
After initialization:
• The CCM_CLK1_* inputs/outputs can be disabled if not used. Any of the unused CCM_CLK1_*
pins may be left floating.
• The CCM_CLK2 input should be grounded if not used.
RTC_XTALI/RTC_XTALO If the user wishes to configure RTC_XTALI and RTC_XTALO as an RTC oscillator, a 32.768 kHz
crystal, (100 k ESR, 10 pF load) should be connected between RTC_XTALI and RTC_XTALO. It
is recommended to use the configurable load capacitors provided in the IP instead of adding them
externally. To hit the exact oscillation frequency, the configurable capacitors need to be reduced
to account for board and chip parasitics.
The integrated oscillation amplifier is self biasing, but relatively weak. Care must be taken to limit
parasitic leakage from RTC_XTALI and RTC_XTALO to either power or ground (>100 M). This will
debias the amplifier and cause a reduction of startup margin. Typically RTC_XTALI and
RTC_XTALO should bias to approximately 0.5 V.
If it is desired to feed an external low frequency clock into RTC_XTALI, the RTC_XTALO pin
should be left floating or driven with a complimentary signal. The logic level of this forcing clock
should not exceed VDD_SNVS_CAP level.
In the case when a high-accuracy realtime clock is not required, the system may use internal low
frequency oscillator. It is recommended to connect RTC_XTALI to ground and keep RTC_XTALO
floating. This will however result in increased power consumption, because the internal oscillator
uses higher power than the RTC oscillator. Thus for lowest power configuration it is recommended
to always install a crystal.
XTALI/XTALO
A 24.0 MHz crystal should be connected between XTALI and XTALO.
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Modules list
Table 3. Special signal considerations(continued)
Remarks
Signal Name
DRAM_VREF
When using DDR_VREF with DDR I/O, the nominal reference voltage must be half of the
NVCC_DRAM supply. The user must tie DDR_VREF to a precision external resistor divider. Use
a 1 kΩ 0.5% resistor to GND and a 1 kΩ 0.5% resistor to NVCC_DRAM. Shunt each resistor with
a closely-mounted 0.1 µF capacitor.
To reduce supply current, a pair of 1.5 kΩ 0.1% resistors can be used. Using resistors with
recommended tolerances ensures the 2% DDR_VREF tolerance (per the DDR3 specification)
is maintained when four DDR3 ICs plus the i.MX 7Dual are drawing current on the resistor divider.
It is recommended to use regulated power supply for “big” memory configurations (more than
eight devices)
ZQPAD
DRAM calibration resistor 240 Ω 1% used as reference during DRAM output buffer driver
calibration should be connected between this pad and GND.
PCIE_VPH/PCIE_VPH_TX/ Short these pins to VDDA_PHY1P8 if using PCIe. User can tie these pins to ground if not using
PCIE_VPH_RX PCIe.
PCIE_VP/PCIE_VP_TX/PC Short these pins to VDDD_1P0CAP if using PCIe. User can tie these pins to ground with a 10 KΩ
IE_VP_RX
resistor if not using PCIe.
VDDA_MIPI_1P8
Short these pins to VDDA_PHY_1P8 if using MIPI. User can leave these pins floating or grounded
if not using MIPI.
VDD_MIPI_1P0
Short these pins to VDDD_1P0_CAP if using MIPI. User can leave these pins floating or grounded
if not using MIPI.
GPANAIO
This signal is reserved for manufacturing use only. User must leave this connection floating.
JTAG_nnnn
The JTAG interface is summarized in Table 4. Use of external resistors is unnecessary. However,
if external resistors are used, the user must ensure that the on-chip pull-up/down configuration is
followed. For example, do not use an external pull down on an input that has on-chip pull-up.
JTAG_TDO is configured with a keeper circuit such that the floating condition is eliminated if an
external pull resistor is not present. An external pull resistor on JTAG_TDO is detrimental and
should be avoided.
JTAG_MOD is referenced as SJC_MOD in the i.MX 7Dual Application Processor Reference
Manual (IMX7DRM). Both names refer to the same signal. JTAG_MOD must be externally
connected to GND for normal operation. Termination to GND through an external pull-down
resistor (such as 1 kΩ) is allowed. JTAG_MOD set to high configures the JTAG interface to a
mode compatible with the IEEE 1149.1 standard. JTAG_MOD set to low configures the JTAG
interface for common SW debug adding all the system TAPs to the chain.
NC
Do not connect. These signals are reserved and should be floated by the user.
POR_B
This cold reset negative logic input resets all modules and logic in the IC.
May be used in addition to internally generated power on reset signal (logical AND, both internal
and external signals are considered active low).
ONOFF
In Normal mode, may be connected to ON/OFF button (De-bouncing provided at this input).
Internally this pad is pulled up. Short connection to GND in OFF mode causes internal power
management state machine to change state to ON. In ON mode short connection to GND
generates interrupt (intended to SW controllable power down). Long above ~5s connection to
GND causes “forced” OFF.
TEST_MODE
TEST_MODE is for factory use. This signal is internally connected to an on-chip pull-down device.
The user must tie this signal to GND.
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Modules list
Table 3. Special signal considerations(continued)
Remarks
Signal Name
PCIE_REXT
The impedance calibration process requires connection of reference resistor 4.7 KΩ 1% precision
resistor on PCIE_REXT pad to ground.
USB_OTG1_REXT/USB_O The bias generation and impedance calibration process for the USB OTG PHYs requires
TG2_REXT
connection of 200 Ω (1% precision) reference resistors on each of the USB_OTG1_REXT and
USB_OTG2_REXT pads to ground.
USB_OTG1_CHD_B
An external pullup resistor with value in range from 10 kΩ to 100 kΩ should be connected
between open-drain output USB_OTG1_CHD_B and supply VDD_USB_OTG1_3P3_IN for 3.3 V
signaling. Optionally, a similarly valued pullup resistor could be connected instead between
USB_OTG1_CHD_B and an unrelated supply up to 1.8 V, but in that case the output is only valid
when both that supply and VDD_USB_OTG1_3P3_IN are powered.
TEMPSENSOR_REXT
External 100 KΩ (1% precision) resistor connection pin
Table 4. JTAG controller interface summary
JTAG
I/O Type
On-chip Termination
JTAG_TCK
JTAG_TMS
JTAG_TDI
Input
Input
47 kΩ pull-up
47 kΩ pull-up
47 kΩ pull-up
100 kΩ pull-up
47 kΩ pull-up
100 kΩ pull-up
Input
JTAG_TDO
JTAG_TRSTB
JTAG_MOD
3-state output
Input
Input
3.2
Recommended connections for unused analog interfaces
Table 5 shows the recommended connections for unused analog interfaces.
Table 5. Recommended connections for unused analog interfaces
Recommendation
if Unused
Module
Package Net Name
ADC
VDDA_ADC2_1P8, VDDA_ADC2_1P8, VDDA_ADC1_1P8, 1.8 V
VDDA_ADC1_1P8
ADC2_IN3, ADC2_IN2, ADC2_IN1, ADC2_IN0, ADC1_IN0, Tie to ground
ADC1_IN1, ADC1_IN2, ADC1_IN3
LDO
MIPI
VDD_1P2_CAP
Floating if USB_HSIC is not used
VDD_MIPI_1P0, VDDA_MIPI_1P8
Floating or tie to ground
No connect
MIPI_DSI_D0_N, MIPI_DSI_D0_P, MIPI_VREG_0P4V,
MIPI_DSI_CLK_N, MIPI_DSI_CLK_P, MIPI_DSI_D1_N,
MIPI_DSI_D1_P, MIPI_CSI_D0_N, MIPI_CSI_D0_P,
MIPI_CSI_CLK_N, MIPI_CSI_CLK_P, MIPI_CSI_D1_N,
MIPI_CSI_D1_P
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Electrical characteristics
Table 5. Recommended connections for unused analog interfaces(continued)
Recommendation
if Unused
Module
Package Net Name
PCIe
PCIE_REFCLKIN_N, PCIE_REFCLKIN_P,
Floating
PCIE_REFCLKOUT_N, PCIE_REFCLKOUT_P,
PCIE_RX_N, PCIE_RX_P, PCIE_TX_N, PCIE_TX_P
PCIE_VP,PCIE_VP_RX,PCIE_VP_TX,
Tie to ground
PCIE_VPH,PCIE_VPH_RX,PCIE_VPH_TX, PCIE_REXT
SNVS
SNVS_TAMPER00, SNVS_TAMPER01, SNVS_TAMPER02, Float—configure with software
SNVS_TAMPER03, SNVS_TAMPER04, SNVS_TAMPER05,
SNVS_TAMPER06, SNVS_TAMPER07, SNVS_TAMPER08,
SNVS_TAMPER09
Temperature sensor
TEMPSENSOR_REXT
Tie to ground or pulldown with 100 KΩ
resistor
TEMPSENSOR_RESERVE
Floating
VDD_TEMPSENSOR_1P8
1.8 V
USB HSIC
USB OTG1
VDD_USB_H_1P2
Tie to ground
Floating
USB_H_DATA, USB_H_STROBE
VDD_USB_OTG1_3P3_IN, VDD_USB_OTG1_1P0_CAP
Tie to ground
Floating
USB_OTG1_VBUS, USB_OTG1_DP, USB_OTG1_DN,
USB_OTG1_ID, USB_OTG1_REXT, USB_OTG1_CHD_B
USB OTG2
VDD_USB_OTG2_3P3_IN, VDD_USB_OTG2_1P0_CAP
Tie to ground
Floating
USB_OTG2_VBUS, USB_OTG2_DP, USB_OTG2_DN,
USB_OTG2_ID, USB_OTG2_REXT
4 Electrical characteristics
This section provides the device and module-level electrical characteristics for the i.MX 7Dual family of
processors.
4.1
Chip-level conditions
This section provides the device-level electrical characteristics for the IC. See Table 6 for a quick reference
to the individual tables and sections.
Table 6. i.MX 7Dual Chip-level conditions
For these characteristics, …
Absolute maximum ratings
Topic appears …
on page 21
on page 22
on page 23
on page 25
FPBGA case “X” and case “Y” package thermal resistance
Operating ranges
External clock sources
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Electrical characteristics
Topic appears …
Table 6. i.MX 7Dual Chip-level conditions(continued)
For these characteristics, …
Maximum supply currents
Power modes
on page 26
on page 29
USB PHY Suspend current consumption
on page 32
4.1.1
Absolute maximum ratings
CAUTION
Stresses beyond those listed under Table 7 may affect reliability or cause
permanent damage to the device. These are stress ratings only. Functional
operation of the device at these or any other conditions beyond those
indicated in the operating ranges or parameters tables is not implied.
Table 7. Absolute maximum ratings
Parameter Description
Symbol
Min
Max
Unit
Core supply voltages
GPIO supply voltage
VDD_ARM
VDD_SOC
–0.5
1.5
V
NVCC_ENET1
NVCC_EPDC1
NVCC_EPDC2
NVCC_I2C
–0.3
3.6
V
NVCC_LCD
NVCC_SAI
NVCC_SD1
NVCC_SD2
NVCC_SD3
NVCC_SPI
NVCC_UART
DDR I/O supply voltage
NVCC_DRAM
NVCC_DRAM_CKE
VDD_SNVS_IN
–0.3
–0.3
–0.3
–0.3
1.975
1.98
3.6
V
V
V
V
Clock I/O supply voltage
VDD_SNVS_IN supply voltage
USB OTG PHY supply voltage
VDD_USB_OTG1_3P3_IN
VDD_USB_OTG2_3P3_IN
3.6
USB_VBUS input detected
USB_OTG1_VBUS
USB_OTG2_VBUS
–0.3
–0.3
—
5.25
3.63
3.6
V
V
V
Input voltage on USB_OTG*_DP, USB_OTG*_DN USB_OTG1_DP/USB_OTG1_DN
pins
USB_OTG2_DP/USB_OTG2_DN
USB_OTG1_CHD_B open-drain pullup voltage
when external pullup resistor is connected to
VDD_USB_OTG1_3P3_IN supply only
USB_OTG1_CHD_B
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Electrical characteristics
Table 7. Absolute maximum ratings(continued)
Parameter Description
Symbol
Min
Max
Unit
USB_OTG1_CHD_B open-drain pullup voltage
when external pullup resistor is connected to any
supply other than VDD_USB_OTG1_3P3_IN
USB_OTG2_CHD_B
—
1.975
V
Input/output voltage range
ESD damage immunity:
Vin/Vout
Vesd
–0.3
OVDD1+0.3
V
V
• Human Body Model (HBM)
• Charge Device Model (CDM)
—
—
2000
500
Storage temperature range
TSTORAGE
–40
150
oC
1
OVDD is the I/O supply voltage.
4.1.2
Thermal resistance
FPBGA case “X” and case “Y” package thermal resistance
4.1.2.1
Table 8 displays the thermal resistance data.
Table 8. Thermal Resistance Data
12x12
pkg value pkg value
19x19
Rating
Test conditions
Symbol
Unit
Junction to Ambient1
Single-layer board (1s); natural convection2
Four-layer board (2s2p); natural convection2
RθJA
RθJA
55.4
32.6
44.4
30.2
oC/W
oC/W
Junction to Ambient1
Single-layer board (1s); airflow 200 ft/min2,3
Four-layer board (2s2p); airflow 200 ft/min2,3
RθJA
RθJA
41.8
28.0
34.3
25.8
oC/W
oC/W
Junction to Board1,4
—
—
RθJB
RθJC
16.0
10.5
0.2
17.4
10.4
0.2
oC/W
oC/W
oC/W
oC/W
Junction to Case1,5
Junction to Package Top1,6
Junction to Package Bottom
Natural Convection
Natural Convection
ΨJT
RθB_CSB
15.3
17.3
1
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2
Per JEDEC JESD51-2 with the single layer board horizontal. Thermal test board meets JEDEC specification for the specified
package.
3
4
Per JEDEC JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
5
6
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1).
Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
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Electrical characteristics
4.1.3
Operating ranges
Table 9 provides the operating ranges of the i.MX 7Dual family of processors. For details on the chip's
power structure, see the “Power Management Unit (PMU)” chapter of the i.MX 7Dual Application
Processor Reference Manual (IMX7DRM).
Table 9. Operating ranges
Parameter
Description
Symbol
Min
Typ
Max1
Unit
Comment
VDD_ARM
0.95
1.0
1.25
V
Operation at 800 MHz and
below
Run Mode
1.045
1.2
1.1
1.25
1.25
V
V
Operation between 800 MHz
and 1 GHz
1.225
Operation between 1.0 GHz
and 1.2 GHz. See Table 1 for
maximum frequencies.
VDD_SOC
VDD_ARM
VDD_SOC
0.95
0
1.0
1.0
1.0
1.25
1.25
V
V
V
—
Standby/
Deep Sleep
mode
See Table 14, “Power modes,”
on page 29.
0.95
1.155
Power
Supply
Analog
Domain and
LDOs
VDDA_1P8
1.71
1.8
1.89
V
Power for analog LDO and
internal analog blocks. Must
match the range of voltages
that the rechargeable backup
battery supports.
Backup
battery
supply range
VDD_SNVS_IN
VDD_LPSR
2.4
3.0
1.8
3.6
V
V
—
LDO for
Low-Power
State
1.71
1.89
Power rail for Low Power State
Retention mode
Retention
mode
Supply for 24
MHz crystal
VDD_XTAL_1P8
1.650
1.710
3.0
1.8
1.8
3.3
3.3
1.950
1.890
3.6
V
V
V
V
—
—
Temperature VDD_TEMPSENSOR
sensor
USB supply
voltages
VDD_USB_OTG1_3
P3_IN
This rail is for USB
This rail is for USB
VDD_USB_OTG2_3
P3_IN
3.0
3.6
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23
Electrical characteristics
Parameter
Table 9. Operating ranges(continued)
Symbol
Min
Typ
Max1
Unit
Comment
Description
DDR I/O
supply
voltage
NVCC_DRAM,
NVCC_DRAM_CKE
1.14
1.425
1.283
0.49 ×
1.2
1.5
1.3
V
V
V
V
LPDDR2, LPDDR3
DDR3
1.575
1.45
1.35
0.5 ×
DDR3L
DRAM_VREF
0.51 ×
Set to one-half NVCC_DRAM
NVCC_DRAM) NVCC_DRAM NVCC_DRAM
GPIO supply
voltages
NVCC_ENET1
NVCC_EPDC1
NVCC_EPDC2
NVCC_I2C
1.65,
3.0
1.8,
3.3
1.95,
3.6
V
—
NVCC_LCD
NVCC_SAI
NVCC_SD1
NVCC_SD2
NVCC_SD3
NVCC_SPI
NVCC_UART
NVCC_GPIO1
NVCC_GPIO2
1.65
3.0
1.8,
3.3
1.95,
3.6
V
V
Power for GPIO1_DATA00 ~
GPIO1_DATA07
1.65
3.0
1.8,
3.3
1.95,
3.6
Power for GPIO1_DATA08 ~
GPIO1_DATA15 and JTAG
port
Voltage rails
supplied from
internal LDO
PCIE_VPH
PCIE_VPH_RX
PCIE_VPH_TX
VDDA_MIPI_1P8
1.71
1.8
1.89
V
V
V
Supplied from
VDDA_PHY_1P8
PCIE_VP
0.95
1.0
1.050
Supplied from
VDDD_CAP_1P0
PCIE_VP_RX
PCIE_VP_TX
VDD_MIPI_1P0
VDD_USB_H_1P2
Tdelta
1.150
—
1.2
3
1.250
—
Supplied from VDD_1P2_CAP
Temperature
sensor
°C Typical accuracy over the
range –40°C to 125°C
accuracy
A/D converter VDDA_ADC1_1P8
VDDA_ADC2_1P8
1.71
1.71
1.710
-20
1.8
1.8
1.8
—
1.89
1.89
1.890
105
V
V
V
—
—
Fuse power
FUSE_FSOURCE
Power supply for internal use
T
J
Junction
oC See Table 1 for complete list of
junction temperature
temperature,
industrial
capabilities.
1
Applying the maximum voltage results in maximum power consumption and heat generation. A voltage set point = (Vmin + the
supply tolerance) is recommended. This results in an optimized power/speed ratio. Operating a voltage of 1.2V and above will
reduce the overall lifetime of the part. For details, see i.MX 7Dual/Solo Product Lifetime Usage (AN5334).
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Electrical characteristics
Table 10 shows on-chip LDO regulators that can supply on-chip loads.
Table 10. On-chip LDOs1 and their on-chip loads
Voltage Source
Load
Comment
VDDD_1P0_CAP
VDD_MIPI_1P0
PCIE_VP
Connect directly (short) via board level
PCIE_VP_RX
PCIE_VP_TX
VDD_USB_H_1P2
VDDA_MIPI_1P8
PCIE_VPH
VDD_1P2_CAP
VDDA_PHY_1P8
Connect directly (short) via board level
Connect directly (short) via board level
PCIE_VPH_RX
PCIE_VPH_TX
1
On-chip LDOs are designed to supply i.MX 7Dual loads and must not be used to supply external loads.
4.1.4
External clock sources
Each i.MX 7Dual processor has two external input system clocks: a low frequency (RTC_XTALI) and a
high frequency (XTALI).
The RTC_XTALI is used for low-frequency functions. It supplies the clock for wake-up circuit,
power-down real time clock operation, and slow system and watch-dog counters. The clock input can be
connected to either external oscillator or a crystal using internal oscillator amplifier. Additionally, there is
an internal resistor-capacitor (RC) oscillator, which can be used instead of the RTC_XTALI if accuracy is
not important.
The system clock input XTALI is used to generate the main system clock. It supplies the PLLs and other
peripherals. The system clock input can be connected to either an external oscillator or a crystal using
internal oscillator amplifier.
Table 11 shows the interface frequency requirements.
Table 11. External input clock frequency
Parameter Description
RTC_XTALI Oscillator1,2
XTALI Oscillator2,4
Symbol
Min
Typ
Max
Unit
fckil
fxtal
External oscillator or a crystal with internal oscillator amplifier.
—
32.7683
24
—
kHz
MHz
1
2
The required frequency stability of this clock source is application dependent. See Hardware Development Guide for
i.MX7Dual and 7Solo Applications Processors.
3
4
Recommended nominal frequency 32.768 kHz.
External oscillator or a fundamental frequency crystal appropriately coupled to the internal oscillator amplifier.
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25
Electrical characteristics
The typical values shown in Table 11 are required for use with NXP BSPs to ensure precise time keeping
and USB operation. For RTC_XTALI operation, two clock sources are available. If there is not an
externally applied oscillator to RTC_XTALI, the internal oscillator takes over.
•
On-chip 32 kHz RC oscillator—this clock source has the following characteristics:
— Approximately 25 µA more I than crystal oscillator
DD
— Approximately ±10% tolerance
— No external component required
— Starts up faster than 32 kHz crystal oscillator
— Three configurations for this input:
– External oscillator
– External crystal coupled to RTC_XTALI and RTC_XTALO
– Internal oscillator
External crystal oscillator with on-chip support circuit:
— At power up, RC oscillator is utilized. After crystal oscillator is stable, the clock circuit
switches over to the crystal oscillator automatically.
— Higher accuracy than RC oscillator
— If no external crystal is present, then the RC oscillator is utilized
The decision of choosing a clock source should be taken based on real-time clock use and precision
timeout.
4.1.5
Maximum supply currents
The Power Virus numbers shown in Table 12 represent a use case designed specifically to show the
maximum current consumption possible. All cores are running at the defined maximum frequency and are
limited to L1 cache accesses only to ensure no pipeline stalls. Although a valid condition, it would have a
very limited practical use case, if at all, and be limited to an extremely low duty cycle unless the intention
was to specifically show the worst case power consumption.
The MC3xPF3000xxxx, NXP’s power management IC targeted for the i.MX 7Dual family of processors,
supports the Power Virus mode operating at 1% duty cycle. Higher duty cycles are allowed, but a robust
thermal design is required for the increased system power dissipation.
Table 12 represents the maximum momentary current transients on power lines, and should be used for
power supply selection. Maximum currents are higher by far than the average power consumption of
typical use cases. For typical power consumption information, see the application note, i.MX 7DS Power
Consumption Measurement (AN5383).
Table 12. Maximum supply currents
Power Rail
Source
Conditions
Max Current
Unit
VDD_ARM
VDD_SOC
From PMIC
From PMIC
—
—
500
mA
mA
1000
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NXP Semiconductors
Electrical characteristics
Table 12. Maximum supply currents(continued)
Source Conditions
Power Rail
VDDA_1P8_IN
Max Current
Unit
From PMIC
—
—
1501
1
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
VDD_SNVS_IN
VDD_XTAL_1P8
VDD_LPSR_IN
VDD_TEMPSENSOR_1P8
VDDA_ADC1_1P8
VDDA_ADC2_1P8
FUSE_FSOURCE
VDD_MIPI_1P0
PCIE_VP
From PMIC or Coin cell
From PMIC
—
5
From PMIC
—
5
From PMIC
—
1
From PMIC
—
5
From PMIC
—
5
From PMIC
—
150
80
70
35
35
25
15
15
From i.MX 7 internal LDO
From i.MX 7 internal LDO
From i.MX 7 internal LDO
From i.MX 7 internal LDO
From i.MX 7 internal LDO
From i.MX 7 internal LDO
From i.MX 7 internal LDO
From PMIC
—
—
PCIE_VP_RX
—
PCIE_VP_TX
—
PCIE_VPH
—
PCIE_VPH_RX
PCIE_VPH_TX
NVCC_GPIO1
NVCC_GPIO2
NVCC_SD2
—
—
N=12
N=14
N=9
N=12
N=9
N=16
N=16
N=17
N=11
N=29
N=8
N=8
N=8
N=8
—
Use max IO
equation2
From PMIC
From PMIC
NVCC_SD3
From PMIC
NVCC_SD1
From PMIC
NVCC_ENET1
NVCC_EPDC1
NVCC_EPDC2
NVCC_SAI
From PMIC
From PMIC
From PMIC
From PMIC
NVCC_LCD
From PMIC
NVCC_SPI
From PMIC
NVCC_ECSPI
NVCC_I2C
From PMIC
From PMIC
NVCC_UART
From PMIC
VDD_USB_OTG1_3P3_IN
VDD_USB_OTG2_3P3_IN
VDD_USB_H_1P2
VDDA_MIPI_1P8
From PMIC
50
50
20
5
From PMIC
—
From i.MX 7 internal LDO
From i.MX 7 internal LDO
—
—
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Electrical characteristics
Power Rail
Table 12. Maximum supply currents(continued)
Source Conditions
Max Current
Unit
DRAM_VREF
From PMIC
From PMIC
From PMIC
—
—
—
30
30
mA
mA
mA
NVCC_DRAM_CKE
3
NVCC_DRAM
—
1
The actual maximum current drawn from VDDA_1P8_IN is as shown plus any additional current drawn from the
VDDD_1P0_CAP, VDD_1P2_CAP, VDDA_PHY_1P8 outputs, depending on actual application configuration (for example,
VDD_MIPI_1P0, VDD_USB_H_1P2 and PCIE_VP/VPH supplies).
2
General equation for estimated, maximal power consumption of an I/O power supply:
Imax = N × C × V × (0.5 × F)
where:
N = Number of I/O pins supplied by the power line
C = Equivalent external capacitive load
V = IO voltage
(0.5 × F) = Data change rate, up to 0.5 of the clock rate (F)
In this equation, Imax is in amps, C in farads, V in volts, and F in hertz.
3
The DRAM power consumption is dependent on several factors, such as external signal termination. DRAM power calculators
are typically available from the memory vendors. They take into account factors such as signal termination. See the application
note, i.MX 7DS Power Consumption Measurement (AN5383) for examples of DRAM power consumption during specific use
case scenarios.
4.1.6
Power modes
The i.MX 7Dual has the following power modes:
•
•
•
•
OFF mode: all power rails are off
SNVS mode: only RTC and tamper detection logic is active
LPSR mode: an extension of SNVS mode, with 16 GPIOs in low power state retention mode
RUN Mode: all external power rails are on, CPU is active and running, other internal module can
be on/off based on application;
•
Low Power mode (System Idle, Low Power Idle, and Deep Sleep): most external power rails are
still on, CPU is in WFI state or power gated, most of the internal modules are clock gated or power
gated
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Electrical characteristics
The valid power mode transition is shown in this diagram.
7
8
Low
Power
1
OFF
RUN
3
5
2
4
6
SNVS
LPSR
Figure 3. i.MX 7Dual Power Modes
The power mode transition condition is defined in the following table.
Table 13. Power Mode Transition
Transition
From
To
Condition
1
2
3
4
5
6
7
8
OFF
SNVS
RUN
RUN
OFF
VDD_SVNS_IN supply present.
VDD_SNVS_IN supply removal.
ONOFF long press, or SW.
SNVS
RUN
LPSR
RUN
SNVS
RUN
ONOFF press, or RTC, or tamper event.
SW.
LPSR
RUN
ONOFF press, or RTC, or tamper event, or GPIO event.
Low Power SW (CPU execute WFI)
RUN RTC, tamper event, IRQ.
Low Power
The following table summarizes the external power supply state in all the power modes.
Table 14. Power modes
Power rail
OFF
SVNS
LPSR
RUN
Low Power
VDD_ARM
VDD_SOC
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
OFF
OFF
OFF
ON
ON
ON
ON
ON
ON
ON
ON
ON/ OFF
ON
VDDA_1P8_IN
VDD_SNVS_IN
VDD_LPSR_IN
NVCC_GPIO1/2
NVCC_DRAM
ON
ON
OFF
OFF
OFF
ON
ON
ON
ON
OFF
ON
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Electrical characteristics
Power rail
Table 14. Power modes(continued)
OFF
SVNS
LPSR
RUN
Low Power
NVCC_DRAM_CKE
NVCC_XXX
OFF
OFF
OFF / ON
OFF
OFF / ON
OFF
ON
ON
ON / OFF
ON / OFF
ON / OFF
ON / OFF
VDD_USB_OTG1_3P3_IN
VDD_USB_OTG2_3P3_IN
OFF / ON
OFF / ON
OFF / ON
The NVCC_DRAM_CKE can be still ON during SNVS/LPSR mode to keep the CKE/RESET pad in
correct state to hold DRAM device in self-refresh mode.
The NVCC_XXX can be off in RUN mode / Low Power mode if all the pads in that IO bank is not used
in the application, the NVCC_XXX supply could be tied to GND.
The VDD_USB_OTG1_3P3_IN and VDD_USB_OTG2_3P3_IN are fully asynchronous to other power
rails, so it can be either ON/OFF in any of the power modes.
4.1.6.1
OFF Mode
In OFF mode, all the power rails are shut off.
4.1.6.2
SNVS Mode
SNVS mode is also called RTC mode, where only the power for the SNVS domain remain on. In this
mode, only the RTC and tamper detection logic is still active.
The power consumption in SNVS model with all the tamper detection logic enabled will be less than
5 uA @ 3.0 V on VDD_SNVS_IN for typical silicon at 25°C.
The external DRAM device can keep in self-refresh when the chip stays in SNVS mode with
NVCC_DRAM_CKE still powered. During the state transition between SNVS mode to/from ON mode,
the DRAM_CKE pad and DRAM_RESET pad has to always stay in correct state to keep DRAM in
self-refresh mode. No glitch / floating is allowed.
4.1.6.3
LPSR Mode
LPSR is considered as an extension of the SNVS mode. All the features supported in SNVS mode is also
supported in LPSR mode, including the capability of keeping DRAM device in self-refresh.
In LPSR mode, three additional power rails will remain on: VDD_LPSR_IN, NVCC_GPIO1, and
NVCC_GPIO2. These three power rails are used to supply the logic and IO pads in the LPSR domain. The
purpose of this mode is to retain the state of 16 GPIO pads, so the other components in the whole system
will have their control signal in correct state.
Among all the 16 GPIO pads, the NVCC_GPIO1 supply the power for 8 GPIO pads, and the
NVCC_GPIO2 supply the power for the other 8 GPIO pads. This allows the SoC to have some of its GPIO
working at 1.8 V while others working at 3.3 V in the LPSR mode.
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Electrical characteristics
When LPSR mode is not needed for the application, the VDD_LPSR can be connected to VDDA_1P8 and
NVCC_GPIO1/2 can be connected to the same power supply as NVCC_XXX for other GPIO banks.
In LPSR mode, the supported wakeup source are RTC alarm, ONOFF event, security/tamper and also the
16 GPIO pads.
4.1.6.4
RUN Mode
In RUN mode, the CPU is active and running, and the analog / digital peripheral modules inside the
processor will be enabled. In this mode, all the external power rails to the processor have to be ON and the
SoC will be able to draw as many current as listed in the Table 5 Maximum Power Requirement.
In this mode, the PMIC should allow SoC to change the voltage of power rails through I2C/SPI interface.
Typically, when the CPU is doing DVFS, it switches the VDD_ARM voltage according to Table 9 when
the CPU’s frequency is switching between 1 GHz and 800 MHz (or below).
4.1.6.5
Low Power Mode
When the CPU is not running, the processor can enter low power mode. i.MX 7Dual processor supports a
very flexible set of power mode configurations in low power mode.
Typically there are 3 low power modes used, System IDLE, Low Power IDLE and SUSPEND:
•
System IDLE—This is a mode that the CPU can automatically enter when there is no thread
running. All the peripherals can keep working and the CPU’s state is retained so the interrupt
response can be very short. The cores are able to individually enter the WAIT state.
•
Low Power IDLE—This mode is for the case when the system needs to have lower power but still
keep some of the peripherals alive. Most of the peripherals, analog modules, and PHYs are shut
off; see Table 5-5, “Low Power Mode Definition,” in the i.MX 7Dual Application Processor
Reference Manual (IMX7DRM) for details. The interrupt response in this mode is expected to be
longer than the System IDLE, but its power is much lower.
•
Suspend—This mode has the greatest power savings; all clocks, unused analog/PHYs, and
peripherals are off. The external DRAM stays in Self-Refresh mode. The exit time from this mode
is much longer.
In System IDLE and Low Power IDLE mode, the voltage on external power supplies remains the same as
in RUN mode, so the external PMIC is not aware of the state of the processor. If any low-power setting
needs to be applied to PMIC, it is done through the I2C/SPI interface before the processor enters a
low-power mode.
When the processor enters SUSPEND mode, it will assert the PMIC_STBY_REQ signal to PMIC. When
this signal is asserted, the processor allows the PMIC to shut off VDD_ARM externally. However, in some
application scenario, SW want to keep the data in L2 Cache to avoid performance impact on cache miss.
In this case, the VDD_ARM cannot be shut off. To support both scenarios, the PMIC should have an option
to shut off or keep VDD_ARM when it receives the PMIC_STBY_REQ. This should be configured
through I2C/SPI interface before the processor enters SUSPEND mode.
Except the VDD_ARM, the other power rails have to keep active in SUSPEND mode. Since the current
on each power rail is greatly reduced in this mode, PMIC can enter its own low power mode to get extra
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Electrical characteristics
power saving. For example, the PMIC can change the DCDC rails to PFM mode to reduce the power
consumption.
The power consumption in low power modes is defined in Table 15.
Table 15. Low Power Measurements
System IDLE
Low Power IDLE
SUSPEND
LPSR
Power rail
Voltage Current Power Voltage Current Power Voltage Current Power Voltage Current Power
(V)
(mA)
(mW)
(V)
(mA)
(mW)
(V)
(mA)
(mW)
(V)
(mA)
(mW)
VDD_ARM
1.0
1.0
1.8
3.0
1.8
1.8
2.7
2.70
19.38
6.23
1.0
1.0
1.8
3.0
1.8
1.8
0.428
1.423
0.206
0.005
0.041
0.073
0.43
1.42
0.37
0.015
0.07
0.13
1.0
1.0
1.8
3.0
1.8
1.8
0.3
0.6
0.30
0.60
0.0
0.0
0.0
3.0
1.8
1.8
—
—
0.00
0.00
0.00
0.009
0.07
0.13
VDD_SOC
19.38
3.46
VDDA_1P8_IN
VDD_SNVS_IN
VDD_LPSR_IN
NVCC_GPIO1/2
0.4
0.72
—
0.006
0.04
0.018
0.07
0.006
0.018
0.003
0.04
0.072
0.039 0.0702
0.072
0.13
0.072
0.13
Total
—
—
28.53
—
—
2.45
—
—
1.84
—
—
0.21
All the power numbers defined in Table 15 are based on typical silicon at 25°C.
4.1.7
USB PHY Suspend current consumption
Low Power Suspend Mode
4.1.7.1
The VBUS Valid comparators and their associated bandgap circuits are enabled by default. Table 16
shows the USB interface current consumption in Suspend mode with default settings.
Table 16. USB PHY current consumption with default settings1
VDD_USB_OTG1_3P3_IN
VDD_USB_OTG2_3P3_IN
790 uA
790 uA
Current
1
Low Power Suspend is enabled by setting USBx_PORTSC1 [PHCD]=1 [Clock Disable (PLPSCD)].
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4.1.7.2
4.1.7.2 Power-Down modes
Table 17 shows the USB interface current consumption with only the OTG block powered down.
Table 17. USB PHY current consumption with VBUS Valid Comparators disabled1
VDD_USB_OTG1_3P3_IN
VDD_USB_OTG2_3P3_IN
730 uA
730 uA
Current
1
VBUS Valid comparators can be disabled through software by setting USBNC_OTG*_PHY_CFG2[OTGDISABLE0] to 1. This
signal powers down only the VBUS Valid comparator, and does not control power to the Session Valid Comparator, ADP Probe
and Sense comparators, or the ID detection circuitry.
In Power-Down mode, everything is powered down, including the USB_VBUS valid comparators and
their associated bandgap circuity in typical condition. Table 18 shows the USB interface current
consumption in Power-Down mode.
Table 18. USB PHY current consumption in Power-Down mode1
VDD_USB_OTG1_3P3_IN
VDD_USB_OTG2_3P3_IN
200 uA
200 uA
Current
1
The VBUS Valid Comparators and their associated bandgap circuits can be disabled through software by setting
USBNC_OTG*_PHY_CFG2[OTGDISABLE0] to 1 and USBNC_OTG*_PHY_CFG2[DRVVBUS0] to 0, respectively.
4.1.8
PCIe phy 2.1 DC electrical characteristics
Table 19. PCIe recommended operating conditions
Parameter
Description
Min
Max
Unit
VDD
Low Power Supply Voltage for PHY Core
High Power Supply Voltage for PHY Core
Commercial Temperature Range
1 V
0.95
1.71
0
1.05
1.89
70
V
1.8 V
TA
TJ
°C
°C
Simulation Junction Temperature Range
-40
125
Note: VDD should have no more than 40 mVpp AC power supply noise superimposed on the high power supply voltage for the
PHY core (1.8 V nominal DC value). At the same time, VDD should have no more than 20 mVpp AC power supply noise
superimposed on the low power supply voltage for the PHY core.
The power supply voltage variation for the PHY core should have less than +/-5% including the board-level power supply variation
and on-chip power supply variation due to the finite impedances in the package.
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Electrical characteristics
Parameter
Table 20. PCIe DC electrical characteristics
Description
Min
Typ
Max
Unit
VDD
Power Supply Voltage
(VDD of 1.0 V nominal
gate oxide /1.8 V for thick gate oxide)
1.0 - 5%
1.8 - 5%
1.0
1.8
1.0 + 5%
1.8 + 5%
V
V
PD
Power Consumption
Normal
—
—
—
—
130
108
7
—
—
—
—
mW
mW
mW
mW
Partial Mode
Slumber Mode
Full Powerdown
0.2
Table 21. PCIe PHY high-speed characteristics
High Speed I/O Characteristics
Description
Symbol
Speed
Min.
Typ.
Max.
Unit
Unit Interval
UI
1.5 Gbps
2.5 Gbps
3.0 Gbps
5.0 Gbps
6.0 Gbps
1.5 Gbps
2.5 Gbps
3.0 Gbps
5.0 Gbps
6.0 Gbps
1.5 Gbps
2.5 Gbps
3.0 Gbps
5.0 Gbps
6.0 Gbps
1.5 Gbps
2.5 Gbps
3.0 Gbps
5.0 Gbps
6.0 Gbps
—
—
666.67
400
333.33
200
166.67
—
—
—
ps
—
—
—
—
—
—
TX Serial output rise time (20% to 80%)
TX Serial output fall time (80% to 20%)
TX Serial data output voltage (Differential, pk–pk)
TTXRISE
TTXFALL
ΔVTX
50
273
—
ps
50
—
50
—
136
—
30
—
33
—
80
50
—
273
—
ps
50
—
50
—
136
—
30
—
33
—
80
400
400
400
400
240
—
600
1200
700
1200
900
mVp–p
—
—
—
—
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Table 21. PCIe PHY high-speed characteristics(continued)
High Speed I/O Characteristics
Description
Symbol
Speed
Min.
Typ.
Max.
Unit
PCIe Tx deterministic jitter < 1.5 MHz
TRJ
2.5 Gbps/
5.0 Gbps
—
—
3 ps
ps, rms
PCIe Tx deterministic jitter > 1.5 MHz
TDJ
5.0 Gbps/
2.5 Gbps
—
—
30 ps/
60 ps
ps, pk–pk
mVp–p
RX Serial data input voltage (Differential pk–pk)
ΔVRX
1.5 Gbps
2.5 Gbps
3.0 Gbps
5.0 Gbps
6.0 Gbps
325
120
275
120
240
—
—
—
—
—
600
1200
750
1200
1000
Table 22. PCIe PHY reference clock timing requirements
Description
Frequency Tolerance
Symbol
Min.
Typ.
Max.
Unit
FTOL
DC
–100
40
—
—
—
—
—
—
—
—
—
—
—
—
100
60
ppm
%
Duty Cycle
Rise and Fall Time
TR,TF
Jitter
—
1.5
40
ns
Peak to peak Jitter
—
ps,pk–pk
ps,rms
ps
RMS Jitter
—
2.5
25
Period Jitter
—
External Clock source output impedence
Differential input high voltage
Differential input low voltage
Absolute maximum input voltage
Absolute minimum input voltage
Absolute crossing point voltage
ZC,DC
VIH
40
60
Ω
150
—
mV
mV
V
VIL
-150
1.15
-0.3
VMAX
VMIN
VCROSS
33
400
250
V
1550
mV
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Electrical characteristics
Table 23. PCIe PHY reference clock Transmit requirements
Description
Symbol
Interface
Speed
Min Typ Max Unit
Frequency of TBC
FTBC
20-bit
1.5 Gbps
3.0 Gbps
6.0 Gbps
1.5 Gbps
3.0 Gbps
6.0 Gbps
2.5 Gbps
5.0 Gbps
—
—
—
—
—
—
—
—
—
40
2.0
75
150
300
37.5
75
—
—
—
—
—
—
—
—
60
—
MHz
40-bit
150
250
8-bit
16-bit
—
Duty cycle of TBC
DCTBC
—
—
%
TXD[0:30] setup time to the rising edge of TBC
TSETUP.TX
20-bit
1.5 Gbps
3.0 Gbps
6.0 Gbps
1.5 Gbps
3.0 Gbps
6.0 Gbps
2.5 Gbps
5.0 Gbps
1.5 Gbps
3.0 Gbps
6.0 Gbps
1.5 Gbps
3.0 Gbps
6.0 Gbps
2.5 Gbps
5.0 Gbps
1.5 Gbps
2.5 Gbps
3.0 Gbps
5.0 Gbps
6.0 Gbps
ns
1.0
2.0
—
—
—
—
40-bit
8-bit
16-bit
20-bit
1.0
2.0
—
—
—
—
TXD[0:30] hold time to the rising edge of TBC
THOLD.TX
ns
1.0
2.0
—
—
—
—
40-bit
8-bit
16-bit
—
1.0
—
—
Latency from the rising edge of TBC to the leading edge
of the corresponding first transmitted serial output bit
TXP/TXN
TLAT.TX
—
—
—
—
—
70
100
95
—
—
—
—
—
bits
200
120
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Min Typ Max Unit
Table 24. PCIe PHY reference clock Receive requirements
Description
Symbol
Interface
Speed
Frequency of RBC
FRBC
20-bit
1.5 Gbps
3.0 Gbps
6.0 Gbps
1.5 Gbps
3.0 Gbps
6.0 Gbps
—
—
—
—
—
—
—
40
—
—
—
—
—
—
75
150
300
37.5
75
—
—
MHz
—
40-bit
—
—
150
—
—
Duty cycle of TBC
DCRBC
TDLY,RX
TLAT.RX
—
—
60
1.33
—
%
ns
RXD[0:30] delay time from the falling edge of RBC
—
—
Latency from the leading edge of the corresponding first
received serial input bit, RXP/RXN, to the rising edge of RBC
20-bit
1.5 Gbps
2.5 Gbps
3.0 Gbps
5.0 Gbps
6.0 Gbps
100
230
100
260
100
bits
—
—
—
—
Table 25. PCIe PHY output clock characteristics
Description
Symbol
Interface
Speed
Min
Typ
Max
Unit
Frequency of PC_CLK
FPC_CLK
HIGH_SPEED=1
—
MHz
PCIe
—
—
40
—
—
—
—
—
—
40
250
—
—
60
—
—
—
—
—
—
60
Duty Cycle of PC_CLK
Frequency of TX_CLK
DCPC_CLK
FTX_CLK
—
%
20-bit
1.5 Gbps
3.0 Gbps
6.0 Gbps
1.5 Gbps
3.0 Gbps
6.0 Gbps
—
75
MHz
150
300
37.5
75
40-bit
—
150
—
Duty cycle of TX_CLK
DCTX_CLK
%
The system design must comply with power-up sequence, power-down sequence, and steady state
guidelines as described in this section to guarantee the reliable operation of the device. Any deviation
from these sequences may result in the following situations:
•
•
Excessive current during power-up phase
Prevention of the device from booting
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Electrical characteristics
•
Irreversible damage to the processor (worst-case scenario)
4.1.9
Power-up sequence
The i.MX7 processor has the following power-up sequence requirements:
•
VDD_SNVS_IN to be turned on before any other power supply. If a coin cell is used to power
VDD_SNVS_IN, then ensure that it is connected before any other supply is switched on.
•
•
VDD_SOC to be turned on before NVCC_DRAM and NVCC_DRAM_CKE.
VDD_ARM, VDD_SOC, VDDA_1P8_IN, VDD_LPSR_IN and all I/O power (NVCC_*) should
be turned on after VDD_SVNS_IN is active. But there is no sequence requirement among these
power rails other than the sequence requirement between VDD_SOC and
NVCC_DRAM/NVCC_DRAM_CKE.
•
There are no special timing requirements for VDD_USB_OTG1_3P3_IN and
VDD_USB_OTG2_3P3_IN.
The POR_B input (if used) must be immediately asserted at power-up and remain asserted until the last
power rail reaches its working voltage. In the absence of an external reset feeding the POR_B input, the
internal POR module takes control.
The power-up sequence is shown in Figure 4 with the following timing parameters:
T1
T2
T3
T6
Time from SVNS power stable to other power rails start to ramp, minimal delay is 2ms,
no max delay requirement.
Time from first power rails (except SNVS) ramp up to all the power rails get stable,
minimal delay is 0ms, no max delay requirement.
Time from all power rails get stable to power-on reset, minimal delay is 0ms, no max
delay requirement.
Time from VDD_SOC get stable to NVCC_DRAM/NVCC_DRAM_CKE start to
ramp, minimal delay is 0ms, no max delay requirement.
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Figure 4. i.MX 7Dual power-up sequence
4.1.10 Power-down sequence
The i.MX7 processors have the following power-down sequence requirements:
•
•
•
VDD_SNVS _IN to be turned off last after any other power supply.
NVCC_DRAM/NVCC_DRAM_CKE to be turned off before VDD_SOC.
There are no special timing requirements forVDD_USB_OTG1_3P3_IN
andVDD_USB_OTG2_3P3_IN.
The power-down sequence is shown in Figure 5 with the following timing parameters:
T4
T5
T7
Time from first power rails (except SNVS) to ramp down to all the power rails (except
SNVS) get to ground, minimal delay is 0ms, no max delay requirement.
Time from all the power rails power down (except SNVS) to SVNS power down,
minimal delay is 0ms, no max delay requirement.
Time from NVCC_DRAM/NVCC_DRAM_CKE power down to VDD_SOC power
down, minimal delay is 0ms, no max delay requirement.
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Electrical characteristics
Figure 5. i.MX 7Dual power-down sequence
4.1.11 Power supplies usage
I/O pins should not be externally driven while the I/O power supply for the pin (NVCC_xxx) is OFF. This
can cause internal latch-up and malfunctions due to reverse current flows. For information about I/O power
supply of each pin, see “Power Rail” columns in pin list tables of Section 6, “Package information and
contact assignments.”
4.2
Integrated LDO voltage regulator parameters
Various internal supplies can be powered from internal LDO voltage regulators. All the supply pins named
*_CAP must be connected to external capacitors. The onboard LDOs are intended for internal use only
and should not be used to power any external circuitry. See the i.MX 7Dual Application Processor
Reference Manual (IMX7DRM) for details on the power tree scheme.
NOTE
The *_CAP signals must not be powered externally. The *_CAP pins are for
the bypass capacitor connection only.
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4.2.1
Internal regulators
Table 26. LDO parameters
Parameter
Min
Max
Units
PVCC_GPIO_AT3P3_1P8
VDD_1P2
1.6
1.1
1.98
1.32
V
V
V
V
V
LPSR_1P0
0.95
1.6
1.155
1.98
VDDA_PHY_1P8
USB_OTG1_1P0
0.95
1.155
4.2.1.1
LDO_1P2
The LDO_1P2 regulator implements a programmable linear-regulator function from VDDA_1P8_IN (see
Table 9 for minimum and maximum input requirements). The typical output of the LDO, VDD_1P2_CAP,
is 1.2 V. It is intended for use with the USB HSIC PHY, which uses this voltage level for its output driver.
For additional information, see the “Power Management Unit (PMU)” chapter of the i.MX 7Dual
Application Processor Reference Manual (IMX7DRM).
4.2.1.2
LDO_1P0D
The LDO_1P0D regulator implements a programmable linear-regulator function from VDDA_1P8_IN
(see Table 9 for minimum and maximum input requirements). The typical output of the LDO,
VDD_1P0D_CAP, is 1.0 V. It is intended for use with the internal physical interfaces, including MIPI and
PCIe PHY. For additional information, see the i.MX 7Dual Application Processor Reference Manual
(IMX7DRM).
4.2.1.3
LDO_1P0A
The LDO_1P0A regulator implements a programmable linear-regulator function from VDDA_1P8_IN
(see Table 9 for minimum and maximum input requirements). The typical output of the LDO,
VDD_1P0A_CAP, is 1.0 V. It is intended for use with the internal analog modules, including the XTAL,
ADC, PLL, and Temperature Sensor. For additional information, see the i.MX 7Dual Application
Processor Reference Manual (IMX7DRM).
4.2.1.4
LDO_USB1_1PO/LDO_USB2_1P0
The LDO_USB1_1P0/LDO_USB2_1P0 regulators implement a fixed linear-regulator function from
VDD_USB_OTG1_3P3_IN and VDD_USB_OTG2_3P3_IN power inputs respectively (see Table 9 for
minimum and maximum input requirements). The typical output voltage is 1.0 V. It is intended for use
with the internal USB physical interfaces (USB PHY1 and USB PHY2). For additional information, see
the i.MX 7Dual Application Processor Reference Manual (IMX7DRM).
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Electrical characteristics
4.2.1.5
LDO_SVNS_1P8
1.8 V LDO from coin cell to generate 1.8 V power for SNVS and 32 K RTC. The LDO_SNVS_1P8
regulator implements a fixed linear-regulator function from VDD_SNVS_IN (see Table 9 for minimum
and maximum input requirements). The typical output is 1.7 V. It is intended for use with the internal
SNVS circuitry and 32 K RTC. For additional information, see the i.MX 7Dual Application Processor
Reference Manual (IMX7DRM).
4.3
PLL electrical characteristics
Table 27. PLL Electrical Parameters
PLL type
Parameter
Value
AUDIO_PLL
Clock output range
Reference clock
Lock time
650 MHz–1.3 GHz
24 MHz
<11250 reference cycles
650 MHz–1.3 GHz
24 MHz
VIDEO_PLL
SYS_PLL
Clock output range
Reference clock
Lock time
<383 reference cycles
480 MHz
Clock output range
Reference clock
Lock time
24 MHz
<383 reference cycles
650 MHz–1.3 GHz, set to 1.0 GHz
24 MHz
ENET_PLL
ARM_PLL
DRAM_PLL
Clock output range
Reference clock
Lock time
<11250 reference cycles
800 MHz–1.2 GHz
24 MHz
Clock output range
Reference clock
Lock time
<2250 reference cycles
800 MHz–1066 MHz
24 MHz
Clock output range
Reference clock
Lock time
>2250 reference cycles
4.4
On-chip oscillators
OSC24M
4.4.1
Power for the oscillator is supplied from a clean source of VDDA_1P8. This block implements an
amplifier that when combined with a suitable quartz crystal and external load capacitors implements an
oscillator. The oscillator is powered from VDDA_1P8.
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The system crystal oscillator consists of a Pierce-type structure running off the digital supply. A straight
forward biased-inverter implementation is used.
4.4.2
OSC32K
This block implements an internal amplifier, trimable load capacitors and a resistor that when combined
with a suitable quartz crystal implements a low power oscillator.
In addition, if the clock monitor determines that the OSC32K is not present then the source of the 32 kHz
clock will automatically switch to the internal relaxation oscillator of lesser frequency accuracy.
CAUTION
The internal RTC oscillator does not provide an accurate frequency and is
affected by process, voltage and temperature variations. NXP strongly
recommends using an external crystal as the RTC_XTALI reference. If the
internal oscillator is used instead, careful consideration must be given to the
timing implications on all of the SoC modules dependent on this clock.
The OSC32k runs from VDD_SNVS_1p8_CAP, which is regulated from
VDD_SNVS. The target battery is an ~3 V coin cell for VDD_SNVS and
the regulated output is ~1.75V.
Table 28. OSC32K Main Characteristics
Min
Typ
Max
Comments
Fosc
—
32.768 KHz
—
This frequency is nominal and determined by the crystal selected. 32.0 K
would work as well.
Current consumption
—
—
350 nA
—
The typical value shown is only for the oscillator, driven by an external
crystal. If the interrelaxation oscillator is used instead of an external crystal
then approximately 250 nA should be added to this value.
Bias resistor
200 MΩ
This is the integrated bias resistor that sets the amplifier into a high gain
state. Any leakage through the ESD network, external board leakage, or
even a scope probe that is significant relative to this value will debias the
amp. The debiasing will result in low gain and will impact the circuit's ability
to start up and maintain oscillations.
Target Crystal Properties
Cload
ESR
—
—
10 pF
—
—
Usually, crystals can be purchased tuned for different Cload. This Cload
value is typically 1/2 of the capacitances realized on the PCB on either side
of the quartz. A higher Cload will decrease oscillation margin but increases
current oscillating through the crystal. The Cload is programmable in 2 pF
steps.
50 KΩ
Equivalent series resistance of the crystal. Choosing a crystal with a higher
value will decrease oscillating margin.
4.5
I/O DC parameters
This section includes the DC parameters of the following I/O types:
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Electrical characteristics
•
•
•
General Purpose I/O (GPIO)
Double Data Rate I/O (DDR) for LPDDR3 and DDR3 modes
Differential I/O (CCM_CLK1)
4.5.1
General purpose I/O (GPIO) DC parameters
Table 29 shows DC parameters for GPIO pads. The parameters in Table 29 are guaranteed per the
operating ranges in Table 9, unless otherwise noted.
Table 29. GPIO DC Parameters
Parameter
Symbol
Test Conditions
Min
Max
Units
High-level output voltage
Low-level output voltage
High-level input voltage
VOH
VOL
VIH
VIL
VHYS
—
IOH= –1.8mA, –3.6mA, –7.2mA, –10.8mA 0.8 × OVDD
OVDD
V
IOL=1.8mA, 3.6mA, 7.2mA, 10.8mA
—
0
0.2 × OVDD
V
0.7 × OVDD OVDD + 0.3
V
Low-level input voltage
—
–0.3
0.15
5.94
4.8
0.3 × OVDD
—
V
Input hysteresis
—
V
Pull-up resistor (5_kΩ PU)
Pull-up resistor (5_kΩ PU)
Pull-up resistor (47_kΩ PU)
Pull-up resistor (47_kΩ PU)
Pull-up resistor (100_kΩ PU)
Pull-up resistor (100_kΩ PU)
Pull-down resistor (100_kΩ PU)
Pull-down resistor (100_kΩ PD)
Input current (no PU/PD)
VDD = 1.8 0.15 V
VDD = 3.3 0.3 V
VDD = 1.8 0.15 V
VDD = 3.3 0.3 V
VDD = 1.8 0.15 V
VDD = 3.3 0.3 V
VDD = 1.8 0.15 V
VDD = 3.3 0.3 V
—
5.98
5.3
KΩ
KΩ
KΩ
KΩ
KΩ
KΩ
KΩ
KΩ
μΑ
mA
—
—
46.1
45.8
97.5
101
101
101
–5
50.6
49.8
105.9
105
—
—
—
—
108.6
108
—
IOZ
—
5
Sink/source current in Push-Pull
mode
Driving currents (@100MHz,
VOL/H = 0.5×OVDD, SS, 125°C)
OVDD = 2.7 V
–32.9
32.9
4.5.2
DDR I/O DC electrical characteristics
The DDR I/O pads support DDR3/DDR3L, LPDDR2, and LPDDR3 operational modes. The DDR
Memory Controller (DDRMC) is designed to be compatible with JEDEC-compliant SDRAMs. The
DDRC supports the following memory types:
•
•
•
DDR3 SDRAM compliant to JESD79-3E DDR3 JEDEC standard release July, 2010
LPDDR2 SDRAM compliant to JESD209-2B LPDDR2 JEDEC standard release June, 2009
LPDDR3 SDRAM compliant to JESD209-3B LPDDR3 JEDEC standard release August, 2013
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Electrical characteristics
DDRMC operation with the standards stated above is contingent upon the board DDR design adherence
to the DDR design and layout requirements stated in the hardware development guide for the i.MX 7
application processor.
Table 30. DC input logic level
Characteristics
DC input logic high1
DC input logic low1
Symbol
Min
Max
Unit
VIH(DC)
VIL(DC)
VREF +100
—
—
mV
VREF –100
1
It is the relationship of the VDDQ of the driving device and the VREF of the receiving device that determines noise margins.
However, in the case of VIH(DC) max (that is, input overdrive), it is the VDDQ of the receiving device that is referenced.
Table 31. Output DC current drive
Characteristics
Symbol
OH(DC)
Min
Max
Unit
Output minimum source DC current1
Output minimum sink DC current1
I
–4
—
mA
mA
V
IOL(DC)
VOH
4
0.9 × VDDQ
—
—
—
DC output high voltage(IOH = –0.1mA)1,2
DC output low voltage(IOL = 0.1mA)1,2
VOL
0.1 × VDDQ
V
1
When DDS=[111] and without ZQ calibration.
2
The values of VOH and VOL are valid only for 1.2 V range.
Table 32. Input DC current
Characteristics
High level input current1,2
Low level input current1,2
Symbol
Min
–25
–25
Max
25
Unit
μA
IIH
IIL
25
μA
1
The values of VOH and VOL are valid only for 1.2 V range.
Driver Hi-Z and input power-down (PD=High)
2
4.5.2.1
LPDDR3 mode I/O DC parameters
Table 33. LPDDR3 I/O DC electrical parameters
Test
Symbol
Parameters
Min
Max
Unit
Conditions
High-level output voltage
Low-level output voltage
Input Reference Voltage
VOH
VOL
Vref
Ioh= -0.1mA
Iol= 0.1mA
—
0.9 × OVDD
—
V
V
V
—
0.1 × OVDD
0.49 × OVDD 0.51 × OVDD
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Electrical characteristics
Table 33. LPDDR3 I/O DC electrical parameters(continued)
Test
Parameters
Symbol
Min
Max
Unit
Conditions
DC High-Level input voltage
DC Low-Level input voltage
Differential Input Logic High
Differential Input Logic Low
Pull-up/Pull-down Impedance Mismatch
240 ?unit calibration resolution
Keeper Circuit Resistance
Vih_DC
Vil_DC
Vih_diff
Vil_diff
Mmpupd
Rres
—
VRef + 0.100
OVSS
0.26
OVDD
VRef – 0.100
See note1
-0.26
V
V
—
—
—
—
%
?
—
See note1
–15
—
15
—
—
—
10
Rkeep
Iin
110
175
k?
μA
Input current (no pull-up/down)
VI = 0, VI = OVDD
-2.5
2.5
1
The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as
the limitations for overshoot and undershoot.
4.5.3
Differential I/O port (CCM_CLK1P/N)
The clock I/O interface is designed to be compatible with TIA/EIA 644-A standard. See TIA/EIA
STANDARD 644-A, Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface
Circuits (2001), for details.
Table 34 shows the clock I/O DC parameters.
Table 34. Differential clock I/O DC electrical characteristics
Symbol
Vod
Parameter
Test conditions
Min
Typ Max Unit
Notes
Output Differential Voltage
High-level output voltage
Low-level output voltage
Output common mode voltage
Input Differential Voltage
Input common mode voltage
Rload=100 Ω between padp
and padn
250
350
450 mV Vpadp–Vpadn
1
Voh
Vol
1.025 1.175 1.325
0.675 0.825 0.975
V
2
Vocm
Vid
0.9
100
50m
1
1.1
Core supply is used
600 mV Vpadp–Vpadn
Vicm
1.57
V
Vicm(max)=ovdd(m
in)–Vid(min)/2
Icc-ovdd
Tri-state I/O supply current
ipp_ibe=ipp_obe=0 irefin
disabled (0uA)
0.46 uA
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Electrical characteristics
Table 34. Differential clock I/O DC electrical characteristics(continued)
Symbol
Parameter
Test conditions
Min
Typ Max Unit
Notes
Icc-ovdd-lp Tri-state I/O supply current in ipp_pwr_stable_b_1p8 =1
0.35
1
uA
low-power mode
(means 1.8 V)
vddi is OFF
irefin disabled (0 uA)
Icc-vddi
Icc
ipp_ibe=ipp_obe=0
irefin disabled (0 uA)
0.8
Tri-state core supply current
Power supply current (ovdd)
Rload=100 Ω between padp
and padn
4.7 mA This is not including
current through
external
Rload=100 Ω
1
2
VOH_max = Vos_max + Vod_max/2 = 1.1+0.225 = 1.325 V. VOH_min = Vos_min + Vod_min/2 = 0.9+0.125 = 1.025 V.
VOL_max = Vos_max - Vod_min/2 = 1.1-0.125 = 0.975 V. VOL_min = Vos_min - Vod_max/2 = 0.9 - 0.225 = 0.675 V
4.6
I/O AC parameters
This section includes the AC parameters of the following I/O types:
•
•
•
General Purpose I/O (GPIO)
Double Data Rate I/O (DDR) for LPDDR2, LPDDR3 and DDR3/DDR3L modes
Differential I/O (CCM_CLK1)
The GPIO and DDR I/O load circuit and output transition time waveforms are shown in Figure 6 and
Figure 7.
From Output
Under Test
Test Point
CL
CL includes package, probe and fixture capacitance
Figure 6. Load circuit for output
OVDD
0 V
80%
20%
80%
20%
tr
Output (at pad)
tf
Figure 7. Output transition time waveform
4.6.1
General purpose I/O AC parameters
This section presents the I/O AC parameters for GPIO in different modes. Note that the fast or slow I/O
behavior is determined by the appropriate control bits in the IOMUXC control registers.
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Table 35. Maximum input cell delay time
Max Delay PAD → Y (ns)
Cell name
VDD=1.65 V
T=125°C
VDD=2.3 V
T=125°C
VDD=3.0 V
T=125°C
Process=Slow
Process=Slow
Process=Slow
PBIDIRPUD_E33_33_NT_DR
0.9
1.5
1.4
Table 36. Output cell delay time for fixed load
Simulated Cell Delay A PAD (ns)
Parameter
VDD = 1.65 V, T = 125°C
VDD = 2.3 V, T = 125°C
VDD = 3.0 V, T = 125°C
CL=
5 pF
CL=
10 pF
CL=
40 pF
CL=
5 pF
CL=
10 pF
CL=
40 pF
CL=
5 pF
CL=
10 pF
CL=
40 pF
DS0 DS1 SR Driver Type
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1× Slow Slew
1× Fast Slew
2× Slow Slew
2× Fast Slew
4× Slow Slew
4× Fast Slew
6× Slow Slew
6× Fast Slew
4.9
3.8
4.1
2.8
3.6
2.2
3.6
2.0
6.0
4.7
4.8
3.3
4.1
2.5
4.0
2.3
12.5
11.2
8.2
6.4
6.0
4.1
5.5
3.4
4.8
3.8
4.2
2.9
3.7
2.3
3.6
2.1
6.1
5.1
4.9
3.4
4.1
2.6
4.0
2.3
11.9
12.8
8.8
7.2
6.4
4.6
5.9
3.8
5.4
4.2
4.5
3.1
3.9
2.4
3.8
2.2
6.7
5.3
5.3
3.7
4.4
2.8
4.3
2.5
14.6
13.5
9.1
7.2
6.6
4.8
6.2
3.9
Table 37. Maximum frequency of operation for input
Maximum frequency (MHz)
VDD = 1.8 V, CL = 50 fF
VDD=2.5 V, CL =5 0 fF
VDD = 3.3 V, CL = 50 fF
550
400
430
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Table 38. Maximum frequency of operation for output1
Maximum frequency (MHz)
Parameter
VDD = 1.8 V
CL=
VDD = 2.5 V
CL=
VDD = 3.3 V
CL= CL=
CL=
CL=
CL=
CL=
CL=
DS0
DS1
SR Driver Type
5 pF 10 pF 40 pF 5 pF 10 pF 40 pF 5 pF 10 pF 40 pF
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1× Slow Slew
1× Fast Slew
100
110
120
185
140
235
140
250
70
25
25
90
60
20
20
40
40
70
80
85
120
95
60
65
20
20
40
40
70
80
80
120
75
100
120
180
135
225
135
240
65
100
115
170
130
215
130
235
2× Slow Slew
2× Fast Slew
4× Slow Slew
4× Fast Slew
6× Slow Slew
6× Fast Slew
100
145
125
200
125
225
50
100
130
120
195
120
215
95
50
130
115
185
115
205
85
100
90
140
1
Maximum frequency value is obtained with lumped capacitor load. If you consider transmission line or SSN noise
effect, it could be worse than suggested value.
4.6.2
Clock I/O AC parameters—CCM_CLK1_N/CCM_CLK1_P
The differential output transition time waveform is shown in Figure 8.
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Figure 8. Differential LVDS driver transition time waveform
Table 39 shows the AC parameters for clock I/O.
Table 39. I/O AC Parameters of LVDS Pad
Parameter Test conditions
Symbol
Min Typ Max Unit Notes
1
Tphld
Tplhd
Ttlh
Output Differential propagation delay high to low Rload=100 Ω between padp and
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.61 ns
0.61
padn,
Output Differential propagation delay low to high
Cload = 2pF
2
3
Output Transition time low to high
0.17
Tthl
Output Transition time high to low
0.17
Tphlr
Tplhr
Ttx
Input Differential propagation delay high to low
Input Differential propagation delay low to high
Transmitter startup time (ipp-obe low to high)
Operating frequency
Rload=100 Ω between padp and
0.33 ns
0.33
padn, Cload on ipp_ind=0.1 pF
4
—
—
40
ns
F
500 1000 MHz
—
1
At WCS, 125C, 1.62 V ovdd, 0.9 V vddi. Measurement levels are 50-50%. Output differential signal measured.
WCS, 125C, 1.62 V ovdd, 0.9 V vddi. Measurement levels are 20-80%. Output differential signal measured
At WCS, 125C, 1.62 V ovdd, 0.9 V vddi. Measurement levels are 50-50%.
2
3
4
TX startup time is defined as the time taken by transmitter for settling after its ipp_obe has been asserted. It is to stabilize the
current reference. Functionality is guaranteed only after the startup time
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4.7
Output buffer impedance parameters
This section defines the I/O impedance parameters of the i.MX 7Dual family of processors for the
following I/O types:
•
•
•
Double Data Rate I/O (DDR) for LPDDR2, LPDDR3, and DDR3/DDR3L modes
Differential I/O (CCM_CLK1)
USB battery charger detection open-drain output (USB_OTG1_CHD_B)
NOTE
DDR I/O output driver impedance is measured with “long” transmission
line of impedance Ztl attached to I/O pad and incident wave launched into
transmission line. Rpu/Rpd and Ztl form a voltage divider that defines
specific voltage of incident wave relative to OVDD. Output driver
impedance is calculated from this voltage divider (see Figure 9).
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OVDD
PMOS (Rpu)
Ztl Ω, L = 20 inches
ipp_do
pad
predriver
Cload = 1p
NMOS (Rpd)
OVSS
U,(V)
VDD
(do)
Vin
t,(ns)
0
U,(V)
Vout (pad)
OVDD
Vref2
Vref1
Vref
t,(ns)
0
Vovdd - Vref1
Vref1
Rpu =
× Ztl
× Ztl
Vref2
Rpd =
Vovdd - Vref2
Figure 9. Impedance matching load for measurement
4.7.1
DDR I/O output buffer impedance
The LPDDR2 interface is designed to be fully compatible with JESD209-2B LPDDR2 JEDEC standard
release June, 2009. The LPDDR3 interface mode is designed to be compatible with JESD209-3B JEDEC
standard released August, 2013. The DDR3 interface is designed to be fully compatible with JESD79-3F
DDR3 JEDEC standard release July, 2012.
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Table 40 shows DDR I/O output buffer impedance of i.MX 7Dual family of processors.
Table 40. DDR I/O output buffer impedance
Typical
Test Conditions DSE
(Drive Strength)
Parameter
Symbol
Unit
NVCC_DRAM=1.5 V
(DDR3)
NVCC_DRAM=1.2 V
(LPDDR2)
DDR_SEL=11
DDR_SEL=10
000
001
010
011
100
101
110
111
Hi-Z
240
120
80
60
48
Hi-Z
240
120
80
60
48
Output Driver
Impedance
Ω
Rdrv
40
34
40
34
Note:
1. Output driver impedance is controlled across PVTs using ZQ calibration procedure.
2. Calibration is done against 240 Ω external reference resistor.
3. Output driver impedance deviation (calibration accuracy) is 5% (max/min impedance) across PVTs.
4.7.2
Differential I/O output buffer impedance
The Differential CCM interface is designed to be compatible with TIA/EIA 644-A standard. See, TIA/EIA
STANDARD 644-A, Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface
Circuits (2001) for details.
4.7.3
USB battery charger detection driver impedance
The USB_OTG1_CHD_B open-drain output pin can be used to signal the results of USB Battery Charger
detection routines for the USB_OTG1 PHY instance to power management and monitoring devices. Use
of this pin requires an external pullup resistor, for more information see Table 3, and Table 7.
Table 41 shows the USB_OTG1_CHD_B pulldown driver impedance for the USB_OTG1_CHD_B pin.
Table 41. USB_OTG1_CHD_B pulldown driver impedance (VDD_USB_OTG1_3P3_IN 3.3 V)
Parameter
Symbol
Typical
Unit
Open-drain output driver pulldown impedance
Rdrv_pd
1000
Ω
4.8
System modules timing
This section contains the timing and electrical parameters for the modules in each i.MX 7Dual processor.
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4.8.1
Reset timings parameters
Figure 10 shows the reset timing and Table 42 lists the timing parameters.
POR_B
(Input)
CC1
Figure 10. Reset timing diagram
Table 42. Reset timing parameters
ID
Parameter
Min Max
Unit
CC1
Duration of POR_B to be qualified as valid.
1
—
RTC_XTALI cycle
Note: POR_B rise/fall times must be 5 ns or less.
4.8.2
WDOG Reset timing parameters
Figure 11 shows the WDOG reset timing and Table 43 lists the timing parameters.
WDOGx_B
(Output)
CC3
Figure 11. WDOGx_B timing diagram
Table 43. WDOGx_B timing parameters
ID
Parameter
Duration of WDOG1_B Assertion
Min
Max
Unit
CC3
1
—
RTC_XTALI cycle
NOTE
RTC_XTALI is approximately 32 kHz. RTC_XTALI cycle is one period or
approximately 30 μs.
NOTE
WDOGx_B output signals (for each one of the Watchdog modules) do not
have dedicated pins, but are muxed out through the IOMUX. See the
IOMUXC chapter of the i.MX 7Dual Application Processor Reference
Manual (IMX7DRM) for detailed information.
4.8.3
External interface module (EIM)
The following subsections provide information on the EIM.
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4.8.3.1
EIM interface pads allocation
EIM supports 16-bit and 8-bit devices operating in address/data separate or multiplexed modes. Table 44
provides EIM interface pads allocation in different modes.
Table 44. EIM internal module multiplexing1
Multiplexed Address/
Non Multiplexed Address/Data Mode
Data Mode
Setup
8 Bit
16 Bit
16 Bit
MUM = 0,
MUM = 0,
MUM = 0,
MUM = 1,
DSZ = 100
DSZ = 101
DSZ = 001
DSZ = 001
EIM_ADDR
[15:00]
EIM_AD
[15:00]
EIM_AD
[15:00]
EIM_AD
[15:00]
EIM_AD
[15:00]
EIM_ADDR
[25:16]
EIM_ADDR
[25:16]
EIM_ADDR
[25:16]
EIM_ADDR
[25:16]
EIM_ADDR
[25:16]
EIM_DATA
[07:00],
EIM_DATA
[07:00]
—
EIM_DATA
[07:00]
EIM_AD
[07:00]
EIM_EB0_B
EIM_DATA
[15:08],
—
EIM_DATA
[15:08]
EIM_DATA
[15:08]
EIM_AD
[15:08]
EIM_EB1_B
1
For more information on configuration ports mentioned in this table, see the i.MX 7Dual Application Processor Reference
Manual (IMX7DRM).
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4.8.3.2
General EIM Timing—Synchronous mode
Figure 12, Figure 13, and Table 45 specify the timings related to the EIM module. All EIM output control
signals may be asserted and deasserted by an internal clock synchronized to the EIM_BCLK rising edge
according to corresponding assertion/negation control fields.
,
WE2
...
WE3
EIM_BCLK
WE1
WE4
WE6
WE5
WE7
WE9
EIM_ADDRxx
EIM_CSx_B
WE8
WE10
WE12
EIM_WE_B
EIM_OE_B
EIM_EBx_B
WE11
WE13
WE15
WE17
WE14
WE16
EIM_LBA_B
Output Data
Figure 12. EIM outputs timing diagram
EIM_BCLK
WE18
Input Data
WE19
WE20
EIM_WAIT_B
WE21
Figure 13. EIM inputs timing diagram
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4.8.3.3
Examples of EIM synchronous accesses
Table 45. EIM bus timing parameters 1
BCD = 0
BCD = 1
BCD = 2
Max
BCD = 3
ID
Parameter
Min
Max
Min
Max
Min
Min
Max
WE1 EIM_BCLK Cycle
t
—
2 x t
—
3 x t
—
—
—
4 x t
—
2
time
WE2 EIM_BCLK Low
Level Width
0.4 x t
0.4 x t
—
—
0.8 x t
0.8 x t
—
—
1.2 x t
1.2 x t
1.6 x t
1.6 x t
—
—
WE3 EIM_BCLK High
Level Width
WE4 Clock rise to
-0.5 x t - -0.5 x t + 1.75 -t - 1.25 -t + 1.75 -1.5 x t -
-1.5 x t
+1.75
-2 x t - -2 x t + 1.75
1.25
3
address valid
1.25
1.25
WE5 Clock rise to
address invalid
0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25
t + 1.75 1.5 x t - 1.5 x t +1.75 2 x t - 1.25 2 x t + 1.75
1.25
WE6 Clock rise to
EIM_CSx_B valid
-0.5 x t - -0.5 x t + 1.75 -t - 1.25 - t + 1.75 -1.5 x t -
-1.5 x t
+1.75
-2 x t - -2 x t + 1.75
1.25
1.25
1.25
WE7 Clock rise to
EIM_CSx_B invalid
0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25
t + 1.75 1.5 x t - 1.5 x t +1.75 2 x t - 1.25 2 x t + 1.75
1.25
WE8 Clock rise to
EIM_WE_B Valid
-0.5 x t - -0.5 x t + 1.75 -t - 1.25 - t + 1.75 -1.5 x t -
-1.5 x t
+1.75
-2 x t - -2 x t + 1.75
1.25
1.25
1.25
WE9 Clock rise to
EIM_WE_B Invalid
0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25
t + 1.75 1.5 x t - 1.5 x t +1.75 2 x t - 1.25 2 x t + 1.75
1.25
WE10 Clock rise to
EIM_OE_B Valid
-0.5 x t - -0.5 x t + 1.75 -t - 1.25 - t + 1.75 -1.5 x t -
-1.5 x t
+1.75
-2 x t - -2 x t + 1.75
1.25
1.25
1.25
WE11 Clock rise to
EIM_OE_B Invalid
0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25
t + 1.75 1.5 x t - 1.5 x t +1.75 2 x t - 1.25 2 x t + 1.75
1.25
WE12 Clock rise to
EIM_EBx_B Valid
-0.5 x t - -0.5 x t + 1.75 -t - 1.25 - t + 1.75 -1.5 x t -
-1.5 x t
+1.75
-2 x t - -2 x t + 1.75
1.25
1.25
1.25
WE13 Clock rise to
EIM_EBx_B Invalid
0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25
t + 1.75 1.5 x t - 1.5 x t +1.75 2 x t - 1.25 2 x t + 1.75
1.25
WE14 Clock rise to
EIM_LBA_B Valid
-0.5 x t - -0.5 x t + 1.75 -t - 1.25 - t + 1.75 -1.5 x t -
-1.5 x t
+1.75
-2 x t - -2 x t + 1.75
1.25
1.25
1.25
WE15 Clock rise to
EIM_LBA_B Invalid
0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25
t + 1.75 1.5 x t - 1.5 x t +1.75 2 x t - 1.25 2 x t + 1.75
1.25
WE16 Clock rise to Output -0.5 x t - -0.5 x t + 1.75 -t - 1.25 - t + 1.75 -1.5 x t -
Data Valid 1.25 1.25
-1.5 x t
+1.75
-2 x t - -2 x t + 1.75
1.25
WE17 Clock rise to Output 0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25
Data Invalid
t + 1.75 1.5 x t - 1.5 x t +1.75 2 x t - 1.25 2 x t + 1.75
1.25
WE18 Input Data setup
time to Clock rise
2
2
2
2
—
—
—
—
4
2
4
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
WE19 Input Data hold time
from Clock rise
WE20 EIM_WAIT_B setup
time to Clock rise
WE21 EIM_WAIT_B hold
time from Clock rise
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1
t is the maximum EIM logic (axi_clk) cycle time. The maximum allowed axi_clk frequency depends on the fixed/non-fixed
latency configuration, whereas the maximum allowed EIM_BCLK frequency is:
—Fixed latency for both read and write is 132 MHz.
—Variable latency for read only is 132 MHz.
—Variable latency for write only is 52 MHz.
In variable latency configuration for write, if BCD = 0 & WBCDD = 1 or BCD = 1, axi_clk must be 104 MHz. Write BCD = 1 and
104 MHz axi_clk, will result in a EIM_BCLK of 52 MHz. When the clock branch to EIM is decreased to 104 MHz, other buses
are impacted which are clocked from this source. See the CCM chapter of the i.MX 7Dual Application Processor Reference
Manual (IMX7DRM) for a detailed clock tree description.
2
EIM_BCLK parameters are being measured from the 50% point, that is, high is defined as 50% of signal value and low is
defined as 50% as signal value.
3
For signal measurements, “High” is defined as 80% of signal value and “Low” is defined as 20% of signal value.
Figure 14 to Figure 17 provide few examples of basic EIM accesses to external memory devices with the
timing parameters mentioned previously for specific control parameters settings.
EIM_BCLK
WE4
WE6
WE5
WE7
EIM_ADDRxx
Address v1
Last Valid Address
EIM_CSx_B
EIM_WE_B
EIM_LBA_B
WE14
WE10
WE12
WE15
WE18
WE11
WE13
EIM_OE_B
EIM_EBx_B
EIM_DATAxx
D(v1)
WE19
Figure 14. Synchronous memory read access, WSC=1
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EIM_BCLK
WE5
WE4
EIM_ADDRxx
Last Valid Address
Address V1
WE7
WE6
WE8
EIM_CSx_B
EIM_WE_B
EIM_LBA_B
EIM_OE_B
WE9
WE14
WE15
WE13
WE12
WE16
EIM_EBx_B
WE17
EIM_DATAxx
D(V1)
Figure 15. Synchronous memory, write access, WSC=1, WBEA=0 and WADVN=0
EIM_BCLK
WE16
WE17
WE5
WE4
EIM_ADDRxx/
EIM_ADxx
Write Data
Last Valid Address
Address V1
WE6
WE7
WE9
EIM_CSx_B
EIM_WE_B
WE8
WE14
WE15
EIM_LBA_B
EIM_OE_B
WE10
WE11
EIM_EBx_B
Figure 16. Muxed Address/Data (A/D) mode, synchronous write access, WSC=6, ADVA=0, ADVN=1, and
ADH=1
NOTE
In 32-bit Muxed Address/Data (A/D) mode the 16 MSBs are driven on the
data bus.
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EIM_BCLK
WE4
Valid Address
WE6
WE5
Address V1
WE19
WE18
EIM_ADDRxx/
EIM_ADxx
Last
Data
EIM_CSx_B
EIM_WE_B
WE7
WE15
WE10
WE14
WE12
EIM_LBA_B
EIM_OE_B
WE11
WE13
EIM_EBx_B
Figure 17. 16-Bit Muxed A/D Mode, Synchronous Read Access, WSC=7, RADVN=1, ADH=1, OEA=0
4.8.3.4
General EIM timing—Asynchronous mode
Figure 18 through Figure 22, and Table 46 help you determine timing parameters relative to the chip
select (CS) state for asynchronous and DTACK EIM accesses with corresponding EIM bit fields and the
timing parameters mentioned above.
Asynchronous read & write access length in cycles may vary from what is shown in Figure 18 through
Figure 21 as RWSC, OEN and CSN is configured differently. See the i.MX 7Dual Application Processor
Reference Manual (IMX7DRM) for the EIM programming model.
end of
access
start of
access
INT_CLK
MAXCSO
EIM_CSx_B
EIM_ADDRxx/
EIM_ADxx
WE31
Last Valid Address
WE32
Next Address
Address V1
EIM_WE_B
EIM_LBA_B
WE39
WE40
WE36
WE38
WE35
WE37
EIM_OE_B
EIM_EBx_B
WE44
MAXCO
EIM_DATAxx[7:0]
D(V1)
MAXDI
Figure 18. Asynchronous memory read access (RWSC = 5)
WE43
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Electrical characteristics
end of
access
start of
access
INT_CLK
MAXCSO
EIM_CSx_B
MAXDI
D(V1)
WE31
EIM_ADDRxx/
EIM_ADxx
Addr. V1
WE32A
WE44
EIM_WE_B
EIM_LBA_B
WE40A
WE39
WE35A
WE37
WE36
WE38
EIM_OE_B
EIM_EBx_B
MAXCO
Figure 19. Asynchronous A/D muxed read access (RWSC = 5)
EIM_CSx_B
EIM_ADDRxx
EIM_WE_B
EIM_LBA_B
EIM_OE_B
WE31
Last Valid Address
WE33
WE32
WE34
WE40
Next Address
Address V1
WE39
WE45
WE41
WE46
EIM_EBx_B
WE42
EIM_DATAxx
D(V1)
Figure 20. Asynchronous memory write access
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Electrical characteristics
EIM_CSx_B
WE41
D(V1)
WE31
EIM_ADDRxx/
Addr. V1
WE32A
EIM_DATAxx
EIM_WE_B
WE42
WE33
WE39
WE34
WE40A
EIM_LBA_B
EIM_OE_B
WE45
WE46
WE42
EIM_EBx_B
Figure 21. Asynchronous A/D muxed write access
EIM_CSx_B
EIM_ADDRxx
WE31
WE32
Next Address
Last Valid Address
Address V1
EIM_WE_B
EIM_LBA_B
EIM_OE_B
WE39
WE35
WE37
WE40
WE36
WE38
EIM_EBx_B
WE44
D(V1)
EIM_DATAxx[7:0]
EIM_DTACK_B
WE43
WE48
WE47
Figure 22. DTACK mode read access (DAP=0)
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EIM_CSx_B
WE31
Last Valid Address
WE32
WE34
WE40
EIM_ADDRxx
EIM_WE_B
Next Address
Address V1
WE33
WE39
EIM_LBA_B
EIM_OE_B
EIM_EBx_B
WE45
WE41
WE46
WE42
EIM_DATAxx
D(V1)
WE48
EIM_DTACK_B
WE47
Figure 23. DTACK Mode write access (DAP=0)
Table 46. EIM asynchronous timing parameters table relative chip to select
Determination by
Ref No.
Parameter
Synchronous measured
Min
Max
Unit
parameters1
2
WE31
WE32
EIM_CSx_B valid to Address
Valid
WE4 – WE6 – CSA
—
—
3 – CSA
3 – CSN
ns
ns
ns
ns
ns
ns
ns
3
Address Invalid to EIM_CSx_B
invalid
WE7 – WE5 – CSN
4
5
WE32A(m EIM_CSx_B valid to Address
uxed A/D Invalid
t + WE4 – WE7 + (ADVN +
–3 + (ADVN +
ADVA + 1 – CSA)
—
6
ADVA + 1 – CSA)
WE33
WE34
WE35
EIM_CSx_B Valid to
EIM_WE_B Valid
WE8 – WE6 + (WEA – WCSA)
WE7 – WE9 + (WEN – WCSN)
WE10 – WE6 + (OEA – RCSA)
WE10 – WE6 + (OEA +
—
3 + (WEA – WCSA)
3 + (WEN – WCSN)
3 + (OEA – RCSA)
3 + (OEA +
EIM_WE_B Invalid to
EIM_CSx_B Invalid
—
—
EIM_CSx_B Valid to
EIM_OE_B Valid
WE35A EIM_CSx_B Valid to
(muxed EIM_OE_B Valid
A/D)
–3 + (OEA +
RADVN + RADVA + ADH + 1 – RADVN+RADVA+ RADVN+RADVA+AD
RCSA)
ADH+1–RCSA)
H+1–RCSA)
WE36
EIM_OE_B Invalid to
EIM_CSx_B Invalid
WE7 – WE11 + (OEN – RCSN)
—
3 – (OEN – RCSN)
ns
ns
WE37
EIM_CSx_B Valid to
EIM_EBx_B Valid (Read
access)
WE12 – WE6 + (RBEA –
RCSA)
—
3 + (RBEA – RCSA)
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Table 46. EIM asynchronous timing parameters table relative chip to select(continued)
Determination by
Synchronous measured
parameters1
Ref No.
Parameter
Min
Max
Unit
WE38
EIM_EBx_B Invalid to
EIM_CSx_B Invalid (Read
access)
WE7 – WE13 + (RBEN –
RCSN)
—
3 – (RBEN– RCSN)
ns
WE39
WE40
EIM_CSx_B Valid to
EIM_LBA_B Valid
WE14 – WE6 + (ADVA – CSA)
WE7 – WE15 – CSN
—
—
3 + (ADVA – CSA)
3 – CSN
ns
ns
EIM_LBA_B Invalid to
EIM_CSx_B Invalid (ADVL is
asserted)
WE40A EIM_CSx_B Valid to
(muxed EIM_LBA_B Invalid
A/D)
WE14 – WE6 + (ADVN + ADVA
+ 1 – CSA)
–3 + (ADVN +
ADVA + 1 – CSA)
3 + (ADVN + ADVA +
1 – CSA)
ns
WE41
EIM_CSx_B Valid to Output
Data Valid
WE16 – WE6 – WCSA
—
—
3 – WCSA
ns
ns
WE41A EIM_CSx_B Valid to Output
(muxed Data Valid
A/D)
WE16 – WE6 + (WADVN +
WADVA + ADH + 1 – WCSA)
3 + (WADVN +
WADVA + ADH + 1 –
WCSA)
WE42
Output Data Invalid to
EIM_CSx_B Invalid
WE17 – WE7 – CSN
10
—
—
3 – CSN
ns
ns
MAXCO Output maximum delay from
internal driving
—
EIM_ADDRxx/control FFs to
chip outputs
MAXCSO Output maximum delay from
CSx internal driving FFs to CSx
out
10
5
—
—
—
—
—
ns
ns
ns
MAXDI EIM_DATAxx maximum delay
from chip input data to its
internal FF
WE43
Input Data Valid to EIM_CSx_B MAXCO – MAXCSO + MAXDI
Invalid
MAXCO –
MAXCSO +
MAXDI
WE44
WE45
EIM_CSx_B Invalid to Input
Data invalid
0
0
—
ns
ns
EIM_CSx_B Valid to
EIM_EBx_B Valid (Write
access)
WE12 – WE6 + (WBEA –
WCSA)
—
3 + (WBEA – WCSA)
WE46
EIM_EBx_B Invalid to
EIM_CSx_B Invalid (Write
access)
WE7 – WE13 + (WBEN –
WCSN)
—
–3 + (WBEN –
WCSN)
ns
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Table 46. EIM asynchronous timing parameters table relative chip to select(continued)
Determination by
Synchronous measured
parameters1
Ref No.
Parameter
Min
Max
Unit
MAXDTI MAXIMUM delay from
EIM_DTACK_B to its internal
FF + 2 cycles for
10
—
—
ns
synchronization
WE47
WE48
EIM_DTACK_B Active to
EIM_CSx_B Invalid
MAXCO – MAXCSO +
MAXDTI
MAXCO –
MAXCSO +
MAXDTI
—
—
ns
ns
EIM_CSx_B Invalid to
EIM_DTACK_B Invalid
0
0
1
For more information on configuration parameters mentioned in this table, see the i.MX 7Dual Application Processor Reference
Manual (IMX7DRM).
2
3
4
5
6
In this table, CSA means WCSA when write operation or RCSA when read operation.
In this table, CSN means WCSN when write operation or RCSN when read operation.
t is axi_clk cycle time.
In this table, ADVN means WADVN when write operation or RADVN when read operation.
In this table, ADVA means WADVA when write operation or RADVA when read operation.
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4.8.4
DDR SDRAM-specific parameters (DDR3, DDR3L, LPDDR3, and
LPDDR2)
4.8.4.1
DDR3/DDR3L parameters
Figure 24 shows the DDR3 basic timing diagram with the timing parameters provided in Table 47.
DDR1
DRAM_SDCLKx_N
DRAM_SDCLKx_P
DDR2
DDR4
DRAM_CSx_B
DDR5
DRAM_RAS_B
DDR5
DDR4
DRAM_CAS_B
DDR4
DDR5
DDR5
DRAM_SDWE_B
DRAM_ODTx /
DRAM_SDCKEx
DDR4
DDR6
DRAM_ADDRxx
DDR7
ROW/BA
COL/BA
Figure 24. DDR3 Command and Address Timing Diagram
Table 47. DDR3 timing parameters
CK = 533 MHz
ID
Parameter
Symbol
Unit
Min
Max
DDR1 DRAM_SDCLKx_P clock high-level width
DDR2 DRAM_SDCLKx_P clock low-level width
t
CH
CL
0.47
0.47
425
0.53
0.53
—
t
t
CK
CK
t
DDR4 DRAM_CSx_B, DRAM_RAS_B, DRAM_CAS_B, DRAM_SDCKE, DRAM_SDWE_B,
DRAM_SDODTx setup time
t
IS
ps
DDR5 DRAM_CSx_B, DRAM_RAS_B, DRAM_CAS_B, DRAM_SDCKE, DRAM_SDWE_B,
DRAM_SDODTx hold time
t
IH
375
—
ps
DDR6 Address output setup time
DDR7 Address output hold time
t
IS
IH
425
375
—
—
ps
ps
t
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2
3
All measurements are in reference to Vref level.
Measurements were done using balanced load and 25
Ω resistor from outputs to VDD_REF.
Figure 25 shows the DDR3 write timing diagram. The timing parameters for this diagram appear in
Table 48.
DRAM_SDCLKx_P
DRAM_SDCLKx_N
DDR21
DDR17
DDR22
DDR23
DRAM_SDQSx_P
(output)
DDR18
Data
DDR17
DDR18
Data
DM
Data
Data
DM
Data
Data
DM
Data
DM
Data
DM
DRAM_DATAxx
(output)
DRAM_DQMx
(output)
DM
DM
DM
DDR17
DDR17
DDR18
DDR18
Figure 25. DDR3 write cycle
Table 48. DDR3 write cycle
CK = 533 MHz
ID
Parameter
Symbol
Unit
Min
Max
DDR17
DDR18
DRAM_DATAxx and DRAM_DQMx setup time to DRAM_SDQSx_P
(differential strobe)
t
DS
225
—
ps
ps
DRAM_DATAxx and DRAM_DQMx hold time to DRAM_SDQSx_P
t
DH
250
—
(differential strobe)
DDR21
DDR22
DDR23
DRAM_SDQSx_P latching rising transitions to associated clock edges
DRAM_SDQSx_P high level width
t
DQSS
DQSH
DQSL
-0.25
0.45
0.45
+0.25
0.55
tCK
tCK
tCK
t
DRAM_SDQSx_P low level width
t
0.55
1
To receive the reported setup and hold values, write calibration should be performed in order to locate the DRAM_SDQSx_P in
the middle of DRAM_DATAxx window.
2
3
All measurements are in reference to Vref level.
Measurements were taken using balanced load and 25
Ω resistor from outputs to DDR_VREF.
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Electrical characteristics
Figure 26 shows the DDR3 read timing diagram. The timing parameters for this diagram appear in
Table 49.
DRAM_SDCLKx_P
DRAM_SDCLKx_N
DRAM_SDQSx_P
(input)
DRAM_DATAxx
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
(input)
DDR26
Figure 26. DDR3 read cycle
Table 49. DDR3 read cycle
CK = 533 MHz
ID
Parameter
Symbol
Unit
Min
510
Max
DDR26
Minimum required DRAM_DATAxx valid window width
—
—
ps
1
To receive the reported setup and hold values, read calibration should be performed in order to locate the DRAM_SDQSx_P
in the middle of DRAM_DATAxx window.
2
3
All measurements are in reference to Vref level.
Measurements were done using balanced load and 25
Ω resistor from outputs to VDD_REF.
4.8.4.2
LPDDR3 parameters
Figure 27 shows the LPDDR3 basic timing diagram. The timing parameters for this diagram appear in
Table 50.
Figure 27. LPDDR3 command and address timing diagram
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Table 50. LPDDR3 timing parameters1,2
CK = 533 MHz
ID
Parameter
Symbol
Unit
Min
Max
LP1 SDRAM clock high-level width
LP2 SDRAM clock low-level width
LP3 DRAM_CSx_B
t
0.45
0.45
390
390
275
275
0.55
0.55
—
t
t
CH
CK
CK
t
CL
t
ps
ps
ps
ps
IS
IH
IS
IH
LP4 DRAM_CSx_E
t
—
LP3 DRAM_CAS_B setup time
LP4 DRAM_CAS_B hold time
t
t
—
—
1
2
All measurements are in reference to V level.
ref
Measurements were done using balanced load and 25
Ω resistor from outputs to DDR_VREF.
Figure 28 shows the LPDDR3 write timing diagram. The timing parameters for this diagram appear in
Table 51.
Figure 28. LPDDR3 write cycle
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Electrical characteristics
Table 51. LPDDR3 write cycle1,2,3
Parameter
CK = 533 MHz
ID
Symbol
Unit
Min
Max
LP17
LP18
DRAM_DATAxx and DRAM_DQMx setup time to DRAM_SDQSx_P
(differential strobe)
t
DS
275
—
ps
ps
DRAM_DATAxx and DRAM_DQMx hold time to DRAM_SDQSx_P
(differential strobe)
t
DH
275
—
LP21
LP22
LP23
DRAM_SDQSx_P latching rising transitions to associated clock edges
DRAM_SDQSx_P high level width
t
DQSS
DQSH
DQSL
-0.25
0.4
+0.25
—
t
t
t
CK
CK
CK
t
DRAM_SDQSx_P low level width
t
0.4
—
1
To receive the reported setup and hold values, write calibration should be performed in order to locate the DRAM_SDQS in
the middle of DRAM_DATAxx window.
2
3
All measurements are in reference to V level.
ref
Measurements were done using balanced load and 25
Ω resistor from outputs to DDR_VREF.
Figure 29 shows the LPDDR3 read timing diagram. The timing parameters for this diagram appear in
Table 52.
Figure 29. LPDDR3 read cycle
Table 52. LPDDR3 read cycle1,2,3
CK = 533 MHz
ID
Parameter
Symbol
Unit
Min
Max
LP26
Minimum required DRAM_DATAxx valid window width for LPDDR3
—
460
—
ps
1
To receive the reported setup and hold values, read calibration should be performed in order to locate the DRAM_SDQSx_P
in the middle of DRAM_DATA_xx window.
2
3
All measurements are in reference to V level.
ref
Measurements were done using balanced load and 25
Ω resistor from outputs to DDR_VREF.
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4.8.4.3
LPDDR2 parameters
Figure 30 shows the LPDDR2 basic timing diagram. The timing parameters for this diagram appear in
Table 53.
DRAM_SDCLKx_P
LP1
LP4
LP4
DRAM_CSx_B
LP2
LP3
DRAM_SDCKEx
LP3
LP3
DRAM_CAS_B
LP4
LP3
Figure 30. LPDDR2 command and address timing diagram
Table 53. LPDDR2 timing parameters1,2
CK = 533 MHz
ID
Parameter
Symbol
Unit
Min
Max
LP1
LP2
LP3
LP4
LP3
LP4
SDRAM clock high-level width
SDRAM clock low-level width
t
CH
CL
0.45
0.45
370
370
770
770
0.55
0.55
—
t
t
CK
CK
t
DRAM_CSx_B, DRAM_SDCKEx setup time
DRAM_CSx_B, DRAM_SDCKEx hold time
DRAM_CAS_B setup time
t
IS
ps
ps
ps
ps
t
IH
—
t
IS
—
DRAM_CAS_B hold time
t
—
IH
1
2
All measurements are in reference to Vref level.
Measurements were done using balanced load and 25
Ω resistor from outputs to DDR_VREF
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Electrical characteristics
Figure 31 shows the LPDDR2 write timing diagram. The timing parameters for this diagram appear in
Table 54.
DRAM_SDCLKx_P
DRAM_SDCLKx_N
LP21
LP23
DRAM_SDCLKx_P
(output)
LP22
LP17
LP18
Data
LP17
LP18
Data
Data
DM
Data
Data
DM
Data
DM
Data
DM
Data
DM
DRAM_DATAxx
(output)
DM
LP17
DM
DM
DRAM_DQMx
(output)
LP17
LP18
LP18
Figure 31. LPDDR2 write cycle
Table 54. LPDDR2 write cycle
CK = 533 MHz
ID
Parameter
Symbol
Unit
Min
Max
LP17
LP18
DRAM_DATAxx and DRAM_DQMx setup time to DRAM_SDQSx_P
(differential strobe)
t
DS
360
—
ps
ps
DRAM_DATAxx and DRAM_DQMx hold time to DRAM_SDQSx_P
(differential strobe)
t
DH
360
—
LP21
LP22
LP23
DRAM_SDQSx_P latching rising transitions to associated clock edges
DRAM_SDQSx_P high level width
t
DQSS
DQSH
DQSL
-0.25
0.4
+0.25
—
tCK
tCK
tCK
t
DRAM_SDQSx_P low level width
t
0.4
—
1
To receive the reported setup and hold values, write calibration should be performed in order to locate the DRAM_SDQS in
the middle of DRAM_DATAxx window.
2
3
All measurements are in reference to Vref level.
Measurements were done using balanced load and 25
Ω resistor from outputs to DDR_VREF.
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Figure 32 shows the LPDDR2 read timing diagram. The timing parameters for this diagram appear in
Table 55.
DRAM_SDCLKx_P
DRAM_SDCLKx_N
DRAM_SDQSx_P
(input)
LP26
DRAM_DATAxx
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
(input)
Figure 32. LPDDR2 read cycle
Table 55. LPDDR2 read cycle
CK = 533 MHz
ID
Parameter
Symbol
Unit
Min
Max
LP26
Minimum required DRAM_DATAxx valid window width for LPDDR2
—
230
—
ps
1
To receive the reported setup and hold values, read calibration should be performed in order to locate the DRAM_SDQSx_P
in the middle of DRAM_DATA_xx window.
2
3
All measurements are in reference to Vref level.
Measurements were done using balanced load and 25
Ω resistor from outputs to DDR_VREF.
4.9
General-purpose media interface (GPMI) timing
The i.MX 7Dual GPMI controller is a flexible interface NAND Flash controller with 8-bit data width, up
to 200 MB/s I/O speed and individual chip select.
It supports Asynchronous Timing mode, Source Synchronous Timing mode and Toggle Timing mode
separately, as described in the following subsections.
4.9.1
Asynchronous mode AC timing (ONFI 1.0 compatible)
Asynchronous mode AC timings are provided as multiplications of the clock cycle and fixed delay. The
maximum I/O speed of GPMI in asynchronous mode is about 50 MB/s. Figure 33 through Figure 36
depicts the relative timing between GPMI signals at the module level for different operations under
asynchronous mode. Table 56 describes the timing parameters (NF1–NF17) that are shown in the figures.
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Electrical characteristics
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Figure 34. Address Latch cycle timing diagram
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Figure 36. Read Data Latch cycle timing diagram (Non-EDO Mode)
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Electrical characteristics
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Figure 37. Read Data Latch cycle timing diagram (EDO mode)
Table 56. Asynchronous mode timing parameters1
Timing
T = GPMI Clock Cycle
ID
Parameter
Symbol
Unit
Min.
Max.
2,3
NF1
NF2
NF3
NF4
NF5
NF6
NF7
NF8
NF9
NAND_CLE setup time
NAND_CLE hold time
NAND_CE0_B setup time
NAND_CE0_B hold time
NAND_WE_B pulse width
NAND_ALE setup time
NAND_ALE hold time
Data setup time
tCLS
tCLH
tCS
(AS + DS)
×
T - 0.12 [see notes
]
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
DH
×
T - 0.72 [see note ]
3,2
(AS + DS + 1)
×
T [see notes
]
2
tCH
(DH+1)
DS
×
T - 1 [see note ]
2
tWP
tALS
tALH
tDS
×
T [see note ]
3,2
(AS + DS)
×
T - 0.49 [see notes
]
2
(DH
DS
×
T - 0.42 [see note ]
2
×
T - 0.26 [see note ]
2
Data hold time
tDH
DH
×
T - 1.37 [see note ]
2
NF10 Write cycle time
tWC
tWH
(DS + DH)
×
T [see note ]
2
NF11 NAND_WE_B hold time
NF12 Ready to NAND_RE_B low
NF13 NAND_RE_B pulse width
NF14 READ cycle time
DH
×
T [see note ]
4
3,2
tRR
(AS + 2)
×
T [see
]
—
2
tRP
tRC
DS
×
T [see note ]
2
(DS + DH)
DH
×
T [see note ]
2
NF15 NAND_RE_B high hold time
NF16 Data setup on read
tREH
tDSR
×
T [see note ]
—
(DS
×
T -0.67)/18.38 [see
notes
5,6
]
5,6
NF17 Data hold on read
tDHR
0.82/11.83 [see notes
]
—
ns
1
GPMI’s Asynchronous mode output timing can be controlled by the module’s internal registers
HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD.
This AC timing depends on these registers settings. In the table, AS/DS/DH represents each of these settings.
2
3
4
5
6
AS minimum value can be 0, while DS/DH minimum value is 1.
T = GPMI clock period -0.075ns (half of maximum p-p jitter).
NF12 is guaranteed by the design.
Non-EDO mode.
EDO mode, GPMI clock
≈ 100 MHz
(AS=DS=DH=1, GPMI_CTL1 [RDN_DELAY] = 8, GPMI_CTL1 [HALF_PERIOD] = 0).
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Electrical characteristics
In EDO mode (Figure 36), NF16/NF17 are different from the definition in non-EDO mode (Figure 35).
They are called tREA/tRHOH (RE# access time/RE# HIGH to output hold). The typical value for them
are 16 ns (max for tREA)/15 ns (min for tRHOH) at 50 MB/s EDO mode. In EDO mode, GPMI will
sample NAND_DATAxx at rising edge of delayed NAND_RE_B provided by an internal DPLL. The
delay value can be controlled by GPMI_CTRL1.RDN_DELAY (see the GPMI chapter of the i.MX 7Dual
Application Processor Reference Manual [IMX7DRM]). The typical value of this control register is 0x8
at 50 MT/s EDO mode. But if the board delay is big enough and cannot be ignored, the delay value should
be made larger to compensate the board delay.
4.9.2
Source Synchronous mode AC timing (ONFI 2.x compatible)
Figure 38 to Figure 40 show the write and read timing of Source Synchronous mode.
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76
NXP Semiconductors
Electrical characteristics
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Figure 40. Source Synchronous mode data read timing diagram
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77
Electrical characteristics
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Figure 41. NAND_DQS/NAND_DQ Read Valid window
Table 57. Source Synchronous mode timing parameters1
Timing
T = GPMI Clock Cycle
ID
Parameter
Symbol
Unit
Min.
Max.
2
NF18 NAND_CE0_B access time
NF19 NAND_CE0_B hold time
tCE
tCH
CE_DELAY
×
T - 0.79 [see note ]
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
0.5
×
tCK - 0.63 [see note ]
NF20 Command/address NAND_DATAxx setup time
NF21 Command/address NAND_DATAxx hold time
NF22 clock period
tCAS
tCAH
tCK
0.5
0.5
×
×
tCK - 0.05
tCK - 1.23
—
2
NF23 preamble delay
tPRE
tPOST
tCALS
tCALH
tDQSS
PRE_DELAY
×
T - 0.29 [see note ]
2
NF24 postamble delay
POST_DELAY
×
T - 0.78 [see note ]
NF25 NAND_CLE and NAND_ALE setup time
NF26 NAND_CLE and NAND_ALE hold time
NF27 NAND_CLK to first NAND_DQS latching transition
NF28 Data write setup
0.5
0.5
×
tCK - 0.86
×
tCK - 0.37
2
T - 0.41 [see note ]
0.25
0.25
×
×
tCK - 0.35
tCK - 0.85
NF29 Data write hold
NF30 NAND_DQS/NAND_DQ read setup skew
NF31 NAND_DQS/NAND_DQ read hold skew
—
2.06
1.95
—
1
GPMI’s Source Synchronous mode output timing can be controlled by the module’s internal registers
GPMI_TIMING2_CE_DELAY, GPMI_TIMING_PREAMBLE_DELAY, GPMI_TIMING2_POST_DELAY. This AC timing
depends on these registers settings. In the table, CE_DELAY/PRE_DELAY/POST_DELAY represents each of these settings.
2
T = tCK(GPMI clock period) –0.075 ns (half of maximum p-p jitter).
For DDR Source Synchronous mode, Figure 41 shows the timing diagram of
NAND_DQS/NAND_DATAxx read valid window. The typical value of tDQSQ is 0.85 ns (max) and 1 ns
(max) for tQHS at 200 MB/s. GPMI will sample NAND_DATA[7:0] at both rising and falling edge of an
delayed NAND_DQS signal, which can be provided by an internal DPLL. The delay value can be
controlled by GPMI register GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI
chapter of the i.MX 7Dual Application Processor Reference Manual [IMX7DRM]). Generally, the typical
delay value of this register is equal to 0x7 which means 1/4 clock cycle delay expected. But if the board
delay is big enough and cannot be ignored, the delay value should be made larger to compensate the board
delay.
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NXP Semiconductors
Electrical characteristics
4.9.3
ONFI NV-DDR2 mode (ONFI 3.2 compatible)
Command and address timing
4.9.3.1
ONFI 3.2 mode command and address timing is the same as ONFI 1.0 compatible Async mode AC timing.
See Section 4.9.1, “Asynchronous mode AC timing (ONFI 1.0 compatible),” for details.
4.9.3.2
Read and write timing
ONFI 3.2 mode read and write timing is the same as Toggle mode AC timing. See Section 4.9.4, “Toggle
mode AC Timing,” for details.
4.9.4
Toggle mode AC Timing
4.9.4.1
Command and address timing
NOTE
Toggle mode command and address timing is the same as ONFI 1.0
compatible Asynchronous mode AC timing. See Section 4.9.1,
“Asynchronous mode AC timing (ONFI 1.0 compatible),” for details.
4.9.4.2
Read and write timing
Figure 42. Toggle mode data write timing
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79
Electrical characteristics
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Figure 43. Toggle mode data read timing
Table 58. Toggle mode timing parameters1
Timing
T = GPMI Clock Cycle
ID
Parameter
Symbol
Unit
Min.
Max.
2 ,3
NF1 NAND_CLE setup time
NF2 NAND_CLE hold time
tCLS
tCLH
tCS
(AS + DS)
DH
(AS + DS)
DH
DS
(AS + DS)
×
T - 0.12 [see note s ]
2
×
T - 0.72 [see note ]
,2
NF3 NAND_CE0_B setup time
NF4 NAND_CE0_B hold time
NF5 NAND_WE_B pulse width
NF6 NAND_ALE setup time
NF7 NAND_ALE hold time
× T - 0.58 [see notes ]
2
tCH
×
T - 1 [see note ]
2
tWP
tALS
tALH
tCAS
tCAH
tCE
×
T [see note ]
,2
×
T - 0.49 [see notes ]
2
DH
DS
DH
×
×
×
T - 0.42 [see note ]
2
NF8 Command/address NAND_DATAxx setup time
NF9 Command/address NAND_DATAxx hold time
NF18 NAND_CEx_B access time
NF22 clock period
T - 0.26 [see note ]
2
T - 1.37 [see note ]
4,2
CE_DELAY
×
T [see notes
—
]
—
—
—
—
ns
ns
ns
ns
tCK
5,2
NF23 preamble delay
tPRE PRE_DELAY
×
T [see notes
]
NF24 postamble delay
tPOST POST_DELAY
× T +0.43 [see
2
note ]
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Electrical characteristics
Table 58. Toggle mode timing parameters1(continued)
Timing
T = GPMI Clock Cycle
ID
Parameter
Symbol
Unit
Min.
Max.
6
NF28 Data write setup
NF29 Data write hold
tDS
0.25
0.25
×
×
tCK - 0.32
tCK - 0.79
—
—
—
ns
ns
6
tDH
7
NF30 NAND_DQS/NAND_DQ read setup skew
NF31 NAND_DQS/NAND_DQ read hold skew
tDQSQ
3.18
3.27
7
tQHS
—
1
The GPMI toggle mode output timing can be controlled by the module’s internal registers
HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD.
This AC timing depends on these registers settings. In the table, AS/DS/DH represents each of these settings.
2
3
4
AS minimum value can be 0, while DS/DH minimum value is 1.
T = tCK (GPMI clock period) -0.075 ns (half of maximum p-p jitter).
CE_DELAY represents HW_GPMI_TIMING2[CE_DELAY]. NF18 is guaranteed by the design. Read/Write operation is started
with enough time of ALE/CLE assertion to low level.
5
6
7
PRE_DELAY+1)
≥
(AS+DS)
Shown in Figure 42.
Shown in Figure 43.
For DDR Toggle mode, Figure 41 shows the timing diagram of NAND_DQS/NAND_DATAxx read valid
window. The typical value of tDQSQ is 1.4 ns (max) and 1.4 ns (max) for tQHS at 133 MB/s. GPMI will
sample NAND_DATA[7:0] at both rising and falling edge of an delayed NAND_DQS signal, which is
provided by an internal DPLL. The delay value of this register can be controlled by GPMI register
GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the i.MX 7Dual
Application Processor Reference Manual [IMX7DRM]). Generally, the typical delay value is equal to 0x7
which means 1/4 clock cycle delay expected. But if the board delay is big enough and cannot be ignored,
the delay value should be made larger to compensate the board delay.
4.10 External peripheral interface parameters
The following subsections provide information on external peripheral interfaces.
4.10.1 ECSPI timing parameters
This section describes the timing parameters of the ECSPI blocks. The ECSPI have separate timing
parameters for master and slave modes.
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Electrical characteristics
4.10.1.1 ECSPI Master mode timing
Figure 44 depicts the timing of ECSPI in master mode. Table 59 lists the ECSPI master mode timing
characteristics.
ECSPIx_RDY_B
ECSPIx_SS_B
CS10
CS5
CS2
CS6
CS3
CS1
CS4
ECSPIx_SCLK
ECSPIx_MOSI
ECSPIx_MISO
CS2
CS3
CS7
CS9
CS8
Figure 44. ECSPI Master mode timing diagram
Table 59. ECSPI Master mode timing parameters
Parameter Symbol
ID
Min
Max Unit
CS1 ECSPIx_SCLK Cycle Time–Read
ECSPIx_SCLK Cycle Time–Write
t
43
15
—
ns
clk
CS2 ECSPIx_SCLK High or Low Time–Read
ECSPIx_SCLK High or Low Time–Write
t
21.5
7
—
ns
SW
1
CS3 ECSPIx_SCLK Rise or Fall
t
—
—
—
—
—
1
ns
ns
ns
ns
ns
ns
ns
ns
RISE/FALL
CS4 ECSPIx_SS_B pulse width
t
Half ECSPIx_SCLK period
CSLH
CS5 ECSPIx_SS_B Lead Time (CS setup time)
CS6 ECSPIx_SS_B Lag Time (CS hold time)
t
Half ECSPIx_SCLK period - 4
SCS
t
Half ECSPIx_SCLK period - 2
HCS
CS7 ECSPIx_MOSI Propagation Delay (C
CS8 ECSPIx_MISO Setup Time
CS9 ECSPIx_MISO Hold Time
= 20 pF)
t
-1
18
0
LOAD
PDmosi
t
—
—
—
Smiso
t
Hmiso
2
CS10 RDY to ECSPIx_SS_B Time
t
5
SDRY
1
2
See specific I/O AC parameters Section 4.6, “I/O AC parameters.”
SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.
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Electrical characteristics
4.10.1.2 ECSPI Slave mode timing
Figure 45 depicts the timing of ECSPI in Slave mode. Table 60 lists the ECSPI Slave mode timing
characteristics.
ECSPIx_SS_B
CS5
CS6
CS2
CS1
CS4
ECSPIx_SCLK
ECSPIx_MISO
CS2
CS9
CS8
CS7
ECSPIx_MOSI
Figure 45. ECSPI Slave mode timing diagram
Table 60. ECSPI Slave mode timing parameters
ID
Parameter
Symbol
Min
Max Unit
CS1 ECSPIx_SCLK Cycle Time–Read
ECSPI_SCLK Cycle Time–Write
t
15
43
—
—
ns
ns
clk
CS2 ECSPIx_SCLK High or Low Time–Read
ECSPIx_SCLK High or Low Time–Write
t
7
21.5
SW
CS4 ECSPIx_SS_B pulse width
t
Half ECSPIx_SCLK period
—
—
—
—
—
19
ns
ns
ns
ns
ns
ns
CSLH
CS5 ECSPIx_SS_B Lead Time (CS setup time)
CS6 ECSPIx_SS_B Lag Time (CS hold time)
CS7 ECSPIx_MOSI Setup Time
t
5
5
4
4
4
SCS
t
HCS
t
t
Smosi
Hmosi
CS8 ECSPIx_MOSI Hold Time
CS9 ECSPIx_MISO Propagation Delay (C
= 20 pF)
t
PDmiso
LOAD
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83
Electrical characteristics
4.10.2 Ultra-high-speed SD/SDIO/MMC host interface (uSDHC) AC
timing
This section describes the electrical information of the uSDHC, which includes SD/eMMC4.3 (single data
rate) timing, eMMC4.4/4.41 (dual data rate) timing and SDR104/50(SD3.0) timing.
4.10.2.1 SD/eMMC4.3 (single data rate) AC timing
Figure 46 depicts the timing of SD/eMMC4.3, and Table 61 lists the SD/eMMC4.3 timing characteristics.
SD4
SD2
SD1
SD5
SDx_CLK
SD3
SD6
Output from uSDHC to card
SDx_DATA[7:0]
SD7
SD8
Input from card to uSDHC
SDx_DATA[7:0]
Figure 46. SD/eMMC4.3 Timing
Table 61. SD/eMMC4.3 interface timing specification
ID
Parameter
Symbols
Min
Max
Unit
Card Input Clock
1
SD1 Clock Frequency (Low Speed)
f
f
f
0
0
400
25/50
20/52
400
—
kHz
MHz
MHz
kHz
ns
PP
PP
PP
2
3
Clock Frequency (SD/SDIO Full Speed/High Speed)
Clock Frequency (MMC Full Speed/High Speed)
Clock Frequency (Identification Mode)
0
f
100
7
OD
WL
WH
SD2 Clock Low Time
t
SD3 Clock High Time
SD4 Clock Rise Time
SD5 Clock Fall Time
t
7
—
ns
t
t
—
—
3
ns
TLH
THL
3
ns
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)
SD6 uSDHC Output Delay -6.6
t
3.6
ns
OD
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Electrical characteristics
Table 61. SD/eMMC4.3 interface timing specification(continued)
Parameter Symbols Min
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)
ID
Max
Unit
SD7 uSDHC Input Setup Time
t
2.5
1.5
—
—
ns
ns
ISU
4
SD8 uSDHC Input Hold Time
t
IH
1
2
In Low-Speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.
In Normal (Full) -Speed mode for SD/SDIO card, clock frequency can be any value between 0 25 MHz. In High-speed mode,
clock frequency can be any value between 0 50 MHz.
In Normal (Full) -Speed mode for MMC card, clock frequency can be any value between 0
clock frequency can be any value between 0 52 MHz.
To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.
–
–
3
4
–
20 MHz. In High-speed mode,
–
4.10.2.2 eMMC4.4/4.41 (dual data rate) AC timing
Figure 47 depicts the timing of eMMC4.4/4.41. Table 62 lists the eMMC4.4/4.41 timing characteristics.
Be aware that only DATA is sampled on both edges of the clock (not applicable to CMD).
SD1
SDx_CLK
SD2
SD2
Output from eSDHCv3 to card
SDx_DATA[7:0]
......
......
SD3
SD4
Input from card to eSDHCv3
SDx_DATA[7:0]
Figure 47. eMMC4.4/4.41 timing
Table 62. eMMC4.4/4.41 interface timing specification
ID
Parameter
Symbols
Card Input Clock
Min
Max
Unit
SD1
SD1
Clock Frequency (eMMC4.4/4.41 DDR)
Clock Frequency (SD3.0 DDR)
f
f
0
0
52
50
MHz
MHz
PP
PP
uSDHC Output / Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)
uSDHC Output Delay 2.7
SD2
t
6.9
ns
OD
uSDHC Input / Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)
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Electrical characteristics
Table 62. eMMC4.4/4.41 interface timing specification(continued)
ID
Parameter
Symbols
Min
Max
Unit
SD3
SD4
uSDHC Input Setup Time
uSDHC Input Hold Time
t
2.4
1.3
—
—
ns
ns
ISU
t
IH
4.10.2.3 HS400 AC timing—eMMC5.0 only
Figure 48 depicts the timing of HS400. Table 63 lists the HS400 timing characteristics. Be aware that only
data is sampled on both edges of the clock (not applicable to CMD). The CMD input/output timing for
HS400 mode is the same as CMD input/output timing for SDR104 mode. Check SD5, SD6 and SD7
parameters in Table 65 SDR50/SDR104 Interface Timing Specification for CMD input/output timing for
HS400 mode.
Figure 48. HS400 timing
Table 63. HS400 interface timing specifications
ID
Parameter
Symbols
Min
Max
Unit
Card Input clock
SD1
Clock Frequency
Clock Low Time
Clock High Time
fPP
0
200
Mhz
ns
SD2
SD3
t
0.46
0.46
×
×
t
t
0.54
0.54
×
×
t
t
CL
CLK
CLK
CLK
CLK
t
ns
CH
uSDHC Output/Card inputs DAT (Reference to SCK)
SD4
SD5
Output Skew from Data of
Edge of SCK
t
0.45
—
—
ns
ns
OSkew1
Output Skew from Edge of
SCK to Data
t
0.45
OSkew2
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Electrical characteristics
Unit
Table 63. HS400 interface timing specifications(continued)
ID
Parameter
Symbols
Min
Max
uSDHC input/Card Outputs DAT (Reference to Strobe)
—
—
SD6
SD7
uSDHC input skew
uSDHC hold skew
t
t
0.45
0.45
ns
ns
RQ
RQH
4.10.2.4 HS200 Mode Timing
Figure 49 depicts the timing of HS200 mode, and Table 64 lists the HS200 timing characteristics.
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6'ꢀ
Figure 49. HS200 Mode Timing
Table 64. HS200 Interface Timing Specification
ID
Parameter
Symbols
Min
Max
Unit
Card Input Clock
SD1 Clock Frequency Period
SD2 Clock Low Time
t
5.0
—
ns
ns
ns
CLK
t
0.3*t
0.7*t
CL
CLK
CLK
CLK
CLK
SD2 Clock High Time
t
0.3*t
0.7*t
CH
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)
uSDHC Output Delay –1.6
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)1
Card Output Data Window 0.5*t
t
1
ns
ns
SD5
OD
t
—
SD8
ODW
CLK
1
HS200 is for 8 bits while SDR104 is for 4 bits.
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4.10.2.5 SDR50/SDR104 AC timing
Figure 50 depicts the timing of SDR50/SDR104, and Table 65 lists the SDR50/SDR104 timing
characteristics.
SD1
SD2
SD3
SCK
SD4/SD5
8-bit output from uSDHC to eMMC
8-bit input from eMMC to uSDHC
SD6
SD7
SD8
Figure 50. SDR50/SDR104 timing
Table 65. SDR50/SDR104 interface timing specification
ID
Parameter
Symbols
Min
Max
Unit
Card Input Clock
SD1 Clock Frequency Period
SD2 Clock Low Time
t
5
—
ns
ns
ns
CLK
t
0.46
0.46
×
×
t
t
0.54
0.54
×
×
t
t
CL
CLK
CLK
CLK
SD3 Clock High Time
t
CH
CLK
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)
SD4 uSDHC Output Delay –3
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)
uSDHC Output Delay –1.6
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)
t
1
ns
ns
OD
t
1
SD5
OD
uSDHC Input Setup Time
uSDHC Input Hold Time
t
2.4
1.4
—
—
ns
ns
SD6
SD7
ISU
t
IH
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)1
Card Output Data Window 0.5*t
t
—
ns
SD8
ODW
CLK
1
Data window in SDR100 mode is variable.
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4.10.2.6 Bus operation condition for 3.3 V and 1.8 V signaling
Signaling level of SD/eMMC4.3 and eMMC4.4/4.41 modes is 3.3 V. Signaling level of SDR104/SDR50
mode is 1.8 V. The DC parameters for the NVCC_SD1, NVCC_SD2 and NVCC_SD3 supplies are
identical to those shown in Table 29, "GPIO DC Parameters," on page 44.
4.10.3 Ethernet controller (ENET) AC electrical specifications
The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive
at timing specs/constraints for the physical interface.
4.10.3.1 ENET MII mode timing
This subsection describes MII receive, transmit, asynchronous inputs, and serial management signal
timings.
4.10.3.1.1 MII receive signal timing (ENET_RX_DATA3,2,1,0, ENET_RX_EN,
ENET_RX_ER, and ENET_RX_CLK)
The receiver functions correctly up to an ENET_RX_CLK maximum frequency of 25 MHz + 1%. There
is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the
ENET_RX_CLK frequency.
Figure 51 shows MII receive signal timings. Table 66 describes the timing parameters (M1–M4) shown in
the figure.
M3
ENET_RX_CLK (input)
M4
ENET_RX_DATA3,2,1,0
(inputs)
ENET_RX_EN
ENET_RX_ER
M1
M2
Figure 51. MII receive signal timing diagram
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Table 66. MII receive signal timing
Characteristic1
ID
Min.
Max.
Unit
M1
M2
ENET_RX_DATA3,2,1,0, ENET_RX_EN, ENET_RX_ER to
ENET_RX_CLK setup
5
—
ns
ENET_RX_CLK to ENET_RX_DATA3,2,1,0, ENET_RX_EN,
ENET_RX_ER hold
5
—
ns
M3
M4
ENET_RX_CLK pulse width high
ENET_RX_CLK pulse width low
35%
35%
65%
65%
ENET_RX_CLK period
ENET_RX_CLK period
1
ENET_RX_EN, ENET_RX_CLK, and ENET0_RXD0 have the same timing in 10 Mbps 7-wire interface mode.
4.10.3.1.2 MII transmit signal timing (ENET_TX_DATA3,2,1,0, ENET_TX_EN,
ENET_TX_ER, and ENET_TX_CLK)
The transmitter functions correctly up to an ENET_TX_CLK maximum frequency of 25 MHz + 1%.
There is no minimum frequency requirement. Additionally, the processor clock frequency must exceed
twice the ENET_TX_CLK frequency.
Figure 52 shows MII transmit signal timings. Table 67 describes the timing parameters (M5–M8) shown
in the figure.
M7
ENET_TX_CLK (input)
M5
M8
ENET_TX_DATA3,2,1,0
(outputs)
ENET_TX_EN
ENET_TX_ER
M6
Figure 52. MII transmit signal timing diagram
Table 67. MII transmit signal timing
ID
Characteristic1
Min.
Max.
Unit
M5
M6
ENET_TX_CLK to ENET_TX_DATA3,2,1,0, ENET_TX_EN,
ENET_TX_ER invalid
5
—
ns
ENET_TX_CLK to ENET_TX_DATA3,2,1,0, ENET_TX_EN,
ENET_TX_ER valid
—
20
ns
M7
M8
ENET_TX_CLK pulse width high
ENET_TX_CLK pulse width low
35%
35%
65%
65%
ENET_TX_CLK period
ENET_TX_CLK period
1
ENET_TX_EN, ENET_TX_CLK, and ENET0_TXD0 have the same timing in 10-Mbps 7-wire interface mode.
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4.10.3.1.3 MII asynchronous inputs signal timing (ENET_CRS and ENET_COL)
Figure 53 shows MII asynchronous input timings. Table 68 describes the timing parameter (M9) shown in
the figure.
ENET_CRS, ENET_COL
M9
Figure 53. MII async inputs timing diagram
Table 68. MII asynchronous inputs signal timing
ID
Characteristic
Min.
Max.
Unit
1
M9
ENET_CRS to ENET_COL minimum pulse width
1.5
—
ENET_TX_CLK period
1
ENET_COL has the same timing in 10-Mbit 7-wire interface mode.
4.10.3.1.4 MII Serial management channel timing (ENET_MDIO and ENET_MDC)
The MDC frequency is designed to be equal to or less than 2.5 MHz to be compatible with the IEEE 802.3
MII specification. However the ENET can function correctly with a maximum MDC frequency of
15 MHz.
Figure 54 shows MII asynchronous input timings. Table 69 describes the timing parameters (M10–M15)
shown in the figure.
M14
M15
ENET_MDC (output)
M10
ENET_MDIO (output)
M11
ENET_MDIO (input)
M12
M13
Figure 54. MII serial management channel timing diagram
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Table 69. MII serial management channel timing
ID
Characteristic
Min.
Max.
Unit
M10
ENET_MDC falling edge to ENET_MDIO output invalid (min.
propagation delay)
0
—
ns
M11
ENET_MDC falling edge to ENET_MDIO output valid (max.
propagation delay)
—
5
ns
M12
M13
M14
M15
ENET_MDIO (input) to ENET_MDC rising edge setup
ENET_MDIO (input) to ENET_MDC rising edge hold
ENET_MDC pulse width high
18
0
—
—
ns
ns
40%
40%
60%
60%
ENET_MDC period
ENET_MDC period
ENET_MDC pulse width low
4.10.3.2 RMII mode timing
In RMII mode, ENET_CLK is used as the REF_CLK, which is a 50 MHz ± 50 ppm continuous reference
clock. ENET_RX_EN is used as the ENET_RX_EN in RMII. Other signals under RMII mode include
ENET_TX_EN, ENET_TX_DATA[1:0], ENET_RX_DATA[1:0] and ENET_RX_ER.
Figure 55 shows RMII mode timings. Table 70 describes the timing parameters (M16–M21) shown in the
figure.
M16
M17
ENET_CLK (input)
M18
ENET_TX_DATA (output)
ENET_TX_EN
M19
ENET_RX_EN (input)
ENET_RX_DATA[1:0]
ENET_RX_ER
M20
M21
Figure 55. RMII mode signal timing diagram
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Table 70. RMII signal timing
Characteristic
ID
M16
Min.
Max.
Unit
ENET_CLK pulse width high
ENET_CLK pulse width low
35%
35%
4
65%
65%
—
ENET_CLK period
M17
M18
M19
M20
ENET_CLK period
ENET_CLK to ENET0_TXD[1:0], ENET_TX_DATA invalid
ENET_CLK to ENET0_TXD[1:0], ENET_TX_DATA valid
ns
ns
ns
—
15
ENET_RX_DATAD[1:0], ENET_RX_EN(ENET_RX_EN), ENET_RX_ER to
ENET_CLK setup
4
—
M21
ENET_CLK to ENET_RX_DATAD[1:0], ENET_RX_EN, ENET_RX_ER
hold
2
—
ns
4.10.3.3 Signal switching specifications
The following timing specifications meet the requirements for RGMII interfaces for a range of transceiver
devices.
Table 71. RGMII signal switching specifications1
Symbol
Description
Min.
Max.
Unit
2
T
Clock cycle duration
7.2
-500
1
8.8
500
2.6
55
ns
ps
ns
%
cyc
3
3
T
Data to clock output skew at transmitter
Data to clock input skew at receiver
Duty cycle for Gigabit
skewT
T
skewR
4
Duty_G
45
4
Duty_T
Tr/Tf
Duty cycle for 10/100T
40
60
%
Rise/fall time (20–80%)
—
0.75
ns
1
The timings assume the following configuration:
DDR_SEL = (11)b
DSE (drive-strength) = (111)b
2
3
For 10 Mbps and 100 Mbps, T will scale to 400 ns 40 ns and 40 ns 4 ns respectively.
cyc
For all versions of RGMII prior to 2.0; This implies that PC board design will require clocks to be routed such that an additional
trace delay of greater than 1.5 ns and less than 2.0 ns will be added to the associated clock signal. For 10/100, the Max value
is unspecified.
4
Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domain as long
as minimum duty cycle is not violated and stretching occurs for no more than three Tcyc of the lowest speed transitioned
between.
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Figure 56. RGMII transmit signal timing diagram original
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Figure 57. RGMII receive signal timing diagram original
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4 HOLD 4
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Figure 58. RGMII receive signal timing diagram with internal delay
4.10.4 Flexible controller area network (flexcan) ac electrical specifications
The Flexible Controller Area Network (FlexCAN) module is a communication controller implementing
the CAN protocol according to the CAN 2.0 B protocol specification. The processor has two CAN
modules available for systems design. Tx and Rx ports for both modules are multiplexed with other I/O
pins. See the IOMUXC chapter of the i.MX 7Dual Application Processor Reference Manual (IMX7DRM)
to see which pins expose Tx and Rx pins; these ports are named FLEXCAN_TX and FLEXCAN_RX,
respectively.
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2
4.10.5 I C module timing parameters
2
2
This section describes the timing parameters of the I C module. Figure 59 depicts the timing of I C
2
module, and Table 72 lists the I C module timing characteristics.
IC11
IC9
IC10
I2Cx_SDA
I2Cx_SCL
IC7
IC4
IC2
IC3
IC8
IC10
IC6
IC11
STOP
START
START
START
IC5
IC1
Figure 59. I2C bus timing
Table 72. I2C module timing parameters
Standard Mode
Fast Mode
ID
Parameter
Unit
Min
Max
Min
Max
IC1
IC2
IC3
IC4
IC5
IC6
IC7
IC8
IC9
IC10
IC11
IC12
I2Cx_SCL cycle time
10
4.0
4.0
—
—
—
2.5
0.6
0.6
—
—
—
µ
µ
µ
µ
µ
µ
µ
s
s
s
s
s
s
s
Hold time (repeated) START condition
Set-up time for STOP condition
1
2
1
2
Data hold time
0
3.45
—
0
0.9
—
—
—
—
—
HIGH Period of I2Cx_SCL Clock
LOW Period of the I2Cx_SCL Clock
Set-up time for a repeated START condition
Data set-up time
4.0
4.7
4.7
250
4.7
—
0.6
1.3
0.6
—
—
3
—
100
1.3
ns
Bus free time between a STOP and START condition
Rise time of both I2Cx_SDA and I2Cx_SCL signals
Fall time of both I2Cx_SDA and I2Cx_SCL signals
—
µs
4
4
1000
300
400
20 + 0.1C
20 + 0.1C
—
300 ns
300 ns
400 pF
b
b
—
Capacitive load for each bus line (C )
—
b
1
A device must internally provide a hold time of at least 300 ns for I2Cx_SDA signal to bridge the undefined region of the falling
edge of I2Cx_SCL.
2
3
The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2Cx_SCL signal.
2
2
A Fast-mode I C-bus device can be used in a Standard-mode I C-bus system, but the requirement of Set-up time (ID No IC7)
of 250 ns must be met. This automatically is the case if the device does not stretch the LOW period of the I2Cx_SCL signal.
If such a device does stretch the LOW period of the I2Cx_SCL signal, it must output the next data bit to the I2Cx_SDA line
2
max_rise_time (IC9) + data_setup_time (IC7) = 1000 + 250 = 1250 ns (according to the Standard-mode I C-bus specification)
before the I2Cx_SCL line is released.
4
C = total capacitance of one bus line in pF.
b
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4.10.6 LCD controller (LCDIF) timing parameters
Figure 60 shows the LCDIF timing and Table yy lists the timing parameters.
Figure 60. LCD timing
Table 73. LCD timing parameters
ID
Parameter
Symbol
tCLK(LCD)
Min Max Unit
L1
L2
L3
L4
L5
L6
L7
LCD pixel clock frequency
-
150 MHz
LCD pixel clock high (falling edge capture)
tCLKH(LCD)
3
-
ns
ns
ns
ns
ns
ns
LCD pixel clock low (rising edge capture)
tCLKL(LCD)
3
-
LCD pixel clock high to data valid (falling edge capture)
LCD pixel clock low to data valid (rising edge capture)
LCD pixel clock high to control signals valid (falling edge capture)
LCD pixel clock low to control signals valid (rising edge capture)
td(CLKH-DV)
td(CLKL-DV)
-1
-1
-1
-1
1
1
1
1
td(CLKH-CTRLV)
td(CLKL-CTRLV)
4.10.7 Parallel CMOS sensor interface (CSI) timing parameters
4.10.7.1 Gated clock mode timing
Figure 61 and Figure 62 shows the gated clock mode timings for CSI, and Table 74 describes the timing
parameters (P1–P7) shown in the figures. A frame starts with a rising/falling edge on CSI_VSYNC
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(VSYNC), then CSI_HSYNC (HSYNC) is asserted and holds for the entire line. The pixel clock,
CSI_PIXCLK (PIXCLK), is valid as long as HSYNC is asserted.
CSI_VSYNC
P1
CSI_HSYNC
P7
P2
P5 P6
CSI_PIXCLK
P3 P4
CSI_DATA[15:00]
Figure 61. CSI Gated Clock Mode—Sensor Data at Falling Edge, Latch Data at Rising Edge
CSI_VSYNC
P1
CSI_HSYNC
P7
P2
P6 P5
CSI_PIXCLK
P3 P4
CSI_DATA[15:00]
Figure 62. CSI Gated Clock Mode—Sensor Data at Rising Edge, Latch Data at Falling Edge
Table 74. CSI Gated Clock Mode Timing Parameters
ID
Parameter
Symbol
Min.
Max.
Units
P1
P2
P3
CSI_VSYNC to CSI_HSYNC time
CSI_HSYNC setup time
CSI DATA setup time
tV2H
tHsu
tDsu
33.5
1
—
—
—
ns
ns
ns
1
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ID
Table 74. CSI Gated Clock Mode Timing Parameters(continued)
Parameter
Symbol
Min.
Max.
Units
P4
P5
P6
P7
CSI DATA hold time
CSI pixel clock high time
tDh
1
—
—
ns
ns
tCLKh
tCLKl
fCLK
3.75
3.75
—
CSI pixel clock low time
CSI pixel clock frequency
—
ns
148.5
MHz
4.10.7.2 Ungated clock mode timing
Figure 63 shows the ungated clock mode timings of CSI, and Table 75 describes the timing parameters
(P1–P6) that are shown in the figure. In ungated mode the CSI_VSYNC and CSI_PIXCLK signals are
used, and the CSI_HSYNC signal is ignored.
CSI_VSYNC
P1
P6
P4 P5
CSI_PIXCLK
P2 P3
CSI_DATA[15:00]
Figure 63. CSI Ungated Clock Mode—Sensor Data at Falling Edge, Latch Data at Rising Edge
Table 75. CSI Ungated Clock Mode Timing Parameters
ID
Parameter
Symbol
Min.
Max.
Units
P1
P2
P3
P4
P5
P6
CSI_VSYNC to pixel clock time
CSI DATA setup time
tVSYNC
tDsu
33.5
1
—
—
ns
ns
CSI DATA hold time
tDh
1
—
ns
CSI pixel clock high time
CSI pixel clock low time
CSI pixel clock frequency
tCLKh
tCLKl
fCLK
3.75
3.75
—
—
ns
—
ns
148.5
MHz
The CSI enables the chip to connect directly to external CMOS image sensors, which are classified as
dumb or smart as follows:
•
Dumb sensors only support traditional sensor timing (vertical sync (VSYNC) and horizontal sync
(HSYNC)) and output-only Bayer and statistics data.
•
Smart sensors support CCIR656 video decoder formats and perform additional processing of the
image (for example, image compression, image pre-filtering, and various data output formats).
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The following subsections describe the CSI timing in gated and ungated clock modes.
4.10.8 MIPI PHY timing parameters
4.10.8.1 This section describes MIPI PHY electrical specificationsElectrical and Timing
Information
Table 76. Electrical and Timing Information
Symbol
Parameters
Test Conditions
Min
Typ
Max
Unit
Input DC Specifications - Apply to DSI_CLK_P/DSI_CLK_N and DSI_DATA_P/DSI_DATA_N inputs
V
V
Input signal voltage range
Input leakage current
Transient voltage range is
limited from -300 mV to
1600 mV
-50
-10
—
—
1350
10
mV
I
VGNDSH(min) = VI =
VGNDSH(max) +
VOH(absmax)
mA
LEAK
Lane module in LP Receive
Mode
V
V
Ground Shift
—
—
-50
—
—
—
50
mV
V
GNDSH
Maximum transient output
voltage level
1.45
OH(absmax)
t
Maximum transient time
above VOH(absmax)
—
—
—
20
ns
voh(absmax)
HS Line Drivers DC Specifications
|V
|
HS Transmit Differential
output voltage magnitude
80 Ω<= RL< = 125
Ω
140
—
200
—
270
10
mV
mV
OD
Δ
|V
|
Change in Differential output
voltage magnitude between
logic states
80 Ω<= RL< = 125
Ω
OD
V
Steady-state common-mode
output voltage.
80 Ω<= RL< = 125
80 Ω<= RL< = 125
Ω
Ω
150
—
200
—
250
5
mV
mV
CMTX
ΔV
(1,0)
Changes in steady-state
common-mode output voltage
between logic states
CMTX
V
Z
HS output high voltage
80 Ω<= RL< = 125
Ω
—
—
360
mV
OHHS
Single-ended output
impedance.
—
40
50
62.5
Ω
OS
Δ
Z
Single-ended output
impedance mismatch.
—
—
—
10
%
OS
LP Line Drivers DC Specifications
V
V
Output low-level SE voltage
Output high-level SE voltage
—
—
-50
1.1
50
mV
V
OL
1.2
1.3
OH
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Symbol
Table 76. Electrical and Timing Information(continued)
Parameters
Test Conditions
Min
Typ
Max
Unit
Z
Single-ended output
impedance.
—
110
—
—
Ω
OLP
Δ
Z
Single-ended output
impedance mismatch driving
opposite level
—
—
—
—
—
—
20
5
%
%
OLP(01-10)
Δ
Z
Single-ended output
impedance mismatch driving
same level
OLP(0-11)
HS Line Receiver DC Specifications
V
V
V
V
Differential input high voltage
threshold
—
—
—
—
—
-70
—
—
—
—
—
70
—
mV
mV
mV
mV
IDTH
Differential input low voltage
threshold
IDTL
Single ended input high
voltage
460
—
IHHS
Single ended input low
voltage
-40
ILHS
V
Z
Input common mode voltage
Differential input impedance
—
—
70
80
—
—
330
125
mV
CMRXDC
Ω
ID
LP Line Receiver DC Specifications
V
Input low voltage
Input high voltage
Input hysteresis
—
—
—
—
920
25
—
—
—
550
—
mV
mV
mV
IL
V
V
IH
—
HYST
Contention Line Receiver DC Specifications
Input low fault threshold 200
V
—
—
450
mV
ILF
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4.10.8.2 MIPI PHY signaling levels
The signal levels are different for differential HS mode and single-ended LP mode. Figure 64 shows both
the HS and LP signal levels on the left and right sides, respectively. The HS signaling levels are below
the LP low-level input threshold such that LP receiver always detects low on HS signals.
VOH,MAX
LP
VOL
VOH,MIN
VIH
LP
VIH
LP Threshold
Region
VIL
VOHHS
Max VOD
VCMTX,MAX
LP VIL
HS Vout
Range
HS Vcm
Range
VGNDSH,MA
VCMTX,MIN
VOLHS
Min VOD
X
LP VOL
GND
VGNDSH,MIN
HS Differential Signaling
LP Single-ended Signaling
Figure 64. MIPI PHY Signaling Levels
4.10.8.3 MIPI HS line driver characteristics
Ideal Single-Ended High Speed Signals
VDN
VCMTX = (VDP + VDN)/2
VOD(0)
VOD(1)
VDP
Ideal Differential High Speed Signals
VOD(1)
0V
(Differential)
VOD(0)
VOD = VDP - VDN
Figure 65. Ideal Single-ended and Resulting Differential HS Signals
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Electrical characteristics
4.10.8.4 Possible
ΔVCMTX and ΔVOD Distortions of the Single-ended HS Signals
VOD/2
Δ
VOD (SE HS Signals)
Δ
VDN
VOD (1)
VCM TX
VOD(0)
VDP
VOD /2
Δ
Static VCMTX (SE HS Signals)
Δ
VDN
VCMTX
VOD(0)
VDP
Dynamic VCMTX (SE HS Signals)
Δ
VDN
VCM TX
VDP
Figure 66. Possible ΔVCMTX and ΔVOD Distortions of the Single-ended HS Signals
4.10.8.5 MIPI PHY switching characteristics
Table 77. Electrical and Timing Information
Symbol
Parameters
Test Conditions
Min
Typ
Max
Unit
HS Line Drivers AC Specifications
—
Maximum serial data rate (forward
direction)
On DATAP/N outputs.
80 <= RL <= 125
80
—
1500
Mbps
Ω
Ω
F
DDR CLK frequency
On DATAP/N outputs.
40
1.33
—
—
—
750
25
MHz
DDRCLK
P
t
DDR CLK period
80 Ω<= RL< = 125
Ω
ns
DDRCLK
DDR CLK duty cycle
t
=
t
/
P
50
1
—
%
CDC
CPH
CPL
CDC
CPH
DDRCLK
t
t
DDR CLK high time
—
—
—
—
—
—
—
UI
DDR CLK low time
—
1
—
UI
ps pk–pk
UI
—
DDR CLK / DATA Jitter
Intra-Pair (Pulse) skew
Data to Clock Skew
—
75
0.075
—
—
t
t
t
t
—
—
SKEW[PN]
0.350
150
150
—
0.650
0.3UI
0.3UI
15
UI
SKEW[TX]
Differential output signal rise time
Differential output signal fall time
20% to 80%, RL = 50
20% to 80%, RL = 50
Ω
Ω
—
ps
r
f
—
ps
ΔV
Common level variation above 450 MHz 80
Ω
Ω
<= RL< = 125
<= RL< = 125
Ω
Ω
—
mV
CMTX(HF)
CMTX(LF)
rms
ΔV
Common level variation between 50
MHz and 450 MHz.
80
—
—
25
mV
p
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Table 77. Electrical and Timing Information(continued)
Symbol
Parameters
Test Conditions
Min
Typ
Max
Unit
LP Line Drivers AC Specifications
t
t
t
Single ended output rise/fall time
15% to 85%, C <70 pF
—
—
—
0
—
—
—
—
25
35
ns
ns
rlp, flp
L
30% to 85%, C <70 pF
reo
L
δ
C
V/δ SR
t
Signal slew rate
15% to 85%, C <70 pF
120
70
mV/ns
pF
L
Load capacitance
—
L
HS Line Receiver AC Specifications
t
t
Data to Clock Receiver Setup time
—
—
—
0.15
0.15
—
—
—
—
—
—
UI
UI
SETUP[RX]
HOLD[RX]
Clock to Data Receiver Hold time
Δ
V
Common mode interference beyond
450 MHz
200
mVpp
CMRX(HF)
Δ
V
Common mode interference between
50 MHz and 450 MHz.
—
—
-50
—
—
—
50
60
mVpp
pF
CMRX(LF)
C
Common mode termination
CM
LP Line Receiver AC Specifications
e
Input pulse rejection
—
—
—
—
—
—
—
—
300
Vps
ns
SPIKE
T
Minimum pulse response
Pk-to-Pk interference voltage
Interference frequency
50
—
MIN
V
400
—
mV
MHz
INT
f
450
INT
Model Parameters used for Driver Load switching performance evaluation
C
C
Equivalent Single ended I/O PAD
capacitance.
—
—
—
—
—
—
1
2
pF
pF
PAD
PIN
Equivalent Single ended Package +
PCB capacitance.
L
Equivalent wire bond series inductance
Equivalent wire bond series resistance
Load resistance
—
—
—
—
—
80
—
—
1.5
0.15
125
nH
Ω
S
R
R
S
L
100
Ω
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Electrical characteristics
4.10.8.6 High-speed clock timing
#,+P
#,+N
ꢄ$ATA "IT 4IME ꢋ ꢄ5)
ꢄ$ATA "IT 4IME ꢋ ꢄ5)
5)).34 ꢉꢆꢊ
5)).34 ꢉꢄꢊ
5)).34 ꢉꢄꢊ ꢌ 5)).34 ꢉꢆꢊ
ꢄ $$2 #LOCK 0ERIOD ꢋ
Figure 67. DDR Clock Definition
4.10.8.7 Forward high-speed data transmission timing
The timing relationship of the DDR Clock differential signal to the Data differential signal is shown in
Figure 68:
2EFERENCE 4IME
43%450
4(/,$
ꢌ
ꢀꢍꢎ5)).34
43+%7
#,+P
#,+N
ꢄ 5)).34
4#,+P
Figure 68. Data to Clock Timing Definitions
4.10.8.8 Reverse high-speed data transmission timing
4
4$
.2: $ATA
#,+?.
#,+?0
#LOCK TO $ATA
3KEW
ꢆ5)
ꢆ5)
Figure 69. Reverse High-Speed Data Transmission Timing at Slave Side
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Electrical characteristics
4.10.8.9 Low-power receiver timing
2*TLPX
2*TLPX
eSPIKE
VIH
VIL
Input
eSPIKE
TMIN-RX
TMIN-RX
Output
Input Glitch Rejection of Low-Power Receivers
4.10.9 PCIe PHY parameters
The PCIe interface is designed to be compatible with PCIe specification Gen2 x1 lane and supports the
PCI Express 1.1/2.0 standard.
4.10.9.1 PCIE_REXT reference resistor connection
The impedance calibration process requires connection of reference resistor 4.7 kΩ. 1% precision resistor
on PCIE_REXT pads to ground. It is used for termination impedance calibration.
4.10.10 Pulse width modulator (PWM) timing parameters
This section describes the electrical information of the PWM. The PWM can be programmed to select one
of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before
being input to the counter. The output is available at the pulse-width modulator output (PWMO) external
pin.
Figure 70 depicts the timing of the PWM, and Table 78 lists the PWM timing parameters.
0ꢄ
0ꢆ
07-N?/54
Figure 70. PWM Timing
Table 78. PWM output timing parameters
ID
Parameter
PWM Module Clock Frequency
Min
Max
ipg_clk
Unit
0
MHz
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Electrical characteristics
Table 78. PWM output timing parameters(continued)
P1
P2
PWM output pulse width high
PWM output pulse width low
15
ns
ns
15
4.10.11 QUAD SPI (QSPI) Timing Parameters
Measurement conditions are with 35 pF load on SCK and SIO pins and input slew rate of 1 V/ns.
4.10.11.1 SDR Mode
463,[B6&/.
7,6
7,+
7,6
7,+
463,[B'$7$>ꢅꢌꢆ@
Figure 71. QuadSPI Input/Read Timing (SDR mode with internal sampling)
Table 79. QuadSPI Input Timing (SDR mode with internal sampling)
Value
Symbol
Parameter
Unit
Min
8.67
Max
T
T
Setup time for incoming data
—
—
ns
ns
IS
IH
Hold time requirement for incoming data
0
ꢊ
ꢈ
ꢉ
ꢅ
463,[B6&/.
463,[B'$7$>ꢋꢌꢉ@
463,[B'46
7,6
7,+
7,6
7,+
Figure 72. QuadSPI Input/Read Timing (SDR mode with loopback DQS sampling)
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Table 80. QuadSPI Input/Read Timing (SDR mode with loopback DQS sampling)
Value
Symbol
Parameter
Unit
Min
Max
T
T
Setup time for incoming data
2
1
—
—
ns
ns
IS
IH
Hold time requirement for incoming data
NOTE
•
•
For internal sampling, the timing values assumes using sample point 0,
that is QuadSPIx_SMPR[SDRSMP] = 0.
For loopback DQS sampling, the data strobe is output to the DQS pad
together with the serial clock. The data strobe is looped back from DQS
pad and used to sample input data.
463,[B6&/.
463,[B&6
7&6+
7&66
7&.
7'92
7'92
463,[B6,2
7'+2
7'+2
Figure 73. QuadSPI Output/Write Timing (SDR mode)
Table 81. QuadSPI Output/Write Timing (SDR mode)
Value
Symbol
Parameter
Unit
Min
Max
T
T
T
T
T
Output data valid time
Output data hold time
SCK clock period
—
-0.5
10
3
2.5
—
—
—
—
ns
ns
ns
DVO
DHO
CK
Chip select output setup time
Chip select output hold time
SCK cycle(s)
SCK cycle(s)
CSS
CSH
3
NOTE
and T are configured by the QuadSPIx_FLSHCR register, the default
T
css
csh
value of 3 are shown on the timing. Please refer to the i.MX 6SoloX
Reference Manual (IMX6ULLRM) for more details.
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4.10.11.2 DDR Mode
463,[B6&/.
7,6
7,+
7,6
7,+
463,[B'$7$>ꢋꢌꢉ@
Figure 74. QuadSPI Input/Read Timing (DDR mode with internal sampling)
Table 82. QuadSPI Input/Read Timing (DDR mode with internal sampling)
Value
Symbol
Parameter
Unit
Min
8.67
Max
T
T
Setup time for incoming data
—
—
ns
ns
IS
IH
Hold time requirement for incoming data
0
ꢊ
ꢈ
ꢉ
ꢅ
463,[B6&/.
463,[B'$7$>ꢋꢌꢉ@
463,[B'46
7,6
7,+
7,6
7,+
Figure 75. QuadSPI Input/Read Timing (DDR mode with loopback DQS sampling)
Table 83. QuadSPI Input/Read Timing (DDR mode with loopback DQS sampling)
Value
Symbol
Parameter
Unit
Min
Max
T
T
Setup time for incoming data
2
1
—
—
ns
ns
IS
IH
Hold time requirement for incoming data
NOTE
•
For internal sampling, the timing values assumes using sample point 0,
that is QuadSPIx_SMPR[SDRSMP] = 0.
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•
For loopback DQS sampling, the data strobe is output to the DQS pad
together with the serial clock. The data strobe is looped back from DQS
pad and used to sample input data.
ꢊ
ꢈ
463,[B6&/.
463,[B&6
7&66
7&.
7&6+
7'92
7'92
463,[B6,2
7'+2
7'+2
Figure 76. QuadSPI Output/Write Timing (DDR mode)
Table 84. QuadSPI Output/Write Timing (DDR mode)
Value
Symbol
Parameter
Unit
Min
Max
T
T
T
T
T
Output data valid time
Output data hold time
SCK clock period
—
(0.25 x T
) + 2.5
ns
ns
ns
DVO
DHO
CK
SCLK
(0.25 x T
) - 0.5
—
—
—
—
SCLK
20
3
Chip select output setup time
Chip select output hold time
SCK cycle(s)
SCK cycle(s)
CSS
CSH
3
NOTE
and T are configured by the QuadSPIx_FLSHCR register, the default
T
css
csh
value of 3 are shown on the timing. See the i.MX 7Dual Reference Manual
(IMX7DRM) for more details.
2
4.10.12 SAI/I S switching specifications
This section provides the AC timings for the SAI in master (clocks driven) and slave (clocks input) modes.
All timings are given for noninverted serial clock polarity (SAI_TCR[TSCKP] = 0, SAI_RCR[RSCKP] =
0) and noninverted frame sync (SAI_TCR[TFSI] = 0, SAI_RCR[RFSI] = 0). If the polarity of the clock
and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal
(SAI_BCLK) and/or the frame sync (SAI_FS) shown in the figures below.
Table 85. Master mode SAI timing
Num
Characteristic
SAI_MCLK cycle time
Min
Max
Unit
S1
S2
S3
S4
20
40%
40
—
60%
—
ns
SAI_MCLK pulse width high/low
SAI_BCLK cycle time
MCLK period
ns
SAI_BCLK pulse width high/low
40%
60%
BCLK period
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Num
Table 85. Master mode SAI timing(continued)
Characteristic
Min
Max
Unit
S5
S6
S7
S8
S9
S10
SAI_BCLK to SAI_FS output valid
SAI_BCLK to SAI_FS output invalid
SAI_BCLK to SAI_TXD valid
—
0
15
—
15
—
—
—
ns
ns
ns
ns
ns
ns
—
0
SAI_BCLK to SAI_TXD invalid
SAI_RXD/SAI_FS input setup before SAI_BCLK
SAI_RXD/SAI_FS input hold after SAI_BCLK
15
0
Figure 77. SAI timing — master modes
Table 86. Master mode SAI timing
Num
Characteristic
SAI_BCLK cycle time (input)
Min
Max
Unit
S11
S12
S13
S14
S15
S16
S17
S18
40
40%
10
2
—
60%
—
ns
SAI_BCLK pulse width high/low (input)
SAI_FS input setup before SAI_BCLK
SAI_FA input hold after SAI_BCLK
SAI_BCLK to SAI_TXD/SAI_FS output valid
SAI_BCLK to SAI_TXD/SAI_FS output invalid
SAI_RXD setup before SAI_BCLK
BCLK period
ns
ns
ns
ns
ns
ns
—
—
0
20
—
10
2
—
SAI_RXD hold after SAI_BCLK
—
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Figure 78. SAI timing — slave modes
4.10.13 SCAN JTAG controller (SJC) timing parameters
Figure 79 depicts the SJC test clock input timing. Figure 80 depicts the SJC boundary scan timing.
Figure 81 depicts the SJC test access port. Signal parameters are listed in Table 87.
SJ1
SJ2
SJ2
JTAG_TCK
(Input)
VM
VM
VIH
VIL
SJ3
SJ3
Figure 79. Test clock input timing diagram
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JTAG_TCK
(Input)
VIH
VIL
SJ5
SJ4
Input Data Valid
Data
Inputs
SJ6
Data
Outputs
Output Data Valid
SJ7
SJ6
Data
Outputs
Data
Outputs
Output Data Valid
Figure 80. Boundary scan (JTAG) timing diagram
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JTAG_TCK
(Input)
VIH
SJ9
VIL
SJ8
Input Data Valid
JTAG_TDI
JTAG_TMS
(Input)
SJ10
SJ11
SJ10
JTAG_TDO
(Output)
Output Data Valid
JTAG_TDO
(Output)
JTAG_TDO
(Output)
Output Data Valid
Figure 81. Test access port timing diagram
JTAG_TCK
(Input)
SJ13
JTAG_TRST_B
(Input)
SJ12
Figure 82. JTAG_TRST_B timing diagram
Table 87. JTAG timing
All Frequencies
Min Max
ID
Parameter1,2
Unit
1
SJ0
SJ1
SJ2
SJ3
SJ4
SJ5
SJ6
SJ7
SJ8
JTAG_TCK frequency of operation 1/(3•T
JTAG_TCK cycle time in Crystal mode
)
0.001
45
22.5
—
22
—
—
3
MHz
ns
DC
2
JTAG_TCK clock pulse width measured at
JTAG_TCK rise and fall times
V
ns
M
ns
Boundary scan input data set-up time
Boundary scan input data hold time
JTAG_TCK low to output data valid
JTAG_TCK low to output high impedance
JTAG_TMS, JTAG_TDI data set-up time
5
—
—
40
40
—
ns
24
—
ns
ns
—
ns
5
ns
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Table 87. JTAG timing(continued)
Parameter1,2
All Frequencies
ID
Unit
Min
Max
SJ9
JTAG_TMS, JTAG_TDI data hold time
JTAG_TCK low to JTAG_TDO data valid
JTAG_TCK low to JTAG_TDO high impedance
JTAG_TRST_B assert time
25
—
—
44
44
—
—
ns
ns
ns
ns
ns
SJ10
SJ11
SJ12
SJ13
—
100
40
JTAG_TRST_B set-up time to JTAG_TCK low
1
2
T
= target frequency of SJC
= mid-point voltage
DC
V
M
4.10.14 UART I/O configuration and timing parameters
4.10.14.1 UART RS-232 I/O configuration in different modes
The i.MX 7Dual UART interfaces can serve both as DTE or DCE device. This can be configured by the
DCEDTE control bit (default 0—DCE mode). Table 88 shows the UART I/O configuration based on the
enabled mode.
Table 88. UART I/O configuration vs. mode
DTE Mode
Description
DCE Mode
Description
Port
Direction
Direction
UARTx_RTS_B
UARTx_CTS_B
UARTx_TX_ DATA
Output
Input
UARTx_RTS_B from DTE to DCE
UARTx_CTS_B from DCE to DTE
Serial data from DCE to DTE
Serial data from DTE to DCE
Input
Output
Output
Input
UARTx_RTS_B from DTE to DCE
UARTx_CTS_B from DCE to DTE
Serial data from DCE to DTE
Serial data from DTE to DCE
Input
UARTx_RX
_DATA
Output
4.10.14.2 UART RS-232 Serial mode timing
This section describes the electrical information of the UART module in the RS-232 mode.
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4.10.14.2.1 UART transmitter
Figure 83 depicts the transmit timing of UART in the RS-232 Serial mode, with 8 data bit/1 stop bit
format. Table 89 lists the UART RS-232 Serial mode transmit timing characteristics.
Possible
UA1
UA1
Parity
Bit
Next
Start
Bit
Start
Bit
UARTx_TX_DATA
(output)
STOP
BIT
Bit 7
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Par Bit
UA1
UA1
Figure 83. UART RS-232 Serial mode transmit timing diagram
Table 89. RS-232 Serial mode transmit timing parameters
ID
Parameter
Symbol
Min
Max
+ T
ref_clk
Unit
1
2
UA1 Transmit Bit Time
t
1/F
- T
1/F
—
Tbit
baud_rate
ref_clk
baud_rate
1
2
F
: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
baud_rate
T
: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).
ref_clk
4.10.14.2.2 UART receiver
Figure 84 depicts the RS-232 Serial mode receive timing with 8 data bit/1 stop bit format. Table 90 lists
Serial mode receive timing characteristics.
Possible
Parity
UA2
UA2
Bit 3
Bit
Next
Start
Bit
Start
Bit
STOP
BIT
UARTx_RX_DATA
(output)
Bit 7
Bit 0
Bit 1
Bit 2
Bit 4
Bit 5
Bit 6
Par Bit
UA2
UA2
Figure 84. UART RS-232 Serial mode receive timing diagram
Table 90. RS-232 Serial mode receive timing parameters
ID
Parameter
Symbol
Min
Max
Unit
1
2
UA2
Receive Bit Time
t
1/F
- 1/(16
1/F
baud_rate
+
—
Rbit
baud_rate
x F
)
1/(16 x F
)
baud_rate
baud_rate
1
2
The UART receiver can tolerate 1/(16 x F
) tolerance in each bit. But accumulation tolerance in one frame must not
baud_rate
exceed 3/(16 x F
).
baud_rate
F
: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
baud_rate
4.10.15 USB HSIC timing
This section describes the electrical information of the USB HSIC port.
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NOTE
HSIC is DDR signal, following timing spec is for both rising and falling
edge.
4.10.15.1 Transmit timing
Tstrobe
USB_H_STROBE
USB_H_DATA
Todelay
Todelay
Figure 85. USB HSIC transmit waveform
Table 91. USB HSIC transmit parameters
Name
Parameter
Min
Max
Unit
Comment
Tstrobe strobe period
4.165
550
4.169
1350
2
ns
ps
Todelay data output delay time
Measured at 50% point
Tslew
strobe/data rising/falling time
0.7
V/ns
Averaged from 30% – 70% points
4.10.15.2 Receive timing
Tstrobe
USB_H_STROBE
USB_H_DATA
Thold
Tsetup
Figure 86. USB HSIC receive waveform
Table 92. USB HSIC receive parameters1
Name
Parameter
strobe period
Min
Max
Unit
Comment
Tstrobe
Thold
4.165
300
365
0.7
4.169
ns
ps
data hold time
Measured at 50% point
Tsetup
Tslew
data setup time
ps
Measured at 50% point
strobe/data rising/falling time
2
V/ns
Averaged from 30% – 70% points
1
The timings in the table are guaranteed when:
—AC I/O voltage is between 0.9x to 1x of the I/O supply
—DDR_SEL configuration bits of the I/O are set to (10)b
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4.10.16 USB PHY parameters
This section describes the USB-OTG PHY parameters.
The USB PHY meets the electrical compliance requirements defined in the Universal Serial Bus Revision
2.0 OTG, USB Host with the amendments below (On-The-Go and Embedded Host Supplement to the USB
Revision 2.0 Specification is not applicable to Host port):
•
USB ENGINEERING CHANGE NOTICE
— Title: 5V Short Circuit Withstand Requirement Change
— Applies to: Universal Serial Bus Specification, Revision 2.0
Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000
USB ENGINEERING CHANGE NOTICE
•
•
— Title: Pull-up/Pull-down resistors
— Applies to: Universal Serial Bus Specification, Revision 2.0
USB ENGINEERING CHANGE NOTICE
•
•
— Title: Suspend Current Limit Changes
— Applies to: Universal Serial Bus Specification, Revision 2.0
USB ENGINEERING CHANGE NOTICE
— Title: USB 2.0 Phase Locked SOFs
— Applies to: Universal Serial Bus Specification, Revision 2.0
On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification
— Revision 2.0, version 1.1a, July 27, 2010
•
•
Battery Charging Specification (available from USB-IF)
— Revision 1.2, December 7, 2010
4.10.16.1 USB_OTG*_REXT reference resistor connection
The bias generation and impedance calibration process for the USB OTG PHYs requires connection of
reference resistors 200 Ω 1% precision on each of USB_OTG1_REXT and USB_OTG2_REXT pads to
ground.
4.10.16.2 USB_OTG_CHD_B USB battery charger detection external pullup
resistor connection
The usage and external resistor connection for the USB_OTG_CHD_B pin are described in Table 3,
Table 7, and Section 4.7.3, “USB battery charger detection driver impedance.”
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Electrical characteristics
4.11 12-Bit A/D converter (ADC)
Table 93. Recommended operating conditions for 12-bit ADC
Characteristics
Symbol
Min
Typ
Max
Unit
Supply Voltage
Operating Temp
AVDD18
VDDA10
1.7
0.95
–25
1.8
1
1.9
1.05
105
16
V
V
T
—
—
—
—
—
50
C
Channel
V
J
Analog Input Channel
—
—
1
Analog Input Range
ADC
x_IN
x
AGND
300K
50K
—
VREF
6M
Main Clock Frequency
FCLK
FSOC
Hz
Start of conversion clk frequency (FCLK/3)
1M
Hz
2
External Input Resistance of ADC
R
250
Ω
IEXT
1
2
DO=111111111111 @AIN=AVDD18 & DO=000000000000 @AIN=AVSS18 (Input full-scale voltage = AVDD18)
= Output resistance of the ADC driver = Output resistance of signal generator + Series parasitic resistance between
R
IEXT
signal source and ADC input (for example, PCB and bonding wire resistance and ESD protection resistance)
Table 94. DC Electrical characteristics
Specification
Resolution
Symbol
Min
Typ
Max
Unit
Conditions
—
—
—
12
12
Bits
—
Differential
DNL
2.0
2.0
LSB
PD=Low
Non-Linearity
FCLK=6MHz
FSOC=1MHz
FAIN=10kHz
Ramp wave
Integral
Non-Linearity
INL
—
6.0
6.0
LSB
Top Offset Voltage
EOT
EOB
—
—
10
11
100
100
LSB
LSB
Bottom Offset
Voltage
Table 95. AC Electrical characteristics
Specification
Symbol
Min
Typ
Max
Unit
Main Clock Duty Ratio
—
45
DC
—
45
55
%
Hz
mA
Analog Input Frequency CH #15-0
Normal Operation Current Consumption
FAIN
50k
0.53
100K
1.90
1
VDDA_ADCx_1P8
2
2
VDDA_1P0_CAP
—
0.02
0.10
mA
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Boot mode configuration
Table 95. AC Electrical characteristics(continued)
Specification
Symbol
Min
Typ
Max
Unit
2
3
Power Down Current
IPD
—
3.0
60
300
—
μΑ
Signal to Noise and Distortion Ratio
SNDR
54
dB
1
Normal operation current consumption includes only the current from the ADC core. It does not include static current from the
power pads.
2
3
Power-down current includes only the current from the ADC core. It does not include static current from the power pads.
IOP and IPD are measurable only on the ADC core's test chips. Because AVDD10 is shared with internal logic power, IOP
and IPD in the test plan only measure current consumption @ AVDD18, VREF.
5 Boot mode configuration
This section provides information on Boot mode configuration pins allocation and boot devices interfaces
allocation.
5.1
Boot mode configuration pins
Table 96 provides boot options, functionality, fuse values, and associated pins. Several input pins are also
sampled at reset and can be used to override fuse values, depending on the value of BT_FUSE_SEL fuse.
The boot option pins are in effect when BT_FUSE_SEL fuse is ‘0’ (cleared, which is the case for an
unblown fuse). For detailed Boot mode options configured by the Boot mode pins, see the “System Boot,
Fusemap, and eFuse” chapter in the i.MX 7Dual Application Processor Reference Manual (IMX7DRM).
Table 96. Fuses and associated pins used for boot
State during reset State after reset
Direction
at Reset
eFuse
name
Pin
(POR_B
(POR_B
Details
asserted)
deasserted)
BOOT_MODE0
BOOT_MODE1
Input
Input
N/A
N/A
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Boot mode selection
Boot mode selection
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Boot mode configuration
Table 96. Fuses and associated pins used for boot(continued)
State during reset State after reset
Direction
at Reset
eFuse
name
Pin
(POR_B
asserted)
(POR_B
deasserted)
Details
LCD1_DATA00
LCD1_DATA01
LCD1_DATA02
LCD1_DATA03
LCD1_DATA04
LCD1_DATA05
LCD1_DATA06
LCD1_DATA07
LCD1_DATA08
LCD1_DATA09
LCD1_DATA10
LCD1_DATA11
LCD1_DATA12
LCD1_DATA13
LCD1_DATA14
LCD1_DATA15
LCD1_DATA16
LCD1_DATA17
LCD1_DATA18
LCD1_DATA19
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
BT_CFG[0]
BT_CFG[1]
BT_CFG[2]
BT_CFG[3]
BT_CFG[4]
BT_CFG[5]
BT_CFG[6]
BT_CFG[7]
BT_CFG[8]
BT_CFG[9]
100K Pull Down
100K Pull Down
100K Pull Down
100K Pull Down
100K Pull Down
100K Pull Down
100K Pull Down
100K Pull Down
100K Pull Down
100K Pull Down
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Boot options, pin value overrides fuse
settings for BT_FUSE_SEL=’0’. Signal
configuration as fuse override input at
power up.
These are special I/O lines that control the
boot configuration during product
development. In production, the boot
configuration can be controlled by fuses.
BT_CFG[10] 100K Pull Down
BT_CFG[11] 100K Pull Down
BT_CFG[12] 100K Pull Down
BT_CFG[13] 100K Pull Down
BT_CFG[14] 100K Pull Down
BT_CFG[15] 100K Pull Down
BT_CFG[16] 100K Pull Down
BT_CFG[17] 100K Pull Down
BT_CFG[18] 100K Pull Down
BT_CFG[19] 100K Pull Down
5.2
Boot device interface allocation
Table 97 lists the interfaces that can be used by the boot process in accordance with the specific Boot
mode configuration. The table also describes the interface’s specific modes and IOMUXC allocation,
which are configured during boot when appropriate.
Table 97. Interface allocation during boot
Interface
IP Instance
Allocated Pads During Boot
Comment
QSPI
QSPI
EPDC_D0, EPDC_D1, EPDC_D2, EPDC_D3,
EPDC_D4, EPDC_D5, EPDC_D6, EPDC_D7,
EPDC_D8, EPDC_D9, EPDC_D10, EPDC_D11,
EPDC_D12, EPDC_D13, EPDC_D14, EPDC_D15
SPI
ECSPI-1
ECSPI1_SCLK, ECSPI1_MOSI, ECSPI1_MISO,
ECSPI1_SS0, UART1_RXD, UART1_TXD,
UART2_RXD
The chip-select pin used depends
on the fuse "CS select (SPI only)"
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Boot mode configuration
Comment
Table 97. Interface allocation during boot(continued)
Allocated Pads During Boot
Interface
IP Instance
SPI
ECSPI-2
ECSPI2_SCLK, ECSPI2_MOSI, ECSPI2_MISO,
ECSPI2_SS0, ENET1_RX_CTL, ENET1_RXC,
ENET1_TD0
The chip-select pin used depends
on the fuse "CS select (SPI only)"
SPI
SPI
EIM
ECSPI-3
ECSPI-4
EIM
SAI2_TXFS, SAI2_TXC, SAI2_RXD, SAI2_TXD,
SD1_DATA3, SD2_CD_B, SD2_WP
The chip-select pin used depends
on the fuse "CS select (SPI only)"
SD1_CD_B, SD1_WP, SD1_RESET_B, SD1_CLK,
SD1_CMD, SD1_DATA0, SD1_DATA1
The chip-select pin used depends
on the fuse "CS select (SPI only)"
EPDC_SDCE2, EPDC_SDCE3, EPDC_GDCLK,
EPDC_GDOE, EPDC_GDRL, EPDC_GDSP,
Used for NOR, OneNAND boot
Only CS0 is supported. Allocated
EPDC_BDR0, LCD_DAT20, LCD_DAT21, LCD_DAT22, pads may differ depending on mux
LCD_DAT23, EPDC_D8, EPDC_D9, EPDC_D10,
EPDC_D12, EPDC_D14, EPDC_PWRSTAT
mode. See the “System Boot,
Fusemap, and eFuse” chapter of
the i.MX 7Dual Application
Processor Reference Manual
(IMX7DRM) for details.
NAND Flash
SD/MMC
GPMI
SD3_CLK, SD3_CMD, SD3_DATA0, SD3_DATA1,
SD3_DATA2, SD3_DATA3, SD3_DATA4, SD3_DATA5, Only CS0 is supported
SD3_DATA6, SD3_DATA7, SD3_STROBE,
8 bit
SD3_RESET_B, SAI1_TXC, SAI1_TXFS, SAI1_TXD
USDHC-1
USDHC-2
USDHC-3
SD1_CD_B, SD1_RESET_B, SD1_CLK, SD1_CMD,
SD1_DATA0, SD1_DATA1, SD1_DATA2, SD1_DATA3,
GPIO1_IO08, ECSPI2_SCLK, ECSPI2_MOSI,
ECSPI2_MISO, ECSPI2_SS0
1, 4, or 8 bit
1, 4, or 8 bit
SD/MMC
SD2_RESET_B, SD2_CLK, SD2_CMD, SD2_DATA0,
SD2_DATA1, SD2_DATA2, SD2_DATA3, GPIO1_IO12,
ECSPI1_SCLK, ECSPI1_MOSI, ECSPI1_MISO,
ECSPI1_SS0
SD/MMC
USB
SD3_CLK, SD3_CMD, SD3_DAT0, SD3_DAT1,
SD3_DAT2, SD3_DAT3, SD3_DAT4, SD3_DAT5,
SD3_DAT6, SD3_DAT7, SD3_RESET_B
1, 4, or 8 bit
—
USB-OTG
PHY
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Package information and contact assignments
6 Package information and contact assignments
This section includes the contact assignment information and mechanical package drawing.
6.1
12 x 12 mm package information
6.1.1
Case 1997-01, 12 x 12, 0.4 mm pitch, ball matrix
The following figure shows the top, bottom, and side views of the 12×12 mm BGA package.
Figure 87. 12 x 12 mm BGA, Case x Package Top, Bottom, and Side Views
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Package information and contact assignments
6.1.2
12 x 12 mm supplies contact assignments and functional contact
assignments
Table 98 shows supplies contact assignments for the 12 x 12 mm package.
Table 98. i.MX 7Dual 12 x 12 mm supplies contact assignments
Rail
DRAM_VREF
Ball
Comments
T20
Y18
DDR voltage reference input. Connect to a
voltage source that is 50% of NVCC_DRAM
DRAM_ZQPAD
DDR output buffer driver calibration reference
voltage input. Connect DRAM_ZQPAD to an
external 240
Ω 1% resistor to Vss
FUSE_FSOURCE
GND
V09
A01,A28,B05,B23,B26,C03,C05,C07,C10,C1
3,C14,C15,C23,C24,C25,C26,D08,
D12,D17,D21,E03,E05,E24,E26,F08,F10,F12
,F14,F15,F17,F21,H04,H06,H23,H25,L13,L16
,M04,M06,M23,M25,N11,N18,T11,T18,U04,U
06,U23,U25,V13,V16,W03,W06,AA04,AA06,
AA23,AA25,AC08,AC10,AC12,AC14,AC15,A
C17,AC21,AD03,AD05,AD06,AD24,AD26,AE
06,AE07,AE08,AE09,AE17,AE21,AF03,AF05,
AF08,AF09,AF10,AF11,AF13,AF14,AF15,AF2
4,AF26,AG10,AH01,AH28
GPANAIO
AF02
B19
Test signal. Should be left unconnected.
MIPI_VREG_0P4V
NVCC_DRAM
V27,V28,W21,W23,W26,Y20,AA19,AC19,AF Supply input for the DDR I/O interface
17,AF18,AF19,AG18,AH18
NVCC_DRAM_CKE
NVCC_ENET1
NVCC_EPDC1
NVCC_EPDC2
NVCC_GPIO1
NVCC_GPIO2
NVCC_I2C
V20
J18
P20
N20
Y09
Y11
R09
L20
J13
J11
Supply input for the ENET interfaces
Supply for EPDC
Supply for EPDC
Supply for GPIO1
Supply for GPIO2
Supply for I2C
NVCC_LCD
Supply for LCD
NVCC_SAI
Supply for SAI
NVCC_SD1
Supply for SD card
Supply for SD card
Supply for SD card
Supply for SPI
NVCC_SD2
L09
N09
P09
NVCC_SD3
NVCC_SPI
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Package information and contact assignments
Table 98. i.MX 7Dual 12 x 12 mm supplies contact assignments(continued)
Ball Comments
Rail
NVCC_UART
T09
Supply for UART
PCIE_VP
AB13
Y15
G16
Supply input for the PCIe PHY
Supply input for the PCIe PHY
PCIE_VPH
PVCC_ENET_CAP
Secondary supply for ENET. Requires external
capacitor
PVCC_EPDC_LCD_CAP
PVCC_GPIO_CAP
R20
Secondary supply for EPDC, LCD. Requires
external capacitor
AB11
Secondary supply for GPIO. Requires external
capacitor
PVCC_I2C_SPI_UART_CAP W08
Secondary supply for I2C, SPI, UART.
Requires external capacitor
PVCC_SAI_SD_CAP
J14
Secondary supply for SAI, SD. Requires
external capacitor
USB_OTG1_VBUS
USB_OTG2_VBUS
VDD_1P2_CAP
VDD_ARM
C09
C11
VBUS input for USB_OTG1
VBUS input for USB_OTG2
Supply for HSIC
AA10
A20,B20,C16,C17,C18,C19,C20,C21,C22,F1 Supply voltage for ARM
9,H19,J20,K21,K23,K26,L27,L28
VDD_LPSR_1P0_CAP
AG06
Secondary supply for LPSR. Requires external
capacitor
VDD_LPSR_IN
AG05
J16
Supply to LPSR
Supply for MIPI
VDD_MIPI_1P0
VDD_SNVS_1P8_CAP
AG07
Secondary supply for SNVS. Requires external
capacitor
VDD_SNVS_IN
VDD_SOC
Y13
Supply for SNVS
H10,J09,K03,K06,K08,L01,L02,L11,L18,N13, Supply for SOC
N16,P03,P06,P23,P26,R26,T13,T16,V11,V18
,R03,R06,R23
VDD_TEMPSENSOR_1P8
VDD_USB_H_1P2
AH05
Supply for temp sensor
C12,G13
Supply input for the USB HSIC interface
VDD_USB_OTG1_1P0_CAP E09
Secondary supply for OTG1. Requires external
capacitor
VDD_USB_OTG1_3P3_IN
D09
Secondary supply for OTG1. Requires external
capacitor
VDD_USB_OTG2_1P0_CAP F09
Secondary supply for OTG2. Requires external
capacitor
VDD_USB_OTG2_3P3_IN
D11
Secondary supply for OTG2. Requires external
capacitor
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Package information and contact assignments
Table 98. i.MX 7Dual 12 x 12 mm supplies contact assignments(continued)
Rail
Ball
Comments
VDD_XTAL_1P8
VDDA_1P0_CAP
AH02
AH07
Secondary supply for 1.0V. Requires external
capacitor
VDDA_1P8_IN
AF04,AG03,AG04
Supply for 1.8V
Supply for ADC
Supply for MIPI
VDDA_ADC1_1P8
VDDA_MIPI_1P8
VDDA_PHY_1P8
VDDD_1P0_CAP
AH04
J15
Y14
AC13,AE12,AF12
Secondary supply for 1.0V. Requires external
capacitor
Table 99 shows an alpha-sorted list of functional contact assignments for the 12 x 12 mm package.
Table 99. i.MX 7Dual 12 x 12 mm functional contact assignments
Default
Mode1
Default
Ball
Ball Name
Power Group
Ball type1
PD/PU
Function1
AB07
AC07
AD07
AD09
Y01
ADC1_IN0
ADC1_IN1
ADC1_VDDA_1P8
ADC1_VDDA_1P8
ADC1_VDDA_1P8
ADC1_VDDA_1P8
NVCC_GPIO1
NVCC_GPIO1
VDDA_1P8
ADC1_IN0
ADC1_IN1
ADC1_IN2
ADC1_IN2
ADC1_IN3
ADC1_IN3
BOOT_MODE0
BOOT_MODE1
CCM_CLK1_N
CCM_CLK1_P
CCM_CLK2
GPIO
GPIO
ALT0
ALT0
BOOT_MODE0
BOOT_MODE1
CCM_CLK1_N
CCM_CLK1_P
CCM_CLK2
100K PD
100K PD
Y02
AE04
AE03
AE02
AC24
AC25
AC26
AB25
AB24
AE23
AF23
AE22
AD22
AC22
VDDA_1P8
VDDA_1P8
DRAM_ADDR00
DRAM_ADDR01
DRAM_ADDR02
DRAM_ADDR03
DRAM_ADDR04
DRAM_ADDR05
DRAM_ADDR06
DRAM_ADDR07
DRAM_ADDR08
DRAM_ADDR09
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DRAM_ADDR00
DRAM_ADDR01
DRAM_ADDR02
DRAM_ADDR03
DRAM_ADDR04
DRAM_ADDR05
DRAM_ADDR06
DRAM_ADDR07
DRAM_ADDR08
DRAM_ADDR09
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Package information and contact assignments
Table 99. i.MX 7Dual 12 x 12 mm functional contact assignments(continued)
Default
Mode1
Default
Ball
Ball Name
Power Group
Ball type1
PD/PU
Function1
AD23
AG27
AE27
AG28
AE20
AG26
AG25
AE26
AC23
AH22
AG19
AG20
AF22
AF20
AG22
AF21
AH20
AC18
AB18
AD16
AC16
AD18
AE18
AB16
AE16
W27
DRAM_ADDR10
DRAM_ADDR11
DRAM_ADDR12
DRAM_ADDR13
DRAM_ADDR14
DRAM_ADDR15
DRAM_CAS_B
DRAM_CS0_B
DRAM_CS1_B
DRAM_DATA00
DRAM_DATA01
DRAM_DATA02
DRAM_DATA03
DRAM_DATA04
DRAM_DATA05
DRAM_DATA06
DRAM_DATA07
DRAM_DATA08
DRAM_DATA09
DRAM_DATA10
DRAM_DATA11
DRAM_DATA12
DRAM_DATA13
DRAM_DATA14
DRAM_DATA15
DRAM_DATA16
DRAM_DATA17
DRAM_DATA18
DRAM_DATA19
DRAM_DATA20
DRAM_DATA21
DRAM_DATA22
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DRAM_ADDR10
DRAM_ADDR11
DRAM_ADDR12
DRAM_ADDR13
DRAM_ADDR14
DRAM_ADDR15
DRAM_CAS_B
DRAM_CS0_B
DRAM_CS1_B
DRAM_DATA00
DRAM_DATA01
DRAM_DATA02
DRAM_DATA03
DRAM_DATA04
DRAM_DATA05
DRAM_DATA06
DRAM_DATA07
DRAM_DATA08
DRAM_DATA09
DRAM_DATA10
DRAM_DATA11
DRAM_DATA12
DRAM_DATA13
DRAM_DATA14
DRAM_DATA15
DRAM_DATA16
DRAM_DATA17
DRAM_DATA18
DRAM_DATA19
DRAM_DATA20
DRAM_DATA21
DRAM_DATA22
Y27
Y26
Y28
AA26
AB26
AB27
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Table 99. i.MX 7Dual 12 x 12 mm functional contact assignments(continued)
Default
Mode1
Default
Ball
Ball Name
Power Group
Ball type1
PD/PU
Function1
AB28
V23
DRAM_DATA23
DRAM_DATA24
DRAM_DATA25
DRAM_DATA26
DRAM_DATA27
DRAM_DATA28
DRAM_DATA29
DRAM_DATA30
DRAM_DATA31
DRAM_DQM0
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM_CKE
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM_CKE
NVCC_DRAM_CKE
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
DDR
DDR
DRAM_DATA23
DRAM_DATA24
DRAM_DATA25
DRAM_DATA26
DRAM_DATA27
DRAM_DATA28
DRAM_DATA29
DRAM_DATA30
DRAM_DATA31
DRAM_DQM0
V22
DDR
T23
DDR
T22
DDR
V24
DDR
V25
DDR
T25
DDR
T24
DDR
AH24
AD20
AD28
Y25
DDR
DRAM_DQM1
DDR
DRAM_DQM1
DRAM_DQM2
DDR
DRAM_DQM2
DRAM_DQM3
DDR
DRAM_DQM3
AF16
AH25
V26
DRAM_ODT0
DDR
DRAM_ODT0
DRAM_RAS_B
DRAM_RESET
DRAM_SDBA0
DRAM_SDBA1
DRAM_SDBA2
DRAM_SDCKE0
DRAM_SDCKE1
DRAM_SDCLK0_N
DRAM_SDCLK0_P
DRAM_SDQS0_N
DRAM_SDQS0_P
DRAM_SDQS1_N
DRAM_SDQS1_P
DRAM_SDQS2_N
DRAM_SDQS2_P
DRAM_SDQS3_N
DRAM_SDQS3_P
DRAM_SDWE_B
DDR
DRAM_RAS_B
DRAM_RESET
DRAM_SDBA0
DRAM_SDBA1
DRAM_SDBA2
DRAM_SDCKE0
DRAM_SDCKE1
DRAM_SDCLK0_N
DRAM_SDCLK0_P
DRAM_SDQS0_N
DRAM_SDQS0_P
DRAM_SDQS1_N
DRAM_SDQS1_P
DRAM_SDQS2_N
DRAM_SDQS2_P
DRAM_SDQS3_N
DRAM_SDQS3_P
DRAM_SDWE_B
DDR
AE28
AB22
AF27
Y22
DDR
DDR
DDR
DDR
AB23
AF25
AE25
AG23
AG24
AC20
AB20
AD27
AC27
Y24
DDR
DDRCLK
DDRCLK
DDRCLK
DDRCLK
DDRCLK
DDRCLK
DDRCLK
DDRCLK
DDRCLK
DDRCLK
DDR
Y23
AH27
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127
Package information and contact assignments
Table 99. i.MX 7Dual 12 x 12 mm functional contact assignments(continued)
Default
Mode1
Default
Ball
Ball Name
Power Group
Ball type1
PD/PU
Function1
M03
L03
K02
N03
P02
N02
N01
R02
G18
F18
F07
E07
D07
D16
C06
E11
F11
E13
D13
E16
F16
F13
G11
G09
L23
L22
T27
U26
T26
R27
N23
T28
ECSPI1_MISO
ECSPI1_MOSI
ECSPI1_SCLK
ECSPI1_SS0
ECSPI2_MISO
ECSPI2_MOSI
ECSPI2_SCLK
ECSPI2_SS0
ENET1_COL
ENET1_CRS
ENET1_RD0
ENET1_RD1
ENET1_RD2
ENET1_RD3
ENET1_RX_CLK
ENET1_RX_CTL
ENET1_RXC
ENET1_TD0
ENET1_TD1
ENET1_TD2
ENET1_TD3
ENET1_TX_CLK
ENET1_TX_CTL
ENET1_TXC
EPDC_BDR0
EPDC_BDR1
EPDC_D00
NVCC_SPI
NVCC_SPI
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
GPIO4_IO[18]
GPIO4_IO[17]
GPIO4_IO[16]
GPIO4_IO[19]
GPIO4_IO[22]
GPIO4_IO[21]
GPIO4_IO[20]
GPIO4_IO[23]
GPIO7_IO[15]
GPIO7_IO[14]
GPIO7_IO[0]
GPIO7_IO[1]
GPIO_IO[2]
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
NVCC_SPI
NVCC_SPI
NVCC_SPI
NVCC_SPI
NVCC_SPI
NVCC_SPI
NVCC_ENET1
NVCC_ENET1
NVCC_ENET1
NVCC_ENET1
NVCC_ENET1
NVCC_ENET1
NVCC_ENET1
NVCC_ENET1
NVCC_ENET1
NVCC_ENET1
NVCC_ENET1
NVCC_ENET1
NVCC_ENET1
NVCC_ENET1
NVCC_ENET1
NVCC_ENET1
NVCC_EPDC2
NVCC_EPDC2
NVCC_EPDC1
NVCC_EPDC1
NVCC_EPDC1
NVCC_EPDC1
NVCC_EPDC1
NVCC_EPDC1
GPIO7_IO[3]
GPIO7_IO[13]
GPIO7_IO[4]
GPIO7_IO[5]
GPIO7_IO[6]
GPIO_IO[7]
GPIO7_IO[8]
GPIO7_IO[9]
GPIO7_IO[12]
GPIO7_IO[10]
GPIO7_IO[11]
GPIO2_IO[28]
GPIO2_IO[29]
GPIO2_IO[0]
GPIO2_IO[1]
GPIO2_IO[2]
GPIO2_IO[3]
GPIO2_IO[4]
GPIO2_IO[5]
EPDC_D01
EPDC_D02
EPDC_D03
EPDC_D04
EPDC_D05
i.MX 7Dual Family of Applications Processors Datasheet, Rev. 5, 07/2017
128
NXP Semiconductors
Package information and contact assignments
Table 99. i.MX 7Dual 12 x 12 mm functional contact assignments(continued)
Default
Mode1
Default
Ball
Ball Name
Power Group
Ball type1
PD/PU
Function1
P27
N28
N27
N26
N25
N24
M26
L26
L25
N22
J23
EPDC_D06
EPDC_D07
NVCC_EPDC1
NVCC_EPDC1
NVCC_EPDC1
NVCC_EPDC1
NVCC_EPDC1
NVCC_EPDC1
NVCC_EPDC1
NVCC_EPDC1
NVCC_EPDC1
NVCC_EPDC1
NVCC_EPDC2
NVCC_EPDC2
NVCC_EPDC2
NVCC_EPDC2
NVCC_EPDC2
NVCC_EPDC2
NVCC_EPDC2
NVCC_EPDC2
NVCC_EPDC2
NVCC_EPDC2
NVCC_EPDC2
NVCC_EPDC2
NVCC_EPDC2
NVCC_EPDC2
VDDA_1P8
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
GPIO2_IO[6]
GPIO2_IO[7]
GPIO2_IO[8]
GPIO2_IO[9]
GPIO2_IO[10]
GPIO2_IO[11]
GPIO2_IO[12]
GPIO2_IO[13]
GPIO2_IO[14]
GPIO2_IO[15]
GPIO2_IO[24]
GPIO2_IO[25]
GPIO2_IO[26]
GPIO2_IO[27]
GPIO2_IO[30]
GPIO2_IO[31]
GPIO2_IO[20]
GPIO2_IO[21]
GPIO2_IO[22]
GPIO2_IO[23]
GPIO2_IO[16]
GPIO2_IO[17]
GPIO2_IO[18]
GPIO2_IO[19]
GPANAIO
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
EPDC_D08
EPDC_D09
EPDC_D10
EPDC_D11
EPDC_D12
EPDC_D13
EPDC_D14
EPDC_D15
EPDC_GDCLK
EPDC_GDOE
EPDC_GDRL
EPDC_GDSP
EPDC_PWRCOM
EPDC_PWRSTAT
EPDC_SDCE0
EPDC_SDCE1
EPDC_SDCE2
EPDC_SDCE3
EPDC_SDCLK
EPDC_SDLE
EPDC_SDOE
EPDC_SDSHR
GPANAIO
J22
L24
K27
J27
J26
J25
J24
G22
G23
G24
J28
G25
F26
AF02
V04
V05
Y07
Y06
Y05
Y04
V06
GPIO1_IO00
GPIO1_IO01
GPIO1_IO02
GPIO1_IO03
GPIO1_IO04
GPIO1_IO05
GPIO1_IO06
NVCC_GPIO1
NVCC_GPIO1
NVCC_GPIO1
NVCC_GPIO1
NVCC_GPIO1
NVCC_GPIO1
NVCC_GPIO1
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
GPIO1_IO00
GPIO1_IO01
GPIO1_IO02
GPIO1_IO03
GPIO1_IO04
GPIO1_IO05
GPIO1_IO06
100K PU
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
i.MX 7Dual Family of Applications Processors Datasheet, Rev. 5, 07/2017
NXP Semiconductors
129
Package information and contact assignments
Table 99. i.MX 7Dual 12 x 12 mm functional contact assignments(continued)
Default
Mode1
Default
Ball
Ball Name
Power Group
Ball type1
PD/PU
Function1
V07
AB03
AB04
AB05
AB06
AC06
AC05
AC04
AC03
N04
GPIO1_IO07
GPIO1_IO08
GPIO1_IO09
GPIO1_IO10
GPIO1_IO11
GPIO1_IO12
GPIO1_IO13
GPIO1_IO14
GPIO1_IO15
I2C1_SCL
NVCC_GPIO1
NVCC_GPIO2
NVCC_GPIO2
NVCC_GPIO2
NVCC_GPIO2
NVCC_GPIO2
NVCC_GPIO2
NVCC_GPIO2
NVCC_GPIO2
NVCC_I2C
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
GPIO1_IO07
GPIO1_IO08
GPIO1_IO09
GPIO1_IO10
GPIO1_IO11
GPIO1_IO12
GPIO1_IO13
GPIO1_IO14
GPIO1_IO15
GPIO4_IO[8]
GPIO4_IO[9]
GPIO4_IO[10]
GPIO4_IO[11]
GPIO4_IO[12]
GPIO4_IO[13]
GPIO4_IO[14]
GPIO4_IO[15]
JTAG_MOD
JTAG_TCK
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PU
47K PU
N05
I2C1_SDA
NVCC_I2C
N06
I2C2_SCL
NVCC_I2C
N07
I2C2_SDA
NVCC_I2C
T06
I2C3_SCL
NVCC_I2C
T07
I2C3_SDA
NVCC_I2C
T05
I2C4_SCL
NVCC_I2C
T04
I2C4_SDA
NVCC_I2C
AB01
AD01
AC02
AE01
AD02
AB02
D20
JTAG_MOD
JTAG_TCK
JTAG_TDI
NVCC_GPIO2
NVCC_GPIO2
NVCC_GPIO2
NVCC_GPIO2
NVCC_GPIO2
NVCC_GPIO2
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
JTAG_TDI
47K PU
JTAG_TDO
JTAG_TMS
JTAG_TRST_B
LCD_CLK
JTAG_TDO
100K PU
47K PU
JTAG_TMS
JTAG_TRST_B
GPIO3_IO[0]
GPIO3_IO[5]
GPIO3_IO[6]
GPIO3_IO[7]
GPIO3_IO[8]
GPIO3_IO[9]
GPIO3_IO[10]
GPIO3_IO[11]
GPIO3_IO[12]
47K PU
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
F22
LCD_DATA00
LCD_DATA01
LCD_DATA02
LCD_DATA03
LCD_DATA04
LCD_DATA05
LCD_DATA06
LCD_DATA07
F23
E23
E22
D22
D23
E18
D18
i.MX 7Dual Family of Applications Processors Datasheet, Rev. 5, 07/2017
130
NXP Semiconductors
Package information and contact assignments
Table 99. i.MX 7Dual 12 x 12 mm functional contact assignments(continued)
Default
Mode1
Default
Ball
Ball Name
Power Group
Ball type1
PD/PU
Function1
F20
G20
A27
E27
F27
E28
G27
B28
C27
D26
D27
D28
G26
H26
B27
D25
G28
F25
E20
F24
B16
A16
B18
A18
B15
B14
B24
A24
B25
A25
A22
B22
LCD_DATA08
LCD_DATA09
LCD_DATA10
LCD_DATA11
NVCC_LCD
NVCC_LCD
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
GPIO3_IO[13]
GPIO3_IO[14]
GPIO3_IO[15]
GPIO3_IO[16]
GPIO3_IO[17]
GPIO3_IO[18]
GPIO3_IO[19]
GPIO3_IO[20]
GPIO3_IO[21]
GPIO3_IO[22]
GPIO3_IO[23]
GPIO3_IO[24]
GPIO3_IO[25]
GPIO3_IO[26]
GPIO3_IO[27]
GPIO3_IO[28]
GPIO3_IO[1]
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
NVCC_LCD
NVCC_LCD
LCD_DATA12
LCD_DATA13
LCD_DATA14
LCD_DATA15
LCD_DATA16
LCD_DATA17
LCD_DATA18
LCD_DATA19
LCD_DATA20
LCD_DATA21
LCD_DATA22
LCD_DATA23
LCD_ENABLE
LCD_HSYNC
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
GPIO3_IO[2]
LCD_RESET
NVCC_LCD
GPIO3_IO[4]
LCD_VSYNC
NVCC_LCD
GPIO3_IO[3]
MIPI_CSI_CLK_N
MIPI_CSI_CLK_P
MIPI_CSI_D0_N
MIPI_CSI_D0_P
MIPI_CSI_D1_N
MIPI_CSI_D1_P
MIPI_DSI_CLK_N
MIPI_DSI_CLK_P
MIPI_DSI_D0_N
MIPI_DSI_D0_P
MIPI_DSI_D1_N
MIPI_DSI_D1_P
MIPI_VDDA_1P8
MIPI_VDDA_1P8
MIPI_VDDA_1P8
MIPI_VDDA_1P8
MIPI_VDDA_1P8
MIPI_VDDA_1P8
MIPI_VDDA_1P8
MIPI_VDDA_1P8
MIPI_VDDA_1P8
MIPI_VDDA_1P8
MIPI_VDDA_1P8
MIPI_VDDA_1P8
MIPI_CSI_CLK_N
MIPI_CSI_CLK_P
MIPI_CSI_D0_N
MIPI_CSI_D0_P
MIPI_CSI_D1_N
MIPI_CSI_D1_P
MIPI_DSI_CLK_N
MIPI_DSI_CLK_P
MIPI_DSI_D0_N
MIPI_DSI_D0_P
MIPI_DSI_D1_N
MIPI_DSI_D1_P
i.MX 7Dual Family of Applications Processors Datasheet, Rev. 5, 07/2017
NXP Semiconductors
131
Package information and contact assignments
Table 99. i.MX 7Dual 12 x 12 mm functional contact assignments(continued)
Default
Mode1
Default
Ball
Ball Name
Power Group
Ball type1
PD/PU
Function1
AD13
AG13
AH13
AG11
AH11
Y16
ONOFF
PCIE_REFCLKIN_N
PCIE_REFCLKIN_P
PCIE_REFCLKOUT_N
PCIE_REFCLKOUT_P
PCIE_REXT
VDD_SNVS_IN
PCIE_VPH
ONOFF
PCIE_REFCLKIN_N
PCIE_REFCLKIN_P
PCIE_REFCLKOUT_N
PCIE_REFCLKOUT_P
PCIE_REXT
PCIE_VPH
PCIE_VPH
PCIE_VPH
PCIE_VPH
AG16
AH16
AG14
AG15
PCIE_RX_N
PCIE_VPH_RX
PCIE_VPH_RX
PCIE_VPH_TX
PCIE_VPH_TX
VDD_SNVS_IN
NVCC_GPIO1
VDD_SNVS_1P8_CAP
VDD_SNVS_1P8_CAP
NVCC_SAI
PCIE_RX_N
PCIE_RX_P
PCIE_RX_P
PCIE_TX_N
PCIE_TX_N
PCIE_TX_P
PCIE_TX_P
AD11 CCM_PMIC_STBY_REQ
GPIO
GPIO
CCM_PMIC_STBY_REQ
POR_B
Y03
AG09
AH09
D03
G04
F03
C04
F04
G05
F05
E06
D04
D06
F06
A05
B03
A02
B04
A04
B02
B01
POR_B
ALT0
100K PU
RTC_XTALI
RTC_XTALO
SAI1_MCLK
SAI1_RXC
SAI1_RXD
SAI1_RXFS
SAI1_TXC
SAI1_TXD
SAI1_TXFS
SAI2_RXD
SAI2_TXC
SAI2_TXD
SAI2_TXFS
SD1_CD_B
SD1_CLK
RTC_XTALI
RTC_XTALO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
GPIO6_IO[18]
GPIO6_IO[17]
GPIO6_IO[12]
GPIO6_IO[16]
GPIO6_IO[13]
GPIO6_IO[15]
GPIO6_IO[14]
GPIO6_IO[21]
GPIO6_IO[20]
GPIO6_IO[22]
GPIO6_IO[19]
GPIO5_IO[0]
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
NVCC_SAI
NVCC_SAI
NVCC_SAI
NVCC_SAI
NVCC_SAI
NVCC_SAI
NVCC_SAI
NVCC_SAI
NVCC_SAI
NVCC_SAI
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
GPIO5_IO[3]
SD1_CMD
SD1_DATA0
SD1_DATA1
SD1_DATA2
SD1_DATA3
GPIO5_IO[4]
GPIO5_IO[5]
GPIO5_IO[6]
GPIO5_IO[7]
GPIO5_IO[8]
i.MX 7Dual Family of Applications Processors Datasheet, Rev. 5, 07/2017
132
NXP Semiconductors
Package information and contact assignments
Table 99. i.MX 7Dual 12 x 12 mm functional contact assignments(continued)
Default
Mode1
Default
Ball
Ball Name
Power Group
Ball type1
PD/PU
Function1
C02
D02
E01
G01
G02
F02
E02
H03
G03
J03
SD1_RESET_B
SD1_WP
NVCC_SD1
NVCC_SD1
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
GPIO5_IO[2]
GPIO5_IO[1]
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
SD2_CD_B
NVCC_SD2
GPIO5_IO[9]
SD2_CLK
NVCC_SD2
GPIO5_IO[12]
GPIO5_IO[13]
GPIO5_IO[14]
GPIO5_IO[15]
GPIO5_IO[16]
GPIO5_IO[17]
GPIO5_IO[11]
GPIO5_IO[10]
GPIO6_IO[0]
SD2_CMD
NVCC_SD2
SD2_DATA0
SD2_DATA1
SD2_DATA2
SD2_DATA3
SD2_RESET_B
SD2_WP
NVCC_SD2
NVCC_SD2
NVCC_SD2
NVCC_SD2
NVCC_SD2
D01
J06
NVCC_SD2
SD3_CLK
NVCC_SD3
L04
SD3_CMD
NVCC_SD3
GPIO6_IO[1]
G06
G07
L07
SD3_DATA0
SD3_DATA1
SD3_DATA2
SD3_DATA3
SD3_DATA4
SD3_DATA5
SD3_DATA6
SD3_DATA7
SD3_RESET_B
SD3_STROBE
SNVS_PMIC_ON_REQ
SNVS_TAMPER0
SNVS_TAMPER1
SNVS_TAMPER2
SNVS_TAMPER9
NVCC_SD3
GPIO6_IO[2]
NVCC_SD3
GPIO6_IO[3]
NVCC_SD3
GPIO6_IO[4]
L06
NVCC_SD3
GPIO6_IO[5]
L05
NVCC_SD3
GPIO6_IO[6]
J07
NVCC_SD3
GPIO6_IO[7]
J05
NVCC_SD3
GPIO6_IO[8]
J04
NVCC_SD3
GPIO6_IO[9]
J02
NVCC_SD3
GPIO6_IO[11]
GPIO6_IO[10]
SNVS_PMIC_ON_REQ
SNVS_TAMPER0
SNVS_TAMPER1
SNVS_TAMPER2
SNVS_TAMPER9
J01
NVCC_SD3
AE13
AE11
AC11
AC09
AB09
VDD_SNVS_IN
VDDD_SNVS_1P8_CAP
VDD_SNVS_1P8_CAP
VDDD_SNVS_1P8_CAP
VDD_SNVS_1P8_CAP
Analog
Analog
Analog
Analog
AF06 TEMPSENSOR_RESERVE VDD_TEMPSENSOR_1P8
AF07
AA03
T01
TEMPSENSOR_REXT
TEST_MODE
VDD_TEMPSENSOR_1P8
NVCC_GPIO1
TEMPSENSOR_REXT
TEST_MODE
GPIO
GPIO
ALT0
ALT5
100K PD
100K PD
UART1_RXD
NVCC_UART
GPIO4_IO[0]
i.MX 7Dual Family of Applications Processors Datasheet, Rev. 5, 07/2017
NXP Semiconductors
133
Package information and contact assignments
Table 99. i.MX 7Dual 12 x 12 mm functional contact assignments(continued)
Default
Mode1
Default
Ball
Ball Name
Power Group
Ball type1
PD/PU
Function1
V01
T02
T03
V03
W02
V02
U03
A13
B13
B06
B07
A07
B09
C08
B11
UART1_TXD
UART2_RXD
NVCC_UART
NVCC_UART
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
GPIO4_IO[1]
GPIO4_IO[2]
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
UART2_TXD
NVCC_UART
GPIO4_IO[3]
UART3_CTS
NVCC_UART
GPIO4_IO[7]
UART3_RTS
NVCC_UART
GPIO4_IO[6]
UART3_RXD
NVCC_UART
GPIO4_IO[4]
UART3_TXD
NVCC_UART
GPIO4_IO[5]
USB_H_DATA
USB_H_STROBE
USB_OTG1_CHD_B
USB_OTG1_DN
USB_OTG1_DP
USB_OTG1_ID
USB_OTG1_REXT
USB_OTG2_DN
USB_OTG2_DP
USB_OTG2_ID
USB_OTG2_REXT
XTALI
USB_H_VDD_1P2
USB_H_VDD_1P2
USB_OTG1_VDDA_3P3
USB_OTG1_VDDA_3P3
USB_OTG1_VDDA_3P3
USB_OTG1_VDDA_3P3
USB_OTG1_VDDA_3P3
USB_OTG2_VDDA_3P3
USB_OTG2_VDDA_3P3
USB_OTG2_VDDA_3P3
USB_OTG2_VDDA_3P3
VDDA_1P8
USB_H_DATA
USB_H_STROBE
USB_OTG1_CHD_B
USB_OTG1_DN
USB_OTG1_DP
USB_OTG1_ID
USB_OTG1_REXT
USB_OTG2_DN
USB_OTG2_DP
USB_OTG2_ID
USB_OTG2_REXT
XTALI
A11
B10
A09
AG02
AG01
XTALO
VDDA_1P8
XTALO
1
The state immediately after RESET and before ROM firmware or software has executed.
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134
NXP Semiconductors
Package information and contact assignments
6.1.3
i.MX 7Dual 12 x 12 mm 0.4 mm Pitch Ball Map
The following table shows the i.MX 7Dual 12 x 12 mm 0.4 mm pitch ball map.
Table 100. i.MX 7Dual 12 x 12 mm 0.4 mm pitch ball map
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
A
B
C
A
B
C
D
D
E
E
F
F
G
G
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
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135
Package information and contact assignments
Table 100. i.MX 7Dual 12 x 12 mm 0.4 mm pitch ball map(continued)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
H
H
J
J
K
L
K
L
M
N
P
M
N
P
R
R
T
T
U
U
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
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136
NXP Semiconductors
Package information and contact assignments
Table 100. i.MX 7Dual 12 x 12 mm 0.4 mm pitch ball map(continued)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
V
V
W
W
Y
Y
AA
AA
AB
AC
AD
AB
AC
AD
AE
AE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
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NXP Semiconductors
137
Package information and contact assignments
Table 100. i.MX 7Dual 12 x 12 mm 0.4 mm pitch ball map(continued)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
AF
AF
AG
AG
AH
AH
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
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138
NXP Semiconductors
Package information and contact assignments
6.2
19 x 19 mm package information
6.2.1
Case “Y”, 19 x 19 mm, 0.75 mm pitch, ball matrix
Figure 88 shows the top, bottom, and side views of the 19×19 mm BGA package.
Figure 88. 19 x 19 mm BGA, Case x Package Top, Bottom, and Side Views
i.MX 7Dual Family of Applications Processors Datasheet, Rev. 5, 07/2017
NXP Semiconductors
139
Package information and contact assignments
6.2.2
19 x 19 mm supplies contact assignments and functional contact
assignments
Table 101 shows supplies contact assignments for the 19 x 19 mm package.
Table 101. i.MX 7Dual 19 x 19 mm supplies contact assignments
Rail
Pins
Comments
ADC2_VDDA_1P8
DRAM_VREF
AB03
AC13
AB13
DRAM_ZQPAD
DDR output buffer driver calibration reference
voltage input. Connect DRAM_ZQPAD to an
external 240
Ω 1% resistor to Vss
FUSE_FSOURCE0
GND
V08
A01,A03,A06,A09,A13,A17,A21,A25,B03,B06 Ground
,B09,B13,B17,B21,C09,C13,C15,C16,C18,C1
9,D01,D02,D04,D07,D10,D22,F07,F08,F11,F
13,G07,G04,G09,G11,G13,G15,G17,G19,G2
2,H01,H02,J07,J19,K04,K10,K12,K14,K16,K2
2,L07,L11,L13,L15,L19,M10,M12,M14,M16,M
24,M25,N04,N07,N11,N13,N15,N19,P10,P12,
P14,P16,R07,R11,R13,R15,R19,R20,R21,R2
3,T04,T10,T12,T14,T16,T20,U07,U11,U19,U2
0,U23,V20,W01,W02,W04,W07,W09,W11,W1
3,W15,W17,W19,W20,W23,Y06,Y13,Y14,Y15
,Y16,Y17,Y18,Y19,AA01,AA02,AA06,AA08,A
A15,AA23,AB04,AB05,AB07,AB09,AB12,AC0
6,AC09,AC12,AC15,AC17,AC19,AC21,AC23,
AD02,AD07,AD09,AD12,AE01,AE05,AE07,A
E09,AE12,AE24,AE25, AD05
GPANIO
V04
H18
Test signal. Should be left unconnected.
MIPI_VREG_0P4V
NVCC_DRAM
T21,U21,V21,W21,Y21,AA16,AA17,AA18,AA
19,AA20,AA21
NVCC_DRAM_CKE
NVCC_ENET1
NVCC_EPDC1
NVCC_EPDC2
NVCC_GPIO1
NVCC_GPIO2
NVCC_I2C
Y20
H16
M18
L17
P08
T08
M08
K18
F12
E07
Supply for ENET interface
Supply for EPDC interface
Supply for EPDC interface
Supply for GPIO1 interface
Supply for GPIO2 interface
Supply for I2C interface
Supply for LCD interface
Supply for SAI interface
Supply for SD card interface
NVCC_LCD
NVCC_SAI
NVCC_SD1
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140
NXP Semiconductors
Package information and contact assignments
Table 101. i.MX 7Dual 19 x 19 mm supplies contact assignments(continued)
Rail
Pins
Comments
NVCC_SD2
NVCC_SD3
NVCC_SPI
H08
K08
Supply for SD card interface
Supply for SD card interface
Supply for SPI interface
Supply for UART interface
Supply for PCIe' interface
Supply for PCIe PHY
L09
NVCC_UART
PCIE_VP
N09
AA10
AA12
AA11
Y10
PCIE_VP_RX
PCIE_VP_TX
PCIE_VPH
Supply for PCIe PHY
PCIE_VPH_RX
PCIE_VPH_TX
PVCC_ENET_CAP
Y12
Y11
H14
Secondary supply for ENET (internal regulator
output). Requires external capacitors
PVCC_EPDC_LCD_CAP
PVCC_GPIO_CAP
N17
V10
Secondary supply for EPDC_LCD (internal
regulator output). Requires external capacitors
Secondary supply for GPIO (internal regulator
output). Requires external capacitors
PVCC_I2C_SPI_UART_CAP R09
Secondary supply for I2C_SPI_UART (internal
regulator output). Requires external capacitors
PVCC_SAI_SD_CAP
USB_OTG1_VBUS
J09
Secondary supply for SAI_SD (internal
regulator output). Requires external capacitors
C08
USB_OTG1_VDDA_3P3_IN F10
USB_OTG2_VBUS C10
USB_OTG2_VDDA_3P3_IN F09
VDD_1P2_CAP
VDD_ARM
U09
Supply for HSIC
Supply for ARM
C17,C20,D17,D20,F22,F23,J22,J23
AC05
VDD_LPSR_1P0_CAP
Secondary supply for LPSR (internal regulator
output). Requires external capacitors
VDD_LPSR_IN
W06
Supply for LPSR
VDD_SNVS_1P8_CAP
AE08
Secondary supply for SNVS (internal regulator
output). Requires external capacitors
VDD_SNVS_IN
VDD_SOC
AD08
Primary supply for the SNVS regulator
C14,D14,F03,F04,F18,F19,J03,J04,M03,M04, Supply for SOC
P18,R03,R04,R17,T18,U13,U15,U17,V12,V1
4,V16,V18
VDD_TEMPSENSOR_1P8
AC04
Supply for VDDe PHY
i.MX 7Dual Family of Applications Processors Datasheet, Rev. 5, 07/2017
NXP Semiconductors
141
Package information and contact assignments
Table 101. i.MX 7Dual 19 x 19 mm supplies contact assignments(continued)
Rail
Pins
Comments
VDD_USB_H_1P2
H12
Supply input for the USB HSIC Interface
VDD_USB_OTG1_1P0_CAP H10
Secondary supply for USB OTG (internal
regulator output). Requires external capacitors
VDD_USB_OTG2_1P0_CAP J11
Secondary supply for USB OTG (internal
regulator output). Requires external capacitors
VDD_XTAL_1P8
VDDA_1P0_CAP
V05
V03
Secondary supply for 1P0 (internal regulator
output). Requires external capacitors
VDDA_1P8_IN
V06,W05
AC03
Y09
VDDA_ADC1_1P8
VDDA_PHY_1P8
VDDD_1P0_CAP
Supply for ADC
AA09
Secondary supply for 1P0 (internal regulator
output). Requires external capacitors
Table 102 shows an alpha-sorted list of functional contact assignments for the 19 x 19 mm package.
Table 102. i.MX 7Dual 19 x 19 mm functional contact assignments
Ball
Default
Mode1
Default
Ball
Ball Name
Power Group
PD/PU
type1
Function1
AD01
AD03
AE02
AE03
AC01
AC02
AB01
AB02
P04
ADC1_IN0
ADC1_IN1
ADC1_VDDA_1P8
ADC1_VDDA_1P8
ADC1_VDDA_1P8
ADC1_VDDA_1P8
ADC2_VDDA_1P8
ADC2_VDDA_1P8
ADC2_VDDA_1P8
ADC2_VDDA_1P8
NVCC_GPIO1
ADC1_IN0
ADC1_IN1
ADC1_IN2
ADC1_IN2
ADC1_IN3
ADC1_IN3
ADC2_IN0
ADC2_IN0
ADC2_IN1
ADC2_IN1
ADC2_IN2
ADC2_IN2
ADC2_IN3
ADC2_IN3
BOOT_MODE0
BOOT_MODE1
CCM_CLK1_N
CCM_CLK1_P
CCM_CLK2
GPIO
GPIO
ALT0
ALT0
BOOT_MODE0
BOOT_MODE1
CCM_CLK1_N
CCM_CLK1_P
CCM_CLK2
100K PD
100K PD
P05
NVCC_GPIO1
Y01
VDDA_1P8
Y02
VDDA_1P8
W03
VDDA_1P8
AC07 CCM_PMIC_STBY_REQ
VDD_SNVS_IN
NVCC_DRAM
CCM_PMIC_STBY_REQ
DRAM_ADDR00
DRAM_ADDR01
AB19
AB16
DRAM_ADDR00
DRAM_ADDR01
DDR
DDR
NVCC_DRAM
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142
NXP Semiconductors
Package information and contact assignments
Table 102. i.MX 7Dual 19 x 19 mm functional contact assignments(continued)
Ball
Default
Mode1
Default
Ball
Ball Name
Power Group
PD/PU
type1
Function1
AC18
AC20
AB21
Y23
DRAM_ADDR02
DRAM_ADDR03
DRAM_ADDR04
DRAM_ADDR05
DRAM_ADDR06
DRAM_ADDR07
DRAM_ADDR08
DRAM_ADDR09
DRAM_ADDR10
DRAM_ADDR11
DRAM_ADDR12
DRAM_ADDR13
DRAM_ADDR14
DRAM_ADDR15
DRAM_CAS_B
DRAM_CS0_B
DRAM_CS1_B
DRAM_DATA00
DRAM_DATA01
DRAM_DATA02
DRAM_DATA03
DRAM_DATA04
DRAM_DATA05
DRAM_DATA06
DRAM_DATA07
DRAM_DATA08
DRAM_DATA09
DRAM_DATA10
DRAM_DATA11
DRAM_DATA12
DRAM_DATA13
DRAM_DATA14
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DRAM_ADDR02
DRAM_ADDR03
DRAM_ADDR04
DRAM_ADDR05
DRAM_ADDR06
DRAM_ADDR07
DRAM_ADDR08
DRAM_ADDR09
DRAM_ADDR10
DRAM_ADDR11
DRAM_ADDR12
DRAM_ADDR13
DRAM_ADDR14
DRAM_ADDR15
DRAM_CAS_B
DRAM_CS0_B
DRAM_CS1_B
DRAM_DATA00
DRAM_DATA01
DRAM_DATA02
DRAM_DATA03
DRAM_DATA04
DRAM_DATA05
DRAM_DATA06
DRAM_DATA07
DRAM_DATA08
DRAM_DATA09
DRAM_DATA10
DRAM_DATA11
DRAM_DATA12
DRAM_DATA13
DRAM_DATA14
V22
Y22
W22
V23
T23
U22
T22
P23
AB18
AB20
AC14
AB23
AA22
AD22
AD23
AE20
AE23
AE22
AD19
AD18
AE19
AE14
AE18
AE17
AD16
AE16
AD14
AD13
i.MX 7Dual Family of Applications Processors Datasheet, Rev. 5, 07/2017
NXP Semiconductors
143
Package information and contact assignments
Table 102. i.MX 7Dual 19 x 19 mm functional contact assignments(continued)
Ball
Default
Mode1
Default
Ball
Ball Name
Power Group
PD/PU
type1
Function1
AE13
AA25
W24
V25
DRAM_DATA15
DRAM_DATA16
DRAM_DATA17
DRAM_DATA18
DRAM_DATA19
DRAM_DATA20
DRAM_DATA21
DRAM_DATA22
DRAM_DATA23
DRAM_DATA24
DRAM_DATA25
DRAM_DATA26
DRAM_DATA27
DRAM_DATA28
DRAM_DATA29
DRAM_DATA30
DRAM_DATA31
DRAM_DQM0
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM_CKE
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM_CKE
NVCC_DRAM_CKE
NVCC_DRAM
NVCC_DRAM
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDRCLK
DDRCLK
DRAM_DATA15
DRAM_DATA16
DRAM_DATA17
DRAM_DATA18
DRAM_DATA19
DRAM_DATA20
DRAM_DATA21
DRAM_DATA22
DRAM_DATA23
DRAM_DATA24
DRAM_DATA25
DRAM_DATA26
DRAM_DATA27
DRAM_DATA28
DRAM_DATA29
DRAM_DATA30
DRAM_DATA31
DRAM_DQM0
W25
AC25
AB25
AB24
AC24
R25
N24
P25
N25
U25
R24
U24
V24
AD20
AD17
AA24
P24
DRAM_DQM1
DRAM_DQM1
DRAM_DQM2
DRAM_DQM2
DRAM_DQM3
DRAM_DQM3
AC16
AA14
AB15
AC22
R22
DRAM_ODT0
DRAM_ODT0
DRAM_ODT1
DRAM_ODT1
DRAM_RAS_B
DRAM_RESET
DRAM_SDBA0
DRAM_SDBA1
DRAM_SDBA2
DRAM_SDCKE0
DRAM_SDCKE1
DRAM_SDCLK0_N
DRAM_SDCLK0_P
DRAM_RAS_B
DRAM_RESET
DRAM_SDBA0
DRAM_SDBA1
DRAM_SDBA2
DRAM_SDCKE0
DRAM_SDCKE1
DRAM_SDCLK0_N
DRAM_SDCLK0_P
P22
N23
AB17
AB22
AD25
AD24
i.MX 7Dual Family of Applications Processors Datasheet, Rev. 5, 07/2017
144
NXP Semiconductors
Package information and contact assignments
Table 102. i.MX 7Dual 19 x 19 mm functional contact assignments(continued)
Ball
Default
Mode1
Default
Ball
Ball Name
Power Group
PD/PU
type1
Function1
AD21
AE21
AE15
AD15
Y25
Y24
T25
DRAM_SDQS0_N
DRAM_SDQS0_P
DRAM_SDQS1_N
DRAM_SDQS1_P
DRAM_SDQS2_N
DRAM_SDQS2_P
DRAM_SDQS3_N
DRAM_SDQS3_P
DRAM_SDWE_B
ECSPI1_MISO
ECSPI1_MOSI
ECSPI1_SCLK
ECSPI1_SS0
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_SPI
DDRCLK
DDRCLK
DDRCLK
DDRCLK
DDRCLK
DDRCLK
DDRCLK
DDRCLK
DDR
DRAM_SDQS0_N
DRAM_SDQS0_P
DRAM_SDQS1_N
DRAM_SDQS1_P
DRAM_SDQS2_N
DRAM_SDQS2_P
DRAM_SDQS3_N
DRAM_SDQS3_P
DRAM_SDWE_B
GPIO4_IO[18]
GPIO4_IO[17]
GPIO4_IO[16]
GPIO4_IO[19]
GPIO4_IO[22]
GPIO4_IO[21]
GPIO4_IO[20]
GPIO4_IO[23]
GPIO7_IO[15]
GPIO7_IO[14]
GPIO7_IO[0]
T24
AB14
H04
G05
H03
H05
H06
G06
J05
GPIO
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
NVCC_SPI
GPIO
NVCC_SPI
GPIO
NVCC_SPI
GPIO
ECSPI2_MISO
ECSPI2_MOSI
ECSPI2_SCLK
ECSPI2_SS0
NVCC_SPI
GPIO
NVCC_SPI
GPIO
NVCC_SPI
GPIO
J06
NVCC_SPI
GPIO
D19
E19
E14
F14
ENET1_COL
NVCC_ENET1
NVCC_ENET1
NVCC_ENET1
NVCC_ENET1
NVCC_ENET1
NVCC_ENET1
NVCC_ENET1
NVCC_ENET1
NVCC_ENET1
NVCC_ENET1
NVCC_ENET1
NVCC_ENET1
NVCC_ENET1
NVCC_ENET1
NVCC_ENET1
GPIO
ENET1_CRS
GPIO
ENET1_RD0
GPIO
ENET1_RD1
GPIO
GPIO7_IO[1]
D13
E13
D15
E15
F15
ENET1_RD2
GPIO
GPIO_IO[2]
ENET1_RD3
GPIO
GPIO7_IO[3]
ENET1_RX_CLK
ENET1_RX_CTL
ENET1_RXC
GPIO
GPIO7_IO[13]
GPIO7_IO[4]
GPIO
GPIO
GPIO7_IO[5]
F17
ENET1_TD0
GPIO
GPIO7_IO[6]
E17
E18
D18
D16
E16
ENET1_TD1
GPIO
GPIO_IO[7]
ENET1_TD2
GPIO
GPIO7_IO[8]
ENET1_TD3
GPIO
GPIO7_IO[9]
ENET1_TX_CLK
ENET1_TX_CTL
GPIO
GPIO7_IO[12]
GPIO7_IO[10]
GPIO
i.MX 7Dual Family of Applications Processors Datasheet, Rev. 5, 07/2017
NXP Semiconductors
145
Package information and contact assignments
Table 102. i.MX 7Dual 19 x 19 mm functional contact assignments(continued)
Ball
Default
Mode1
Default
Ball
Ball Name
Power Group
PD/PU
type1
Function1
F16
K24
K23
P20
P21
N20
N21
N22
M20
M21
M22
M23
L25
L24
L23
L22
L21
L20
K25
J25
ENET1_TXC
EPDC_BDR0
EPDC_BDR1
EPDC_D00
NVCC_ENET1
NVCC_EPDC2
NVCC_EPDC2
NVCC_EPDC1
NVCC_EPDC1
NVCC_EPDC1
NVCC_EPDC1
NVCC_EPDC1
NVCC_EPDC1
NVCC_EPDC1
NVCC_EPDC1
NVCC_EPDC1
NVCC_EPDC1
NVCC_EPDC1
NVCC_EPDC1
NVCC_EPDC1
NVCC_EPDC1
NVCC_EPDC1
NVCC_EPDC1
NVCC_EPDC2
NVCC_EPDC2
NVCC_EPDC2
NVCC_EPDC2
NVCC_EPDC2
NVCC_EPDC2
NVCC_EPDC2
NVCC_EPDC2
NVCC_EPDC2
NVCC_EPDC2
NVCC_EPDC2
NVCC_EPDC2
NVCC_EPDC2
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
GPIO7_IO[11]
GPIO2_IO[28]
GPIO2_IO[29]
GPIO2_IO[0]
GPIO2_IO[1]
GPIO2_IO[2]
GPIO2_IO[3]
GPIO2_IO[4]
GPIO2_IO[5]
GPIO2_IO[6]
GPIO2_IO[7]
GPIO2_IO[8]
GPIO2_IO[9]
GPIO2_IO[10]
GPIO2_IO[11]
GPIO2_IO[12]
GPIO2_IO[13]
GPIO2_IO[14]
GPIO2_IO[15]
GPIO2_IO[24]
GPIO2_IO[25]
GPIO2_IO[26]
GPIO2_IO[27]
GPIO2_IO[30]
GPIO2_IO[31]
GPIO2_IO[20]
GPIO2_IO[21]
GPIO2_IO[22]
GPIO2_IO[23]
GPIO2_IO[16]
GPIO2_IO[17]
GPIO2_IO[18]
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
EPDC_D01
EPDC_D02
EPDC_D03
EPDC_D04
EPDC_D05
EPDC_D06
EPDC_D07
EPDC_D08
EPDC_D09
EPDC_D10
EPDC_D11
EPDC_D12
EPDC_D13
EPDC_D14
EPDC_D15
EPDC_GDCLK
EPDC_GDOE
EPDC_GDRL
EPDC_GDSP
EPDC_PWRCOM
EPDC_PWRSTAT
EPDC_SDCE0
EPDC_SDCE1
EPDC_SDCE2
EPDC_SDCE3
EPDC_SDCLK
EPDC_SDLE
EPDC_SDOE
J24
K21
H25
H24
K20
G25
G24
H23
H22
J21
J20
H21
i.MX 7Dual Family of Applications Processors Datasheet, Rev. 5, 07/2017
146
NXP Semiconductors
Package information and contact assignments
Table 102. i.MX 7Dual 19 x 19 mm functional contact assignments(continued)
Ball
Default
Mode1
Default
Ball
Ball Name
Power Group
PD/PU
type1
Function1
H20
N01
N02
N03
N05
N06
P01
P02
P03
R01
R02
R05
T01
T02
T03
T05
T06
J02
EPDC_SDSHR
GPIO1_IO00
GPIO1_IO01
GPIO1_IO02
GPIO1_IO03
GPIO1_IO04
GPIO1_IO05
GPIO1_IO06
GPIO1_IO07
GPIO1_IO08
GPIO1_IO09
GPIO1_IO10
GPIO1_IO11
GPIO1_IO12
GPIO1_IO13
GPIO1_IO14
GPIO1_IO15
I2C1_SCL
NVCC_EPDC2
NVCC_GPIO1
NVCC_GPIO1
NVCC_GPIO1
NVCC_GPIO1
NVCC_GPIO1
NVCC_GPIO1
NVCC_GPIO1
NVCC_GPIO1
NVCC_GPIO2
NVCC_GPIO2
NVCC_GPIO2
NVCC_GPIO2
NVCC_GPIO2
NVCC_GPIO2
NVCC_GPIO2
NVCC_GPIO2
NVCC_I2C
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT5
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT5
GPIO2_IO[19]
GPIO1_IO00
GPIO1_IO01
GPIO1_IO02
GPIO1_IO03
GPIO1_IO04
GPIO1_IO05
GPIO1_IO06
GPIO1_IO07
GPIO1_IO08
GPIO1_IO09
GPIO1_IO10
GPIO1_IO11
GPIO1_IO12
GPIO1_IO13
GPIO1_IO14
GPIO1_IO15
GPIO4_IO[8]
GPIO4_IO[9]
GPIO4_IO[10]
GPIO4_IO[11]
GPIO4_IO[12]
GPIO4_IO[13]
GPIO4_IO[14]
GPIO4_IO[15]
JTAG_MOD
JTAG_TCK
100K PD
100K PU
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PU
47K PU
K01
K02
K03
K05
K06
L01
L02
U01
U05
U03
U06
U04
U02
E20
I2C1_SDA
NVCC_I2C
I2C2_SCL
NVCC_I2C
I2C2_SDA
NVCC_I2C
I2C3_SCL
NVCC_I2C
I2C3_SDA
NVCC_I2C
I2C4_SCL
NVCC_I2C
I2C4_SDA
NVCC_I2C
JTAG_MOD
JTAG_TCK
JTAG_TDI
NVCC_GPIO2
NVCC_GPIO2
NVCC_GPIO2
NVCC_GPIO2
NVCC_GPIO2
NVCC_GPIO2
NVCC_LCD
JTAG_TDI
47K PU
JTAG_TDO
JTAG_TMS
JTAG_TRST_B
LCD_CLK
JTAG_TDO
100K PU
47K PU
JTAG_TMS
JTAG_TRST_B
GPIO3_IO[0]
47K PU
100K PD
i.MX 7Dual Family of Applications Processors Datasheet, Rev. 5, 07/2017
NXP Semiconductors
147
Package information and contact assignments
Table 102. i.MX 7Dual 19 x 19 mm functional contact assignments(continued)
Ball
Default
Mode1
Default
Ball
Ball Name
Power Group
PD/PU
type1
Function1
D21
A22
B22
A23
C22
B23
A24
F20
E21
C23
B24
G20
F21
E22
D23
C24
B25
G21
E23
D24
C25
E24
D25
G23
F25
E25
C21
F24
A15
B15
A16
B16
LCD_DATA00
LCD_DATA01
LCD_DATA02
LCD_DATA03
LCD_DATA04
LCD_DATA05
LCD_DATA06
LCD_DATA07
LCD_DATA08
LCD_DATA09
LCD_DATA10
LCD_DATA11
LCD_DATA12
LCD_DATA13
LCD_DATA14
LCD_DATA15
LCD_DATA16
LCD_DATA17
LCD_DATA18
LCD_DATA19
LCD_DATA20
LCD_DATA21
LCD_DATA22
LCD_DATA23
LCD_ENABLE
LCD_HSYNC
LCD_RESET
LCD_VSYNC
MIPI_CSI_CLK_N
MIPI_CSI_CLK_P
MIPI_CSI_D0_N
MIPI_CSI_D0_P
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
MIPI_VDDA_1P8
MIPI_VDDA_1P8
MIPI_VDDA_1P8
MIPI_VDDA_1P8
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
GPIO3_IO[5]
GPIO3_IO[6]
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
GPIO3_IO[7]
GPIO3_IO[8]
GPIO3_IO[9]
GPIO3_IO[10]
GPIO3_IO[11]
GPIO3_IO[12]
GPIO3_IO[13]
GPIO3_IO[14]
GPIO3_IO[15]
GPIO3_IO[16]
GPIO3_IO[17]
GPIO3_IO[18]
GPIO3_IO[19]
GPIO3_IO[20]
GPIO3_IO[21]
GPIO3_IO[22]
GPIO3_IO[23]
GPIO3_IO[24]
GPIO3_IO[25]
GPIO3_IO[26]
GPIO3_IO[27]
GPIO3_IO[28]
GPIO3_IO[1]
GPIO3_IO[2]
GPIO3_IO[4]
GPIO3_IO[3]
MIPI_CSI_CLK_N
MIPI_CSI_CLK_P
MIPI_CSI_D0_N
MIPI_CSI_D0_P
i.MX 7Dual Family of Applications Processors Datasheet, Rev. 5, 07/2017
148
NXP Semiconductors
Package information and contact assignments
Table 102. i.MX 7Dual 19 x 19 mm functional contact assignments(continued)
Ball
Default
Mode1
Default
Ball
Ball Name
Power Group
PD/PU
type1
Function1
A14
B14
MIPI_CSI_D1_N
MIPI_CSI_D1_P
MIPI_DSI_CLK_N
MIPI_DSI_CLK_P
MIPI_DSI_D0_N
MIPI_DSI_D0_P
MIPI_DSI_D1_N
MIPI_DSI_D1_P
MIPI_VDDA_1P8
MIPI_VDDD_1P0
MIPI_VDDD_1P0
ONOFF
MIPI_VDDA_1P8
MIPI_VDDA_1P8
MIPI_VDDA_1P8
MIPI_VDDA_1P8
MIPI_VDDA_1P8
MIPI_VDDA_1P8
MIPI_VDDA_1P8
MIPI_VDDA_1P8
MIPI_VDDA_1P8
MIPI_VDDD_1P0
MIPI_VDDD_1P0
VDD_SNVS_IN
PCIE_VPH
MIPI_CSI_D1_N
MIPI_CSI_D1_P
MIPI_DSI_CLK_N
MIPI_DSI_CLK_P
MIPI_DSI_D0_N
MIPI_DSI_D0_P
MIPI_DSI_D1_N
MIPI_DSI_D1_P
MIPI_VDDA_1P8
MIPI_VDDD_1P0
MIPI_VDDD_1P0
ONOFF
A19
B19
A20
B20
A18
B18
J13
J15
J17
AC08
AE10
AD10
AC10
AB10
AA13
AE11
AD11
AC11
AB11
AA10
AA12
AA11
Y10
PCIE_REFCLKIN_N
PCIE_REFCLKIN_P
PCIE_REFCLKOUT_N
PCIE_REFCLKOUT_P
PCIE_REXT
PCIE_REFCLKIN_N
PCIE_REFCLKIN_P
PCIE_REFCLKOUT_N
PCIE_REFCLKOUT_P
PCIE_REXT
PCIE_VPH
PCIE_VPH
PCIE_VPH
PCIE_VPH
PCIE_RX_N
PCIE_VPH_RX
PCIE_VPH_RX
PCIE_VPH_TX
PCIE_VPH_TX
PCIE_VP
PCIE_RX_N
PCIE_RX_P
PCIE_RX_P
PCIE_TX_N
PCIE_TX_N
PCIE_TX_P
PCIE_TX_P
PCIE_VP
PCIE_VP
PCIE_VP_RX
PCIE_VP_TX
PCIE_VP_RX
PCIE_VP_RX
PCIE_VP_TX
PCIE_VP_TX
PCIE_VPH
PCIE_VPH
PCIE_VPH
Y12
PCIE_VPH_RX
PCIE_VPH_TX
POR_B
PCIE_VPH_RX
PCIE_VPH_TX
NVCC_GPIO1
VDD_SNVS_1P8_CAP
VDD_SNVS_1P8_CAP
NVCC_SAI
PCIE_VPH_RX
PCIE_VPH_TX
POR_B
Y11
R06
GPIO
ALT0
100K PU
AE06
AD06
E10
RTC_XTALI
RTC_XTALI
RTC_XTALO
RTC_XTALO
SAI1_MCLK
GPIO
GPIO
ALT5
ALT5
GPIO6_IO[18]
GPIO6_IO[17]
100K PD
100K PD
D12
SAI1_RXC
NVCC_SAI
i.MX 7Dual Family of Applications Processors Datasheet, Rev. 5, 07/2017
NXP Semiconductors
149
Package information and contact assignments
Table 102. i.MX 7Dual 19 x 19 mm functional contact assignments(continued)
Ball
Default
Mode1
Default
Ball
Ball Name
Power Group
PD/PU
type1
Function1
E12
C12
C11
E11
D11
E09
D08
E08
D09
C06
B05
C05
A05
D06
A04
D05
B04
C04
D03
E03
F06
E04
E05
F05
E06
G03
C03
C01
E01
B02
A02
G02
SAI1_RXD
SAI1_RXFS
SAI1_TXC
NVCC_SAI
NVCC_SAI
NVCC_SAI
NVCC_SAI
NVCC_SAI
NVCC_SAI
NVCC_SAI
NVCC_SAI
NVCC_SAI
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD2
NVCC_SD2
NVCC_SD2
NVCC_SD2
NVCC_SD2
NVCC_SD2
NVCC_SD2
NVCC_SD2
NVCC_SD2
NVCC_SD3
NVCC_SD3
NVCC_SD3
NVCC_SD3
NVCC_SD3
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
GPIO6_IO[12]
GPIO6_IO[16]
GPIO6_IO[13]
GPIO6_IO[15]
GPIO6_IO[14]
GPIO6_IO[21]
GPIO6_IO[20]
GPIO6_IO[22]
GPIO6_IO[19]
GPIO5_IO[0]
GPIO5_IO[3]
GPIO5_IO[4]
GPIO5_IO[5]
GPIO5_IO[6]
GPIO5_IO[7]
GPIO5_IO[8]
GPIO5_IO[2]
GPIO5_IO[1]
GPIO5_IO[9]
GPIO5_IO[12]
GPIO5_IO[13]
GPIO5_IO[14]
GPIO5_IO[15]
GPIO5_IO[16]
GPIO5_IO[17]
GPIO5_IO[11]
GPIO5_IO[10]
GPIO6_IO[0]
GPIO6_IO[1]
GPIO6_IO[2]
GPIO6_IO[3]
GPIO6_IO[4]
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
SAI1_TXD
SAI1_TXFS
SAI2_RXD
SAI2_TXC
SAI2_TXD
SAI2_TXFS
SD1_CD_B
SD1_CLK
SD1_CMD
SD1_DATA0
SD1_DATA1
SD1_DATA2
SD1_DATA3
SD1_RESET_B
SD1_WP
SD2_CD_B
SD2_CLK
SD2_CMD
SD2_DATA0
SD2_DATA1
SD2_DATA2
SD2_DATA3
SD2_RESET_B
SD2_WP
SD3_CLK
SD3_CMD
SD3_DATA0
SD3_DATA1
SD3_DATA2
i.MX 7Dual Family of Applications Processors Datasheet, Rev. 5, 07/2017
150
NXP Semiconductors
Package information and contact assignments
Table 102. i.MX 7Dual 19 x 19 mm functional contact assignments(continued)
Ball
Default
Mode1
Default
Ball
Ball Name
Power Group
PD/PU
type1
Function1
F01
F02
SD3_DATA3
SD3_DATA4
NVCC_SD3
NVCC_SD3
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
GPIO6_IO[5]
GPIO6_IO[6]
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
E02
SD3_DATA5
NVCC_SD3
GPIO6_IO[7]
C02
SD3_DATA6
NVCC_SD3
GPIO6_IO[8]
B01
SD3_DATA7
NVCC_SD3
GPIO6_IO[9]
G01
J01
SD3_RESET_B
SD3_STROBE
NVCC_SD3
GPIO6_IO[11]
NVCC_SD3
GPIO6_IO[10]
AB08
AA07
Y08
SNVS_PMIC_ON_REQ
SNVS_TAMPER0
SNVS_TAMPER1
SNVS_TAMPER2
SNVS_TAMPER3
SNVS_TAMPER4
SNVS_TAMPER5
SNVS_TAMPER6
SNVS_TAMPER7
SNVS_TAMPER8
SNVS_TAMPER9
TEMPSENSOR_REXT
VDD_SNVS_IN
SNVS_PMIC_ON_REQ
SNVS_TAMPER0
SNVS_TAMPER1
SNVS_TAMPER2
SNVS_TAMPER3
SNVS_TAMPER4
SNVS_TAMPER5
SNVS_TAMPER6
SNVS_TAMPER7
SNVS_TAMPER8
SNVS_TAMPER9
TEMPSENSOR_REXT
TEMPSENSOR_RESERVE
TEST_MODE
VDDD_SNVS_1P8_CAP
VDD_SNVS_1P8_CAP
VDDD_SNVS_1P8_CAP
VDD_SNVS_1P8_CAP
VDDD_SNVS_1P8_CAP
VDD_SNVS_1P8_CAP
VDDD_SNVS_1P8_CAP
VDD_SNVS_1P8_CAP
VDDD_SNVS_1P8_CAP
VDD_SNVS_1P8_CAP
VDD_TEMPSENSOR_1P8
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
AB06
Y07
AA05
Y05
AA04
Y04
AA03
Y03
AE04
AD04 TEMPSENSOR_RESERVE VDD_TEMPSENSOR_1P8
P06
L03
L04
L05
L06
M06
M05
M01
M02
A12
B12
C07
TEST_MODE
UART1_RXD
UART1_TXD
NVCC_GPIO1
NVCC_UART
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT0
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
100K PD
GPIO4_IO[0]
NVCC_UART
GPIO4_IO[1]
UART2_RXD
UART2_TXD
NVCC_UART
GPIO4_IO[2]
NVCC_UART
GPIO4_IO[3]
UART3_CTS
NVCC_UART
GPIO4_IO[7]
UART3_RTS
NVCC_UART
GPIO4_IO[6]
UART3_RXD
UART3_TXD
NVCC_UART
GPIO4_IO[4]
NVCC_UART
GPIO4_IO[5]
USB_H_DATA
USB_H_STROBE
USB_OTG1_CHD_B
USB_H_VDD_1P2
USB_H_VDD_1P2
USB_OTG1_VDDA_3P3
USB_H_DATA
USB_H_STROBE
USB_OTG1_CHD_B
i.MX 7Dual Family of Applications Processors Datasheet, Rev. 5, 07/2017
NXP Semiconductors
151
Package information and contact assignments
Table 102. i.MX 7Dual 19 x 19 mm functional contact assignments(continued)
Ball
Default
Mode1
Default
Ball
Ball Name
Power Group
PD/PU
type1
Function1
A08
B08
B07
A07
A10
B10
B11
A11
V01
V02
USB_OTG1_DN
USB_OTG1_DP
USB_OTG1_ID
USB_OTG1_REXT
USB_OTG2_DN
USB_OTG2_DP
USB_OTG2_ID
USB_OTG2_REXT
XTALI
USB_OTG1_VDDA_3P3
USB_OTG1_VDDA_3P3
USB_OTG1_VDDA_3P3
USB_OTG1_VDDA_3P3
USB_OTG2_VDDA_3P3
USB_OTG2_VDDA_3P3
USB_OTG2_VDDA_3P3
USB_OTG2_VDDA_3P3
VDDA_1P8
USB_OTG1_DN
USB_OTG1_DP
USB_OTG1_ID
USB_OTG1_REXT
USB_OTG2_DN
USB_OTG2_DP
USB_OTG2_ID
USB_OTG2_REXT
XTALI
XTALO
VDDA_1P8
XTALO
1
The state immediately after RESET and before ROM firmware or software has executed.
6.2.3
Case “Y”, i.MX 7Dual 19 × 19 mm 0.75 mm pitch ball map
The following table shows the i.MX 7Dual 19 × 19 mm, 0.75 mm pitch ball map.
Table 103. i.MX 7Dual 19 × 19 mm 0.75 mm pitch ball map
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
A
A
B
B
C
C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
i.MX 7Dual Family of Applications Processors Datasheet, Rev. 5, 07/2017
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Package information and contact assignments
Table 103. i.MX 7Dual 19 × 19 mm 0.75 mm pitch ball map (continued)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
D
D
E
E
F
F
G
G
H
H
J
J
K
K
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
i.MX 7Dual Family of Applications Processors Datasheet, Rev. 5, 07/2017
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153
Package information and contact assignments
Table 103. i.MX 7Dual 19 × 19 mm 0.75 mm pitch ball map (continued)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
L
L
M
M
N
N
P
P
R
R
T
T
U
U
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
i.MX 7Dual Family of Applications Processors Datasheet, Rev. 5, 07/2017
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Package information and contact assignments
Table 103. i.MX 7Dual 19 × 19 mm 0.75 mm pitch ball map (continued)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
V
V
W
W
Y
Y
AA
AA
AB
AB
AC
AC
AD
AD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
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155
Package information and contact assignments
Table 103. i.MX 7Dual 19 × 19 mm 0.75 mm pitch ball map (continued)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
AE
AE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
i.MX 7Dual Family of Applications Processors Datasheet, Rev. 5, 07/2017
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NXP Semiconductors
Revision history
7 Revision history
Table 104 provides a revision history for this data sheet.
Table 104. Revision history
Substantive Change(s)
Rev.
Number
Date
Rev. 5
7/2017 • Throughout: Updated document to reflect change from silicon revision 1.2 to silicon revision 1.3,
including:
• Updates to part numbers on page 1 and in Table 1, “Orderable parts.”
• Updates to Figure 1, “Part number nomenclature—i.MX 7Dual family of processors”
• In Table 3, “Special signal considerations,” updated remarks related to
PCIE_VPH/PCIE_VPH_TX/PCIE_VPH_RX and PCIE_VP/PCIE_VP_TX/PCIE_VP_RX
• Updated Table 19, “PCIe recommended operating conditions”
• Updated Table 20, “PCIe DC electrical characteristics”
• Updated Section 4.2.1.5, “LDO_SVNS_1P8”
• Updated Table 99, “i.MX 7Dual 12 x 12 mm functional contact assignments”
• Updated Table 101, “i.MX 7Dual 19 x 19 mm supplies contact assignments”
i.MX 7Dual Family of Applications Processors Datasheet, Rev. 5, 07/2017
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157
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