MCIMX6L2EVN10AC [NXP]
i.MX 6SoloLite;Document Number: IMX6SLCEC
Rev. 5, 10/2017
NXP Semiconductors
Data Sheet: Technical Data
MCIMX6LxDVN10xx
MCIMX6LxEVN10xx
i.MX 6SoloLite
Applications Processors
for Consumer Products
Package Information
Plastic Package
13 x 13 mm, 0.5 mm pitch
Ordering Information
See Table 1 on page 3
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Updated Signal Naming Convention . . . . . . . . . . . . 7
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Special Signal Considerations. . . . . . . . . . . . . . . . 15
3.2 Recommended Connections for Unused Analog
Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . . 17
4.2 Power Supplies Requirements and Restrictions . . 26
4.3 Integrated LDO Voltage Regulator Parameters. . . 27
4.4 PLL’s Electrical Characteristics . . . . . . . . . . . . . . . 29
4.5 On-Chip Oscillators . . . . . . . . . . . . . . . . . . . . . . . . 30
4.6 I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 31
4.7 I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 35
4.8 Output Buffer Impedance Parameters. . . . . . . . . . 38
4.9 System Modules Timing . . . . . . . . . . . . . . . . . . . . 40
4.10 External Peripheral Interface Parameters . . . . . . . 52
Boot Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . 80
5.1 Boot Mode Configuration Pins. . . . . . . . . . . . . . . . 80
5.2 Boot Devices Interfaces Allocation . . . . . . . . . . . . 81
Package Information and Contact Assignments . . . . . . . 82
6.1 Updated Signal Naming Convention . . . . . . . . . . . 82
6.2 13 x 13mm Package Information. . . . . . . . . . . . . . 83
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
1 Introduction
The i.MX 6SoloLite processor represents the latest
achievement in integrated multimedia applications
processors, which are part of a growing family of
multimedia-focused products that offer high
performance processing and are optimized for lowest
power consumption.
2
3
4
The processor features NXP’s advanced implementation
®
®
of the a single ARM Cortex -A9 MPCore™ multicore
processor, which operates at speeds up to 1 GHz. It
includes 2D graphics processor and integrated power
management. The processor provides a 32-bit
DDR3-800 memory interface and a number of other
interfaces for connecting peripherals, such as WLAN,
Bluetooth™, GPS, hard drive, displays, and camera
sensors.
5
6
7
The i.MX 6SoloLite processor is specifically useful for
applications, such as:
•
•
•
Color and monochrome eReaders
Entry level tablets
Barcode scanners
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Introduction
The i.MX 6SoloLite processor features:
•
•
•
Applications processor—The processor enhances the capabilities of high-tier portable applications
by fulfilling the ever increasing MIPS requirements of operating systems and games. The Dynamic
Voltage and Frequency Scaling (DVFS) provides significant power reduction, allowing the device
to run at lower voltage and frequency with sufficient MIPS for tasks, such as audio decode.
Multilevel memory system—The multilevel memory system of each processor is based on the L1
instruction and data caches, L2 cache, and internal and external memory. The processor supports
many types of external memory devices, including DDR3, LPDDR2, NOR Flash, PSRAM,
cellular RAM, and managed NAND, including eMMC up to rev 4.4/4.41.
Smart speed technology—The processor has power management throughout the IC that enables the
rich suite of multimedia features and peripherals to consume minimum power in both active and
various low power modes. Smart speed technology enables the designer to deliver a feature-rich
product, requiring levels of power far lower than industry expectations.
•
•
Dynamic voltage and frequency scaling—The processor improves the power efficiency of devices
by scaling the voltage and frequency to optimize performance.
Multimedia powerhouse—The multimedia performance of each processor is enhanced by a
multilevel cache system, NEON™ MPE (Media Processor Engine) co-processor, and a
programmable smart DMA (SDMA) controller.
•
•
Powerful graphics acceleration—Each processor provides three independent, integrated graphics
processing units: 2D BLit engine, a 2D graphics accelerator, and dedicated OpenVG™ 1.1
accelerator.
Interface flexibility—The processor supports connections to a variety of interfaces: LCD
controller, CMOS sensor interface (parallel), high-speed USB on-the-go with PHY, high-speed
USB host PHY, multiple expansion card ports (high-speed MMC/SDIO host and other),
2
10/100 Mbps Ethernet controller, and a variety of other popular interfaces (such as UART, I C, and
2
I S serial audio).
•
•
Electronic Paper Display Controller—The processor integrates EPD controller that supports E Ink
color and monochrome with up to 2048 x 1536 resolution at 106 Hz refresh, 4096 x 4096 resolution
at 20 Hz refresh and 5-bit grayscale (32-levels per color channel).
Advanced security—The processor delivers hardware-enabled security features that enable secure
e-commerce, digital rights management (DRM), information encryption, secure boot, and secure
software downloads. The security features are discussed in detail in the i.MX 6SoloLite security
reference manual (IMX6SLSRM). Contact your local NXP representative for more information.
•
•
Integrated power management—The processor integrates linear regulators and generate internally
all the voltage levels for different domains. This significantly simplifies system power
management structure.
GPIO with interrupt capabilities—The new GPIO pad design supports configurable dual voltage
rails at 1.8 V and 3.3 V supplies. The pad is configurable to interface at either voltage level.
1.1
Ordering Information
Table 1 provides examples of orderable part numbers covered by this data sheet. Table 1 does not include
all possible orderable part numbers. The latest part numbers are available on nxp.com/imx6series. If your
i.MX 6SoloLite Applications Processors for Consumer Products, Data Sheet, Rev. 5, 10/2017
2
NXP Semiconductors
Introduction
desired part number is not listed in Table 1, or you have questions about available parts, see
nxp.com/imx6series or contact your NXP representative.
Table 1. Example Orderable Part Numbers
Speed
Temperature
(Tj)
Part Number
Options
Package2
Grade1
MCIMX6L8DVN10AB
MCIMX6L8DVN10AC
MCIMX6L7DVN10AB
MCIMX6L7DVN10AC
MCIMX6L3DVN10AB
MCIMX6L3DVN10AC
MCIMX6L3EVN10AB
MCIMX6L3EVN10AC
MCIMX6L2DVN10AB
MCIMX6L2DVN10AC
MCIMX6L2EVN10AB
MCIMX6L2EVN10AC
GPU, EPDC
GPU, EPDC
1GHz
1GHz
1GHz
1GHz
1GHz
1GHz
1GHz
1GHz
1GHz
1GHz
1GHz
1GHz
0°C to +95°C
0°C to +95°C
0°C to +95°C
0°C to +95°C
0°C to +95°C
0°C to +95°C
-40°C to +105°C
-40°C to +105°C
0°C to +95°C
0°C to +95°C
-40°C to +105°C
-40°C to +105°C
13x13mm, 0.5mm pitch BGA
13x13mm, 0.5mm pitch BGA
13x13mm, 0.5mm pitch BGA
13x13mm, 0.5mm pitch BGA
13x13mm, 0.5mm pitch BGA
13x13mm, 0.5mm pitch BGA
13x13mm, 0.5mm pitch BGA
13x13mm, 0.5mm pitch BGA
13x13mm, 0.5mm pitch BGA
13x13mm, 0.5mm pitch BGA
13x13mm, 0.5mm pitch BGA
13x13mm, 0.5mm pitch BGA
EPDC, no GPU
EPDC, no GPU
GPU, no EPDC
GPU, no EPDC
GPU, no EPDC
GPU, no EPDC
no GPU, no EPDC
no GPU, no EPDC
no GPU, no EPDC
no GPU, no EPDC
1
If a 24 MHz input clock is used (required for USB), the maximum SoC speed is limited to 996 MHz.
Case 2240 is RoHS compliant, lead-free moisture sensitivity level 3 (MSL).
2
Figure 1 describes the part number nomenclature so that users can identify the characteristics of the
specific part number they have (for example, Cores, Frequency, Temperature Grade, Fuse options, Silicon
revision).
i.MX 6SoloLite Applications Processors for Consumer Products, Data Sheet, Rev. 5, 10/2017
NXP Semiconductors
3
Introduction
MC
IMX6
X
@
+
VV
$$
%
A
Silicon revision1
A
Qualification level
Prototype samples
Mass production
Special
MC
Rev 1.0
A
PC
MC
SC
Rev 1.2
Rev 1.3
B2
C
Rev 1.4
Fusing
%
Part # series
X
Supports E-INK EPDC if EPD
enabled
A
i.MX 6SoloLite
L
Part differentiator
GPU, EPD
@
8
Frequency
$$
1 GHz
10
No GPU, EPD
GPU, no EPD
7
Package type
RoHS
3
MAPBGA 13x13 0.5mm
VN
No GPU, no EPD
2
Temperature Tj
+
Commercial: 0 to + 95°C
D
E
Extended commercial: -40 to + 105°C
1. See the nxp.com\imx6series Web page for latest information on the available silicon revision.
2. Rev 1.2 (USB_ANALOG_DIGPROG register = 0x0062_0002)
Rev 1.3 (USB_ANALOG_DIGPROG register = 0x0062_0003)
Figure 1. Part Number Nomenclature—i.MX 6SoloLite
1.2
Features
The i.MX 6SoloLite processor is based on ARM Cortex-A9 MPCore multicore processor, which has the
following features:
•
•
ARM Cortex-A9 MPCore CPU processor (with TrustZone)
The core configuration is symmetric, where each core includes:
— 32 KByte L1 Instruction Cache
— 32 KByte L1 Data Cache
— Private Timer and Watchdog
— Cortex-A9 NEON MPE (Media Processing Engine) co-processor
The ARM Cortex-A9 MPCore complex includes:
•
•
•
•
•
•
General Interrupt Controller (GIC) with 128 interrupt support
Global Timer
Snoop Control Unit (SCU)
256 KB unified I/D L2 cache
Two Master AXI (64-bit) bus interfaces output of L2 cache
Frequency of the core (including NEON and L1 cache) as per Table 9, "Operating Ranges," on
page 21
i.MX 6SoloLite Applications Processors for Consumer Products, Data Sheet, Rev. 5, 10/2017
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NXP Semiconductors
Introduction
•
NEON MPE coprocessor
— SIMD Media Processing Architecture
— NEON register file with 32x64-bit general-purpose registers
— NEON Integer execute pipeline (ALU, Shift, MAC)
— NEON dual, single-precision floating point execute pipeline (FADD, FMUL)
— NEON load/store and permute pipeline
The SoC-level memory system consists of the following additional components:
— Boot ROM, including HAB (96 KB)
— Internal multimedia / shared, fast access RAM (OCRAM, 128 KB)
•
External memory interfaces:
— 16-bit, and 32-bit DDR3-800, and LPDDR2-800 channels
— 16/32-bit NOR Flash.
— 16/32-bit PSRAM, Cellular RAM (32 bits or less)
Each i.MX 6SoloLite processor enables the following interfaces to external devices (some of them are
muxed and not available simultaneously):
•
Displays—Total of three interfaces are available.
— LCD, 24-bit display port, up to 225 Mpixels/sec (for example, WUXGA at 60 Hz)
— EPDC, color, and monochrome E Ink, up to 1650 x 2332 resolution and 5-bit grayscale
Camera sensors:
•
•
— Parallel Camera port (up to 16-bit and up to 66 MHz peak)
Expansion cards:
— Four MMC/SD/SDIO card ports all supporting:
– 1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to UHS-I SDR-104
mode (104 MB/s max)
– 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 52 MHz in both SDR
and DDR modes (104 MB/s max)
– 4-bit or 8-bit transfer mode specifications for eMMC chips up to 200 MHz in HS200 mode
(200 MB/s max)
•
•
USB:
— Two High Speed (HS) USB 2.0 OTG (Up to 480 Mbps), with integrated HS USB Phy
— One USB 2.0 (480 Mbps) hosts:
– One HS hosts with integrated HS-IC USB (High Speed Inter-Chip USB) Phy
Miscellaneous IPs and interfaces:
— SSI block—capable of supporting audio sample frequencies up to 192 kHz stereo inputs and
2
outputs with I S mode
— Five UARTs, up to 5.0 Mbps each:
– Providing RS232 interface
– Supporting 9-bit RS485 multidrop mode
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NXP Semiconductors
5
Introduction
– One of the five UARTs (UART1) supports 8-wire while others four supports 4-wire. This is
due to the SoC IOMUX limitation, since all UART IPs are identical.
— Four eCSPI (Enhanced CSPI)
2
— Three I C, supporting 400 kbps
— Ethernet Controller, 10/100 Mbps
— Four Pulse Width Modulators (PWM)
— System JTAG Controller (SJC)
— GPIO with interrupt capabilities
— 8x8 Key Pad Port (KPP)
— Sony Philips Digital Interface (SPDIF), Rx and Tx
— Two Watchdog timers (WDOG)
— Audio MUX (AUDMUX)
The i.MX 6SoloLite processor integrates advanced power management unit and controllers:
•
•
•
•
•
•
Provide PMU, including LDO supplies, for on-chip resources
Use Temperature Sensor for monitoring the die temperature
Support DVFS techniques for low power modes
Use Software State Retention and Power Gating for ARM and MPE
Support various levels of system power modes
Use flexible clock gating control scheme
The i.MX 6SoloLite processor uses dedicated hardware accelerators to meet the targeted multimedia
performance. The use of hardware accelerators is a key factor in obtaining high performance at low power
consumption numbers, while having the CPU core relatively free for performing other tasks.
The i.MX 6SoloLite processor incorporates the following hardware accelerators:
•
•
•
GPU2Dv2—2D Graphics Processing Unit (BitBlt).
GPUVG—OpenVG 1.1 Graphics Processing Unit.
PXP—PiXel Processing Pipeline. Off loading key pixel processing operations are required to
support the EPD display applications.
Security functions are enabled and accelerated by the following hardware:
•
ARM TrustZone including the TZ architecture (separation of interrupts, memory mapping, and so
on.)
•
SJC—System JTAG Controller. Protecting JTAG from debug port attacks by regulating or
blocking the access to the system debug features.
•
•
SNVS—Secure Non-Volatile Storage, including Secure Real Time Clock.
CSU—Central Security Unit. Enhancement for the IC Identification Module (IIM). Will be
configured during boot and by eFUSEs and will determine the security level operation mode as
well as the TZ policy.
•
A-HAB—Advanced High Assurance Boot—HABv4 with the new embedded enhancements:
SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization.
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NXP Semiconductors
Introduction
NOTE
The actual feature set depends on the part numbers as described in Table 1,
"Example Orderable Part Numbers," on page 3. Functions, such as 2D
hardware graphics acceleration or E Ink may not be enabled for specific part
numbers.
1.3
Updated Signal Naming Convention
The signal names of the i.MX6 series of products have been standardized to better align the signal names
within the family and across the documentation. Some of the benefits of these changes are as follows:
•
•
•
•
The names are unique within the scope of an SoC and within the series of products
Searches will return all occurrences of the named signal
The names are consistent between i.MX 6 series products implementing the same modules
The module instance is incorporated into the signal name
This change applies only to signal names. The original ball names have been preserved to prevent the need
to change schematics, BSDL models, IBIS models, and so on.
Throughout this document, the updated signal names are used except where referenced as a ball name
(such as the Functional Contact Assignments table, Ball Map table, and so on). A master list of the signal
name changes is in the document, IMX 6 Series Signal Name Mapping (EB792). This list can be used to
map the signal names used in older documentation to the new standardized naming conventions.
i.MX 6SoloLite Applications Processors for Consumer Products, Data Sheet, Rev. 5, 10/2017
NXP Semiconductors
7
Architectural Overview
2 Architectural Overview
The following subsections provide an architectural overview of the i.MX 6SoloLite processor system.
2.1
Block Diagram
Figure 2 shows the functional modules in the i.MX 6SoloLite processor system.
Figure 2. i.MX 6SoloLite System Block Diagram
NOTE
The numbers in brackets indicate number of module instances. For example,
PWM (4) indicates four separate PWM peripherals.
i.MX 6SoloLite Applications Processors for Consumer Products, Data Sheet, Rev. 5, 10/2017
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NXP Semiconductors
Modules List
3 Modules List
The i.MX 6SoloLite processor contains a variety of digital and analog modules. Table 2 describes these
modules in alphabetical order.
Table 2. i.MX 6SoloLite Modules List
Block
Mnemonic
Block Name
Subsystem
Brief Description
128x8
Fuse Box
Electrical Fuse
Array
Security
Electrical Fuse Array. Enables to setup Boot Modes, Security Levels, Security
Keys, and many other system parameters.
The i.MX 6SoloLite processor consists of 2-128x8-bit fuse box accessible
through OCOTP_CTRL interface.
ARM
ARM Platform
ARM
The ARM Cortex-A9 platform consists of a Cortex-A9 core version r2p10 and
associated sub-blocks, including Level 2 Cache Controller, SCU (Snoop
Control Unit), GIC (General Interrupt Controller), private timers, Watchdog,
and CoreSight debug modules.
AUDMUX
Digital
Audio Mux
Multimedia The AUDMUX is a programmable interconnect for voice, audio, and
Peripherals synchronous data routing between host serial interfaces (for example, SSI1,
SSI2, and SSI3) and peripheral serial interfaces (audio and voice codecs).
The AUDMUX has seven ports with identical functionality and programming
models. A desired connectivity is achieved by configuring two or more
AUDMUX ports.
CCM
GPC
SRC
Clock Control Clocks, Resets, These modules are responsible for clock and reset distribution in the system,
Module,
General Power
Controller,
and Power
Control
and also for the system power management.
System Reset
Controller
CSU
Central
Security Unit
Security
The Central Security Unit (CSU) is responsible for setting comprehensive
security policy within the i.MX 6SoloLite platform. The Security Control
Registers (SCR) of the CSU are set during boot time by the HAB and are
locked to prevent further writing.
CTI-1
CTI-2
CTI-3
CTI-4
CTI-5
Cross Trigger
Interfaces
Debug / Trace Cross Trigger Interfaces allows cross-triggering based on inputs from masters
attached to CTIs. The CTI module is internal to the Cortex-A9 Core Platform.
CTM
Cross Trigger
Matrix
Debug / Trace Cross Trigger Matrix IP is used to route triggering events between CTIs. The
CTM module is internal to the Cortex-A9 Core Platform.
DAP
Debug Access System Control The DAP provides real-time access for the debugger without halting the core
Port
Peripherals to:
• System memory and peripheral registers
• All debug configuration registers
The DAP also provides debugger access to JTAG scan chains. The DAP
module is internal to the Cortex-A9 Core Platform.
DCP
Data
co-processor
Security
This module provides support for general encryption and hashing functions
typically used for security functions. Because its basic job is moving data
from memory to memory, it also incorporates a memory-copy (memcopy)
function for both debugging and as a more efficient method of copying data
between memory blocks than the DMA-based approach.
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9
Modules List
Table 2. i.MX 6SoloLite Modules List (continued)
Block
Mnemonic
Block Name
Subsystem
Brief Description
eCSPI-1
eCSPI-2
eCSPI-3
eCSPI-4
Configurable
SPI
Connectivity Full-duplex enhanced Synchronous Serial Interface. It is configurable to
Peripherals support Master/Slave modes, four chip selects to support multiple peripherals.
EIM
NOR-Flash
/PSRAM
interface
Connectivity The EIM NOR-FLASH / PSRAM provides:
Peripherals
• Support 16-bit (in muxed IO mode only) PSRAM memories (sync andasync
operating modes), at slow frequency
• Support 16-bit (in muxed IO mode only) NOR-Flash memories, at slow
frequency
• Multiple chip selects
EPDC
Electrophoretic
Display
Peripherals The EPDC is a feature-rich, low power, and high-performance direct-drive,
active matrix EPD controller. It is specifically designed to drive E Ink EPD
panels, supporting a wide variety of TFT backplanes.
Controller
EPIT-1
EPIT-2
Enhanced
Periodic
Interrupt
Timer
Timer
Each EPIT is a 32-bit “set and forget” timer that starts counting after the EPIT
Peripherals is enabled by software. It is capable of providing precise interrupts at regular
intervals with minimal processor intervention. It has a 12-bit prescaler for
division of input clock frequency to get the required time setting for the
interrupts to occur, and counter value can be programmed on the fly.
FEC
Fast Ethernet
Controller
Connectivity The Ethernet Media Access Controller (MAC) is designed to support 10 and
Peripherals 100 Mbps Ethernet/IEEE 802.3 networks. An external transceiver interface
and transceiver function are required to complete the interface to the media.
GPIO-1
GPIO-2
GPIO-3
GPIO-4
GPIO-5
General Purpose System Control Used for general purpose input/output to external ICs. Each GPIO module
I/O Modules
Peripherals supports 32 bits of I/O.
GPT
General
Purpose
Timer
Timer
Each GPT is a 32-bit “free-running” or “set and forget” mode timer with
Peripherals programmable prescaler and compare and capture register. A timer counter
value can be captured using an external event and can be configured to trigger
a capture event on either the leading or trailing edges of an input pulse. When
the timer is configured to operate in “set and forget” mode, it is capable of
providing precise interrupts at regular intervals with minimal processor
intervention. The counter has output compare logic to provide the status and
interrupt at comparison. This timer can be configured to run either on an
external clock or on an internal clock.
GPU2Dv2
Graphics
Processing
Unit-2D, ver 2
Multimedia The GPU2Dv2 provides hardware acceleration for 2D graphics algorithms,
Peripherals such as Bit BLT, stretch BLT, and many other 2D functions.
GPUVGv2 Vector Graphics
Processing
Multimedia OpenVG graphics accelerator provides OpenVG 1.1 support as well as other
Peripherals accelerations, including Real-time hardware curve tesselation of lines,
quadratic and cubic Bezier curves, 16x Line Anti-aliasing, and various Vector
Drawing functions.
Unit, ver2
I2C-1
I2C-2
I2C-3
I2C Interface
Connectivity I2C provide serial interface for external devices. Data rates of up to 400 kbps
Peripherals are supported.
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10
Modules List
Table 2. i.MX 6SoloLite Modules List (continued)
Subsystem Brief Description
Block
Mnemonic
Block Name
IOMUXC
KPP
IOMUX
Control
System Control This module enables flexible IO multiplexing. Each IO pad has default and
Peripherals several alternate functions. The alternate functions are software configurable.
Key Pad Port
LCD Interface
Connectivity KPP Supports 8 x 8 external key pad matrix. KPP features are:
Peripherals
• Open drain design
• Glitch suppression circuit design
• Multiple keys detection
• Standby key press detection
LCDIF
Multimedia The LCDIF provides display data for external LCD panels from simple text-only
Peripherals displays to WVGA, 16/18/24 bpp color TFT panels. The LCDIF supports all of
these different interfaces by providing fully programmable functionality and
sharing register space, FIFOs, and ALU resources at the same time. The
LCDIF supports RGB (DOTCLK) modes as well as system mode including
both VSYNC and WSYNC modes.
MMDC
DDR
Connectivity DDR Controller has the following features:
Controller
Peripherals
• Support 16/32-bit DDR3-800 or LPDDR2-800
• Supports up to 2 GByte DDR memory space
OCOTP_
CTRL
OTP
Controller
Security
The On-Chip OTP controller (OCOTP_CTRL) provides an interface for
reading, programming, and/or overriding identification and control information
stored in on-chip fuse elements. The module supports
electrically-programmable poly fuses (eFUSEs). The OCOTP_CTRL also
provides a set of volatile software-accessible signals that can be used for
software control of hardware elements, not requiring non-volatility. The
OCOTP_CTRL provides the primary user-visible mechanism for interfacing
with on-chip fuse elements. Among the uses for the fuses are unique chip
identifiers, mask revision numbers, cryptographic keys, JTAG secure mode,
boot characteristics, and various control signals, requiring permanent
non-volatility.
OCRAM
On-Chip Memory
Controller
Data Path
Data Path
The On-Chip Memory controller (OCRAM) module is designed as an interface
between system’s AXI bus and internal (on-chip) SRAM memory module.
In i.MX 6SoloLite processor, the OCRAM is used for controlling the 128 KB
multimedia RAM through a 64-bit AXI bus.
OCRAM_L2 On-Chip Memory
Controller for
The On-Chip Memory controller for L2 cache (OCRAM_L2) module is
designed as an interface between system’s AXI bus and internal (on-chip) L2
cache memory module during boot mode.
L2 Cache
OSC 32 kHz
PMU
OSC 32 kHz
Clocking
Generates 32.768 kHz clock from external crystal.
Power
Management
functions
Data Path
Integrated power management unit. Used to provide power to various SoC
domains.
PWM-1
PWM-2
PWM-3
PWM-4
Pulse Width
Modulation
Connectivity The pulse-width modulator (PWM) has a 16-bit counter and is optimized to
Peripherals generate sound from stored sample audio images and it can also generate
tones. It uses 16-bit resolution and a 4x16 data FIFO to generate sound.
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11
Modules List
Table 2. i.MX 6SoloLite Modules List (continued)
Block
Mnemonic
Block Name
Subsystem
Brief Description
A high-performance pixel processor capable of 1 pixel/clock performance for
PXP
PiXel
Display
Processing
Pipeline
Peripherals combined operations, such as color-space conversion, alpha blending,
gamma-mapping, and rotation. The PXP isenhanced with features specifically
for gray scale applications. In addition, the PXP supports traditional
pixel/frame processing paths for still-image and video processing applications,
allowing it to interface with either of the integrated EPD controllers.
RAM
128 KB
Internal RAM
Internal
Memory
Internal RAM, which is accessed through OCRAM memory controller.
RNGB
Random Number
Generator
Security
Random number generating module.
ROM
96KB
Boot ROM
Internal
Memory
Supports secure and regular Boot Modes. Includes read protection on 4K
region for content protection.
ROMCP
ROM Controller
with Patch
Data Path
ROM Controller with ROM Patch support.
SDMA
Smart Direct
Memory
System Control The SDMA is multi-channel flexible DMA engine. It helps in maximizing
Peripherals system performance by off-loading the various cores in dynamic data routing.
It has the following features:
Access
• Powered by a 16-bit Instruction-Set micro-RISC engine
• Multi-channel DMA supporting up to 32 time-division multiplexed DMA
channels
• 48 events with total flexibility to trigger any combination of channels
• Memory accesses including linear, FIFO, and 2D addressing
• Shared peripherals between ARM and SDMA
• Very fast Context-Software switching with 2-level priority based preemptive
multi-tasking
• DMA units with auto-flush and prefetch capability
• Flexible address management for DMA transfers (increment, decrement,
and no address changes on source and destination address)
• DMA ports can handle unit-directional and bi-directional flows (copy mode)
• Up to 8-word buffer for configurable burst transfers
• Support of byte-swapping and CRC calculations
• Library of Scripts and API is available
SJC
System JTAG System Control The SJC provides JTAG interface, which complies with JTAG TAP standards,
Controller
Peripherals to internal logic. The i.MX 6SoloLite processor uses JTAG port for production,
testing, and system debugging. In addition, the SJC provides BSR (Boundary
Scan Register) standard support, which complies with IEEE1149.1 and
IEEE1149.6 standards.
The JTAG port must be accessible during platform initial laboratory bring-up,
for manufacturing tests and troubleshooting, aswell asfor software debugging
by authorized entities. The i.MX 6SoloLite SJC incorporates three security
modes for protecting against unauthorized accesses. Modes are selected
through eFUSE configuration.
SNVS
SPDIF
Secure
Non-Volatile
Storage
Security
Secure Non-Volatile Storage, including Secure Real Time Clock, Security
State Machine, Master Key Control, and Violation/Tamper Detection and
reporting.
Sony Phillips
Digital Interface
Multimedia A standard audio file transfer format, developed jointly by the Sony and Phillips
Peripherals corporations. Has Transmitter and Receiver functionality.
i.MX 6SoloLite Applications Processors for Consumer Products, Data Sheet, Rev. 5, 10/2017
NXP Semiconductors
12
Modules List
Table 2. i.MX 6SoloLite Modules List (continued)
Subsystem Brief Description
Block
Mnemonic
Block Name
SSI-1
SSI-2
SSI-3
I2S/SSI/AC97
Interface
Connectivity The SSI is a full-duplex synchronous interface, which is used on the AP to
Peripherals provide connectivity with off-chip audio peripherals. The SSI supports a wide
variety of protocols (SSI normal, SSI network, I2S, and AC-97), bit depths (up
to 24 bits per word), and clock / frame sync options.
The SSI has two pairs of 8x24 FIFOs and hardware support for an external
DMA controller in order to minimize its impact on system performance. The
second pair of FIFOs provides hardware interleaving of asecond audio stream
that reduces CPU overhead in use cases where two time slots are being used
simultaneously.
TEMPMON
Temperature
Monitor
System Control The temperature monitor/sensor IP, for detecting high temperature conditions.
Peripherals The Temperature sensor IP for detecting die temperature. The temperature
read out does not reflectcase or ambient temperature, but the proximity of the
temperature sensor location on the die. Temperature distribution may not be
uniformly distributed, therefore the read out value may not be the reflection of
the temperature value of the entire die.
TZASC
Trust-Zone
Address Space
Controller
Security
The TZASC (TZC-380 by ARM) provides security address region control
functions required for intended application. It is used on the path to the DRAM
controller.
UART-1
UART-2
UART-3
UART-4
UART-5
UART
Interface
Connectivity Each of the UARTv2 modules support the following serial data
Peripherals transmit/receive protocols and configurations:
• 7- or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd or
none)
• Programmable baud rates up to 5.0 Mbps.
• 32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting auto-baud
• IrDA 1.0 support (up to SIR speed of 115200 bps)
• Option to operate as 8-pins full UART, DCE, or DTE
USBOH2A 2x USB 2.0 High Connectivity USBO2H contains:
Speed OTG and
1x HS Hosts
Peripherals
• Two high-speed OTG module with integrated HS USB PHY
• One identical high-speed Host modules connected to HSIC USB ports
i.MX 6SoloLite Applications Processors for Consumer Products, Data Sheet, Rev. 5, 10/2017
NXP Semiconductors
13
Modules List
Table 2. i.MX 6SoloLite Modules List (continued)
Block
Mnemonic
Block Name
Subsystem
Brief Description
uSDHC-1
uSDHC-2
uSDHC-2
SD/MMC and
SDXC
Enhanced
Connectivity i.MX 6SoloLite specific SoC characteristics:
Peripherals All four MMC/SD/SDIO controller IPs are identical and are based on the
uSDHC IP. They are:
uSDHC-4 Multi-Media Card
/ Secure Digital
• Conforms to the SD Host Controller Standard Specification version 3.0.
• Fully compliant with MMC command/response sets and Physical Layer as
defined in the Multimedia Card System Specification, v4.2/4.3/4.4/4.41/4.5
including high-capacity (size > 2 GB) cards HC MMC. Hardware reset as
specified for eMMC cards is supported at ports 3 and 4 only.
• Fully compliant with SD command/response sets and Physical Layer as
defined in the SD Memory Card Specifications, v3.0 including high-capacity
SDHC cards up to 32 GB and SDXC cards up to 2 TB.
Host Controller
• Fully compliant with SDIO command/response sets and interrupt/read-wait
mode as defined in the SDIO Card Specification, Part E1, v1.10
• Fully compliant with SD Card Specification, Part A2, SD Host Controller
Standard Specification, v2.00
All four ports support:
• 1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to
UHS-I SDR104 mode (104 MB/s max)
• 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to
52 MHz in both SDR and DDR modes (104 MB/s max)
• 4-bit or 8-bit transfer mode specifications for eMMC chips up to 200 MHz in
HS200 mode (200 MB/s max)
However, the SoC level integration and I/O muxing logic restrict the
functionality to the following:
• Instances 1 and 2 are primarily intended to serve as external slots or
interfaces to on-board SDIO devices. These ports are equipped with “Card
detection” and “Write Protection” pads and do not support hardware reset.
• All ports can work with 1.8 V and 3.3 V cards. There are two completely
independent I/O power domains for Ports 1 and 2 in four bit configuration
(SD interface). Port 3 is placed in an independent power domain and port 4
shares its power domain with other interfaces.
WDOG-1
Watchdog
Timer
The Watchdog Timer supports two comparison points during each counting
Peripherals period. Each of the comparison points is configurable to evoke an interrupt to
the ARM core, and a second point evokes an external event on the WDOG
line.
WDOG-2
(TZ)
Watchdog
(TrustZone)
Timer
The TrustZone Watchdog (TZ WDOG) timer module protects against
Peripherals TrustZone starvation by providing a method of escaping normal mode and
forcing a switch to the TZ mode. TZ starvation is a situation where the normal
OS prevents switching to the TZ mode. Such situation is undesirable as it can
compromise the system’s security. Once the TZ WDOG module is activated, it
must be serviced by TZ software on a periodic basis. If servicing does not take
place, the timer times out. Upon a time-out, the TZ WDOG asserts a TZ
mapped interrupt that forces switching to the TZ mode. If it is still not served,
the TZ WDOG asserts a security violation signal to the CSU. The TZ WDOG
module cannot be programmed or deactivated by a normal mode Software.
XTALOSC
Crystal
Oscillator I/F
Clocking
The XTALOSC module enables connectivity to external crystal oscillator
device. In a typical application use-case, it is used for 24 MHz oscillator.
i.MX 6SoloLite Applications Processors for Consumer Products, Data Sheet, Rev. 5, 10/2017
NXP Semiconductors
14
Modules List
3.1
Special Signal Considerations
Table 3 lists special signal considerations for the i.MX 6SoloLite processor. The signal names are listed in
alphabetical order.
The package contact assignments can be found in Section 6, “Package Information and Contact
Assignments.” Signal descriptions are provided in the i.MX 6SoloLite reference manual (IMX6SLRM).
Table 3. Special Signal Considerations
Signal Name
Remarks
XTALOSC_CLK1_P/ One general purpose differential high speed clock Input/output is provided.
XTALOSC_CLK1_N It could be used to:
• To feed external reference clock to the PLLs and further to the modules inside SoC, for example as
alternate reference clock for Audio interfaces, etc.
• To output internal SoC clock to be used outside the SoC as either reference clock or as a functional
clock for peripherals.
See the i.MX 6SoloLite reference manual for details on the respective clock trees.
The clock inputs/outputs are LVDS differential pairs compatible with TIA/EIA-644 standard, the maximum
clock out frequency range supported is 528 MHz.
Alternatively one may use single ended signal to drive XTALOSC_CLK1_P input. In this case, the
corresponding XTALOSC_CLK1_N input should be tied to theconstant voltage level equal 1/2 of theinput
signal swing.
Termination should be provided in case of high frequency signals.
See LVDS pad electrical specification for further details.
After initialization, the XTALOSC_CLK1 input/output could be disabled (if not used). If unused, the
XTALOSC_CLK1_N/P pair can remain unconnected.
DRAM_VREF
When using DRAM_VREF with DDR I/O, the nominal reference voltage must be half of the NVCC_DRAM
supply. The user must tie DRAM_VREF to a precision external resistor divider. Use a 1 kΩ 0.5% resistor
to GND and a 1 kΩ 0.5% resistor to NVCC_DRAM. Shunt each resistor with a closely-mounted 0.1 µF
capacitor.
To reduce supply current, a pair of1.5 kΩ 0.1% resistors can be used. Using resistors with recommended
tolerances ensures the ± 2% DRAM_VREF tolerance (per the DDR3 specification) is maintained when
four DDR3 ICs plus the i.MX 6SoloLite are drawing current on the resistor divider.
It is recommended to use regulated power supply for “big” memory configurations (more that eight
devices).
JTAG_nnnn
The JTAG interface is summarized in Table 4. Use of external resistors is unnecessary. However, if
external resistors are used, the user must ensure that the on-chip pull-up/down configuration is followed.
For example, do not use an external pull down on an input that has on-chip pull-up.
JTAG_TDO is configured with a keeper circuit such that the floating condition is eliminated if an external
pull resistor is not present. An external pull resistor on JTAG_TDO is detrimental and should be avoided.
JTAG_MODE must be externally connected to GND for normal operation. Termination to GND through
an external pull-down resistor (such as 1 kΩ) is allowed. JTAG_MODE set to high configures the JTAG
interface to mode compliant with IEEE1149.1 standard. JTAG_MODE set to low configures the JTAG
interface for common Software debug adding all the system TAPs to the chain.
NC
These signals are No Connect (NC) and must remain unconnected by the user.
SRC_ONOFF
In normal mode may be connected to ONOFF button (de-bouncing provided at this input). Internally this
pad is pulled up. A short duration (<5s) connection to GND in OFF mode causes the internal power
management state machine to change the state to ON. In ON mode, a short duration connection to GND
generates interrupt (intended to initiate a software controllable power down). A long duration (above ~5s)
connection to GND causes “forced” OFF.
SRC_POR_B
This cold reset negative logic input resets all modules and logic in the IC.
i.MX 6SoloLite Applications Processors for Consumer Products, Data Sheet, Rev. 5, 10/2017
NXP Semiconductors
15
Modules List
Table 3. Special Signal Considerations (continued)
Remarks
Signal Name
RTC_XTALI/
RTC_XTALO
If the user wishes to configure RTC_XTALI and RTC_XTALO as an RTC oscillator, a 32.768 kHz crystal
(≤100 kΩ ESR, 10 pF load) should be connected between RTC_XTALI and RTC_XTALO. Keep in mind
the capacitors implemented on either side of the crystal are about twice the crystal load capacitor. To hit
the exact oscillation frequency, the board capacitors need to be reduced to account for board and chip
parasitics. The integrated oscillation amplifier is self biasing, but relatively weak. Care must be taken to
limit parasitic leakage from RTC_XTALI and RTC_XTALO to either power or ground (>100 MΩ). This will
debias the amplifier and cause a reduction of startup margin. Typically RTC_XTALI and RTC_XTALO
should bias to approximately 0.5 V.
If it is desired to feed an external low frequency clock into RTC_XTALI, the RTC_XTALO pin must remain
unconnected or driven with a complimentary signal. The logic level of this forcing clock should not exceed
VDD_SNVS_CAP level and the frequency should be <100 kHz under typical conditions.
In the case when a high accuracy real time clock is not required, the system may use an internal low
frequency ring oscillator. It is recommended to connect RTC_XTALI to GND and leave RTC_XTALO
unconnected.
TEST_MODE
XTALI/XTALO
TEST_MODE is for NXP factory use. This signal is internally connected to an on-chip pull-down device.
The user must either leave this signal unconnected or tie it to GND.
• A 24.0 MHz crystal must be connected between XTALI and XTALO. The level and frequency must be
<32 MHz under typical conditions.
• The crystal must be rated for a maximum drive level of 250 μW. An ESR (equivalent series resistance)
of typically 80 Ω is recommended. NXP BSP (board support package) software requires 24 MHz on
XTALI/XTALO.
• The crystal can be eliminated if an external 24 MHz oscillator is available in the system. In this case,
XTALI must be directly driven by the external oscillator and XTALO remains unconnected.
The XTALI signal level must swing from ~0.8 x NVCC_PLL_OUT to ~0.2 V.
• This clock is used as a reference for USB, so there are strict frequency tolerance and jitter
requirements.
• See the XTALOSC chapter and relevant interface specifications chapters of the i.MX 6SoloLite
reference manual (IMX6SLRM), for details.
ZQPAD
DRAM calibration resistor 240 Ω 1% used as reference during DRAM output buffer driver calibration
should be connected between this pad and GND.
Table 4. JTAG Controller Interface Summary
JTAG
I/O Type
On-Chip Termination
JTAG_TCK
JTAG_TMS
JTAG_TDI
Input
Input
47 kΩ pull-up
47 kΩ pull-up
47 kΩ pull-up
Keeper
Input
JTAG_TDO
JTAG_TRST_B
JTAG_MODE
3-state output
Input
47 kΩ pull-up
100 kΩ pull-up
Input
i.MX 6SoloLite Applications Processors for Consumer Products, Data Sheet, Rev. 5, 10/2017
NXP Semiconductors
16
Electrical Characteristics
3.2
Recommended Connections for Unused Analog Interfaces
Table 5 shows the recommended connections for unused analog interfaces.
Table 5. Recommended Connections for Unused Analog Interfaces
Module
Pad Name Recommendations if Unused?
XTALOSC XTALOSC_CLK1_N, XTALOSC_CLK1_P
USB USB_OTGx_DN, USB_OTGx_DP, USB_OTGx_VBUS, USB_OTG_CHD_B
Leave unconnected
Leave unconnected
4 Electrical Characteristics
This section provides the device and module-level electrical characteristics for the i.MX 6SoloLite.
4.1
Chip-Level Conditions
This section provides the device-level electrical characteristics for the IC. See Table 6 for a quick reference
to the individual tables and sections.
Table 6. i.MX 6SoloLite Chip-Level Conditions
For these characteristics, …
Absolute Maximum Ratings
Topic appears …
on page 18
on page 19
on page 21
on page 23
on page 24
on page 25
on page 26
BGA Case 2240 Package Thermal Resistance
Operating Ranges
External Clock Sources
Maximum Supply Currents
Low Power Mode Supply Currents
USB PHY Current Consumption
4.1.1
Absolute Maximum Ratings
CAUTION
Stresses beyond those listed under Table 7 may cause permanent damage to
the device. These are stress ratings only. Functional operation of the device
at these or any other conditions beyond those indicated in the Table 9,
"Operating Ranges” or subsequent parameters tables is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability.
Table 7 provides the absolute maximum operating ratings.
i.MX 6SoloLite Applications Processors for Consumer Products, Data Sheet, Rev. 5, 10/2017
NXP Semiconductors
17
Electrical Characteristics
Table 7. Absolute Maximum Ratings
Parameter Description
Symbol
Min
Max
Unit
Core supply input voltage (LDO enabled)
Core supply input voltage (LDO bypass)
Core supply output voltage (LDO enabled)
VDD_ARM_IN
VDD_SOC_IN
VDD_PU_IN
-0.3
1.6
V
VDD_ARM_IN
VDD_SOC_IN
VDD_PU_IN
-0.3
1.4
1.4
V
V
VDD_ARM_CAP -0.3
VDD_SOC_CAP
VDD_PU_CAP
VDD_HIGH_IN supply voltage
VDD_HIGH_IN
VDD_HIGH_CAP -0.3
NVCC_DRAM -0.4
NVCC_DRAM_2P5 -0.3
-0.3
3.7
V
V
V
V
V
V
V
VDD_HIGH_CAP supply output voltage
DDR I/O supply voltage
2.6
1.975 (See note 1)
DDR pre-drivers supply voltage
2.85
2.1
GPIO dual supply 1P8V I/O supply voltage
GPIO dual supply 3P3V I/O supply voltage
NVCC18_IO
NVCC33_IO
-0.5
-0.5
-0.3
3.7
SNVS IN supply voltage
VDD_SNVS_IN
3.7
(Secure Non-Volatile Storage and Real Time Clock)
USB I/O supply voltage
USB_H1_DN
USB_H1_DP
-0.3
3.63
V
USB_OTG_DN
USB_OTG_DP
USB_OTG_CHD_B
USB VBUS supply voltage
USB_OTG_VBUS
Vin/Vout
—
5.25
V
V
Vin/Vout I/O voltage range (non-DDR pins)
Vin/Vout I/O voltage range (DDR pins)
ESD immunity (HBM)
-0.5 OVDD+0.3 (See note 2)
-0.5 OVDD+0.4 (See notes1& 2)
Vin/Vout
V
Vesd_HBM
Vesd_CDM
TSTORAGE
—
—
2000
500
V
ESD immunity (CDM)
V
oC
Storage temperature range
-40
150
1
The absolute maximum voltage includes an allowance for 400 mV of overshoot on the IO pins. Per JEDEC standards, the
allowed signal overshoot must be derated if NVCC_DRAM exceeds 1.575V.
2
OVDD is the I/O supply voltage.
4.1.2
Thermal Resistance
NOTE
Per JEDEC JESD51-2, the intent of thermal resistance measurements is
solely for a thermal performance comparison of one package to another in a
standardized environment. This methodology is not meant to and will not
predict the performance of a package in an application-specific
environment.
i.MX 6SoloLite Applications Processors for Consumer Products, Data Sheet, Rev. 5, 10/2017
18
NXP Semiconductors
Electrical Characteristics
4.1.2.1
BGA Case 2240 Package Thermal Resistance
Table 8 provides the MAPBGA package thermal resistance data.
Table 8. Package Thermal Resistance Data
Rating
Board
Symbol
No Lid
Unit
Junction to Ambient1 (natural convection)
Single layer board (1s)
Four layer board (2s2p)
Single layer board (1s)
Four layer board (2s2p)
—
RθJA
RθJA
51
28
40
24
14
9
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Junction to Ambient1 (at 200 ft/min)
RθJMA
RθJMA
RθJB
Junction to Board2
Junction to Case3 (Top)
Junction to Package Top4
—
RθJCtop
ΨJT
Natural Convection
2
1
Junction-to-Ambient Thermal Resistance was determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets
JEDEC specification for this package.
2
3
4
Junction-to-Board Thermal Resistance was determined per JEDEC JESD51-8. Thermal test board meetsJEDEC specification
for the specified package.
Junction-to-Case at the top of the package was determined by using MIL-STD 883 Method 1012.1. The cold plate temperature
is used for the case temperature. Reported value includes the thermal resistance of the interface layer.
Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
4.1.3
Operating Ranges
Figure 3 shows major power systems blocks and internal/external connections for the i.MX 6SoloLite
processor.
i.MX 6SoloLite Applications Processors for Consumer Products, Data Sheet, Rev. 5, 10/2017
NXP Semiconductors
19
Electrical Characteristics
External Supplies
i.MX 6SL Chip
VDDPU_IN
VDDPU_CAP
LDO_PU
GPU2D
DCDC Low
GND
OpenVG
VDDARM_IN
VDDARM_CAP
LDO_ARM
GND
ARM Core
L2 Cache
L1 Cache
Sw itch
VDDSOC_IN
VDDSOC_CAP
LDO_SoC
Display
SoC
Sw itch
GND
VDDHIGH_CAP
LDO_2P5
DCDC High
VDDHIGH_IN
GND
GND
eFUSE
USB
PLLs
LVDS
24M
OSC
NVCC_PLL_OUT
VDDSNVS_CAP
LDO_1P1
SNVS
VDDSNVS_IN
LDO_SNVS
Coin
Cell
32K
GND
VDDUSB_CAP
OSC
USB_OTG1_VBUS
USB_OTG2_VBUS
LDO_USB
GND
Figure 3. i.MX 6SoloLite SoC Power Block Diagram
i.MX 6SoloLite Applications Processors for Consumer Products, Data Sheet, Rev. 5, 10/2017
NXP Semiconductors
20
Electrical Characteristics
Table 9 provides the operating ranges of the i.MX 6SoloLite processor. For details on the chip's power
structure, see the “Power Management Unit (PMU)” chapter of the i.MX 6SoloLite Reference Manual
(IMX6SLRM).
Table 9. Operating Ranges
Parameter
Description
Symbol
Min
Typ
Max1
Unit
Comment
Run mode: LDO
enabled
VDD_ARM_IN
1.3752
—
1.5
V
LDO output set at 1.250V minimum for
operation up to 996 MHz
1.2752
1.0752
1.0752
1.0502
1.2752,4
—
—
—
—
—
1.5
1.5
1.5
1.5
1.5
V
V
V
V
V
LDO output set at 1.150V minimum for
operation up to 792 MHz
LDO output set at 0.95V minimum for
operation up to 396 MHz
LDO output set at 0.950V minimum for
operation up to 192 MHz
LDO output set at 0.9250V minimum for
operation up to 24 MHz
VDD_SOC_IN3
VDD_PU_IN
VDD_SOC and VDD_PU LDO outputs
(VDD_SOC_CAP and VDD_PU_CAP)
require 1.15 V minimum
Run mode: LDO
bypassed
VDD_ARM_IN
1.250
1.150
0.950
0.950
0.925
1.154
—
—
—
—
—
—
1.3
1.3
1.3
1.3
1.3
1.3
V
V
V
V
V
V
LDO bypassed for operation up to 996 MHz
LDO bypassed for operation up to 792 MHz
LDO bypassed for operation up to 396 MHz
LDO bypassed for operation up to 192 MHz
LDO bypassed for operation up to 24 MHz
—
VDD_SOC_IN3
VDD_PU_IN
Standby/DSM Mode
VDD_ARM_IN
0.9
0.9
—
—
1.3
1.3
V
V
See Table 12, "Stop Mode Current and
Power Consumption," on page 25.
VDD_SOC_IN
VDD_PU_IN
VDDHIGH internal
Regulator
VDD_HIGH_IN5
2.8
2.7
—
—
3.3
3.6
V
V
Must match the range of voltages that the
rechargeable backup battery supports.
Backup battery
supply range
VDD_SNVS_IN5
Should be supplied from thesamesupply as
VDD_HIGH_IN if the system does not
require keeping real time and other data on
OFF state.
USB supply voltages USB_OTG1_VBUS
USB_OTG2_VBUS
4.4
—
5.25
V
—
DDR I/O supply
NVCC_DRAM
1.14
1.425
2.5
1.2
1.5
2.5
1.3
1.575
2.75
V
V
V
LPDDR2
DDR3
—
NVCC_DRAM_2P5
i.MX 6SoloLite Applications Processors for Consumer Products, Data Sheet, Rev. 5, 10/2017
NXP Semiconductors
21
Electrical Characteristics
Table 9. Operating Ranges (continued)
Parameter
Description
Symbol
Min
Typ
Max1
Unit
Comment
GPIO supplies6
NVCC33_IO
2.8
3.0
3.3
V
Worst case, assuming all SOC I/O operating
at 1.8V. NVCC33_IO must always be
greater than NVCC18_IO.
NVCC18_IO
NVCC_1P2V
TJ
1.62
1.14
0
1.8
1.2
—
1.98
1.3
95
V
V
—
—
Junction
temperature
°C Commercial
See i.MX 6SoloLite Product Lifetime Usage
Estimates Application Note, AN4726, for
information on product lifetime (power-on
years) for this processor.
Junction
TJ
-40
—
105
—
Extended commercial
temperature
See i.MX 6SoloLite Product Lifetime Usage
Estimates Application Note, AN4726, for
information on product lifetime (power-on
years) for this processor.
1
Applying the maximum voltage results in maximum power consumption and heat generation. NXP recommends a voltage set
point = (Vmin + the supply tolerance). This results in an optimized power/speed ratio.
2
3
4
5
VDD_ARM_IN and VDD_SOC_IN must be at least 125 mV higher than the LDO Output Set Point for correct voltage regulation.
VDD_SOC_CAP and VDD_PU_CAP must be equal.
VDD_SOC and VDD_PU output voltage must be set to this rule: VDD_ARM - VDD_SOC / VDD_PU < 50mV.
While setting VDD_SNVS_IN voltage with respect to Charging Currents and RTC, refer to Hardware Development Guide for
i.MX 6Dual, 6Quad, 6Solo, 6DualLite Families of Applications Processors (IMX6DQ6SDLHDG).
6
All digital I/O supplies (NVCC_xxxx) must be powered under normal conditions whether the associated I/O pins are in use or
not, and associated I/O pins need to have a pull-up or pull-down resistor applied to limit any floating gate current.
4.1.4
External Clock Sources
Each i.MX 6SoloLite processor has two external input system clocks: a low frequency (RTC_XTALI) and
a high frequency (XTALI).
The RTC_XTALI is used for low-frequency functions. It supplies the clock for wake-up circuit,
power-down real time clock operation, and slow system and watchdog counters. The clock input can be
connected to either an external oscillator or a crystal using the internal oscillator amplifier. Additionally,
there is an internal ring oscillator, which can substitute the RTC_XTALI, in case accuracy is not important.
The system clock input XTALI is used to generate the main system clock. It supplies the PLLs and other
peripherals. The system clock input can be connected to either an external oscillator or a crystal using the
internal oscillator amplifier.
NOTE
The internal RTC oscillator does not provide an accurate frequency and is
affected by process, voltage, and temperature variations. NXP strongly
recommends using an external crystal as the RTC_XTALI reference. If the
internal oscillator is used instead, careful consideration must be given to the
timing implications on all of the SoC modules dependent on this clock.
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Table 10 shows the interface frequency requirements.
Table 10. External Input Clock Frequency
Parameter Description
Symbol
Min
Typ
Max
Unit
RTC_XTALI Oscillator1, 2
XTALI Oscillator4, 2
fckil
fxtal
—
—
32.768(see 3)/32.0
24
—
—
kHz
MHz
1
External oscillator or a crystal with internal oscillator amplifier.
2
The required frequency stability of this clock source is application dependent. For recommendations, see Hardware
Development Guide for i.MX 6Dual, 6Quad, 6Solo, 6DualLite Families of Applications Processors (IMX6DQ6SDLHDG).
3
4
Recommended nominal frequency 32.768 kHz.
External oscillator or a fundamental frequency crystal with internal oscillator amplifier.
The typical values shown in Table 10 are required for use with NXP BSPs to ensure precise time keeping
and USB operation. For RTC_XTALI operation, two clock sources are available:
•
On-chip 40 kHz ring oscillator: This clock source has the following characteristics:
— Approximately 25 μA more Idd than crystal oscillator
— Approximately ±50% tolerance
— No external component required
— Starts up quicker than 32 kHz crystal oscillator
External crystal oscillator with on-chip support circuit
•
— At power up, ring oscillator is utilized. After crystal oscillator is stable, the clock circuit
switches over to the crystal oscillator automatically.
— Higher accuracy than ring oscillator
— If no external crystal is present, then the ring oscillator is utilized
The decision to choose a clock source should be taken based on real-time clock use and precision time-out.
4.1.5
Maximum Supply Currents
The Power Virus numbers shown in Table 11 represent a use case designed specifically to show the
maximum current consumption possible. All cores are running at the defined maximum frequency and are
limited to L1 cache accesses only to ensure no pipeline stalls. Although a valid condition, it would have a
very limited practical use case, if at all, and be limited to an extremely low duty cycle unless the intention
was to specifically show the worst case power consumption.
The NXP power management IC, MMPF0100xxxx, which is targeted for the i.MX 6 series processor
family, supports the power consumption shown in Table 11, however a robust thermal design is required
for the increased system power dissipation.
See the i.MX 6SoloLite Power Consumption Measurement Application Note (AN4580) for more details on
typical power consumption under various use case definitions.
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Electrical Characteristics
Table 11. Maximum Supply Currents
Conditions
Power Line
Max Current
Unit
VDD_ARM_IN
1 GHz ARM clock based on
Power Virus operation
1100
mA
VDD_SOC_IN
VDD_PU_IN
1 GHz ARM clock
650
150
301
mA
mA
mA
μA
1 GHz ARM clock
VDD_HIGH_IN
VDD_SNVS_IN
—
—
—
2502
253
USB_OTG1_VBUS
USB_OTG2_VBUS
mA
Primary Interface (IO) Supplies
NVCC_DRAM
NVCC33_IO
NVCC18_IO
NVCC_1P2V
—
(see4)
N=156
N=156
N=2
Use maximum IO Equation5
Use maximum IO Equation5
Use maximum IO Equation5
mA
mA
MISC
DRAM_VREF
—
1
1
The actual maximum current drawn from VDD_HIGH_IN will be as shown plus any additional current drawn from the
VDD_HIGH_CAP outputs, depending upon actual application configuration (for example, NVCC_DRAM_2P5 supplies).
2
The maximum VDD_SNVS_IN current may be higher depending on specific operating configurations, such as
BOOT_MODE[1:0] not equal to 00, or use ofthe Tamper feature. During initial power on, VDD_SNVS_IN can draw up to 1mA,
if available. VDD_SNVS_CAP charge time will increase if less than 1 mA is available.
3
4
This is the maximum current per active USB physical interface.
The DRAM power consumption is dependent on several factors, such as external signal termination. DRAM power calculators
are typically available from the memory vendors. They take in account factors, such as signal termination.
See the i.MX 6SoloLite Power Consumption Measurement Application Note or examples of DRAM power consumption during
specific use case scenarios.
5
General equation for estimated, maximum power consumption of an IO power supply:
Imax = N x C x V x (0.5 x F)
Where:
N—Number of IO pins supplied by the power line
C—Equivalent external capacitive load
V—IO voltage
(0.5 xF)—Data change rate. Up to 0.5 of the clock rate (F)
In this equation, Imax is in Amps, C in Farads, V in Volts, and F in Hertz.
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Electrical Characteristics
4.1.6
Low Power Mode Supply Currents
Table 12 shows the current core consumption (not including I/O) of i.MX 6SoloLite processor in selected
low power modes.
Table 12. Stop Mode Current and Power Consumption
Mode
Test Conditions
Supply
Typical1
Unit
WAIT
• ARM, SoC, and PU LDOs are set to 1.225 V
• HIGH LDO set to 2.5 V
• Clocks are gated
• DDR is in self refresh
• PLLs are active in bypass (24 MHz)
• Supply voltages remain ON
VDD_ARM_IN (1.375 V)
VDD_SOC_IN (1.375 V)
VDD_PU_IN (1.375 V)
VDD_HIGH_IN(3.0 V)
Total
4
mA
7.5
1.5
9
44.9
2.5
7.5
1.5
4.5
29.3
2.5
7.5
0.1
4.0
25.9
0.1
1.0
0.1
3
mW
mA
STOP_ON
STOP_OFF
STANDBY
• ARM LDO set to 0.9 V
• SoC and PU LDOs set to 1.225 V
• HIGH LDO set to 2.5 V
• PLLs disabled
VDD_ARM_IN (1.375 V)
VDD_SOC_IN (1.375 V)
VDD_PU_IN (1.375 V)
VDD_HIGH_IN (3.0 V)
Total
• DDR is in self refresh
mW
mA
• ARM LDO set to 0.9 V
• SoC LDO set to 1.225 V
• PU LDO is power gated
• HIGH LDO set to 2.5 V
• PLLs disabled
VDD_ARM_IN (1.375 V)
VDD_SOC_IN (1.375 V)
VDD_PU_IN (1.375 V)
VDD_HIGH_IN (3.0 V)
Total
• DDR is in self refresh
mW
mA
• ARM and PU LDOs are power gated
• SoC LDO is in bypass
• HIGH LDO is set to 2.5 V
• PLLs are disabled
• Low voltage
• Well Bias ON
VDD_ARM_IN (0.9 V)
VDD_SoC_IN (0.9 V)
VDD_PU_IN (0.9 V)
VDD_HIGH_IN (3.0 V)
Total
• XTAL is enabled
10.1
0.1
0.75
0.1
0.15
1.3
41
mW
mA
Deep Sleep Mode
(DSM)
• ARM and PU LDOs are power gated
• SoC LDO is in bypass
• HIGH LDO is set to 2.5 V
• PLLs are disabled
• Low voltage
• Well Bias ON
VDD_ARM_IN (0.9 V)
VDD_SoC_IN (0.9 V)
VDD_PU_IN (0.9 V)
VDD_HIGH_IN (3.0 V)
Total
• XTAL and bandgap are disabled
mW
μA
SNVS Only
• VDD_SNVS_IN powered
• All other supplies off
• SRTC running
VDD_SNVS_IN (2.8V)
Total
115
μW
1
The typical values shown here are for information only and are not guaranteed. These values are average values measured
on a worst-case wafer at 25°C.
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Electrical Characteristics
4.1.7
USB PHY Current Consumption
4.1.7.1
Power Down Mode
In power down mode, everything is powered down, including the USB_OTGx_VBUS valid detectors,
typical condition. Table 13 shows the USB interface current consumption in power down mode.
Table 13. USB PHY Current Consumption in Power Down Mode
VDD_USB_CAP (3.0 V)
VDDHIGH_CAP (2.5 V)
NVCC_PLL_OUT (1.1 V)
Current
5.1 μA
1.7 μA
<0.5 μA
NOTE
The currents on the VDD_HIGH_CAP and VDD_USB_CAP were
identified to be the voltage divider circuits in the USB-specific level
shifters.
4.2
Power Supplies Requirements and Restrictions
The system design must comply with power-up sequence, power-down sequence, and steady state
guidelines as described in this section to guarantee the reliable operation of the device. Any deviation
from these sequences may result in the following situations:
•
•
•
Excessive current during power-up phase
Prevention of the device from booting
Irreversible damage to the processor (worst-case scenario)
4.2.1
Power-Up Sequence
For power-up sequence, the restrictions are as follows:
•
•
•
VDD_SNVS_IN supply must be turned ON before any other power supply. It may be connected
(shorted) with VDD_HIGH_IN supply.
If a coin cell is used to power VDD_SNVS_IN, then ensure that it is connected before any other
supply is switched on.
SRC_POR_B signal is used to control the processor POR. SRC_POR_B must be immediately
asserted at power-up and remain asserted until the VDD_ARM_CAP, VDD_SOC_CAP, and
VDD_PU_CAP supplies are stable. VDD_ARM_IN and VDD_SOC_IN may be applied in either
order with no restrictions.
NOTE
Ensure that there is no back voltage (leakage) from any supply on the board
towards the 3.3 V supply (for example, from the external components that
use both the 1.8 V and 3.3 V supplies).
NOTE
USB_OTG_VBUS and USB_H1_VBUS are not part of the power supply
sequence and can be powered at any time.
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NOTE
For customers beginning new designs with the i.MX 6SoloLite and the
PF0100 PMIC, it is recommended to use the F3 OTP option instead of the
F1 OTP option and the F4 OTP option instead of the F2 OTP option.
4.2.2
Power-Down Sequence
There are no special requirements on the power-down sequence other than the VDD_SNVS_IN supply
should be the last to turn off.
4.2.3
Power Supplies Usage
All I/O pins should not be externally driven while the I/O power supply for the pin (NVCC_xxx) is OFF.
This can cause internal latch-up and malfunctions due to reverse current flows. For information about I/O
power supply of each pin, see “Power Group” column of Table 66, "13 x 13 mm Functional Contact
Assignments," on page 86.
4.3
Integrated LDO Voltage Regulator Parameters
Various internal supplies can be powered ON from internal LDO voltage regulators. All the supply pins
named *_CAP must be connected to external capacitors. The onboard LDOs are intended for internal use
only and should not be used to power any external circuitry. See the i.MX 6SoloLite reference manual for
details on the power tree scheme recommended operation.
NOTE
The *_CAP signals should not be powered externally. These signals are
intended for internal LDO or LDO bypass operation only.
4.3.1
Digital Regulators (LDO_ARM, LDO_PU, LDO_SOC)
There are three digital LDO regulators (“Digital”, because of the logic loads that they drive, not because
of their construction). The advantages of the regulators are to reduce the input supply variation because of
their input supply ripple rejection and their on die trimming. This translates into more voltage for the die
producing higher operating frequencies. These regulators have three basic modes.
•
Bypass. The regulation FET is switched fully on passing the external voltage, DCDC_LOW, to the
load unaltered. The analog part of the regulator is powered down in this state, removing any loss
other than the IR drop through the power grid and FET.
•
•
Power Gate. The regulation FET is switched fully off limiting the current draw from the supply.
The analog part of the regulator is powered down here limiting the power consumption.
Analog regulation mode. The regulation FET is controlled such that the output voltage of the
regulator equals the programmed target voltage. The target voltage is fully programmable in 25 mV
steps.
For additional information, see the i.MX 6SoloLite reference manual.
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Electrical Characteristics
4.3.2
Regulators for Analog Modules
4.3.2.1
LDO_1P1
The LDO_1P1 regulator implements a programmable linear-regulator function from VDD_HIGH_IN (see
Table 9 for min and max input requirements). Typical Programming Operating Range is 1.0 V to 1.2 V
with the nominal default setting as 1.1 V. LDO_1P1 supplies the USB Phy and the PLLs. A programmable
brown-out detector is included in the regulator that can be used by the system to determine when the load
capability of the regulator is being exceeded to take the necessary steps. Current-limiting can be enabled
to allow for in-rush current requirements during start-up, if needed. Active-pull-down can also be enabled
for systems requiring this feature.
For information on external capacitor requirements for this regulator, see the Hardware Development
Guide for i.MX 6SoloLite Applications Processors (IMX6SLHDG). For additional information, see the
i.MX 6SoloLite reference manual.
4.3.2.2
LDO_2P5
The LDO_2P5 module implements a programmable linear-regulator function from VDD_HIGH_IN (see
Table 9 for minimum and maximum input requirements). Typical Programming Operating Range is
2.25 V to 2.75 V with the nominal default setting as 2.5 V. LDO_2P5 supplies the USB Phy, LVDS Phy
and PLLs. A programmable brown-out detector is included in the regulator that can be used by the system
to determine when the load capability of the regulator is being exceeded, to take the necessary steps.
Current-limiting can be enabled to allow for in-rush current requirements during start-up, if needed.
Active-pull-down can also be enabled for systems requiring this feature. An alternate self-biased
low-precision weak-regulator is included that can be enabled for applications needing to keep the output
voltage alive during low-power modes where the main regulator driver and its associated global bandgap
reference module are disabled. The output of the weak-regulator is not programmable and is a function of
the input supply as well as the load current. Typically, with a 3 V input supply the weak-regulator output
is 2.525 V and its output impedance is approximately 40 Ω.
For information on external capacitor requirements for this regulator, see the Hardware Development
Guide for i.MX 6SoloLite Applications Processors (IMX6SLHDG).
For additional information, see the i.MX 6SoloLite reference manual.
4.3.2.3
LDO_USB
The LDO_USB module implements a programmable linear-regulator function from the
USB_OTG1_VBUS and USB_OTG2_VBUS voltages (4.4 V–5.25 V) to produce a nominal 3.0 V output
voltage. A programmable brown-out detector is included in the regulator that can be used by the system
to determine when the load capability of the regulator is being exceeded, to take the necessary steps. This
regulator has a built in power-mux that allows the user to select to run the regulator from either VBUS
supply, when both are present. If only one of the VBUS voltages is present, then, the regulator
automatically selects this supply. Current limit is also included to help the system meet in-rush current
targets. If no VBUS voltage is present, then the VBUSVALID threshold setting will prevent the regulator
from being enabled.
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For information on external capacitor requirements for this regulator, see the Hardware Development
Guide for i.MX 6SoloLite Applications Processors (IMX6SLHDG).
For additional information, see the i.MX 6SoloLite reference manual.
4.4
PLL’s Electrical Characteristics
4.4.1
Audio/Video PLL’s Electrical Parameters
Table 14. Audio/Video PLL’s Electrical Parameters
Parameter
Value
Clock output range
Reference clock
Lock time
650 MHz ~1.3 GHz
24 MHz
<11250 reference cycles (450 μs)
4.4.2
528 MHz PLL
Table 15. 528 MHz PLL’s Electrical Parameters
Parameter
Value
Clock output range
Reference clock
Lock time
528 MHz PLL output
24 MHz
<11250 reference cycles (15 μs)
4.4.3
Ethernet PLL
Table 16. Ethernet PLL’s Electrical Parameters
Parameter
Value
Clock output range
Reference clock
Lock time
500 MHz
24 MHz
<11250 reference cycles (450 μs)
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Electrical Characteristics
4.4.4
480 MHz PLL
Table 17. 480 MHz PLL’s Electrical Parameters
Parameter
Value
Clock output range
Reference clock
Lock time
480 MHz PLL output
24 MHz
<383 reference cycles (15 μs)
4.4.5
ARM PLL
Table 18. ARM PLL’s Electrical Parameters
Parameter
Value
Clock output range
Reference clock
Lock time
650 MHz~1.3 GHz
24 MHz
<2250 reference cycles (50 μs)
4.5
On-Chip Oscillators
OSC24M
4.5.1
This block implements an amplifier that when combined with a suitable quartz crystal and external load
capacitors implements an oscillator. It also implements a power mux such that the oscillator can be
powered from NVCC_1P2V or VDD_SOC. NVCC_1P2V should be the cleaner supply and is the
preferable choice, however, if the oscillator is required to run in stop mode then it is necessary to run from
VDD_SOC, which is 0.9 V in stop mode.
The system crystal oscillator consists of a Pierce-type structure running off the digital supply. A straight
forward biased-inverter implementation is used.
4.5.2
OSC32K
This block implements an amplifier that when combined with a suitable quartz crystal and external load
capacitors implements a low power oscillator. It also implements a power mux such that it can be powered
from either a ~3 V backup battery (VDD_SNVS_IN) or VDD_HIGH_IN such as the oscillator consumes
power from VDD_HIGH_IN when that supply is available and transitions to the back up battery when
VDD_HIGH_IN is lost.
In addition, if the clock monitor determines that the OSC32K is not present, then the source of the 32 kHz
clock will automatically switch to the internal ring oscillator.
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CAUTION
The internal RTC oscillator does not provide an accurate frequency and is
affected by process, voltage and temperature variations. NXP strongly
recommends using an external crystal as the RTC_XTALI reference. If the
internal oscillator is used instead, careful consideration must be given to the
timing implications on all of the SoC modules dependent on this clock.
The OSC32k runs from VDD_SNVS_CAP, which comes from the VDD_HIGH_IN/VDD_SNVS_IN
power mux.
Table 19. OSC32K Main Characteristics
Parameter
Min
Typ
Max
Comments
Fosc
—
32.768 kHz
—
This frequency is nominal and determined mainly by the crystal selected.
32.0 K would work as well.
Current
consumption
—
—
4 μA
—
—
The typical value shown is only for the oscillator, driven by an external
crystal. If the internal ring oscillator is used instead of an external crystal,
then approximately 25 μA should be added to this value.
Bias resistor
14 MΩ
This the integrated bias resistor that sets the amplifier into a highgain state.
Any leakage through the ESD network, external board leakage, or even a
scope probe that is significant relative to this value will debias the amp. The
debiasing will result in low gain, and will impact thecircuit's ability to start up
and maintain oscillations.
Target Crystal Properties
Cload
ESR
—
—
10 pF
—
—
Usually crystals can be purchased tuned for different Cloads. This Cload
value is typically 1/2 of the capacitances realized on the PCB on either side
of the quartz. A higher Cload will decrease oscillation margin, but increases
current oscillating through the crystal.
50 kΩ
Equivalent series resistance of the crystal. Choosing a crystal with a higher
value will decrease the oscillating margin.
4.6
I/O DC Parameters
This section includes the DC parameters of the following I/O types:
•
•
Dual Voltage General Purpose I/O cell set (DVGPIO)
Double Data Rate I/O (DDR) for LPDDR2 and DDR3 modes
NOTE
The term OVDD in this section refers to the associated supply rail of an
input or output.
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Electrical Characteristics
ovdd
pmos (Rpu)
pad
Voh min
Vol max
1
or
pdat
0
Predriver
nmos (Rpd)
ovss
Figure 4. Circuit for Parameters Voh and Vol for I/O Cells
4.6.1
XTALI and RTC_XTALI (Clock Inputs) DC Parameters
Table 20 shows the DC parameters for the clock inputs.
Table 20. XTALI and RTC_XTALI DC Parameters
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
XTALI high-level DC input voltage
XTALI low-level DC input voltage
Vih
Vil
—
—
—
0.8 x NVCC_PLL_OUT — NVCC_PLL_ OUT
V
V
V
0
—
—
0.2V
1.11
RTC_XTALI high-level DC
input voltage
Vih
0.8
RTC_XTALI low-level DC
input voltage
Vil
—
0
—
0.2V
V
Input capacitance
CIN
Simulated data
—
—
5
—
pF
IXTALI_STARTUP
XTALI input leakage at startup
Power-on startup for
0.15 msec with a
driven 24 MHz RTC
clock @1.1 V. 2
—
600
μA
IXTALI_DC
DC input current
—
—
—
2.5
μA
1
This voltage specification must not be exceeded and, as such, is an absolute maximum specification.
This current draw is present even if an external clock source directly drives XTALI.
2
NOTE
The Vil and Vih specifications only apply when an external clock source is
used. If a crystal is used, Vil and Vih do not apply.
4.6.2
Dual Voltage General Purpose IO Cell Set (DVGPIO) DC Parameters
Table 21 shows DC parameters for GPIO pads. The parameters in Table 21 are guaranteed per the
operating ranges in Table 9, unless otherwise noted.
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Table 21. DVGPIO I/O DC Parameters
Parameter
Symbol
Test Conditions
Min
Max
Unit
High-level output voltage1
Voh
Vol
Ioh = -0.1 mA (DSE2 = 001, 010)
Ioh = -1 mA (DSE = 011, 100, 101, 110, 111)
OVDD – 0.15
—
V
Low-level output voltage1
Iol = 0.1 mA (DSE2 = 001, 010)
Iol = 1mA (DSE = 011, 100, 101, 110, 111)
—
0.15
V
High-Level DC input voltage 1, 3
Low-Level DC input voltage 1, 3
Input Hysteresis
Vih
Vil
—
—
0.7 × OVDD
OVDD
V
V
0
0.3 × OVDD
Vhys
OVDD = 1.8 V
OVDD = 3.3 V
0.25
—
V
Schmitt trigger VT+, 3, 4
VT+
VT–
Iin
—
—
0.5 × OVDD
—
0.5 × OVDD
1.25
V
V
Schmitt trigger VT–, 3, 4
—
-1.25
—
Input current (no pull-up/down)
Input current (22 kΩ pull-up)
Vin = OVDD or 0
μA
Iin
Vin = 0 V
Vin = OVDD
212
1
μA
μA
μA
μA
kΩ
Input current (47 kΩ pull-up)
Input current (100 kΩ pull-up)
Input current (100 kΩ pull-down)
Keeper circuit resistance
Iin
Iin
Vin = 0 V
Vin = OVDD
—
—
—
100
1
Vin = 0 V
Vin= OVDD
48
1
Iin
Vin = 0 V
Vin = OVDD
1
48
Rkeep
Vin = 0.3 x OVDD
Vin = 0.7 x OVDD
105
205
1
Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V,
and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must
be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other
methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device.
2
3
DSE is the Drive Strength Field setting in the associated IOMUX control register.
To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC
level through to the target DC level, Vil or Vih. Monotonic input transition time is from 0.1 ns to 1 s.
4
Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.
4.6.3
DDR I/O DC Parameters
The DDR I/O pads support LPDDR2 and DDR3 operational modes.
4.6.3.1 LPDDR2 Mode I/O DC Parameters
The parameters in Table 22 are guaranteed per the operating ranges in Table 9, unless otherwise noted. For
details on supported DDR memory configurations, see Section 4.9.4, “Multi-Mode DDR Controller
(MMDC)”.
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Electrical Characteristics
Parameters
1
Table 22. LPDDR2 I/O DC Electrical Parameters
Symbol
Test Conditions
Min
Max
Unit
High-level output voltage
Voh
Vol
Ioh = -0.1 mA
0.9 × OVDD
—
—
0.1 × OVDD
0.51 × OVDD
OVDD
V
V
Low-level output voltage
Iol = 0.1 mA
Input reference voltage
Vref
—
0.49 × OVDD
Vref+0.13V
OVSS
0.26
V
DC input High Voltage
Vih(dc)
Vil(dc)
Vih(diff)
Vil(diff)
Iin
—
V
DC input Low Voltage
—
Vref-0.13V
See Note 2
-0.26
V
Differential Input Logic High
Differential Input Logic Low
Input current (no pull-up/down)
Pull-up/pull-down impedance Mismatch
240 Ω unit calibration resolution
—
V
—
See Note 2
-2.5
V
Vin = 0 or OVDD
2.5
μA
%
Ω
kΩ
MMpupd
Rres
—
—
—
-15
+15
—
10
Keeper circuit resistance
Rkeep
110
175
1
Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document.
2
The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as
the limitations for overshoot and undershoot (see Table 26).
4.6.3.2
DDR3 Mode I/O DC Parameters
The parameters in Table 23 are guaranteed per the operating ranges in Table 9, unless otherwise noted. For
details on supported DDR memory configurations, see Section 4.9.4, “Multi-Mode DDR Controller
(MMDC)”.
1
Table 23. DDR3 I/O DC Electrical Parameters
Parameters
Symbol
Test Conditions
Min
Max
Unit
High-level output voltage
Voh
Ioh = -0.1 mA
Voh (DSE = 001)
0.8 × OVDD2
—
V
Ioh = -1 mA
Voh (for all except DSE = 001)
Low-level output voltage
Vol
Iol = 0.1 mA
Vol (DSE = 001)
—
0.2 × OVDD
V
Iol = 1 mA
Vol (for all except DSE = 001)
Input reference voltage
DC input Logic High
Vref3
Vih(dc)
Vil(dc)
Vih(diff)
Vil(diff)
Vtt
—
0.49 × OVDD 0.51 × OVDD
—
Vref+0.1
OVSS
OVDD
Vref-0.1
See Note4
-0.2
V
V
V
V
V
DC input Logic Low
—
Differential input Logic High
Differential input Logic Low
Termination Voltage
—
0.2
—
See Note4
Vtt tracking OVDD/2
0.49 × OVDD 0.51 × OVDD
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1
Table 23. DDR3 I/O DC Electrical Parameters (continued)
Parameters
Symbol
Test Conditions
Min
Max
Unit
Input current (no pull-up/down)
Pull-up/pull-down impedance mismatch
240 Ω unit calibration resolution
Keeper circuit resistance5
Iin
Vin = 0 or OVDD
-2.9
-10
—
2.9
10
μA
%
MMpupd
Rres
—
—
—
10
Ω
Rkeep
105
175
kΩ
1
Note that the JEDEC DDR3 specification (JESD79_3D) supersedes any specification in this document.
OVDD – I/O power supply (1.425 V – 1.575 V for DDR3
2
3
4
Vref – DDR3 external reference voltage
The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as
the limitations for overshoot and undershoot (see Table 27).
5
Use an off-chip pull resistor of 10 kΩ or less to override this keeper.
4.7
I/O AC Parameters
This section includes the AC parameters of the following I/O types:
•
•
•
General Purpose I/O (GPIO)
Dual Voltage General Purpose I/O (DVGPIO)
Double Data Rate I/O (DDR) for LPDDR2 and DDR3 modes
The GPIO and DDR I/O load circuit and output transition time waveforms are shown in Figure 5 and
Figure 6.
From Output
Under Test
Test Point
CL
CL includes package, probe and fixture capacitance
Figure 5. Load Circuit for Output
OVDD
0 V
80%
20%
80%
20%
Output (at pad)
tf
tr
Figure 6. Output Transition Time Waveform
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Electrical Characteristics
4.7.1
General Purpose I/O AC Parameters
The I/O AC parameters for GPIO in slow and fast modes are presented in the Table 24 and Table 25,
respectively. Note that the fast or slow I/O behavior is determined by the appropriate control bits in the
IOMUXC control registers.
Table 24. General Purpose I/O AC Parameters 1.8 V Mode
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output Pad Transition Times, rise/fall
(Max Drive, ipp_dse=111)
tr, tf
15 pF Cload, slow slew rate
15 pF Cload, fast slew rate
2.72/2.79
1.51/1.54
—
—
Output Pad Transition Times, rise/fall
(High Drive, ipp_dse=101)
tr, tf
tr, tf
tr, tf
trm
15 pF Cload, slow slew rate
15 pF Cload, fast slew rate
3.20/3.36
1.96/2.07
—
—
—
—
ns
ns
Output Pad Transition Times, rise/fall
(Medium Drive, ipp_dse=100)
15 pF Cload, slow slew rate
15 pF Cload, fast slew rate
3.64/3.88
2.27/2.53
Output Pad Transition Times, rise/fall
(Low Drive. ipp_dse=011)
15 pF Cload, slow slew rate
15 pF Cload, fast slew rate
4.32/4.50
3.16/3.17
—
—
—
—
Input Transition Times1
—
25
1
Hysteresis mode is recommended for inputs with transition times greater than 25 ns.
Table 25. General Purpose I/O AC Parameters 3.3 V Mode
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output Pad Transition Times, rise/fall
(Max Drive, ipp_dse=101)
tr, tf
15 pF Cload, slow slew rate
15 pF Cload, fast slew rate
1.70/1.79
1.06/1.15
—
—
Output Pad Transition Times, rise/fall
(High Drive, ipp_dse=011)
tr, tf
tr, tf
tr, tf
trm
15 pF Cload, slow slew rate
15 pF Cload, fast slew rate
2.35/2.43
1.74/1.77
—
—
—
—
ns
ns
Output Pad Transition Times, rise/fall
(Medium Drive, ipp_dse=010)
15 pF Cload, slow slew rate
15 pF Cload, fast slew rate
3.13/3.29
2.46/2.60
Output Pad Transition Times, rise/fall
(Low Drive. ipp_dse=001)
15 pF Cload, slow slew rate
15 pF Cload, fast slew rate
5.14/5.57
4.77/5.15
—
—
—
—
Input Transition Times1
—
25
1
Hysteresis mode is recommended for inputs with transition times greater than 25 ns.
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Electrical Characteristics
4.7.2
DDR I/O AC Parameters
Table 26 shows the AC parameters for DDR I/O operating in LPDDR2 mode. For details on supported
DDR memory configurations, see Section 4.9.4, “Multi-Mode DDR Controller (MMDC)”.
1
Table 26. DDR I/O LPDDR2 Mode AC Parameters
Parameter
AC input logic high
Symbol
Test Condition
Min
Typ
Max
Unit
Vih(ac)
Vil(ac)
—
Vref + 0.22
—
—
—
—
—
—
—
OVDD
Vref – 0.22
—
V
V
AC input logic low
—
0
0.44
—
AC differential input high voltage2
AC differential input low voltage
Input AC differential cross point voltage3
Over/undershoot peak
Vidh(ac)
Vidl(ac)
Vix(ac)
Vpeak
—
V
—
Relative to Vref
—
0.44
V
-0.12
—
0.12
V
0.35
V
Over/undershoot area (above OVDD
or below OVSS)
Varea
400 MHz
—
0.3
V-ns
Single output slew rate, measured
between Vol (ac) and Voh (ac)
tsr
50 Ω to Vref.
5 pF load.
Drive impedance = 4 0 Ω 30%
1.5
1
—
—
—
3.5
2.5
0.1
V/ns
ns
50 Ω to Vref.
5pF load.
Drive impedance = 60 Ω 30%
Skew between pad rise/fall asymmetry +
skew caused by SSN
tSKD
clk = 400 MHz
—
1
2
Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document.
Vid(ac) specifies the input differential voltage |Vtr – Vcp| required for switching, where Vtr is the “true” input signal and Vcp is
the “complementary” input signal. The Minimum value is equal to Vih(ac) – Vil(ac).
3
The typical value of Vix(ac) is expected to be about 0.5 × OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac)
indicates the voltage at which differential input signal must cross.
Table 27 shows the AC parameters for DDR I/O operating in DDR3 mode.
1
Table 27. DDR I/O DDR3 Mode AC Parameters
Parameter
AC input logic high
Symbol
Test Condition
Min
Typ
Max
Unit
Vih(ac)
Vil(ac)
Vid(ac)
Vix(ac)
Vpeak
Varea
—
Vref + 0.175
—
—
—
—
—
—
OVDD
Vref – 0.175
—
V
V
AC input logic low
—
0
0.35
AC differential input voltage2
Input AC differential cross point voltage3
Over/undershoot peak
—
Relative to Vref
—
V
Vref – 0.15
—
Vref + 0.15
0.4
V
V
Over/undershoot area (above OVDD
or below OVSS)
400 MHz
—
0.5
V-ns
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Electrical Characteristics
Parameter
1
Table 27. DDR I/O DDR3 Mode AC Parameters (continued)
Symbol
Test Condition
Min
Typ
Max
Unit
Single output slew rate, measured between
Vol (ac) and Voh (ac)
tsr
Driver impedance = 34 Ω
2.5
—
5
V/ns
Skew between pad rise/fall asymmetry +
skew caused by SSN
tSKD
clk = 400 MHz
0.1
ns
—
—
1
Note that the JEDEC JESD79_3C specification supersedes any specification in this document.
2
3
Vid(ac) specifies the input differential voltage |Vtr-Vcp| required for switching, where Vtr is the “true” input signal and Vcp is the
“complementary” input signal. The Minimum value is equal to Vih(ac) – Vil(ac).
The typical value of Vix(ac) is expected to be about 0.5 × OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac)
indicates the voltage at which differential input signal must cross.
4.8
Output Buffer Impedance Parameters
This section defines the I/O impedance parameters of the i.MX 6SoloLite processor for the following I/O
types:
•
•
Dual Voltage General Purpose I/O cell set (DVGPIO)
Double Data Rate I/O (DDR) for LPDDR2, and DDR3 modes
NOTE
GPIO and DDR I/O output driver impedance is measured with “long”
transmission line of impedance Ztl attached to I/O pad and incident wave
launched into transmission line. Rpu/Rpd and Ztl form a voltage divider that
defines specific voltage of incident wave relative to OVDD. Output driver
impedance is calculated from this voltage divider (see Figure 7).
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OVDD
PMOS (Rpu)
Ztl Ω, L = 20 inches
ipp_do
pad
predriver
Cload = 1p
NMOS (Rpd)
OVSS
U,(V)
VDD
Vin (do)
t,(ns)
0
U,(V)
Vout (pad)
OVDD
Vref2
Vref1
Vref
t,(ns)
0
Vovdd – Vref1
Vref1
Rpu =
Rpd =
× Ztl
× Ztl
Vref2
Vovdd – Vref2
Figure 7. Impedance Matching Load for Measurement
4.8.1
Dual Voltage GPIO Output Buffer Impedance
Table 28 shows the GPIO output buffer impedance (OVDD 1.8 V).
Table 28. DVGPIO Output Buffer Average Impedance (OVDD 1.8 V)
Parameter
Symbol
Drive Strength (ipp_dse)
Typ Value
Unit
001
010
011
100
101
110
111
262
134
88
62
51
Output Driver
Impedance
Rdrv
Ω
43
37
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Electrical Characteristics
Table 29 shows the GPIO output buffer impedance (OVDD 3.3 V).
Table 29. DVGPIO Output Buffer Average Impedance (OVDD 3.3 V)
Parameter
Symbol
Drive Strength (ipp_dse)
Typ Value
Unit
001
010
011
100
101
110
111
247
126
84
57
47
Output Driver
Impedance
Rdrv
Ω
40
34
4.8.2
DDR I/O Output Buffer Impedance
For details on supported DDR memory configurations, see Section 4.9.4, “Multi-Mode DDR Controller
(MMDC).”
Table 30 shows DDR I/O output buffer impedance of i.MX 6SoloLite processor.
Table 30. DDR I/O Output Buffer Impedance
Typical
NVCC_DRAM=1.5 V
(DDR3)
NVCC_DRAM=1.2 V
(LPDDR2)
Parameter
Symbol
Test Conditions
Unit
DDR_SEL=11
DDR_SEL=10
Drive Strength (DSE) =
000
001
010
011
100
101
110
111
Hi-Z
240
120
80
60
48
Hi-Z
240
120
80
60
48
Output Driver
Impedance
Rdrv
Ω
40
34
40
34
Note:
1. Output driver impedance is controlled across PVTs using ZQ calibration procedure.
2. Calibration is done against 240 W external reference resistor.
3. Output driver impedance deviation (calibration accuracy) is ±5% (max/min impedance) across PVTs.
4.9
System Modules Timing
This section contains the timing and electrical parameters for the modules in each i.MX 6SoloLite
processor.
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4.9.1
Reset Timings Parameters
Figure 8 shows the reset timing and Table 31 lists the timing parameters.
SRC_POR_B
(Input)
CC1
Figure 8. Reset Timing Diagram
Table 31. Reset Timing Parameters
ID
Parameter
Min
Max
Unit
CC1
Duration of POR_B to be qualified as valid.
1
—
XTALOSC_RTC_XTALI
4.9.2
WDOG Reset Timing Parameters
Figure 9 shows the WDOG reset timing and Table 32 lists the timing parameters.
WDOG_B
(Output)
CC3
Figure 9. WDOG_B Timing Diagram
Table 32. WDOG_B Timing Parameters
ID
Parameter
Min
Max
Unit
CC3
Duration of WDOG_B Assertion
1
—
RTC_XTALI cycle
NOTE
RTC_XTALI is approximately 32 kHz. RTC_XTALI cycle is one period or
approximately 30 μs.
NOTE
WDOG_B output signals (for each one of the Watchdog modules) do not have
dedicated bins, but are muxed out through the IOMUX. See the IOMUX
manual for detailed information.
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4.9.3
External Interface Module (EIM)
The following subsections provide information on the EIM. The maximum operating frequency for EIM
data transfer is 104 MHz. Timing parameters in this section that are given as a function of register settings
or clock periods are valid for the entire range of allowed frequencies (0–104 MHz).
4.9.3.1
EIM Interface Pads Allocation
EIM supports 32-bit, 16-bit, and 8-bit devices operating in address/data separate or multiplexed modes.
Table 33 provides EIM interface pads allocation in different modes.
1
Table 33. EIM Internal Module Multiplexing
Non Multiplexed Address/Data Mode
8 Bit 16 Bit
Multiplexed Address/Data mode
16 Bit
32 Bit
Setup
MUM = 0,
MUM = 0,
MUM = 0,
MUM = 1,
MUM = 1,
DSZ = 100
DSZ = 101
DSZ = 001
DSZ = 001
DSZ = 011
EIM_ADDR
[15:00]
EIM_AD
[15:00]
EIM_AD
[15:00]
EIM_AD
[15:00]
EIM_AD
[15:00]
EIM_AD
[15:00]
EIM_ADDR
[25:16]
EIM_ADDR
[25:16]
EIM_ADDR
[25:16]
EIM_ADDR
[25:16]
EIM_ADDR
[25:16]
EIM_DATA
[09:00]
EIM_DATA
[07:00],
EIM_DATA
[07:00]
—
EIM_DATA
[07:00]
EIM_AD
[07:00]
EIM_AD
[07:00]
EIM_EB0_B
EIM_DATA
[15:08],
EIM_EB1_B
—
—
—
EIM_DATA
[15:08]
EIM_DATA
[15:08]
EIM_AD
[15:08]
EIM_AD
[15:08]
EIM_DATA
[23:16],
EIM_EB2_B
—
—
—
—
—
—
EIM_DATA
[07:00]
EIM_DATA
[31:24],
EIM_DATA
[15:08]
EIM_EB3_B
1
For more information on configuration ports mentioned in this table, see the i.MX 6SololLite reference manual.
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4.9.3.2
General EIM Timing-Synchronous Mode
Figure 10, Figure 11, and Table 34 specify the timings related to the EIM module. All EIM output control
signals may be asserted and deasserted by an internal clock synchronized to the BCLK rising edge
according to corresponding assertion/negation control fields.
,
WE2
…
WE3
EIM_BCLK
WE1
WE4
WE6
WE5
WE7
WE9
EIM_ADDR
EIM_CSx_B
WE8
WE10
WE12
EIM_RW_B
EIM_OE_B
EIM_EBx_B
WE11
WE13
WE15
WE17
WE14
WE16
EIM_LBA_B
Output Data
Figure 10. EIM Output Timing Diagram
EIM_BCLK
WE18
Input Data
WE19
WE20
EIM_WAIT_B
WE21
Figure 11. EIM Input Timing Diagram
4.9.3.3
Examples of EIM Synchronous Accesses
Table 34. EIM Bus Timing Parameters
ID
Parameter
Min1
Max1
Unit
WE1
WE2
WE3
WE4
EIM_BCLK cycle time2
t × (k+1)
0.4 × t × (k+1)
—
ns
ns
ns
ns
EIM_BCLK high level width
EIM_BCLK low level width
Clock rise to address valid
—
0.4 × t × (k+1)
—
-0.5 × t × (k+1) -1.25
-0.5 × t × (k+1) +2.25
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Table 34. EIM Bus Timing Parameters (continued)
ID
Parameter
Clock rise to address invalid
Min1
Max1
Unit
WE5
WE6
WE7
WE8
WE9
0.5 × t × (k+1) -1.25
-0.5 × t × (k+1) -1.25
0.5 × t × (k+1) -1.25
-0.5 × t × (k+1) -1.25
0.5 × t × (k+1) -1.25
-0.5 × t × (k+1) -1.25
0.5 × t × (k+1) -1.25
0.5 × t × (k+1) -1.25
0.5 × t × (k+1) -1.25
-0.5 × t × (k+1) -1.25
0.5 × t × (k+1) -1.25
-0.5 × t × (k+1) -1.25
0.5 × t × (k+1) -1.25
2.3
0.5 × t × (k+1) +2.25
-0.5 × t × (k+1) +2.25
0.5 × t × (k+1) +2.25
-0.5 × t × (k+1) +2.25
0.5 × t × (k+1) +2.25
-0.5 × t × (k+1) +2.25
0.5 × t × (k+1) +2.25
-0.5 × t × (k+1) +2.25
0.5 × t × (k+1) +2.25
-0.5 × t × (k+1) +2.25
0.5 × t × (k+1) +2.25
-0.5 × t × (k+1) +2.25
0.5 × t × (k+1) +2.25
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock rise to EIM_CSx_B valid
Clock rise to EIM_CSx_B invalid
Clock rise to EIM_RW_B valid
Clock rise to EIM_RW_B invalid
WE10 Clock rise to EIM_OE_B valid
WE11 Clock rise to EIM_OE_B invalid
WE12 Clock rise to EIM_EBx_B valid
WE13 Clock rise to EIM_EBx_B invalid
WE14 Clock rise to EIM_LBA_B valid
WE15 Clock rise to EIM_LBA_B invalid
WE16 Clock rise to output data valid
WE17 Clock rise to output data invalid
WE18 Input data setup time to clock rise
WE19 Input data hold time from clock rise
WE20 EIM_WAIT_B setup time to clock rise
WE21 EIM_WAIT_B hold time from clock rise
2
—
2
—
2
—
1
2
k represents register setting BCD value
t is clock period (1/Freq). For 104 MHz, t = 9.165 ns
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Figure 12 to Figure 15 provide few examples of basic EIM accesses to external memory devices with the
timing parameters mentioned previously for specific control parameters settings.
EIM_BCLK
WE4
WE6
WE5
WE7
Address v1
Last Valid Address
EIM_ADDRxx
EIM_CSx_B
EIM_RW_B
WE14
WE10
WE12
WE15
WE18
EIM_LBA_B
EIM_OE_B
WE11
WE13
EIM_EBx_B
D(v1)
EIM_DATAxx
WE19
Figure 12. Synchronous Memory Read Access, WSC=1
EIM_BCLK
WE5
WE4
EIM_ADDRxx
Last Valid Address
Address V1
WE7
WE6
WE8
EIM_CSx_B
EIM_RW_B
WE9
WE14
EIM_LBA_B
EIM_OE_B
WE15
WE13
WE12
WE16
EIM_EBx_B
WE17
EIM_DATAxx
D(V1)
Figure 13. Synchronous Memory, Write Access, WSC=1, WBEA=0, and WADVN=0
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Electrical Characteristics
EIM_BCLK
WE16
WE17
WE5
WE4
Last Valid Address
WE6
EIM_ADDRxx/
EIM_DATAxx
Write Data
Address V1
WE7
WE9
EIM_CSx_B
WE8
EIM_RW_B
WE14
WE15
EIM_LBA_B
EIM_OE_B
WE10
WE11
EIM_EBx_B
Figure 14. Muxed Address/Data (A/D) Mode, Synchronous Write Access,
WSC=6, ADVA=0, ADVN=1, and ADH=1
NOTE
In 32-bit muxed address/data (A/D) mode the 16 MSBs are driven on the
data bus.
EIM_BCLK
WE4
WE5
Address V1
WE19
WE18
EIM_ADDRxx/ Last Valid
EIM_DATAxx
Data
Address
WE6
EIM_CSx_B
WE7
EIM_RW_B
EIM_LBA_B
EIM_OE_B
WE15
WE14
WE12
WE10
WE11
WE13
EIM_EBx_B
Figure 15. 16-Bit Muxed A/D Mode, Synchronous Read Access, WSC=7, RADVN=1, ADH=1, OEA=0
4.9.3.4
General EIM Timing-Asynchronous Mode
Figure 16 through Figure 20, and Table 35 help you determine timing parameters relative to the chip
select (CS) state for asynchronous and DTACK EIM accesses with corresponding EIM bit fields and the
timing parameters mentioned above.
Asynchronous read and write access length in cycles may vary from what is shown in Figure 16 through
Figure 19 as RWSC, OEN and CSN is configured differently. See the i.MX 6SoloLite reference manual
for the EIM programming model.
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end of
access
start of
access
Internal
clock
MAXCSO
EIM_CSx_B
WE32
WE31
EIM_ADDRxx/
EIM_DATAxx
Next Address
Last Valid Address
Address V1
EIM_RW_B
EIM_LBA_B
WE40
WE36
WE39
WE35
WE37
EIM_OE_B
WE38
WE44
EIM_EBx_B
MAXCO
EIM_DATA[7:0]
D(V1)
WE43
MAXDI
Figure 16. Asynchronous Memory Read Access (RWSC = 5)
start of
access
end of
access
internal
clock
MAXCSO
EIM_CSx_B
MAXDI
WE31
D(V1)
Addr. V1
WE32A
EIM_ADDRxx/
EIM_DATAxx
WE44
EIM_RW_B
EIM_LBA_B
WE40A
WE39
WE37
WE36
WE38
WE35A
EIM_OE_B
EIM_EBx_B
MAXCO
Figure 17. Asynchronous A/D Muxed Read Access (RWSC = 5)
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EIM_CSx_B
WE31
Last Valid Address
WE32
WE34
WE40
EIM_ADDRxx
Next Address
Address V1
WE33
EIM_RW_B
EIM_LBA_B
EIM_OE_B
WE39
WE45
WE41
WE46
EIM_EBx_B
EIM_DATAxx
WE42
D(V1)
Figure 18. Asynchronous Memory Write Access
EIM_CSx_B
WE41A
WE31
D(V1)
Addr. V1
WE32A
EIM_ADDRxx/
EIM_DATAxx
WE42
WE33
WE39
WE34
EIM_RW_B
WE40A
EIM_LBA_B
EIM_OE_B
WE45
WE46
EIM_EBx_B
Figure 19. Asynchronous A/D Muxed Write Access
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EIM_CSx_B
WE31
WE32
EIM_ADDRxx
Next Address
Last Valid Address
Address V1
EIM_RW_B
EIM_LBA_B
EIM_OE_B
WE39
WE35
WE37
WE40
WE36
WE38
EIM_EBx_B
WE44
WE48
EIM_DATA[7:0]
D(V1)
WE43
EIM_DTACK_B
WE47
Figure 20. DTACK Read Access (DAP=0)
EIM_CSx_B
WE31
WE32
EIM_ADDRxx
Next Address
Last Valid Address
Address V1
WE33
WE34
WE40
EIM_RW_B
EIM_LBA_B
EIM_OE_B
WE39
WE45
WE41
WE46
EIM_EBx_B
WE42
EIM_DATAxx
D(V1)
WE48
EIM_DTACK_B
WE47
Figure 21. DTACK Write Access (DAP=0)
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Table 35. EIM Asynchronous Timing Parameters Table Relative Chip Select
Determination by
Synchronous measured
parameters1
Reference
Number
Parameter
Min
Max
Unit
WE31
WE32
EIM_CSx_B valid to Address
Valid
WE4-WE6-CSA×t2
WE7-WE5-CSN×t3
t4+WE4-WE7+
-3.5-CSA×t
-3.5-CSN×t
3.5-CSA×t
3.5-CSN×t
ns
ns
Address Invalid to EIM_CSx_B
Invalid
WE32A
(muxed A/D) Invalid
EIM_CSx_B valid to Address
t - 3.5 + (ADVN + t + 3.5 + (ADVN + ADVA ns
(ADVN+ADVA+1-CSA2,5,6) ADVA + 1 - CSA)×t
×t
+ 1 - CSA)×t
WE33
WE34
WE35
WE35A
EIM_CSx_B Valid to
EIM_RW_WE_B Valid
WE8-WE6+(WEA-WCSA)
×t
3.5+(WEA-CSA)×t
ns
ns
ns
ns
-3.5+(WEA-WCS
A)×t
EIM_WE_B Invalid to
EIM_CSx_B Invalid
WE7-WE9+(WEN-WCSN)
×t
3.5-(WEN-WCSN)×t
3.5+(OEA-RCSA)×t
-3.5+(WEN-WCS
N)×t
EIM_CSx_B Valid to EIM_OE_B WE10-WE6+(OEA-RCSA)
Valid
-3.5+(OEA-RCS
A)×t
×t
EIM_CSx_B Valid to EIM_OE_B WE10-WE6+(OEA+RADV
-3.5 + (OEA +
3.5+(OEA+RADVN+
RADVA+ADH+1-
RCSA)×t
(muxed A/D) Valid
N+RADVA+ADH+1-RCSA) RADVN+RADVA+
×t
ADH+1-RCSA)×t
WE36
WE37
WE38
EIM_OE_B Invalid to
EIM_CSx_B Invalid
WE7-WE11+(OEN-RCSN)
×t
3.5+(OEN-RCSN)×t
ns
-3.5+(OEN-RCS
N)×t
WE12-WE6+(RBEA-
RCSA)×t
3.5+(RBEA7-RCSA)×t ns
EIM_CSx_B Valid to EIM_EBx_B
Valid (Read access)
-3.5+(RBEA- RC
SA)×t
EIM_EBx_B Invalid to
EIM_CSx_B Invalid (Read
access)
WE7-WE13+(RBEN-RCSN) -3.5+(RBEN-RCS 3.5+(RBEN-RCSN)×t
×t N)×t
ns
WE39
WE40
WE14-WE6+(ADVA-CSA)×t -3.5+(ADVA-CSA)
×t
3.5+(ADVA-CSA)×t
3.5-CSN×t
ns
ns
EIM_CSx_B Valid to EIM_LBA_B
Valid
EIM_LBA_B Invalid to
EIM_CSx_B Invalid (ADVL is
asserted)
WE7-WE15-CSN×t
-3.5-CSN×t
WE40A
(muxed A/D)
WE14-WE6+(ADVN+ADVA+
1-CSA)×t
ns
ns
EIM_CSx_B Valid to EIM_LBA_B
Invalid
-3.5+(ADVN+AD 3.5+(ADVN+ADVA
VA+1-CSA)×t
-3.5-WCSA×t
+1-CSA)×t
WE41
WE16-WE6-WCSA×t
3.5-WCSA×t
EIM_CSx_B Valid to Output Data
Valid
WE41A
EIM_CSx_B Valid to Output Data WE16-WE6+(WADVN+WAD -3.5+(WADVN+ 3.5+(WADVN+WADVA ns
(muxed A/D) Valid
VA+ADH+1-WCSA)×t
WADVA
+ADH+1-WCSA)
×t
+ADH+1-WCSA)×t
WE42
Output Data Invalid to
WE17-WE7-CSN×t
-3.5-CSN×t
3.5-CSN×t
ns
EIM_CSx_B
Invalid
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Table 35. EIM Asynchronous Timing Parameters Table Relative Chip Select (continued)
Determination by
Synchronous measured
parameters1
Reference
Number
Parameter
Min
Max
Unit
MAXCO Output maximum delay from
internal driving
10
—
10
ns
EIM_ADDRxx/control flip-flops to
chip outputs.
MAXCSO Output maximum delay from
internal chip selects driving
10
5
—
—
10
5
ns
ns
flip-flops to EIM_CSx_B out.
MAXDI
EIM_DATAxx MAXIMUM delay
from chip input data to its internal
flip-flop
WE43
WE44
WE45
WE46
Input Data Valid to EIM_CSx_B MAXCO-MAXCSO+MAXDI MAXCO-MAXCS
—
—
ns
ns
Invalid
O+MAXDI
EIM_CSx_B Invalid to Input Data
Invalid
0
0
EIM_CSx_B Valid to EIM_EBx_B
Valid (Write access)
WE12-WE6+(WBEA-
WCSA)×t
-3.5+(WBEA-
WCSA)×t
3.5+(WBEA-WCSA)×t ns
3.5+(WBEN-WCSN)×t ns
EIM_EBx_B Invalid to
EIM_CSx_B Invalid (Write
access)
WE7-WE13+(WBEN-
WCSN)×t
-3.5+(WBEN-WC
SN)×t
MAXDTI Maximum delay from
EIM_DTACK_B input to its
internal flip-flop + 2 cycles for
synchronization
10
—
10
ns
WE47
EIM_DTACK_B Active to
EIM_CSx_B Invalid
MAXCO-MAXCSO+MAXDTI
0
—
—
ns
ns
MAXCO-MAXCS
O+MAXDTI
WE48
EIM_CSx_B Invalid to
EIM_DTACK_B invalid
0
1
2
3
4
5
6
7
For more information on configuration parameters mentioned in this table, see the i.MX 6SoloLite reference manual.
CSA means register setting for WCSA when in write operations or RCSA when in read operations.
CSN means register setting for WCSN when in write operations or RCSN when in read operations.
t means clock period from axi_clk frequency.
ADVA means register setting for WADVA when in write operations or RADVA when in read operations.
ADVN means register setting for WADVN when in write operations or RADVN when in read operations.
BEAssertion.ThisbitfielddetermineswhenBEsignalisassertedduringreadcycles.
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4.9.4
Multi-Mode DDR Controller (MMDC)
The Multi-mode DDR Controller is a dedicated interface to DDR3/LPDDR2 SDRAM.
4.9.4.1
MMDC Compatibility with JEDEC-Compliant SDRAMs
The i.MX 6SoloLite MMDC is compatible with the following JEDEC-compliant memory types:
•
•
LPDDR2 SDRAM compliant to JESD209-2B LPDDR2 JEDEC standard release June, 2009
DDR3 SDRAM compliant to JESD79-3D DDR3 JEDEC standard release April, 2008
MMDC operation with the standards stated above is contingent upon the board DDR design adherence to
the DDR design and layout requirements stated in the Hardware Development Guide for i.MX 6SoloLite
Applications Processors (IMXSLHDG).
4.9.4.2
MMDC Supported DDR3/LPDDR2 Configurations
Table 36 shows the supported DDR3/LPDDR2 configurations.
Table 36. i.MX 6SoloLite Supported DDR3/LPDDR2 Configurations
Parameter
LPDDR2
DDR3
Clock frequency
Bus width
400 MHz
16-/32-bit
Single
2
400 MHz
16-/32-bit
Single
2
Channel
Chip selects
4.10 External Peripheral Interface Parameters
The following subsections provide information on external peripheral interfaces.
4.10.1 AUDMUX Timing Parameters
The AUDMUX provides a programmable interconnect logic for voice, audio, and data routing between
internal serial interfaces (SSIs) and external serial interfaces (audio and voice codecs). The AC timing of
AUDMUX external pins is governed by the SSI module. For more information, see the respective SSI
electrical specifications found within this document.
4.10.2 CMOS Sensor Interface (CSI) Timing Parameters
4.10.2.0.1 Gated Clock Mode Timing
Figure 22 and Figure 23 shows the gated clock mode timings for CSI, and Table 37 describes the timing
parameters (P1–P7) shown in the figures. A frame starts with a rising/falling edge on CSI_VSYNC
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(VSYNC), then CSI_HSYNC (HSYNC) is asserted and holds for the entire line. The pixel clock,
CSI_PIXCLK (PIXCLK), is valid as long as HSYNC is asserted.
CSI_VSYNC
P1
CSI_HSYNC
P7
P2
P5 P6
CSI_PIXCLK
P3 P4
CSI_DATA[15:00]
Figure 22. CSI Gated Clock Mode—Sensor Data at Falling Edge, Latch Data at Rising Edge
CSI_VSYNC
P1
CSI_HSYNC
P7
P2
P6 P5
CSI_PIXCLK
P3 P4
CSI_DATA[15:00]
Figure 23. CSI Gated Clock Mode—Sensor Data at Rising Edge, Latch Data at Falling Edge
Table 37. CSI Gated Clock Mode Timing Parameters
ID
Parameter
Symbol
Min
Max
Units
P1
P2
P3
CSI_VSYNC to CSI_HSYNC time
CSI_HSYNC setup time
CSI DATA setup time
tV2H
tHsu
tDsu
67.5
2
—
—
—
ns
ns
ns
2.5
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Table 37. CSI Gated Clock Mode Timing Parameters (continued)
ID
Parameter
CSI DATA hold time
Symbol
Min
Max
Units
P4
P5
P6
P7
tDh
1.2
7.5
7.5
—
—
—
—
66
ns
ns
CSI pixel clock high time
CSI pixel clock low time
CSI pixel clock frequency
tCLKh
tCLKl
fCLK
ns
MHz
4.10.2.0.2 Ungated Clock Mode Timing
Figure 24 shows the ungated clock mode timings of CSI, and Table 38 describes the timing parameters
(P1–P6) that are shown in the figure. In ungated mode the CSI_VSYNC and CSI_PIXCLK signals are
used, and the CSI_HSYNC signal is ignored.
CSI_VSYNC
P1
P6
P4 P5
CSI_PIXCLK
P2 P3
CSI_DATA[15:00]
Figure 24. CSI Ungated Clock Mode—Sensor Data at Falling Edge, Latch Data at Rising Edge
Table 38. CSI Ungated Clock Mode Timing Parameters
ID
Parameter
Symbol
Min
Max
Units
P1
P2
P3
P4
P5
P6
CSI_VSYNC to pixel clock time
CSI DATA setup time
tVSYNC
tDsu
67.5
2.5
1.2
7.5
7.5
—
—
—
—
—
—
66
ns
ns
CSI DATA hold time
tDh
ns
CSI pixel clock high time
CSI pixel clock low time
CSI pixel clock frequency
tCLKh
tCLKl
fCLK
ns
ns
MHz
The CSI enables the chip to connect directly to external CMOS image sensors, which are classified as
dumb or smart as follows:
•
Dumb sensors only support traditional sensor timing (vertical sync (VSYNC) and horizontal sync
(HSYNC)) and output-only Bayer and statistics data.
•
Smart sensors support CCIR656 video decoder formats and perform additional processing of the
image (for example, image compression, image pre-filtering, and various data output formats).
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The following subsections describe the CSI timing in gated and ungated clock modes.
4.10.3 ECSPI Timing Parameters
This section describes the timing parameters of the ECSPI block. The ECSPI has separate timing
parameters for master and slave modes.
4.10.3.1 ECSPI Master Mode Timing
Figure 25 depicts the timing of ECSPI in master mode and Table 39 lists the ECSPI master mode timing
characteristics.
ECSPIx_RDY
CS10
ECSPIx_SSx
CS5
CS6
CS2
CS1
CS3
CS4
ECSPIx_SCLK
ECSPIx_MOSI
CS2
CS7
CS3
CS9
CS8
ECSPIx_MISO
Figure 25. ECSPI Master Mode Timing Diagram
NOTE
ECSPIx_MOSI is always driven (not tri-stated) between actual data
transmissions. This limits the ECSPI to be connected between a single
master and a single slave.
Table 39. ECSPI Master Mode Timing Parameters
ID
Parameter
Symbol
Min
Max Unit
CS1 ECSPIx_SCLK Cycle Time–Read
• Slow group1
tclk
—
ns
46
40
15
• Fast group2
ECSPIx_SCLK Cycle Time–Write
CS2 ECSPIx_SCLK High or Low Time–Read
• Slow group1
tSW
—
ns
22
20
7
• Fast group2
ECSPIx_SCLK High or Low Time–Write
CS3 ECSPIx_SCLK Rise or Fall3
CS4 ECSPIx_SSx pulse width
tRISE/FALL
tCSLH
—
—
—
—
ns
ns
ns
Half ECSPIx period
CS5 ECSPIx_SSx Lead Time (CS setup time)
tSCS
Half ECSPIx_SCLK period - 4
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Table 39. ECSPI Master Mode Timing Parameters (continued)
ID
Parameter
Symbol
Min
Max Unit
CS6 ECSPIx_SSx Lag Time (CS hold time)
tHCS
tPDmosi
tSmiso
Half ECSPI_SCLK period - 2
-0.5
—
2
ns
ns
ns
CS7 ECSPIx_MOSI Propagation Delay (CLOAD = 20 pF)
CS8 ECSPIx_MISO Setup Time
• Slow group1
—
14
12
—
• Fast group2
CS9 ECSPIx_MISO Hold Time
tHmiso
tSDRY
0
5
—
—
ns
ns
CS10 ECSPIx_RDY to ECSPIx_SSx Time4
1
2
ECSPI slow group includes:
ECSPI2/EPDC_SDLE, ECSPI3/EPDC_D9, ECSPI4/EPDC_D1
ECSPI fast group includes:
ECSPI1/LCD_DATA01, ECSPI1/ECSPI1_MISO, ECSPI2/LCD_DATA10, ECSPI2/ECSPI2_MISO, ECSPI3/AUDx_TXC,
ECSPI3/SD2_DAT1, ECSPI4/KEY_ROW1, ECSPI4/FEC_RX_DV
3
4
See specific I/O AC parameters Section 4.7, “I/O AC Parameters.”
ECSPIx_RDY is sampled internally by ipg_clk and is asynchronous to all other eCSPI signals.
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4.10.3.2 ECSPI Slave Mode Timing
Figure 26 depicts the timing of ECSPI in slave mode and Table 40 lists the ECSPI slave mode timing
characteristics.
CS5
CS6
CS2
CS1
ECSPIx_SSx
CS4
CS2
ECSPIx_SCLK
CS9
ECSPIx_MISO
CS7
CS8
ECSPIx_MOSI
Figure 26. ECSPI Slave Mode Timing Diagram
NOTE
ECSPIx_MISO is always driven (not tri-stated) between actual data
transmissions. This limits the ECSPI to be connected between a single
master and a single slave.
Table 40. ECSPI Slave Mode Timing Parameters
ID
Parameter
Symbol
Min
Max
Unit
CS1
CS2
ECSPIx_SCLK Cycle Time–Read
ECSPIx_SCLK Cycle Time–Write
tclk
40
15
—
—
ns
ECSPIx_SCLK High or Low Time–Read
ECSPIx_SCLK High or Low Time–Write
tSW
20
7
ns
CS4
CS5
CS6
CS7
CS8
CS9
ECSPIx_SSx pulse width
tCSLH
tSCS
Half SCLK period
—
—
—
—
—
17
ns
ns
ns
ns
ns
ns
ECSPIx_SSx Lead Time (CS setup time)
ECSPIx_SSx Lag Time (CS hold time)
ECSPIx_MOSI Setup Time
5
5
4
4
4
tHCS
tSmosi
tHmosi
tPDmiso
ECSPIx_MOSI Hold Time
ECSPIx_MISO Propagation Delay (CLOAD = 20 pF)
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4.10.4 Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC) AC
Timing
This section describes the electrical information of the uSDHC, which includes SD/eMMC4.3 (Single
Data Rate) timing and eMMC4.4/4.41 (Dual Date Rate) timing.
4.10.4.1 SD/eMMC4.3 (Single Data Rate) AC Timing Parameters
Figure 27 depicts the timing of SD/eMMC4.3, and Table 41 lists the SD/eMMC4.3 timing characteristics.
SD4
SD2
SD5
SD1
SDx_CLK
SD3
SD6
Output from uSDHC to card
SDx_DATA[7:0]
SD7
SD8
Input from card to uSDHC
SDx_DATA[7:0]
Figure 27. SD/eMMC4.3 Timing Diagram
Table 41. SD/eMMC4.3 Interface Timing Parameters
ID
Parameter
Symbols
Min
Max
Unit
Card Input Clock1
2
SD1
Clock Frequency (Low Speed)
fPP
0
0
400
25/50
20/52
400
—
kHz
MHz
MHz
kHz
ns
3
Clock Frequency (SD/SDIO Full Speed/High Speed)
Clock Frequency (MMC Full Speed/High Speed)
Clock Frequency (Identification Mode)
Clock Low Time
fPP
4
fPP
0
fOD
tWL
tWH
100
7
SD2
SD3
Clock High Time
7
—
ns
eSDHC Output/Card Inputs SDx_CMD, SDx_DATAx (Reference to CLK)
eSDHC Output Delay tOD –6.6
eSDHC Input/Card Outputs SDx_CMD, SDx_DATAx (Reference to CLK)
SD6
3.6
ns
SD7
SD8
eSDHC Input Setup Time
eSDHC Input Hold Time5
tISU
tIH
2.5
1.5
—
—
ns
ns
1
2
3
Clock duty cycle will be in the range of 47% to 53%.
In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.
In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz. In high-speed mode,
clock frequency can be any value between 0–50 MHz.
4
In normal (full) speed mode for MMC card, clock frequency can be any value between 0–20 MHz. In high-speed mode, clock
frequency can be any value between 0–52 MHz.
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5To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.
4.10.4.2 eMMC4.4/4.41 (Dual Data Rate) eSDHCv3 AC Timing Parameters
Figure 28 depicts the timing of eMMC4.4/4.41. Table 42 lists the eMMC4.4/4.41 timing characteristics.
Be aware that only SDx_DATAx is sampled on both edges of the clock (not applicable to SDx_CMD).
SD1
SDx_CLK
SD2
SD2
Output from eSDHCv3 to card
SDx_DATA[7:0]
… …
… …
SD3
SD4
Input from card to eSDHCv3
SDx_DATA[7:0]
Figure 28. eMMC4.4/4.41 Timing Diagram
Table 42. eMMC4.4/4.41 Interface Timing Parameters
ID
Parameter
Symbols
Min
Max
Unit
Card Input Clock
SD1
SD1
Clock Frequency (eMMC4.4/4.41 DDR)
Clock Frequency (SD3.0 DDR)
fPP
fPP
0
0
52
50
MHz
MHz
uSDHC Output / Card Inputs SD_CMD, SD_DATAx (Reference to CLK)
uSDHC Output Delay tOD 2.5 7.1
uSDHC Input / Card Outputs SD_CMD, SD_DATAx (Reference to CLK)
SD2
ns
SD3
SD4
uSDHC Input Setup Time
uSDHC Input Hold Time
tISU
tIH
1.7
1.5
—
—
ns
ns
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4.10.4.3 SDR50/SDR104 AC Timing Parameters
Figure 29 depicts the timing of SDR50/SDR104, and Table 43 lists the SDR50/SDR104 timing
characteristics.
Figure 29. SDR50/SDR104 Timing Diagram
Table 43. SDR50/SDR104 Interface Timing Parameters
ID
Parameter
Symbols
Min
Max
Unit
Card Input Clock
SD1
SD2
SD3
Clock Frequency Period
Clock Low Time
tCLK
tCL
4.8
—
ns
ns
ns
0.46 × tCLK
0.46 × tCLK
0.54 × tCLK
0.54 × tCLK
Clock High Time
tCH
uSDHC Output/Card Inputs SD_CMD, SD_DATAx in SDR50 (Reference to CLK)
uSDHC Output Delay tOD –3
SD4
SD5
1
ns
ns
uSDHC Output/Card Inputs SD_CMD, SD_DATAx in SDR104 (Reference to CLK)
uSDHC Output Delay1
tOD
–1.6
0.74
uSDHC Input/Card Outputs SD_CMD, SD_DATAx in SDR50 (Reference to CLK)
uSDHC Input Setup Time
uSDHC Input Hold Time
tISU
tIH
2.5
1.5
—
—
ns
ns
SD6
SD7
uSDHC Input/Card Outputs SD_CMD, SD_DATAx in SDR104 (Reference to CLK)2
Card Output Data Window tODW 0.5 × tCLK
—
ns
SD8
1
2
If using KEY_COL1, KEY_ROW1, KEY_COL2 and KEY_ROW2 for SD3_DATA4–SD3_DATA7, note the difference
in timing: tod minimum is -1.1 and tod maximum is 1.5.
Data window in SDR100 mode is variable.
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4.10.5 HS200 Mode Timing Parameters
Figure 30 depicts the timing of HS200 mode, and Table 44 lists the HS200 timing characteristics.
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6'ꢆ
6'ꢇ
6&.
SD5
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ꢀꢁELWꢂLQSXWꢂIURPꢂH00&ꢂWRꢂX6'+&
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Figure 30. HS200 Mode Timing Diagram
Table 44. HS200 Interface Timing Parameters
ID
Parameter
Symbols
Min
Max
Unit
Card Input Clock
SD1
SD2
SD3
Clock Frequency Period
Clock Low Time
tCLK
tCL
5
—
ns
ns
ns
0.46 × tCLK
0.46 × tCLK
0.54 × tCLK
0.54 × tCLK
Clock High Time
tCH
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)
uSDHC Output Delay Setup Time tOD -1.6 0.74
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)1
Card Output Data Window tODW 0.5 × tCLK
ns
ns
SD5
—
SD8
1
HS200 is for 8 bits while SDR104 is for 4 bits.
4.10.6 FEC AC Timing Parameters
This section describes the electrical information of the Fast Ethernet Controller (FEC) module. The FEC
is designed to support both 10 and 100 Mbps Ethernet/IEEE 802.3 networks. An external transceiver
interface and transceiver function are required to complete the interface to the media. The FEC supports
the 10/100 Mbps RMII (10 pins in total) and the 10 Mbps (only 7-wire interface, which uses 7 of the RMII
pins), for connection to an external Ethernet transceiver. For the pin list of RMII and 7-wire, see the i.MX
6SoloLite Reference Manual.
This section describes the AC timing specifications of the FEC. The RMII signals are compatible with
transceivers operating at a voltage of 3.3 V.
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Electrical Characteristics
4.10.6.1 RMII Mode Timing Parameters
In RMII mode, FEC_TX_CLK is used as the REF_CLK which is a 50 MHz ±50 ppm continuous reference
clock. FEC_RX_DV is used as the CRS_DV in RMII, and other signals under RMII mode include
FEC_TX_EN, FEC_TX_DATA[1:0], FEC_RX_DATA[1:0] and optional FEC_RX_ER.
The RMII mode timing parameters are shown in Figure 31 and Table 45.
M16
M17
REF_CLK (input)
M18
FEC_TX_DATA[1:0] (output)
FEC_TX_EN
M19
FEC_RX_DV (input)
FEC_RX_DATA[1:0]
FEC_RX_ER
M20
M21
Figure 31. RMII Mode Signal Timing Diagram
Table 45. RMII Signal Timing Parameters
No.
Characteristics1
Min
Max
Unit
M16
M17
M18
M19
M20
REF_CLK(FEC_TX_CLK) pulse width high
35%
35%
2
65%
65%
—
REF_CLK period
REF_CLK(FEC_TX_CLK) pulse width low
REF_CLK period
REF_CLK to FEC_TX_DATA[1:0], FEC_TX_EN invalid
REF_CLK to FEC_TX_DATA[1:0], FEC_TX_EN valid
ns
ns
ns
—
16
FEC_RX_DATA[1:0], CRS_DV(FEC_RX_DV),
FEC_RX_ER to REF_CLK setup
4
—
M21
REF_CLK to FEC_RX_DATA[1:0], FEC_RX_DV,
FEC_RX_ER hold
2
—
ns
1
Test conditions: 25pF on each output signal.
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Electrical Characteristics
4.10.7 I2C Module Timing Parameters
2
2
This section describes the timing parameters of the I C module. Figure 32 depicts the timing of I C
2
module, and Table 46 lists the I C module timing characteristics.
I2Cx_SDA
IC11
IC9
IC10
IC7
IC4
IC2
IC3
IC8
I2Cx_SCL
IC10
IC6
IC11
STOP
START
START
START
IC5
IC1
2
Figure 32. I C Bus Timing Diagram
2
Table 46. I C Module Timing Parameters
Standard Mode
Fast Mode
ID
Parameter
Unit
Min
Max
Min
Max
IC1
IC2
I2Cx_SCL cycle time
10
4.0
4.0
01
—
—
2.5
0.6
0.6
01
—
—
—
µs
µs
µs
Hold time (repeated) START condition
Set-up time for STOP condition
IC3
—
IC4
Data hold time
3.452
—
0.92 µs
IC5
HIGH Period of I2Cx_SCL
4.0
4.7
4.7
250
4.7
—
0.6
1.3
0.6
1003
1.3
—
—
—
—
—
µs
µs
µs
ns
µs
IC6
LOW Period of the I2Cx_SCL
—
IC7
Set-up time for a repeated START condition
Data set-up time
—
IC8
—
IC9
Bus free time between a STOP and START condition
Rise time of both I2Cx_SDA and I2Cx_SCL signals
Fall time of both I2Cx_SDA and I2Cx_SCL signals
Capacitive load for each bus line (Cb)
—
4
IC10
IC11
IC12
1000
300
400
20 + 0.1Cb 300 ns
4
—
20 + 0.1Cb 300 ns
—
—
400 pF
1
A device must internally provide a hold time of at least 300 ns for I2Cx_SDA signal in order to bridge the undefined region of
the falling edge of I2Cx_SCL.
2
3
The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2Cx_SCL signal.
A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement of Set-up time (ID No IC7)
of 250 ns must be met. This automatically is the case if the device does not stretch the LOW period of the I2Cx_SCL signal.
If such a device does stretch the LOW period of the I2Cx_SCL signal, it must output the next data bit to the I2Cx_SDA line
max_rise_time (IC9) + data_setup_time (IC7) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification)
before the I2Cx_SCL line is released.
4
Cb = total capacitance of one bus line in pF.
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Electrical Characteristics
4.10.8 Pulse Width Modulator (PWM) Timing Parameters
This section describes the electrical information of the PWM. The PWM can be programmed to select one
of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before
being input to the counter. The output is available at the pulse-width modulator output (PWMx_OUT)
external pin (see external signals table in the i.MX 6SoloLite reference manual for PWM pin assignments).
Figure 33 depicts the timing of the PWM, and Table 47 lists the PWM timing parameters.
1
2a
3b
System Clock
2b
4b
3a
4a
PWM Output
Figure 33. PWM Timing Diagram
Table 47. PWM Output Timing Parameters
Reference Number
Parameter
Min
Max
Unit
1
System CLK frequency1
Clock high time
0
ipg_clk
—
MHz
ns
2a
2b
12.29
9.91
Clock low time
—
ns
1
CL of PWMx_OUT = 30 pF
4.10.9 SCAN JTAG Controller (SJC) Timing Parameters
Figure 34 depicts the SJC test clock input timing. Figure 35 depicts the SJC boundary scan timing.
Figure 36 depicts the SJC test access port. Signal parameters are listed in Table 48.
SJ1
SJ2
VM
SJ2
VM
JTAG_TCK
(Input)
VIH
VIL
SJ3
Figure 34. Test Clock Input Timing Diagram
SJ3
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Electrical Characteristics
JTAG_TCK
(Input)
VIH
SJ5
Input Data Valid
VIL
SJ4
Data
Inputs
SJ6
Data
Outputs
Output Data Valid
SJ7
SJ6
Data
Outputs
Data
Outputs
Output Data Valid
Figure 35. Boundary Scan (JTAG) Timing Diagram
JTAG_TCK
(Input)
VIH
VIL
SJ8
Input Data Valid
SJ9
JTAG_TDI
JTAG_TMS
(Input)
SJ10
SJ11
SJ10
JTAG_TDO
(Output)
Output Data Valid
JTAG_TDO
(Output)
JTAG_TDO
(Output)
Output Data Valid
Figure 36. Test Access Port Timing Diagram
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Electrical Characteristics
JTAG_TCK
(Input)
SJ13
JTAG_TRSTB
(Input)
SJ12
Figure 37. TRST Timing Diagram
Table 48. JTAG Timing Parameters
All Frequencies
Min Max
ID
Parameter1,2
Unit
1
SJ0
SJ1
JTAG_TCK frequency of operation 1/(3•TDC
JTAG_TCK cycle time in crystal mode
)
0.001
45
22.5
—
22
—
—
3
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
SJ2
JTAG_TCK clock pulse width measured at VM
JTAG_TCK rise and fall times
SJ3
SJ4
Boundary scan input data set-up time
Boundary scan input data hold time
JTAG_TCK low to output data valid
JTAG_TCK low to output high impedance
JTAG_TMS, JTAG_TDI data set-up time
JTAG_TMS, JTAG_TDI data hold time
JTAG_TCK low to JTAG_TDO data valid
5
—
—
40
40
—
—
44
44
—
—
SJ5
24
—
SJ6
SJ7
—
SJ8
5
SJ9
25
—
SJ10
SJ11
SJ12
SJ13
JTAG_TCK low to JTAG_TDO high impedance
JTAG_TRSTB assert time
—
100
40
JTAG_TRSTB set-up time to JTAG_TCK low
1
2
T
= target frequency of SJC
DC
VM = mid-point voltage
4.10.10 SPDIF Timing Parameters
The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase marking code. When
encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal.
Table 49, Figure 38, and Figure 39 show SPDIF timing parameters for the Sony/Philips Digital
Interconnect Format (SPDIF), including the timing of the modulating Rx clock (SPDIF_SR_CLK) for
SPDIF in Rx mode and the timing of the modulating Tx clock (SPDIF_ST_CLK) for SPDIF in Tx mode.
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Electrical Characteristics
Table 49. SPDIF Timing Parameters
Symbol
Timing Parameter Range
Characteristics
Unit
Min
Max
SPDIF_IN Skew: asynchronous inputs, no specs apply
—
—
0.7
ns
SPDIF_OUT output (Load = 50pf)
• Skew
• Transition rising
• Transition falling
—
—
—
—
—
—
1.5
24.2
31.3
ns
ns
SPDIF_OUT output (Load = 30pf)
• Skew
• Transition rising
• Transition falling
—
—
—
—
—
—
1.5
13.6
18.0
Modulating Rx clock (SPDIF_SR_CLK) period
SPDIF_SR_CLK high period
srckp
srckph
srckpl
stclkp
stclkph
stclkpl
40.0
16.0
16.0
40.0
16.0
16.0
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
SPDIF_SR_CLK low period
Modulating Tx clock (SPDIF_ST_CLK) period
SPDIF_ST_CLK high period
SPDIF_ST_CLK low period
srckp
srckpl
VM
srckph
VM
SPDIF_SR_CLK
(Output)
Figure 38. SRCK Timing Diagram
stclkp
stclkpl
VM
stclkph
VM
SPDIF_ST_CLK
(Input)
Figure 39. STCLK Timing Diagram
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Electrical Characteristics
4.10.11 SSI Timing Parameters
This section describes the timing parameters of the SSI module. The connectivity of the serial
synchronous interfaces are summarized in Table 50.
Table 50. AUDMUX Port Allocation
Port
Signal Nomenclature
Type and Access
AUDMUX port 1
AUDMUX port 2
AUDMUX port 3
AUDMUX port 4
AUDMUX port 5
AUDMUX port 6
AUDMUX port 7
SSI 1
SSI 2
AUD3
AUD4
AUD5
AUD6
SSI 3
Internal
Internal
External – AUD3 I/O
External – I2C2 and LCD, or ECSPI1, or SD2 I/O through IOMUXC
External – EPDC or SD3 I/O through IOMUXC
External – FEC or KEY_ROW and KEY_COL through IOMUXC
Internal
NOTE
The terms WL and BL used in the timing diagrams and tables refer to Word
Length (WL) and Bit Length (BL).
4.10.11.1 SSI Transmitter Timing with Internal Clock
Figure 40 depicts the SSI transmitter internal clock timing and Table 51 lists the timing parameters for
the SSI transmitter internal clock.
.
SS1
SS3
SS5
SS4
SS2
AUDx_TXC
(Output)
SS8
SS6
AUDx_TXFS (bl)
(Output)
SS10
SS12
SS14
SS17
AUDx_TXFS (wl)
(Output)
SS15
SS16
SS18
AUDx_TXD
(Output)
SS43
SS42
SS19
AUDx_RXD
(Input)
Note: AUDx_RXD input in synchronous mode only
Figure 40. SSI Transmitter Internal Clock Timing Diagram
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Electrical Characteristics
Table 51. SSI Transmitter Timing with Internal Clock
ID
Parameter
Internal Clock Operation
Min
Max
Unit
SS1
SS2
AUDx_TXC/AUDx_RXC clock period
81.4
36.0
36.0
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AUDx_TXC/AUDx_RXC clock high period
AUDx_TXC/AUDx_RXC clock low period
—
SS4
—
SS6
AUDx_TXC high to AUDx_TXFS (bl) high
AUDx_TXC high to AUDx_TXFS (bl) low
15.0
15.0
15.0
15.0
6.0
SS8
—
SS10
SS12
SS14
SS15
SS16
SS17
SS18
AUDx_TXC high to AUDx_TXFS (wl) high
AUDx_TXC high to AUDx_TXFS (wl) low
—
—
AUDx_TXC/AUDx_RXC Internal AUDx_TXFS rise time
AUDx_TXC/AUDx_RXC Internal AUDx_TXFS fall time
AUDx_TXC high to AUDx_TXD valid from high impedance
AUDx_TXC high to AUDx_TXD high/low
—
—
6.0
—
15.0
15.0
15.0
—
AUDx_TXC high to AUDx_TXD high impedance
—
Synchronous Internal Clock Operation
SS42
SS43
AUDx_RXD setup before AUDx_TXC falling
AUDx_RXD hold after AUDx_TXC falling
10.0
0.0
—
—
ns
ns
NOTE
•
All the timings for the SSI are given for a non-inverted serial clock
polarity (TXC/RXC = 0) and a non-inverted frame sync (TXFS/RXFS
= 0). If the polarity of the clock and/or the frame sync have been
inverted, all the timing remains valid by inverting the clock signal
TXC/RXC and/or the frame sync TXFS/RXFS shown in the tables and
in the figures.
•
•
•
All timings are on Audiomux Pads when SSI is used for data transfer.
The terms, WL and BL, refer to Word Length(WL) and Bit Length(BL).
For internal Frame Sync operation using external clock, the FS timing is
same as that of TXD (for example, during AC97 mode of operation).
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Electrical Characteristics
4.10.11.2 SSI Receiver Timing with Internal Clock
Figure 41 depicts the SSI receiver internal clock timing and Table 52 lists the timing parameters for the
receiver timing with the internal clock.
SS1
SS3
SS5
SS4
SS2
AUDx_TXC
(Output)
SS9
SS7
AUDx_TXFS (bl)
(Output)
SS11
SS13
AUDx_TXFS (wl)
(Output)
SS20
SS21
AUDx_RXD
(Input)
SS51
SS50
SS47
SS49
SS48
AUDx_RXC
(Output)
Figure 41. SSI Receiver Internal Clock Timing Diagram
Table 52. SSI Receiver with Internal Clock Timing Parameters
ID
Parameter
Internal Clock Operation
Min
Max
Unit
SS1
SS2
AUDx_TXC/AUDx_RXC clock period
81.4
36.0
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AUDx_TXC/AUDx_RXC clock high period
AUDx_TXC/AUDx_RXC clock rise time
AUDx_TXC/AUDx_RXC clock low period
AUDx_TXC/AUDx_RXC clock fall time
AUDx_RXC high to AUDx_TXFS (bl) high
AUDx_RXC high to AUDx_TXFS (bl) low
AUDx_RXC high to AUDx_TXFS (wl) high
AUDx_RXC high to AUDx_TXFS (wl) low
AUDx_RXD setup time before AUDx_RXC low
AUDx_RXD hold time after AUDx_RXC low
SS3
6.0
—
SS4
36.0
—
SS5
6.0
15.0
15.0
15.0
15.0
—
SS7
—
SS9
—
SS11
SS13
SS20
SS21
—
—
10.0
0.0
—
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Electrical Characteristics
Table 52. SSI Receiver with Internal Clock Timing Parameters (continued)
ID
Parameter
Oversampling Clock Operation
Min
Max
Unit
SS47
SS48
SS49
SS50
SS51
Oversampling clock period
15.04
6.0
—
—
—
ns
ns
ns
ns
ns
Oversampling clock high period
Oversampling clock rise time
Oversampling clock low period
Oversampling clock fall time
3.0
—
6.0
—
3.0
NOTE
•
All the timings for the SSI are given for a non-inverted serial clock
polarity (TXC/RXC = 0) and a non-inverted frame sync (TXFS/RXFS
= 0). If the polarity of the clock and/or the frame sync have been
inverted, all the timing remains valid by inverting the clock signal
TXC/RXC and/or the frame sync TXFS/RXFS shown in the tables and
in the figures.
•
All timings are on Audiomux Pads when SSI is being used for data
transfer.
•
•
The terms, WL and BL, refer to Word Length(WL) and Bit Length(BL).
For internal Frame Sync operation using external clock, the FS timing is
same as that of TXD (for example, during AC97 mode of operation).
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Electrical Characteristics
4.10.11.3 SSI Transmitter Timing with External Clock
Figure 42 depicts the SSI transmitter external clock timing and Table 53 lists the timing parameters for
the transmitter timing with the external clock.
SS22
SS25
SS26
SS23
SS24
AUDx_TXC
(Input)
SS27
SS29
AUDx_TXFS (bl)
(Input)
SS33
SS31
AUDx_TXFS (wl)
(Input)
SS39
SS38
SS37
AUDx_TXD
(Output)
SS45
SS44
AUDx_RXD
(Input)
Note: AUDx_RXD Input in Synchronous mode only
SS46
Figure 42. SSI Transmitter External Clock Timing Diagram
Table 53. SSI Transmitter with External Clock Timing Parameters
ID
Parameter
External Clock Operation
Min
Max
Unit
SS22
SS23
SS24
SS25
SS26
SS27
SS29
SS31
SS33
SS37
SS38
SS39
AUDx_TXC/AUDx_RXC clock period
81.4
36.0
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AUDx_TXC/AUDx_RXC clock high period
AUDx_TXC/AUDx_RXC clock rise time
AUDx_TXC/AUDx_RXC clock low period
AUDx_TXC/AUDx_RXC clock fall time
6.0
—
36.0
—
6.0
15.0
—
AUDx_TXC high to AUDx_TXFS (bl) high
AUDx_TXC high to AUDx_TXFS (bl) low
AUDx_TXC high to AUDx_TXFS (wl) high
AUDx_TXC high to AUDx_TXFS (wl) low
AUDx_TXC high to AUDx_TXD valid from high impedance
AUDx_TXC high to AUDx_TXD high/low
AUDx_TXC high to AUDx_TXD high impedance
–10.0
10.0
–10.0
10.0
—
15.0
—
15.0
15.0
15.0
—
—
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Electrical Characteristics
Table 53. SSI Transmitter with External Clock Timing Parameters (continued)
ID
Parameter
Min
Max
Unit
Synchronous External Clock Operation
SS44
SS45
SS46
AUDx_RXD setup before AUDx_TXC falling
AUDx_RXD hold after AUDx_TXC falling
AUDx_RXD rise/fall time
10.0
2.0
—
—
—
ns
ns
ns
6.0
NOTE
All the timings for the SSI are given for a non-inverted serial clock
•
polarity (TXC/RXC = 0) and a non-inverted frame sync (TXFS/RXFS
= 0). If the polarity of the clock and/or the frame sync have been
inverted, all the timing remains valid by inverting the clock signal
TXC/RXC and/or the frame sync TXFS/RXFS shown in the tables and
in the figures.
•
•
•
All timings are on AUDMUX Pads when SSI is used for data transfer.
The terms WL and BL refer to Word Length (WL) and Bit Length (BL).
For internal Frame Sync operation using external clock, the FS timing is
same as that of TXD (for example, during AC97 mode of operation).
4.10.11.4 SSI Receiver Timing with External Clock
Figure 43 depicts the SSI receiver external clock timing and Table 54 lists the timing parameters for the
receiver timing with the external clock.
SS22
SS24
SS26
SS25
SS23
SS28
AUDx_TXC
(Input)
SS30
AUDx_TXFS (bl)
(Input)
SS32
SS35
SS34
AUDx_TXFS (wl)
(Input)
SS41
SS36
SS40
AUDx_RXD
(Input)
Figure 43. SSI Receiver External Clock Timing Diagram
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Electrical Characteristics
Table 54. SSI Receiver Timing with External Clock
ID
Parameter
Min
Max
Unit
External Clock Operation
SS22
SS23
SS24
SS25
SS26
SS28
SS30
SS32
SS34
SS35
SS36
SS40
SS41
AUDx_TXC/AUDx_RXC clock period
AUDx_TXC/AUDx_RXC clock high period
81.4
36
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AUDx_TXC/AUDx_RXC clock rise time
6.0
—
AUDx_TXC/AUDx_RXC clock low period
AUDx_TXC/AUDx_RXC clock fall time
36
—
6.0
15.0
—
AUDx_RXC high to AUDx_TXFS (bl) high
AUDx_RXC high to AUDx_TXFS (bl) low
AUDx_RXC high to AUDx_TXFS (wl) high
AUDx_RXC high to AUDx_TXFS (wl) low
AUDx_TXC/AUDx_RXC External AUDx_TXFS rise time
AUDx_TXC/AUDx_RXC External AUDx_TXFS fall time
AUDx_RXD setup time before AUDx_RXC low
AUDx_RXD hold time after AUDx_RXC low
–10
10
–10
10
—
15.0
—
6.0
6.0
—
—
10
2
—
NOTE
•
All the timings for the SSI are given for a non-inverted serial clock
polarity (TXC/RXC=0) and a non-inverted frame sync
(TXFS/RXFS=0). If the polarity of the clock and/or the frame sync have
been inverted, all the timing remains valid by inverting the clock signal
TXC/RXC and/or the frame sync TXFS/RXFS shown in the tables and
in the figures.
•
All timings are on AUDMUX Pads when SSI is being used for data
transfer.
•
•
The terms, WL and BL, refer to Word Length(WL) and Bit Length(BL).
For internal Frame Sync operation using external clock, the FS timing is
same as that of TXD (for example, during AC97 mode of operation).
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Electrical Characteristics
4.10.12 UART I/O Configuration and Timing Parameters
4.10.12.1 UART RS-232 I/O Configuration in Different Modes
The i.MX 6SoloLite UART interfaces can serve both as DTE or DCE device. This can be configured by
the DCEDTE control bit (default 0 – DCE mode). Table 55 shows the UART I/O configuration based on
the enabled mode.
Table 55. UART I/O Configuration vs. Mode
DTE Mode
Description
DCE Mode
Description
Port
Direction
Direction
UART_RTS_B
UART_CTS_B
UART_DTR_B
UART_DSR_B
UART_DCD_B
UART_RI_B
Output
Input
RTS from DTE to DCE
CTS from DCE to DTE
DTR from DTE to DCE
DSR from DCE to DTE
DCD from DCE to DTE
RING from DCE to DTE
Serial data from DCE to DTE
Serial data from DTE to DCE
Input
Output
Input
RTS from DTE to DCE
CTS from DCE to DTE
DTR from DTE to DCE
DSR from DCE to DTE
DCD from DCE to DTE
RING from DCE to DTE
Serial data from DCE to DTE
Serial data from DTE to DCE
Output
Input
Output
Output
Output
Output
Input
Input
Input
UART_TX_DATA
UART_RX_DATA
Input
Output
4.10.12.2 UART RS-232 Serial Mode Timing
The following sections describe the electrical information of the UART module in the RS-232 mode.
4.10.12.2.1 UART Transmitter
Figure 44 depicts the transmit timing of UART in the RS-232 serial mode, with 8 data bit/1 stop bit
format. Table 56 lists the UART RS-232 serial mode transmit timing characteristics.
Possible
Parity
UA1
UA1
Bit 3
Bit
Next
Start
Bit
Start
Bit
STOP
BIT
UARTx_TX_DATA
(output)
Par Bit
Bit 0
Bit 1
Bit 2
Bit 5
Bit 4
Bit 6
Bit 7
UA1
UA1
Figure 44. UART RS-232 Serial Mode Transmit Timing Diagram
Table 56. RS-232 Serial Mode Transmit Timing Parameters
ID
Parameter
Transmit Bit Time
Symbol
Min
Max
Unit
2
UA1
tTbit
1/Fbaud_rate1 – T
1/Fbaud_rate + T
—
ref_clk
ref_clk
1
2
Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
ref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).
T
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Electrical Characteristics
4.10.12.2.2 UART Receiver
Figure 45 depicts the RS-232 serial mode receive timing with 8 data bit/1 stop bit format. Table 57 lists
serial mode receive timing characteristics.
Possible
Parity
UA2
UA2
Bit 3
Bit
Next
Start
Bit
Start
Bit
STOP
BIT
UARTx_RX_DATA
(input)
Bit 7
Par Bit
UA2
Bit 0
Bit 1
Bit 2
Bit 4
Bit 5
Bit 6
UA2
Figure 45. UART RS-232 Serial Mode Receive Timing Diagram
Table 57. RS-232 Serial Mode Receive Timing Parameters
ID
Parameter
Receive Bit Time1
Symbol
Min
Max
1/Fbaud_rate + 1/(16 × Fbaud_rate
Unit
UA2
tRbit
1/Fbaud_rate2 – 1/(16 × Fbaud_rate
)
)
—
1
2
The UART receiver can tolerate 1/(16 × Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not
exceed 3/(16 × Fbaud_rate).
Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
4.10.12.2.3 UART IrDA Mode Timing
The following subsections give the UART transmit and receive timings in IrDA mode.
UART IrDA Mode Transmitter
Figure 46 depicts the UART IrDA mode transmit timing, with 8 data bit/1 stop bit format. Table 58 lists
the transmit timing characteristics.
UA3
UA3
UA4
UA3
UA3
UARTx_TX_DATA
(output)
Possible
Parity
Bit
STOP
BIT
Start
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Figure 46. UART IrDA Mode Transmit Timing Diagram
Table 58. IrDA Mode Transmit Timing Parameters
ID
Parameter
Symbol
Min
Max
Unit
2
UA3 Transmit Bit Time in IrDA mode
UA4 Transmit IR Pulse Duration
tTIRbit
1/Fbaud_rate1 – T
1/Fbaud_rate + T
—
—
ref_clk
ref_clk
tTIRpulse (3/16) × (1/Fbaud_rate) – T
(3/16) × (1/Fbaud_rate) + T
ref_clk
ref_clk
1
2
Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
ref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).
T
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Electrical Characteristics
UART IrDA Mode Receiver
Figure 47 depicts the UART IrDA mode receive timing, with 8 data bit/1 stop bit format. Table 59 lists
the receive timing characteristics.
UA5
UA5
UA6
UA5
UA5
UARTx_RX_DATA
(input)
Possible
Parity
Bit
STOP
BIT
Start
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Figure 47. UART IrDA Mode Receive Timing Diagram
Table 59. IrDA Mode Receive Timing Parameters
ID
Parameter
Symbol
Min
Max
Unit
UA5 Receive Bit Time1 in IrDA mode
UA6 Receive IR Pulse Duration
tRIRbit
1/Fbaud_rate2 – 1/(16 × Fbaud_rate
1.41 μs
)
1/Fbaud_rate + 1/(16 × Fbaud_rate
)
—
—
tRIRpulse
(5/16) × (1/Fbaud_rate
)
1
The UART receiver can tolerate 1/(16 × Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not
exceed 3/(16 × Fbaud_rate).
Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
2
4.10.13 USB HSIC Timing Parameters
This section describes the electrical information of the USB HSIC port.
NOTE
HSIC is the DDR signal, the following timing parameters are for both rising
and falling edge.
4.10.13.1 Transmit Timing Parameters
Tstrobe
USB_H_STROBE
Todelay
Todelay
USB_H_DATA
Figure 48. USB HSIC Transmit Timing Diagram
Table 60. USB HSIC Transmit Timing Parameters
Name
Parameter
Min
Max
Unit
Comment
Tstrobe Strobe period
4.166
550
4.167
1350
2
ns
ps
—
Todelay Data output delay time
Measured at 50% point
Averaged from 30% – 70% points
Tslew
Strobe/data rising/falling time
0.7
V/ns
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Electrical Characteristics
4.10.13.2 Receive Timing Parameters
Tstrobe
USB_H_STROBE
USB_H_DATA
Thold
Tsetup
Figure 49. USB HSIC Receive Timing Diagram
Table 61. USB HSIC Receive Timing Parameters
1
Name
Parameter
Min
Max
Unit
Comment
Tstrobe Strobe period
4.166
300
365
0.7
4.167
—
ns
ps
—
Thold
Tsetup
Tslew
Data hold time
Measured at 50% point
Data setup time
—
ps
Measured at 50% point
Strobe/data rising/falling time
2
V/ns
Averaged from 30% – 70% points
1
The timings in the table are guaranteed when:
—AC I/O voltage is between 0.9x to 1x of the I/O supply
—DDR_SEL configuration bits of the I/O are set to (10)b
4.10.14 USB PHY Parameters
This section describes the USB-OTG PHY and the USB Host port PHY parameters.
The USB PHY meets the electrical compliance requirements defined in the Universal Serial Bus Revi-
sion 2.0 OTG, USB Host with the amendments below (On-The-Go and Embedded Host Supplement to
the USB Revision 2.0 Specification is not applicable to Host port).
•
USB ENGINEERING CHANGE NOTICE
— Title: 5V Short Circuit Withstand Requirement Change
— Applies to: Universal Serial Bus Specification, Revision 2.0
Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000
USB ENGINEERING CHANGE NOTICE
•
•
— Title: Pull-up/Pull-down resistors
— Applies to: Universal Serial Bus Specification, Revision 2.0
USB ENGINEERING CHANGE NOTICE
•
•
•
— Title: Suspend Current Limit Changes
— Applies to: Universal Serial Bus Specification, Revision 2.0
USB ENGINEERING CHANGE NOTICE
— Title: USB 2.0 Phase Locked SOFs
— Applies to: Universal Serial Bus Specification, Revision 2.0
On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification
— Revision 2.0 plus errata and ecn June 4, 2010
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Electrical Characteristics
•
Battery Charging Specification (available from USB-IF)
— Revision 1.2, December 7, 2010
— Portable device only.
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Boot Mode Configuration
5 Boot Mode Configuration
This section provides information on boot mode configuration pins allocation and boot devices interfaces
allocation.
5.1
Boot Mode Configuration Pins
Table 62 provides boot options, functionality, fuse values, and associated pins. Several input pins are also
sampled at reset and can be used to override fuse values, depending on the value of BT_FUSE_SEL fuse.
The boot option pins are in effect when BT_FUSE_SEL fuse is ‘0’ (cleared, which is the case for an
unblown fuse). For detailed boot mode options configured by the boot mode pins, see the i.MX 6SoloLite
Fuse Map document and the System Boot chapter of the i.MX 6SoloLite reference manual.
Table 62. Fuses and Associated Pins Used for Boot
Ball Name
Direction at Reset
eFuse Name
Boot Mode Selection
BOOT_MODE1
BOOT_MODE0
Input
Input
Boot Mode Selection
Boot Mode Selection
Boot Options1
LCD_DAT0
LCD_DAT1
LCD_DAT2
LCD_DAT3
LCD_DAT4
LCD_DAT5
LCD_DAT6
LCD_DAT7
LCD_DAT8
LCD_DAT9
LCD_DAT10
LCD_DAT11
LCD_DAT12
LCD_DAT13
LCD_DAT14
LCD_DAT15
LCD_DAT16
LCD_DAT17
LCD_DAT18
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
BOOT_CFG1[0]
BOOT_CFG1[1]
BOOT_CFG1[2]
BOOT_CFG1[3]
BOOT_CFG1[4]
BOOT_CFG1[5]
BOOT_CFG1[6]
BOOT_CFG1[7]
BOOT_CFG2[0]
BOOT_CFG2[1]
BOOT_CFG2[2]
BOOT_CFG2[3]
BOOT_CFG2[4]
BOOT_CFG2[5]
BOOT_CFG2[6]
BOOT_CFG2[7]
BOOT_CFG4[0]
BOOT_CFG4[1]
BOOT_CFG4[2]
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Boot Mode Configuration
Table 62. Fuses and Associated Pins Used for Boot (continued)
Ball Name
Direction at Reset
eFuse Name
LCD_DAT19 Input
LCD_DAT20 Input
LCD_DAT21 Input
LCD_DAT22
BOOT_CFG4[3]
BOOT_CFG4[4]
BOOT_CFG4[5]
BOOT_CFG4[6]
BOOT_CFG4[7]
Input
LCD_DAT23 Input
1
Pin value overrides fuse settings for BT_FUSE_SEL = ‘0’. Signal Configuration as Fuse Override Input
at Power Up. These are special I/O lines that control the boot up configuration during product
development. In production, the boot configuration can be controlled by fuses.
5.2
Boot Devices Interfaces Allocation
Table 63 lists the interfaces that can be used by the boot process in accordance with the specific boot
mode configuration. The table also describes the interface’s specific modes and IOMUXC allocation,
which are configured during boot when appropriate.
Table 63. Interfaces Allocation During Boot
Interface
IP Instance
Allocated Ball Names During Boot
Comment
SPI
ECSPI-1
ECSPI1_MISO, ECSPI1_MOSI, ECSPI1_SCLK,
ECSPI1_SS0, I2C1_SCL, I2C1_SDA, ECSPI2_SS0
—
SPI
ECSPI-2
ECSPI2_MISO, ECSPI2_MOSI, ECSPI2_SCLK,
ECSPI2_SS0, EPDC_SDCE0, EPDC_GDCLK,
EPDC_GDOE
—
SPI
SPI
EIM
ECSPI-3
ECSPI-4
EIM
EPDC_D9, EPDC_D8, EPDC_D11, EPDC_D10,
EPDC_D12, EPDC_D13, EPDC_D14
—
—
—
EPDC_D1, EPDC_D0, EPDC_D3, EPDC_D2,
EPDC_D2, EPDC_D5, EPDC_D6
LCD_DAT[21:6], KEY_COL[7:0], KEY_ROW[7:0],
EPDC_D[15:8], EPDC_VCOM0, EPDC_VCOM1,
EPDC_BDR0, EPDC_PWRCTRL[2:0], EPDC_SDCE1
SD/MMC
SD/MMC
SD/MMC
SD/MMC
I2C
USDHC-1
USDHC-2
USDHC-3
USDHC-4
I2C-1
Refer to the table “SD/MMC IOMUX Pin Configuration” in 1, 4, or 8 bit Fastboot
the System Boot Chapter of the i.MX 6SoloLite
Applications Processor Reference Manual
Refer to the table “SD/MMC IOMUX Pin Configuration” in 1, 4, or 8 bit Fastboot
the System Boot Chapter of the i.MX 6SoloLite
Applications Processor Reference Manual
Refer to the table “SD/MMC IOMUX Pin Configuration” in 1, 4, or 8 bit Fastboot
the System Boot Chapter of the i.MX 6SoloLite
(UHSI not supported)
Applications Processor Reference Manual
Refer to the table “SD/MMC IOMUX Pin Configuration” in 1, 4, or 8 bit Fastboot
the System Boot Chapter of the i.MX 6SoloLite
Applications Processor Reference Manual
I2C1_SCL, I2C1_SDA
—
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Package Information and Contact Assignments
Table 63. Interfaces Allocation During Boot (continued)
Interface
IP Instance
Allocated Ball Names During Boot
Comment
I2C
I2C
I2C-2
I2C-3
I2C2_SCL, I2C2_SDA
AUD_RXFS, AUD_RXC
—
—
—
USB
USB_OTG1_PHY USB_OTG1_DP
USB_OTG1_DN
USB_OTG1_VBUS
USB_OTG1_CHD_B
USB_OTG1_DP
USB_OTG1_DN
USB_OTG1_VBUS
6 Package Information and Contact Assignments
This section includes the contact assignment information and mechanical package drawing.
6.1
Updated Signal Naming Convention
The signal names of the i.MX6 series of products have been standardized to better align the signal names
within the family and across the documentation. Some of the benefits of these changes are as follows:
•
•
•
•
The names are unique within the scope of an SoC and within the series of products
Searches will return all occurrences of the named signal
The names are consistent between i.MX 6 series products implementing the same modules
The module instance is incorporated into the signal name
This change applies only to signal names. The original ball names have been preserved to prevent the need
to change schematics, BSDL models, IBIS models, and so on.
Throughout this document, the updated signal names are used except where referenced as a ball name
(such as the Functional Contact Assignments table, Ball Map table, and so on). A master list of the signal
name changes is in the document, IMX 6 Series Signal Name Mapping (EB792). This list can be used to
map the signal names used in older documentation to the new standardized naming conventions.
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Package Information and Contact Assignments
6.2
13 x 13mm Package Information
6.2.1
Case 2240, 13 x 13 mm, 0.5 mm Pitch, 24 x 24 Ball Matrix
Figure 50 shows the top, bottom, and side views of the 13×13 mm BGA package.
Figure 50. 13 x 13, 0.5 mm BGA Package Top, Bottom, and Side Views
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Package Information and Contact Assignments
Table 64 shows the 13 x 13 mm BGA package details.
Table 64. 13 x 13, 0.5 mm BGA Package Details
Common Dimensions
Normal
Parameter
Symbol
Minimum
Maximum
Total Thickness
Stand Off
A
A1
A2
A3
D
0.88
0.16
—
1.1
—
0.26
Substrate Thickness
Mold Thickness
Body Size
0.26 REF
0.54 REF
13 BSC
13 SC
0.3
E
B
Ball Diameter
Ball Opening
—
—
0.275
—
Ball Width
b
0.27
432
0.37
—
Ball Pitch
e
0.5 BSC
—
Ball Count
n
Edge Ball Center to Center
D1
E1
SD
SE
aaa
bbb
ddd
eee
fff
11.5 BSC
11.5 BSC
0.25 BSC
0.25 BSC
0.1
Body Center to Contact Ball
Package Edge Tolerance
Mold Flatness
0.1
Coplanarity
0.08
Ball Offset (Package)
Ball Offset (Ball)
0.15
0.05
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Package Information and Contact Assignments
6.2.2
13 x 13 mm Ground, Power, Sense, Not Connected, and Reference
Contact Assignments
Table 65 shows the device connection list for ground, power, sense, and reference contact signals.
Table 65. 13 x 13 mm Supplies Contact Assignment
Supply Rail Name
Ball(s) Position(s)
Remark
DRAM_VREF
GND
N5
—
—
A1, A4, A7, A24, C6, C10, C14, C19, D1, D2, E5, G1, G8, G9,
G10, G11, G13, G14, G15, G17, G18, H3, H7, H18, H22, J5,
K1, L7, L9, L10, L11, L12, L13, L14, L15, L16, M5, M7, M8, M9,
M10, M11, M12, M13, M14, M15, M16, M17, N3, N7, N8, N9,
N10, N11, N12, N13, N14, N15, N16, N17, N22, P9, P10, P11,
P12, P13, P14, P15, P16, R1, T5, U3, U7, U18, U22, V1, V8,
V9, V10, V11, V12, V13, V14, V15, V16, V18, Y5, AA1, AA2,
AB10, AB14, AB18, AC18, AD1, AD4, AD7, AD24
GND_KELVIN
GPANAIO
V17
Must be connected
AD22
Analog output for NXP use only. This
output must remain unconnected.
NVCC_1P2V
NVCC18_IO
W7
E14, E15, M20, Y11
—
—
NVCC33_IO
H10, H11, H14, H15, L18, M18, T19, U10, U11
E6, Y6, G7, H6, J6, N6, P7, T6, U6, V7
M6
—
NVCC_DRAM
NVCC_DRAM_2P5
NVCC_PLL
Supply of the DDR Interface
—
—
Y19
VDD_ARM_CAP
J15, J16, J17, J18, K15, K16, K17, K18
Secondary Supply for the ARM0 and
ARM1 Cores (internal regulator
output—requires capacitor if internal
regulator is used)
VDD_ARM_IN
J12, J13, J14, K12, K13, K14
R14, R15, T14, T15
Primary Supply, for the ARM0 and
ARM1 Core’ Regulator
VDD_HIGH_CAP
Secondary Supply for the 2.5 V
domain (internal regulator
output—requires capacitor if internal
regulator is used)
VDD_HIGH_IN
VDD_PU_CAP
R12, R13, T12, T13
Primary Supply for the 2.5 V Regulator
R7, R8, R9, T7, T8, T9
Secondary Supply for the VPU and
GPU’s (internal regulator
output—requires capacitor if internal
regulator is used)
VDD_PU_IN
R10, R11, T10, T11
AD20
—
VDD_SNVS_CAP
Secondary Supply for the SNVS
(internal regulator output—requires
capacitor if internal regulator is used)
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Package Information and Contact Assignments
Table 65. 13 x 13 mm Supplies Contact Assignment (continued)
Supply Rail Name
Ball(s) Position(s)
Remark
VDD_SNVS_IN
AC20
Primary Supply, for the SNVS
Regulator
VDD_SOC_CAP
J7, J8, J9, K7, K8, K9, N18, P18, R18
Secondary Supply for the SoC and PU
(internal regulator output—requires
capacitor if internal regulator is used)
VDD_SOC_IN
J10, J11, K10, K11, R16, R17, T16, T17, T18
U14
Primary Supply, for the SoC and PU
Regulators
VDD_USB_CAP
Secondary Supply for the 3V Domain
(USBPHY, MLPBPHY, eFuse),internal
regulator output, requires capacitor if
internal regulator is used.
USB_OTG1_VBUS
USB_OTG2_VBUS
ZQPAD
AA18
AD18
H2
—
—
Connect ZQPAD to an external 240
ohm 1% resistor to GND. This is a
reference used during DRAM output
buffer driver calibration.
NC
C4, C5, C8, C9, C12, C13, C16, C17, C20, C21, D4, D5, D8, No Connections.
D9, D12, D13, D16, D17, D20, D21, E8, E9, E12, E13, E16,
E17, F3,F4, F5,F6, F8,F9, F12, F13, F16, F17, F19, F20, F21,
F22, G3, G4, G5, G6, G19, G20, G21, G22, H8, H9, H12, H13,
H16, H17, K3, K4, K5, K6, K19, K20, K21, K22, L3, L4, L5, L6,
L8, L17, L19, L20, L21, L22, P3, P4, P5, P6, P8, P17, P19, P20,
P21, P22, R3, R4, R5, R6, R19, R20, R21, R22, U8, U9, U12,
U13, U16, U17, V3, V4, V5, V6, V19, V20, V21, V22, W3, W4,
W5, W6, W8, W9, W12, W13, W16, W17, W19, W20, W21,
W22, Y8, Y9, Y12, Y13, Y16,Y17, AA4, AA5, AA8, AA9, AA12,
AA13, AA16, AA17, AA20, AA21, AB4, AB5, AB8, AB9, AB12,
AB13, AB16, AB17 AB20, AB21
Table 66 displays an alpha-sorted list of the signal assignments including power rails. The table also
includes out of reset pad state.
Table 66. 13 x 13 mm Functional Contact Assignments
Out of Reset Condition2
Default
Ball Name
Ball
Power Group1 Ball Type
Mode
(Reset
Mode)
Default Function
Input/Output
Value3
AUD_MCLK
AUD_RXC
AUD_RXD
H19
J21
J20
NVCC33_IO
NVCC18_IO
GPIO
GPIO
GPIO
ALT5
ALT5
ALT5
GPIO1_GPIO[6]
GPIO1_GPIO[1]
GPIO1_GPIO[2]
Input
Input
Input
Keeper
Keeper
Keeper
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
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Package Information and Contact Assignments
Table 66. 13 x 13 mm Functional Contact Assignments (continued)
Out of Reset Condition2
Default
Mode
(Reset
Mode)
Ball Name
Ball
Power Group1 Ball Type
Default Function
Input/Output
Value3
AUD_RXFS
AUD_TXC
AUD_TXD
AUD_TXFS
J19
H20
J22
H21
NVCC33_IO
NVCC18_IO
GPIO
GPIO
GPIO
GPIO
ALT5
ALT5
ALT5
ALT5
GPIO1_GPIO[0]
GPIO1_GPIO[3]
GPIO1_GPIO[5]
GPIO1_GPIO[4]
Input
Input
Input
Input
Keeper
Keeper
Keeper
Keeper
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
BOOT_MODE0
BOOT_MODE1
CLK1_N
AC15
AB15
VDD_SNVS_IN
VDD_SNVS_IN
GPIO
GPIO
—
ALT0
ALT0
—
SRC_BOOT_MODE0
SRC_BOOT_MODE1
CLK1_N
Input
Input
Keeper
Keeper
AD23 VDDHIGH_CAP
—
—
CLK1_P
AC23
U4
U5
J2
VDDHIGH_CAP
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
—
—
CLK1_P
—
—
DRAM_A0
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
DRAM_ADDR00
DRAM_ADDR01
DRAM_ADDR10
DRAM_ADDR11
DRAM_ADDR12
DRAM_ADDR13
DRAM_ADDR14
DRAM_ADDR15
DRAM_ADDR02
DRAM_ADDR03
DRAM_ADDR04
DRAM_ADDR05
DRAM_ADDR06
DRAM_ADDR07
DRAM_ADDR08
DRAM_ADDR09
DRAM_CAS_B
DRAM_CS0_B
DRAM_CS1_B
DRAM_DATA00
DRAM_DATA01
DRAM_DATA10
DRAM_DATA11
DRAM_DATA12
DRAM_DATA13
DRAM_DATA14
DRAM_DATA15
DRAM_DATA16
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
0
DRAM_A1
0
DRAM_A10
DRAM_A11
DRAM_A12
DRAM_A13
DRAM_A14
DRAM_A15
DRAM_A2
0
T2
0
U2
H5
R2
K2
T3
0
0
0
0
0
DRAM_A3
T4
0
DRAM_A4
N4
M3
M4
H4
J3
0
DRAM_A5
0
DRAM_A6
0
DRAM_A7
0
DRAM_A8
0
DRAM_A9
J4
0
DRAM_CAS_B
DRAM_CS0_B
DRAM_CS1_B
DRAM_D0
DRAM_D1
DRAM_D10
DRAM_D11
DRAM_D12
DRAM_D13
DRAM_D14
DRAM_D15
DRAM_D16
P1
N2
L2
0
0
0
AC2
AC1
E3
D3
C1
C2
B1
B2
AD8
PU (100K)
PU (100K)
PU (100K)
PU (100K)
PU (100K)
PU (100K)
PU (100K)
PU (100K)
PU (100K)
Input
Input
Input
Input
Input
Input
Input
Input
i.MX 6SoloLite Applications Processors for Consumer Products, Data Sheet, Rev. 5, 10/2017
NXP Semiconductors
87
Package Information and Contact Assignments
Table 66. 13 x 13 mm Functional Contact Assignments (continued)
Out of Reset Condition2
Default
Mode
(Reset
Mode)
Ball Name
Ball
Power Group1 Ball Type
Default Function
Input/Output
Value3
DRAM_D17
DRAM_D18
AC7
AD6
AC6
AB2
AD5
AC5
AC4
AD3
A3
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDRCLK
DDRCLK
DDR
DDR
DDRCLK
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
—
DRAM_DATA17
DRAM_DATA18
DRAM_DATA19
DRAM_DATA02
DRAM_DATA20
DRAM_DATA21
DRAM_DATA22
DRAM_DATA23
DRAM_DATA24
DRAM_DATA25
DRAM_DATA26
DRAM_DATA27
DRAM_DATA28
DRAM_DATA29
DRAM_DATA03
DRAM_DATA30
DRAM_DATA31
DRAM_DATA04
DRAM_DATA05
DRAM_DATA06
DRAM_DATA07
DRAM_DATA08
DRAM_DATA09
DRAM_DQM0
Input
Input
PU (100K)
PU (100K)
DRAM_D19
Input
PU (100K)
DRAM_D2
Input
PU (100K)
DRAM_D20
Input
PU (100K)
DRAM_D21
Input
PU (100K)
DRAM_D22
Input
PU (100K)
DRAM_D23
Input
PU (100K)
DRAM_D24
Input
PU (100K)
DRAM_D25
B4
Input
PU (100K)
DRAM_D26
B5
Input
PU (100K)
DRAM_D27
A5
Input
PU (100K)
DRAM_D28
B6
Input
PU (100K)
DRAM_D29
A6
Input
PU (100K)
DRAM_D3
AB1
B7
Input
PU (100K)
DRAM_D30
Input
PU (100K)
DRAM_D31
A8
Input
PU (100K)
DRAM_D4
AA3
Y3
Input
PU (100K)
DRAM_D5
Input
PU (100K)
DRAM_D6
Y1
Input
PU (100K)
DRAM_D7
Y2
Input
PU (100K)
DRAM_D8
E2
Input
PU (100K)
DRAM_D9
E1
Input
PU (100K)
DRAM_DQM0
DRAM_DQM1
DRAM_DQM2
DRAM_DQM3
DRAM_RAS_B
DRAM_RESET_B
DRAM_SDBA0
DRAM_SDBA1
DRAM_SDBA2
DRAM_SDCKE0
DRAM_SDCKE1
DRAM_SDCLK_0
DRAM_SDCLK_0_B
DRAM_SDODT0
DRAM_SDODT1
DRAM_SDQS0
V2
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
—
0
0
G2
AB3
C3
DRAM_DQM1
DRAM_DQM2
0
DRAM_DQM3
0
N1
DRAM_RAS_B
DRAM_RESET_B
DRAM_SDBA0
DRAM_SDBA1
DRAM_SDBA2
DRAM_SDCKE0
DRAM_SDCKE1
DRAM_SDCLK0_P
DRAM_SDCLK0_N
DRAM_ODT0
0
D6
0
J1
0
T1
0
H1
0
P2
0
M2
L1
0
0
M1
Y4
—
0
ALT0
ALT0
ALT0
Output
Output
Input
E4
DRAM_ODT1
0
W2
DRAM_SDQS0_P
Hi-Z
i.MX 6SoloLite Applications Processors for Consumer Products, Data Sheet, Rev. 5, 10/2017
NXP Semiconductors
88
Package Information and Contact Assignments
Table 66. 13 x 13 mm Functional Contact Assignments (continued)
Out of Reset Condition2
Default
Mode
(Reset
Mode)
Ball Name
Ball
Power Group1 Ball Type
Default Function
Input/Output
Value3
DRAM_SDQS0_B
DRAM_SDQS1
DRAM_SDQS1_B
DRAM_SDQS2
DRAM_SDQS2_B
DRAM_SDQS3
DRAM_SDQS3_B
DRAM_SDWE
W1
F1
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
NVCC_DRAM
DDRCLK
DDRCLK
DDRCLK
DDRCLK
DDRCLK
DDRCLK
DDRCLK
DDR
—
ALT0
—
DRAM_SDQS0_N
DRAM_SDQS1_P
DRAM_SDQS1_N
DRAM_SDQS2_P
DRAM_SDQS2_N
DRAM_SDQS3_P
DRAM_SDQS3_N
DRAM_SDWE
—
Input
—
—
Hi-Z
—
F2
AC3
AD2
B3
ALT0
—
Input
—
Hi-Z
—
ALT0
—
Input
—
Hi-Z
—
A2
U1
ALT0
ALT5
Output
Input
0
ECSPI1_MISO
M19
NVCC33_IO
NVCC18_IO
GPIO
GPIO4_GPIO[10]
Keeper
ECSPI1_MOSI
ECSPI1_SCLK
ECSPI1_SS0
ECSPI2_MISO
ECSPI2_MOSI
ECSPI2_SCLK
ECSPI2_SS0
EPDC_BDR0
EPDC_BDR1
EPDC_D0
N20
N19
M21
T20
U20
U19
T21
C18
B18
A18
A17
G16
F14
D14
B14
A14
NVCC33_IO
NVCC18_IO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
GPIO4_GPIO[9]
GPIO4_GPIO[8]
GPIO4_GPIO[11]
GPIO4_GPIO[14]
GPIO4_GPIO[13]
GPIO4_GPIO[12]
GPIO4_GPIO[15]
GPIO2_GPIO[5]
GPIO2_GPIO[6]
GPIO1_GPIO[7]
GPIO1_GPIO[8]
GPIO1_GPIO[17]
GPIO1_GPIO[18]
GPIO1_GPIO[19]
GPIO1_GPIO[20]
GPIO1_GPIO[21]
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
EPDC_D1
NVCC33_IO
NVCC18_IO
EPDC_D10
NVCC33_IO
NVCC18_IO
EPDC_D11
NVCC33_IO
NVCC18_IO
EPDC_D12
NVCC33_IO
NVCC18_IO
EPDC_D13
NVCC33_IO
NVCC18_IO
EPDC_D14
NVCC33_IO
NVCC18_IO
i.MX 6SoloLite Applications Processors for Consumer Products, Data Sheet, Rev. 5, 10/2017
NXP Semiconductors
89
Package Information and Contact Assignments
Table 66. 13 x 13 mm Functional Contact Assignments (continued)
Out of Reset Condition2
Default
Mode
(Reset
Mode)
Ball Name
Ball
Power Group1 Ball Type
Default Function
Input/Output
Value3
EPDC_D15
EPDC_D2
A13
B17
A16
B16
A15
B15
C15
D15
F15
A12
B13
B12
A11
B11
D11
E11
F11
G12
F10
E10
NVCC33_IO
NVCC18_IO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
GPIO1_GPIO[22]
GPIO1_GPIO[9]
GPIO1_GPIO[10]
GPIO1_GPIO[11]
GPIO1_GPIO[12]
GPIO1_GPIO[13]
GPIO1_GPIO[14]
GPIO1_GPIO[15]
GPIO1_GPIO[16]
GPIO1_GPIO[31]
GPIO2_GPIO[0]
GPIO2_GPIO[1]
GPIO2_GPIO[2]
GPIO2_GPIO[11]
GPIO2_GPIO[7]
GPIO2_GPIO[8]
GPIO2_GPIO[9]
GPIO2_GPIO[10]
GPIO2_GPIO[12]
GPIO2_GPIO[13]
GPIO2_GPIO[14]
GPIO1_GPIO[27]
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
NVCC33_IO
NVCC18_IO
EPDC_D3
NVCC33_IO
NVCC18_IO
EPDC_D4
NVCC33_IO
NVCC18_IO
EPDC_D5
NVCC33_IO
NVCC18_IO
EPDC_D6
NVCC33_IO
NVCC18_IO
EPDC_D7
NVCC33_IO
NVCC18_IO
EPDC_D8
NVCC33_IO
NVCC18_IO
EPDC_D9
NVCC33_IO
NVCC18_IO
EPDC_GDCLK
EPDC_GDOE
EPDC_GDRL
EPDC_GDSP
EPDC_PWRCOM
EPDC_PWRCTRL0
EPDC_PWRCTRL1
EPDC_PWRCTRL2
EPDC_PWRCTRL3
EPDC_PWRINT
EPDC_PWRSTAT
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
EPDC_PWRWAKEU D10
P
NVCC33_IO
NVCC18_IO
EPDC_SDCE0
C11
NVCC33_IO
NVCC18_IO
i.MX 6SoloLite Applications Processors for Consumer Products, Data Sheet, Rev. 5, 10/2017
NXP Semiconductors
90
Package Information and Contact Assignments
Table 66. 13 x 13 mm Functional Contact Assignments (continued)
Out of Reset Condition2
Default
Mode
(Reset
Mode)
Ball Name
Ball
Power Group1 Ball Type
Default Function
Input/Output
Value3
EPDC_SDCE1
EPDC_SDCE2
EPDC_SDCE3
EPDC_SDCLK
EPDC_SDLE
EPDC_SDOE
EPDC_SDSHR
EPDC_VCOM0
EPDC_VCOM1
FEC_CRS_DV
FEC_MDC
A10
B9
NVCC33_IO
NVCC18_IO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
GPIO1_GPIO[28]
GPIO1_GPIO[29]
GPIO1_GPIO[30]
GPIO1_GPIO[23]
GPIO1_GPIO[24]
GPIO1_GPIO[25]
GPIO1_GPIO[26]
GPIO2_GPIO[3]
GPIO2_GPIO[4]
GPIO4_GPIO[25]
GPIO4_GPIO[23]
GPIO4_GPIO[20]
GPIO4_GPIO[26]
GPIO4_GPIO[19]
GPIO4_GPIO[17]
GPIO4_GPIO[18]
GPIO4_GPIO[21]
GPIO4_GPIO[22]
GPIO4_GPIO[24]
GPIO4_GPIO[16]
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
NVCC33_IO
NVCC18_IO
A9
NVCC33_IO
NVCC18_IO
B10
B8
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
E7
NVCC33_IO
NVCC18_IO
F7
NVCC33_IO
NVCC18_IO
C7
NVCC33_IO
NVCC18_IO
D7
NVCC33_IO
NVCC18_IO
AC9
AA7
AB7
W10
AD9
AA10
AC10
AC8
AD10
Y10
W11
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
FEC_MDIO
NVCC33_IO
NVCC18_IO
FEC_REF_CLK
FEC_RX_ER
FEC_RXD0
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
FEC_RXD1
NVCC33_IO
NVCC18_IO
FEC_TX_CLK
FEC_TX_EN
FEC_TXD0
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
FEC_TXD1
NVCC33_IO
NVCC18_IO
HSIC_DAT
AA6
AB6
NVCC_1P2V
NVCC_1P25
DDR
DDR
—
—
USB_H_DATA
Input
Input
PD (100K)
PD (100K)
HSIC_STROBE
USB_H_STROBE
i.MX 6SoloLite Applications Processors for Consumer Products, Data Sheet, Rev. 5, 10/2017
NXP Semiconductors
91
Package Information and Contact Assignments
Table 66. 13 x 13 mm Functional Contact Assignments (continued)
Out of Reset Condition2
Default
Mode
(Reset
Mode)
Ball Name
Ball
Power Group1 Ball Type
Default Function
Input/Output
Value3
I2C1_SCL
I2C1_SDA
I2C2_SCL
I2C2_SDA
AC13
AD13
E18
NVCC33_IO
NVCC18_IO
GPIO
GPIO
GPIO
GPIO
ALT5
ALT5
ALT5
ALT5
GPIO3_GPIO[12]
GPIO3_GPIO[13]
GPIO3_GPIO[14]
GPIO3_GPIO[15]
Input
Input
Input
Input
Keeper
Keeper
Keeper
Keeper
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
D18
NVCC33_IO
NVCC18_IO
JTAG_MOD
JTAG_TCK
JTAG_TDI
Y14
AA14
W14
W15
Y15
NVCC33_IO
NVCC33_IO
NVCC33_IO
NVCC33_IO
NVCC33_IO
NVCC33_IO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
JTAG_MODE
JTAG_TCK
—
—
PU (100K)
PU (47K)
PU (47K)
Keeper
JTAG_TDI
—
JTAG_TDO
JTAG_TMS
JTAG_TRSTB
KEY_COL0
JTAG_TDO
—
JTAG_TMS
—
PU (47K)
PU (47K)
Keeper
AA15
G23
JTAG_TRSTB
GPIO3_GPIO[24]
—
NVCC33_IO
NVCC18_IO
Input
KEY_COL1
KEY_COL2
KEY_COL3
KEY_COL4
KEY_COL5
KEY_COL6
KEY_COL7
KEY_ROW0
KEY_ROW1
KEY_ROW2
KEY_ROW3
KEY_ROW4
KEY_ROW5
F23
E23
E22
E20
D24
D22
C23
G24
F24
E24
E21
E19
D23
NVCC33_IO
NVCC18_IO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
GPIO3_GPIO[26]
GPIO3_GPIO[28]
GPIO3_GPIO[30]
GPIO4_GPIO[0]
GPIO4_GPIO[2]
GPIO4_GPIO[4]
GPIO4_GPIO[6]
GPIO3_GPIO[25]
GPIO3_GPIO[27]
GPIO3_GPIO[29]
GPIO3_GPIO[31]
GPIO4_GPIO[1]
GPIO4_GPIO[3]
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
i.MX 6SoloLite Applications Processors for Consumer Products, Data Sheet, Rev. 5, 10/2017
NXP Semiconductors
92
Package Information and Contact Assignments
Table 66. 13 x 13 mm Functional Contact Assignments (continued)
Out of Reset Condition2
Default
Mode
(Reset
Mode)
Ball Name
Ball
Power Group1 Ball Type
Default Function
Input/Output
Value3
KEY_ROW6
KEY_ROW7
LCD_CLK
C24
B24
T22
Y24
W23
R23
R24
P23
P24
N21
N23
N24
M22
M23
M24
W24
L23
NVCC33_IO
NVCC18_IO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
GPIO4_GPIO[5]
GPIO4_GPIO[7]
GPIO2_GPIO[15]
GPIO2_GPIO[20]
GPIO2_GPIO[21]
GPIO2_GPIO[30]
GPIO2_GPIO[31]
GPIO3_GPIO[0]
GPIO3_GPIO[1]
GPIO3_GPIO[2]
GPIO3_GPIO[3]
GPIO3_GPIO[4]
GPIO3_GPIO[5]
GPIO3_GPIO[6]
GPIO3_GPIO[7]
GPIO2_GPIO[22]
GPIO3_GPIO[8]
GPIO3_GPIO[9]
GPIO3_GPIO[10]
GPIO3_GPIO[11]
GPIO2_GPIO[23]
GPIO2_GPIO[24]
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
LCD_DAT0
LCD_DAT1
LCD_DAT10
LCD_DAT11
LCD_DAT12
LCD_DAT13
LCD_DAT14
LCD_DAT15
LCD_DAT16
LCD_DAT17
LCD_DAT18
LCD_DAT19
LCD_DAT2
LCD_DAT20
LCD_DAT21
LCD_DAT22
LCD_DAT23
LCD_DAT3
LCD_DAT4
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
L24
NVCC33_IO
NVCC18_IO
K23
K24
V23
V24
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
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Package Information and Contact Assignments
Table 66. 13 x 13 mm Functional Contact Assignments (continued)
Out of Reset Condition2
Default
Mode
(Reset
Mode)
Ball Name
Ball
Power Group1 Ball Type
Default Function
Input/Output
Value3
LCD_DAT5
LCD_DAT6
U21
U23
U24
T23
T24
J24
H23
H24
J23
NVCC33_IO
NVCC18_IO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
GPIO2_GPIO[25]
GPIO2_GPIO[26]
GPIO2_GPIO[27]
GPIO2_GPIO[28]
GPIO2_GPIO[29]
GPIO2_GPIO[16]
GPIO2_GPIO[17]
GPIO2_GPIO[19]
GPIO2_GPIO[18]
Input
Input
Input
Input
Input
Input
Input
Input
Input
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
PU (100K)
NVCC33_IO
NVCC18_IO
LCD_DAT7
NVCC33_IO
NVCC18_IO
LCD_DAT8
NVCC33_IO
NVCC18_IO
LCD_DAT9
NVCC33_IO
NVCC18_IO
LCD_ENABLE
LCD_HSYNC
LCD_RESET
LCD_VSYNC
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
ONOFF
W18
VDD_SNVS_IN
VDD_SNVS_IN
GPIO
GPIO
SRC_ONOFF
Input
PMIC_ON_REQ
AD15
ALT0
SNVS_PMIC_ON_REQ
Output
Open
Drain with
PU (100K)
PMIC_STBY_REQ AD16
VDD_SNVS_IN
VDD_SNVS_IN
GPIO
GPIO
GPIO
ALT0 CCM_PMIC_STBY_REQ
Output
Input
0
POR_B
PWM1
AC16
Y7
ALT0
ALT5
SRC_POR_B
PU (100K)
Keeper
NVCC33_IO
NVCC18_IO
GPIO3_GPIO[23]
Input
REF_CLK_24M
REF_CLK_32K
AC14
AD14
NVCC33_IO
NVCC18_IO
GPIO
GPIO
ALT5
ALT5
GPIO3_GPIO[21]
GPIO3_GPIO[22]
Input
Input
Keeper
Keeper
NVCC33_IO
NVCC18_IO
RTC_XTALI
RTC_XTALO
SD1_CLK
AB19 VDD_SNVS_CAP
AA19 VDD_SNVS_CAP
—
—
—
—
RTC_XTALI
RTC_XTALO
—
—
—
—
B20
B21
B23
A23
C22
NVCC33_IO
NVCC18_IO
GPIO
ALT5
GPIO5_GPIO[15]
Input
Keeper
SD1_CMD
SD1_DAT0
SD1_DAT1
SD1_DAT2
NVCC33_IO
NVCC18_IO
GPIO
GPIO
GPIO
GPIO
ALT5
ALT5
ALT5
ALT5
GPIO5_GPIO[14]
GPIO5_GPIO[11]
GPIO5_GPIO[8]
GPIO5_GPIO[13]
Input
Input
Input
Input
Keeper
Keeper
Keeper
Keeper
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
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Package Information and Contact Assignments
Table 66. 13 x 13 mm Functional Contact Assignments (continued)
Out of Reset Condition2
Default
Mode
(Reset
Mode)
Ball Name
Ball
Power Group1 Ball Type
Default Function
Input/Output
Value3
SD1_DAT3
SD1_DAT4
SD1_DAT5
SD1_DAT6
SD1_DAT7
SD2_CLK
SD2_CMD
SD2_DAT0
SD2_DAT1
SD2_DAT2
SD2_DAT3
SD2_DAT4
SD2_DAT5
SD2_DAT6
SD2_DAT7
SD2_RST
SD3_CLK
SD3_CMD
SD3_DAT0
SD3_DAT1
SD3_DAT2
SD3_DAT3
B22
A22
NVCC33_IO
NVCC18_IO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
ALT5
GPIO5_GPIO[6]
GPIO5_GPIO[12]
GPIO5_GPIO[9]
GPIO5_GPIO[7]
GPIO5_GPIO[10]
GPIO5_GPIO[5]
GPIO5_GPIO[4]
GPIO5_GPIO[1]
GPIO4_GPIO[30]
GPIO5_GPIO[3]
GPIO4_GPIO[28]
GPIO5_GPIO[2]
GPIO4_GPIO[31]
GPIO4_GPIO[29]
GPIO5_GPIO[0]
GPIO4_GPIO[27]
GPIO5_GPIO[18]
GPIO5_GPIO[21]
GPIO5_GPIO[19]
GPIO5_GPIO[20]
GPIO5_GPIO[16]
GPIO5_GPIO[17]
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
Keeper
NVCC33_IO
NVCC18_IO
A21
NVCC33_IO
NVCC18_IO
A20
NVCC33_IO
NVCC18_IO
A19
NVCC33_IO
NVCC18_IO
AC24
AB24
AB22
AB23
AA22
AA23
AA24
Y20
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
Y21
NVCC33_IO
NVCC18_IO
Y22
NVCC33_IO
NVCC18_IO
Y23
NVCC33_IO
NVCC18_IO
AB11
AA11
AC11
AD11
AC12
AD12
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
NVCC33_IO
NVCC18_IO
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Package Information and Contact Assignments
Table 66. 13 x 13 mm Functional Contact Assignments (continued)
Out of Reset Condition2
Default
Mode
(Reset
Mode)
Ball Name
Ball
Power Group1 Ball Type
Default Function
Input/Output
Value3
TAMPER
Y18
U15
B19
VDD_SNVS_IN
VDD_SNVS_IN
GPIO
GPIO
GPIO
ALT0
ALT0
ALT5
SNVS_TAMPER
TEST_MODE
Input
Input
Input
—
—
TEST_MODE
UART1_RXD
NVCC33_IO
NVCC18_IO
GPIO3_GPIO[16]
Keeper
UART1_TXD
D19
NVCC33_IO
NVCC18_IO
GPIO
ALT5
GPIO3_GPIO[17]
Input
Keeper
USB_OTG_CHD_B AC22 VDD_USB_CAP ANALOG
—
—
USB_OTG_CHD_B
USB_OTG1_DN
USB_OTG1_DP
USB_OTG2_DN
USB_OTG2_DP
GPIO3_GPIO[18]
—
—
—
—
USB_OTG1_DN
USB_OTG1_DP
USB_OTG2_DN
USB_OTG2_DP
WDOG_B
AD19 VDD_USB_CAP ANALOG
AC19 VDD_USB_CAP ANALOG
AD17 VDD_USB_CAP ANALOG
AC17 VDD_USB_CAP ANALOG
—
—
—
—
—
—
—
—
—
F18
NVCC33_IO
NVCC18_IO
GPIO
ALT5
Input
Keeper
XTALI
XTALO
ZQPAD
AD21
AC21
H2
NVCC_PLL
NVCC_PLL
ANALOG
ANALOG
ZQPAD
—
—
—
XTALI
XTALO
—
—
—
—
NVCC_DRAM
DRAM_ZQPAD
Input
Hi-Z
1
All balls marked Power Group NVCC33_IO or NVCC18_IO are dual-voltage IOs. The user supplies NVCC33_IO and
NVCC18_IO. In the IOMUX for each ball, the user selects either 3.3 V or 1.8 V operation using the LVE field in the Pad Control
Register for each ball.
2
3
The state immediately after reset and before ROM firmware or software has executed.
Variance of the pull-up and pull-down strengths are shown in the tables as follows:
• Table 21, "DVGPIO I/O DC Parameters," on page 33
• Table 22, "LPDDR2 I/O DC Electrical Parameters," on page 34
• Table 23, "DDR3 I/O DC Electrical Parameters," on page 34
For most of the signals, the state during reset is same as the state after reset, given in the Out of Reset
Condition column of Table 66. However, there are some signals for which the state during reset is different
from the state after reset. These signals along with their state during reset are given in Table 67.
Table 67. Signals with Differing Before Reset and After Reset States
Before Reset State
Ball name
Input/Output
Value
EIM_A16
EIM_A17
EIM_A18
EIM_A19
EIM_A20
EIM_A21
Input
Input
Input
Input
Input
Input
PD (100k)
PD (100k)
PD (100k)
PD (100k)
PD (100k)
PD (100k)
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Package Information and Contact Assignments
Table 67. Signals with Differing Before Reset and After Reset States (continued)
Before Reset State
Input/Output Value
Ball name
EIM_A22
EIM_A23
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
PD (100k)
PD (100k)
PD (100k)
PD (100k)
PD (100k)
PD (100k)
PD (100k)
PD (100k)
PD (100k)
PD (100k)
EIM_A24
EIM_EB0
EIM_EB1
EIM_LBA
EIM_RW
EIM_GPIO19
EIM_GPIO17
KEY_COL0
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Package Information and Contact Assignments
6.2.3
13 x 13 mm, 0.5 mm Pitch Ball Map
Table 68 shows the MAPBGA 13 x 13 mm, 0.5 mm pitch ball map.
Table 68. 13 x 13 mm, 0.5 mm Pitch Ball Map
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NXP Semiconductors
Package Information and Contact Assignments
Table 68. 13 x 13 mm, 0.5 mm Pitch Ball Map (continued)
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Package Information and Contact Assignments
Table 68. 13 x 13 mm, 0.5 mm Pitch Ball Map (continued)
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Revision History
7 Revision History
Table 70 provides a history for revision 4 of this data sheet.
Table 70. i.MX 6SoloLite Data Sheet Document Revision History
Substantive Change(s)
Rev.
Number
Date
5
9/2017
• Figure 1, "Part Number Nomenclature—i.MX 6SoloLite” Updates to the Silicon Revision column to
include Rev. 1.4, C.
• Table 1, "Example Orderable Part Numbers” Added “C” suffix part numbers and descriptions.
• Section 4.8.2, “DDR I/O Output Buffer Impedance” Cross-reference change from JEDEC standards
to MMDC section.
• Table 42, "eMMC4.4/4.41 Interface Timing Parameters,” Corrected SD3 Minimum from 2.6 to 1.7 ns.
• Table 42, "eMMC4.4/4.41 Interface Timing Parameters,” Added footnote related to Clock duty Cycle
range.
• Figure 30, "HS200 Mode Timing Diagram” Updated figure to remove extraneous ID callouts.
(Revision History table continued on next page)
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101
Revision History
Table 70. i.MX 6SoloLite Data Sheet Document Revision History (continued)
Rev.
Number
Date
11/2016 • Changed throughout:
Substantive Change(s)
4
– Changed terminology from “floating” to “not connected.”
– Removed references to DDR3
• Section 1, “Introduction,” i.MX 6SoloLite processor features” Removed “low voltage DDR3” from
second paragraph.
• Table 1, "Example Orderable Part Numbers”: Added new footnote to Speed Grade heading.
– Removed paragraph about selecting the right data sheet.
– Removed silicon revision 1 part numbers ending in “AA”.
• Figure 1, "Part Number Nomenclature—i.MX 6SoloLite”: Added to Silicon revision block Rev 1.3 and
associated footnote.
• Section 1.2, “Features,” added new bullet under Expansion cards, “4-bit or 8-bit…”
• Table 2, "i.MX 6SoloLite Modules List”: UART1–5, UART Interface row:
– Changed bullet about programmable baud rate to “up to 5 Mbps.”
– Added new bullet at top: “Conforms to the SD Host Controller…”
– Added version “4.5” to MMCS specifications listed in second bullet “Fully compliant with MMC…”
– Added new bullet “4-bit or 8-bit transfer mode…”
• Table 3, "Special Signal Considerations,” Content changes in the following rows:
– XTALOSC_CLK1_P/ XTALOSC_CLK1_N: changed “floating” to “unconnected”.
– NC: changed “floating” to “remain unconnected”.
– SRC_POR_B: removed second sentence “May be used…”
– RTC_XTALI/ RTC_XTALO: changed “floating” to “unconnected”.
– RTC_XTALI/ RTC_XTALO: changed “keep RTC_XTALO floating” to “leave RTC_XTALO
unconnected”.
– TEST_MODE: changed “float this signal” to “leave this signal unconnected”.
– XTALI/ XTALO: changed “floated” to “remains unconnected”.
– Separated paragraphs with bullets.
• Table 5, "Recommended Connections for Unused Analog Interfaces”: changed “Float” to “Leave
unconnected” in both lines.
• Section 4.1.1, “Absolute Maximum Ratings”: Added new CAUTION text.
• Table 7, "Absolute Maximum Ratings,”:
– Updated the maximum voltage specifications to an increased of 100 mV.
– NVCC_DRAM maximum value changed to 1.975 V.
– Added footnote regarding NVCC_DRAM maximum voltage allowance.
– Added row to Vin/Vout supply voltage, separating DDR pins and non-DDR pins and included
footnote regarding maximum voltage allowance.
• Section 4.1.2.1, “BGA Case 2240 Package Thermal Resistance” Added NOTE “Per JEDEC
JESD51-2…”.
• Table 9, "Operating Ranges,” Changed within rows:
– Backup battery supply range, minimum reduced (improved) from “2.8” to “2.7”.
– Backup battery supply range, maximum increased (improved) from “3.3” to “3.6”
– Removed from the GPIO supplies row; NVCC_1P2V row for DDR3L
• Section 4.1.5, “Maximum Supply Currents,” Paragraph 3: changed “AN4715” to “AN4580”.
• Section 4.2.1, “Power-Up Sequence,” Removed reference to external SRC_POR_B:
– Bullet 3: Removed “If the external” and final sentence “In the absence of…”
– Removed bullet 4.
– Added third NOTE: “For customers starting new designs…”
Continued on next page
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102
NXP Semiconductors
Revision History
Table 70. i.MX 6SoloLite Data Sheet Document Revision History (continued)
Date Substantive Change(s)
Rev.
Number
4
11/2016 • Section 4.2.2, “Power-Down Sequence,” Replaced contents of section with sentence: “There are no
special requirements on the power-down sequence other than …”.
Continued
• Section 4.5.2, “OSC32K”: Removed text regarding coin cell from third paragraph and removed
second NOTE about third party coin cell manufacturer.
• Section 4.6, “I/O DC Parameters”: Removed second bullet regarding single voltage GPIO cell set.
• Section 4.6.1, “XTALI and RTC_XTALI (Clock Inputs) DC Parameters” Added NOTE after
table.Table 20, "XTALI and RTC_XTALI DC Parameters”:
– Added parameter rows: Input capacitance; XTALI input leakage; and DC input current.
– Added new footnote, “This voltage specification…”
• Section 4.6.3, “Single Voltage General Purpose I/O (GPIO) DC Parameters” removed section.
• Section 4.8, “Output Buffer Impedance Parameters”: Removed second bullet “Single voltage
General Purpose I/O cell set …”.
• Table 28, "DVGPIO Output Buffer Average Impedance (OVDD 1.8 V)”: Changed all Typical values.
• Table 29, "DVGPIO Output Buffer Average Impedance (OVDD 3.3 V)”: Changed all Typical values.
• Section 4.8.2, “Single Voltage GPIO Output Buffer Impedance”: removed section.
• Table 34, "EIM Bus Timing Parameters, Updates throughout table to include min/max values.
• Table 35, "EIM Asynchronous Timing Parameters Table Relative Chip Select, Updates throughout
table to include min/max values.
• Section 4.9.4, “Multi-Mode DDR Controller (MMDC),” created this new section.
• Removed: Section 4.9.5, “DDR SDRAM Specific Parameters (DDR3 and LPDDR2),”
Section 4.9.5.1, “DDR3 Parameters,” and Section 4.9.5.2, “LPDDR2 Parameters.”
• Table 37, "CSI Gated Clock Mode Timing Parameters,”
– Parameter P5 reduced (improved) from 10ns to 7.5 ns.
– Parameter P6 reduced (improved) from 10ns to 7.5 ns.
– Parameter P7 corrected to 66 MHz (no functional change).
• Table 38, "CSI Ungated Clock Mode Timing Parameters,”
– Parameter P4 reduced (improved) from 10ns to 7.5 ns.
– Parameter P5 reduced (improved) from 10ns to 7.5 ns.
– Parameter P6 corrected to 66 MHz (no functional change).
• Section 4.10.3.1, “ECSPI Master Mode Timing,” Added new NOTE under Figure 25.
• Section 4.10.3.2, “ECSPI Slave Mode Timing,” Added new NOTE under Figure 26.
• Section 4.10.4.3, “SDR50/SDR104 AC Timing Parameters,” Figure 29 updated to correct SD5.
• Table 43, "SDR50/SDR104 Interface Timing Parameters,”
– SD2, changed minimum value to “0.46”, and changed maximum value to “0.54”.
– SD3, changed minimum value to “0.46”, and changed maximum value to “0.54”.
– SD2 (parameter Clock High Time), parameter name corrected to SD3.
– SD5, changed maximum value to “0.74”.
• Section 4.10.5, “HS200 Mode Timing Parameters,” Added this new section.
• Section 4.10.14, “USB PHY Parameters,” Added new text to second paragraph “USB Host with the
amendments below…”
• Table 63, "Interfaces Allocation During Boot USDHC-1–USDHC-4 row, replaced existing text with
“Refer to the table “SD/MMC…”
• Table 65, "13 x 13 mm Supplies Contact Assignment,”
– GPANAIO: changed remark from “Analog pad” to “Analog output for NXP use…”
– ZQPAD: changed remark to “Connect ZQPAD to…”
• Table 66, "13 x 13 mm Functional Contact Assignments,” DRAM_SDCLK_0, corrected “Input” to
“Output” and Value to “0”.
• Section 6.2.2, “13 x 13 mm Ground, Power, Sense, Not Connected, and Reference Contact
Assignments,” Added new text “For most of the signals…” after Table 66.
• Table 68, "13 x 13 mm, 0.5 mm Pitch Ball Map,” ball AD6 name corrected to “DRAM_D18”.
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103
Revision History
Table 70. i.MX 6SoloLite Data Sheet Document Revision History (continued)
Rev.
Number
Date
02/2014 • Section 1.2,Feature description for:
Substantive Change(s)
Rev. 3
- Camera sensors: Added to Parallel Camera port “and up to 66 MHz peak”.
- Miscellaneous IPs and interfaces; Changed from:
“Three I2S/SSI/AC97 supported,” to “SSI block is capable of supporting audio sample frequencies
up to 192 kHZ stereo inputs and outputs with I2S mode.”
• Table 2, Modules List: UART1–5, Brief Description; Changed bullet about programmable baud rate
to “up to 5 MHz.”
• Table 2, Modules List: uSDHC1–4, Brief Description; Changed bullet about Fully compliant with SD
command/response to include “and SDXC cards up to 2TB.”
• Table 9, operating range for GPIO supplies: Added NVCC_1P2V min/typ/max values for LPDDR2,
DDR3L, DDR3.
• Section 4.1.4, External Clock Sources; added Note, “The internal oscillator may run high …”
• Table 11, Maximum Supply currents: Added row; NVCC_LVDS2P5.
• Section 4.2.1, Power-Up Sequence: reworded third bulleted item regarding POR control.
• Section 4.2.1, Power-Up Sequence: removed Note.
• Section 4.5.1, OSC24K, first paragraph corrected ‘powered from’ signal from NVCC_1P2 to
NVCC_1P2V.
• Section 4.5.2, OSC32K, Changed second paragraph and added CAUTION.
• Table 31 Reset Timing Parameters, changed Unit from XTALI cycle to XTALOSC_RTC_XTALI cycle.
• Section 4.5.2, External Interface Module; enhanced wording to first paragraph to describe operating
frequency for data transfers, and to explain register settings are valid for entire range of frequencies.
• Table 34, EIM Bus Timing Parameters; reworded footnotes for clarity.
Rev. 3.0
02/2014 • Table 45, DDR3 Write Cycle; changed footnote 3, outputs from “DDR_VREF” to “DRAM_VREF”.
• Figure 25, LPDDR2 Command and Address Timing Diagram; changed signal name from
“DRAM_CAS_B” to “DRAM_ADDRxx”.
• Table 47, LPDDR2 Timing Parameters; changed footnote 2, outputs from “DDR_VREF” to
“DRAM_VREF”.
• Table 48, LPDDR2 Write Cycle; changed footnote 3, outputs from “DDR_VREF” to “DRAM_VREF”.
• Table 49, LPDDR2 Read Cycle; changed footnote 3, outputs from “DDR_VREF” to “DRAM_VREF”.
• Table 65, 13x13mm Supplies Contact Assignment; changed Supply Rail Name “DDR_VREF” to
“DRAM_VREF”.
• Table 65, 13x13mm Supplies Contact Assignment; changed ZQPAD ball position from “AE17” to
“H2”.
• Table 68, 13x13mm Functional Contact Assignment; Changed the following signals to include
active-low “_B” in the Default Function column: DRAM_CAS_B; DRAM_CS0_B; DRAM_CS1_B;
DRAM_RAS_B; DRAM_RESET_B.
• Table 68, 13x13mm Functional Contact Assignment; Changed the Ball Name of DRAM_WE_B to
DRAM_SDWE.
• Table 68, 13 x 13 mm, 0.5 mm Pitch Ball Map; Y19, changed from “ON/OFF” to “NVCC_PLL.
• Table 68, 13 x 13 mm, 0.5 mm Pitch Ball Map; W18, changed from “TEST_MODE” to “ON/OFF”.
• Table 68, 13 x 13 mm, 0.5 mm Pitch Ball Map; U15, changed from “NVCC_PLL” to “TEST_MODE”.
• Table 68, 13 x 13 mm, 0.5 mm Pitch Ball Map; U11 & U10, changed from “NHVCC_3V3” to
“NVCC33_IO”.
Rev. 2.2
8/2013 Substantive Changes are as follows:
• Section 1.2, “Features,” corrected value of OCRAM from 256KB to 128KB:
The SoC-level memory system consists of the following additional components:
— Boot ROM, including HAB (96 KB)
— Internal multimedia / shared, fast access RAM (OCRAM, 128 KB)
• Removed parenthetical statement (input slope <= 5 ns) from Table 31, “Reset Timing Parameters”
CC1: Duration of POR_B to be qualified as valid. The parenthetical statement was a typographical
error and is not a specification requirement for this device.
i.MX 6SoloLite Applications Processors for Consumer Products, Data Sheet, Rev. 5, 10/2017
104
NXP Semiconductors
Revision History
Table 70. i.MX 6SoloLite Data Sheet Document Revision History (continued)
Rev.
Number
Date
Substantive Change(s)
Rev. 2.1
05/2013 Substantive changes throughout this document are as follows:
• Incorporated standardized signal names. This change is extensive throughout the document.
• Added section Section 1.3, “Updated Signal Naming Convention”.
• Added reference to EB792, i.MX Signal Name Mapping.
• Figures updated to align to standardized signal names.
• Updated references to eMMC standard to include 4.41.
• References toConsumer and Extended consumer temperature grades changed to Commercial and
Extended Commercial.
• Figure 1 “Part Number Nomenclature—i.MX 6SoloLite,” updates to Silicon Revision section.
• Table 1 “Orderable Part Numbers” part numbers updated and options updated accordingly.
• Table 2 “i.MX 6SoloLite Modules List” Changed reference to Global Power Controller to read
General Power Controller.
• Table 12. “Stop Mode Current and Power Consumption” Added SNVS only mode information.
• Table 39 “ECSPI Master Mode Timing Parameters,” updated CS5/CS6 Min to
Half ECSPIx_SCLK period-4/Half ECSPIx_SCLK period-2.
• Table 39 “ECSPI Master Mode Timing Parameters,” added to CS8 parameters slow group/fast
group.
• Table 41 “SD/eMMC4.3 Interface Timing Specification,” changed SD8 from 5.6ns to 1.5ns.
• Table 66 “13 x 13 mm Functional Contact Assignments,” Changes throughout. NVCC_GPIO,
NVCC_SD1, NVCC_SD2, NVCC_SD3, and NVCC_LCD entries in the Power Group column
changed to NVCC33_IO or NVCC18_IO.
• Table 66 “13 x 13 mm Functional Contact Assignments,” Added footnote to Value to include
reference information to pull-up and pull-down strengths.
Rev. 2.1
05/2013 • Table 66: “13 x 13 mm Functional Contact Assignments,” for contact ECSPI_MOSI through
ECSPI2_SCLK changed ball type from ALT5 to GPIO.
• Section 1.2, “Features,” added bulleted items regarding the SOC-level memory system.
• Renamed and updated Section 4.3.2, “Regulators for Analog Modules.”
• Section 4.10.6, “FEC AC Timing Parameters,” removed FEC MII subsections and other references
to MII—changed to RMII as applicable.
• Removed section, “EIM Signal Cross Reference.” Signal names are now aligned between Reference
Manual and Data Sheet.
i.MX 6SoloLite Applications Processors for Consumer Products, Data Sheet, Rev. 5, 10/2017
NXP Semiconductors
105
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Document Number: IMX6SLCEC
Rev. 5
10/2017
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