MCF5372L [NXP]
MCF537x ColdFire® Microprocessor Data Sheet;
| 型号： | MCF5372L |
| 厂家： | 
NXP |
| 描述： | MCF537x ColdFire® Microprocessor Data Sheet |
| 文件： | 总46页 (文件大小：1795K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MCF5373DS
Rev. 4, 11/2008
MCF5373
MAPBGA–256
17mm x 17mm
MAPBGA–196
15mm x 15mm
MCF537x ColdFire®
Microprocessor Data Sheet
QFP–160
28mm x 28mm
Features
• Version 3 ColdFire variable-length RISC processor core
• System debug support
• JTAG support for system level board testing
• On-chip memories
– 16-Kbyte unified write-back cache
– 32-Kbyte dual-ported SRAM on CPU internal bus,
accessible by core and non-core bus masters (e.g., DMA,
FEC, and USB host and OTG)
• Power management
• Embedded Voice-over-IP (VoIP) system solution
• SDR/DDR SDRAM Controller
• Universal Serial Bus (USB) Host Controller
• Universal Serial Bus (USB) On-the-Go (OTG) controller
• Synchronous Serial Interface (SSI)
• Fast Ethernet Controller (FEC)
• Cryptography Hardware Accelerators
• FlexCAN Module
• Three Universal Asynchronous Receiver Transmitters
(UARTs)
• I2C Module
• Queued Serial Peripheral Interface (QSPI)
• Pulse Width Modulation (PWM) module
• Real Time Clock
• Four 32-bit DMA Timers
• Software Watchdog Timer
• Four Periodic Interrupt Timers (PITs)
• Phase Locked Loop (PLL)
• Interrupt Controllers (x2)
• DMA Controller
• FlexBus (External Interface)
• Chip Configuration Module (CCM)
• Reset Controller
• General Purpose I/O interface
© Freescale Semiconductor, Inc., 2008. All rights reserved.
Table of Contents
1
2
3
MCF537x Family Comparison . . . . . . . . . . . . . . . . . . . . . . . . .3
5.7.1 SDR SDRAM AC Timing Characteristics . . . . . 21
5.7.2 DDR SDRAM AC Timing Characteristics. . . . . 23
5.8 General Purpose I/O Timing . . . . . . . . . . . . . . . . . . . . 26
5.9 Reset and Configuration Override Timing . . . . . . . . . . 27
5.10 USB On-The-Go . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.11 SSI Timing Specifications . . . . . . . . . . . . . . . . . . . . . . 28
5.12 I2C Input/Output Timing Specifications . . . . . . . . . . . . 29
5.13 Fast Ethernet AC Timing Specifications . . . . . . . . . . . 31
5.13.1 MII Receive Signal Timing . . . . . . . . . . . . . . . . 31
5.13.2 MII Transmit Signal Timing. . . . . . . . . . . . . . . . 31
5.13.3 MII Async Inputs Signal Timing . . . . . . . . . . . . 32
5.13.4 MII Serial Management Channel Timing . . . . . 32
5.14 32-Bit Timer Module Timing Specifications . . . . . . . . . 33
5.15 QSPI Electrical Specifications . . . . . . . . . . . . . . . . . . . 33
5.16 JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . . 34
5.17 Debug AC Timing Specifications . . . . . . . . . . . . . . . . . 36
Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.1 Package Dimensions—196 MAPBGA. . . . . . . . . . . . . 40
7.2 Package Dimensions—160 QFP. . . . . . . . . . . . . . . . . 41
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Hardware Design Considerations. . . . . . . . . . . . . . . . . . . . . . .5
3.1 PLL Power Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3.2 USB Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3.3 Supply Voltage Sequencing and Separation Cautions . .5
3.3.1 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . .5
3.3.2 Power Down Sequence . . . . . . . . . . . . . . . . . . . .6
Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .6
4.1 Signal Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
4.2 Pinout—196 MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . .12
4.3 Pinout—160 QFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
5.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
5.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .15
5.3 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
5.4 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .16
5.5 Oscillator and PLL Electrical Characteristics . . . . . . . .17
5.6 External Interface Timing Characteristics . . . . . . . . . . .18
5.6.1 FlexBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
5.7 SDRAM Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4
5
6
7
8
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
2
Freescale Semiconductor
MCF537x Family Comparison
USB OTG
(To/From SRAM backdoor)
FlexBus
Chip
Selects
USB OTG
USB Host
SDRAMC
S4
S1
USB Host
M6
M5
M2
External
Interface
XBS
SDRAMC
QSPI
2
I C
UART
M1 S7 M0
S6
Cryptography
Modules
SDRAMC
INTC0
INTC1
RNGA
PWM
DMA Timer
SKHA
MDHA
(To/From PADI)
FEC
FEC
CANRX
CANTX
SSI
DREQn
1
2
FlexCAN
DMA Timers
QSPI
I C
UARTs
DACKn
D[31:0]
A[23:0]
(To/From PADI)
DMA
R/W
DIV
EMAC
CS[5:0]
TA
TS
V3 ColdFire CPU
BE/BWE[3:0]
USB OTG
USB Host
PORTS
SDRAMC
SSI
(To/From PADI)
TRST
16 KByte
Cache
TCLK
TMS
TDI
JTAG
TAP
PWMs, EPORT,
Watchdog, PITs
TDO
(1024x32)x4
RESET
RCON
RSTOUT
Reset
PLL
32 KByte
SRAM
JTAG_EN
RTC
(4096x32)x2
Note:
1
FlexCAN is only on the
MCF53721 device
(To/From XBS)
Figure 1. MCF5373 Block Diagram
1
MCF537x Family Comparison
The following table compares the various device derivatives available within the MCF537x family.
Table 1. MCF537x Family Configurations
Module
MCF5372 MCF5372L MCF53721 MCF5373 MCF5373L
ColdFire Version 3 Core with EMAC
(Enhanced Multiply-Accumulate Unit)
•
•
•
•
•
Core (System) Clock
up to
180 MHz
up to
180 MHz
up to
240 MHz
up to 240 MHz
Peripheral and External Bus Clock
(Core clock ÷ 3)
up to
60 MHz
up to
60 MHz
up to
80 MHz
up to 80 MHz
up to 211
Performance (Dhrystone/2.1 MIPS)
Instruction/Data Cache
up to 158
up to 158 up to 211
16 Kbytes
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
3
Ordering Information
Table 1. MCF537x Family Configurations (continued)
MCF5372 MCF5372L MCF53721 MCF5373 MCF5373L
Module
Static RAM (SRAM)
32 Kbytes
SDR/DDR SDRAM Controller
USB 2.0 Host
•
•
•
•
•
—
•
•
—
•
USB 2.0 On-the-Go
—
•
•
—
•
Synchronous Serial Interface (SSI)
Fast Ethernet Controller (FEC)
Cryptography Hardware Accelerators
Embedded Voice-over-IP System Solution
FlexCAN 2.0B communication module
UARTs
•
•
•
•
•
•
•
•
•
•
—
—
—
•
•
—
—
•
—
—
—
—
•
—
—
3
3
3
3
3
I2C
•
•
•
•
•
QSPI
•
•
•
•
•
PWM Module
—
•
•
—
•
Real Time Clock
•
•
•
•
•
32-bit DMA Timers
4
4
4
4
4
Watchdog Timer (WDT)
Periodic Interrupt Timers (PIT)
Edge Port Module (EPORT)
Interrupt Controllers (INTC)
16-channel Direct Memory Access (DMA)
FlexBus External Interface
General Purpose I/O (GPIO)
JTAG - IEEE® 1149.1 Test Access Port
Package
•
•
•
•
•
4
4
4
4
4
•
•
•
•
•
2
2
2
2
2
•
•
•
•
•
•
•
up to 62
•
•
up to 62
•
•
•
up to 46
•
up to 46
•
up to 62
•
160
196
196
160
196
QFP
MAPBGA MAPBGA
QFP
MAPBGA
2
Ordering Information
Table 2. Orderable Part Numbers
Freescale Part
Description
Package
Speed
Temperature
Number
MCF5372CAB180
MCF5372LCVM240
MCF53721CVM240
MCF5373CAB180
MCF5373LCVM240
MCF5372 RISC Microprocessor
MCF5372 RISC Microprocessor
MCF53721 RISC Microprocessor
MCF5373 RISC Microprocessor
MCF5373 RISC Microprocessor
160 QFP
196 MAPBGA
196 MAPBGA
160 QFP
180 MHz
240 MHz
240 MHz
180 MHz
240 MHz
–40° to +85° C
–40° to +85° C
–40° to +85° C
–40° to +85° C
–40° to +85° C
196 MAPBGA
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
4
Freescale Semiconductor
Hardware Design Considerations
3
Hardware Design Considerations
3.1
PLL Power Filtering
To further enhance noise isolation, an external filter is strongly recommended for PLL analog V pins. The filter shown in
DD
Figure 2 should be connected between the board V and the PLLV pins. The resistor and capacitors should be placed as
DD
DD
close to the dedicated PLLV pin as possible.
DD
10 Ω
Board IVDD
PLL VDD Pin
10 µF
0.1 µF
GND
Figure 2. System PLL V Power Filter
DD
3.2
USB Power Filtering
To minimize noise, external filters are required for each of the USB power pins. The filter shown in Figure 3 should be
connected between the board EV or IV and each of the USBV pins. The resistor and capacitors should be placed as
DD
DD
DD
close to the dedicated USBV pin as possible.
DD
0 Ω
Board EVDD
USB VDD Pin
10 µF
0.1 µF
GND
Figure 3. USB V Power Filter
DD
NOTE
In addition to the above filter circuitry, a 0.01 F capacitor is also recommended in parallel
with those shown.
3.3
Supply Voltage Sequencing and Separation Cautions
The relationship between SDV and EV is non-critical during power-up and power-down sequences. SDV (2.5V or
DD
DD
DD
3.3V) and EV are specified relative to IV
.
DD
DD
3.3.1
Power Up Sequence
If EV /SDV are powered up with IV at 0 V, the sense circuits in the I/O pads cause all pad output drivers connected to
DD
DD
DD
the EV /SDV to be in a high impedance state. There is no limit on how long after EV /SDV powers up before IV
DD
DD
DD
DD
DD
must powered up. IV should not lead the EV , SDV , or PLLV by more than 0.4 V during power ramp-up or there is
DD
DD
DD
DD
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
5
Pin Assignments and Reset States
high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than 500 us to avoid
turning on the internal ESD protection clamp diodes.
3.3.2
Power Down Sequence
If IV /PLLV are powered down first, sense circuits in the I/O pads cause all output drivers to be in a high impedance state.
DD
DD
There is no limit on how long after IV and PLLV power down before EV or SDV must power down. IV should
DD
DD
DD
DD
DD
not lag EV , SDV , or PLLV going low by more than 0.4 V during power down or there is undesired high current in the
DD
DD
DD
ESD protection diodes. There are no requirements for the fall times of the power supplies.
The recommended power down sequence is as follows:
1. Drop IV /PLLV to 0 V.
DD
DD
2. Drop EV /SDV supplies.
DD
DD
4
Pin Assignments and Reset States
4.1
Signal Multiplexing
The following table lists all the MCF537x pins grouped by function. The Dir column is the direction for the primary function
of the pin only. Refer to Section 7, “Package Information,” for package diagrams. For a more detailed discussion of the
MCF537x signals, consult the MCF5373 Reference Manual (MCF5373RM).
NOTE
In this table and throughout this document, a single signal within a group is designated
without square brackets (i.e., A23), while designations for multiple signals within a group
use brackets (i.e., A[23:21]) and is meant to include all signals within the two bracketed
numbers when these numbers are separated by a colon.
NOTE
The primary functionality of a pin is not necessarily its default functionality. Pins that are
muxed with GPIO default to their GPIO functionality.
Table 3. MCF5372/3 Signal Information and Muxing
MCF5372L
MCF5372
MCF53721
MCF5373L
196 MAPBGA
Signal Name
GPIO
Alternate 1
Alternate 2
MCF5373
160 QFP
Reset
RESET2
RSTOUT
—
—
—
—
—
—
I
95
86
K13
L12
EVDD
EVDD
O
Clock
EVDD
EVDD
EVDD
EVDD
SDVDD
EXTAL
XTAL2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I
91
93
—
—
40
L14
K14
P13
N13
N1
O
I
EXTAL32K
XTAL32K
FB_CLK
O
O
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
6
Freescale Semiconductor
Pin Assignments and Reset States
Table 3. MCF5372/3 Signal Information and Muxing (continued)
MCF5372L
MCF53721
MCF5373L
MCF5372
MCF5373
160 QFP
Signal Name
GPIO
Alternate 1
Alternate 2
196 MAPBGA
Mode Selection
RCON2
—
—
—
—
—
—
I
I
72
92
P8
EVDD
EVDD
DRAMSEL
J11
FlexBus
SDVDD
SDVDD
A[23:22]
A[21:16]
—
—
FB_CS[5:4]
—
—
—
O
O
134, 133
132–127
A9, B9
C9, D9, A10,
B10, C10, D10
SDVDD
SDVDD
SDVDD
SDVDD
A[15:14]
A[13:11]
A10
—
—
—
—
SD_BA[1:0]3
SD_A[13:11]3
—
—
—
—
—
O
O
O
O
126, 123
120–118
11 7
A11, B11
C11, A12, B12
A13
A[9:0]
SD_A[9:0]3
116–107
A14, B14, B13,
C12, D11, C14,
C13, D14–D12
SD_D[31:16]4
FB_D[31:17]4
—
—
I/O
I/O
27–34, 46–53
16–23, 57–63
J2, J1, K4–K1,
L4, L3, N2, P1,
P2, N3, L5, P3,
N4, P4
SDVDD
SDVDD
D[31:16]
D[15:1]
—
—
F2, F1, G4–G1,
H4, H3, L6, M6,
N6, P6, L7, M7,
N7
D02
BE/BWE[3:0]
OE
—
FB_D[16]4
—
—
—
—
—
—
I/O
O
O
I
64
P7
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
PBE[3:0]
SD_DQM[3:0]3
26, 54, 24, 56
J3, M5, H2, P5
PBUSCTL3
PBUSCTL2
PBUSCTL1
PBUSCTL0
—
—
66
106
65
M8
E14
L8
TA2
R/W
—
O
O
TS
DACK0
12
E2
Chip Selects
SDVDD
SDVDD
SDVDD
SDVDD
FB_CS[5:4]
FB_CS[3:2]
FB_CS1
PCS[5:4]
PCS[3:2]
PCS1
—
—
—
—
—
—
—
—
O
O
O
O
—
—
D8, C8
B8, A8
D7
135
136
FB_CS0
—
C7
SDRAM Controller
SDVDD
SDVDD
SD_A10
SD_CKE
—
—
—
—
—
—
O
O
43
14
M2
F4
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
7
Pin Assignments and Reset States
Table 3. MCF5372/3 Signal Information and Muxing (continued)
MCF5372
MCF5372L
MCF53721
MCF5373L
Signal Name
GPIO
Alternate 1
Alternate 2
MCF5373
160 QFP
196 MAPBGA
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SDVDD
SD_CLK
SD_CLK
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
O
O
O
O
O
O
O
O
O
37
38
15
25
55
44
45
35
13
L1
M1
F3
H1
N5
M3
M4
L2
SD_CS0
SD_DQS3
SD_DQS2
SD_SCAS
SD_SRAS
SD_SDR_DQS
SD_WE
E1
External Interrupts Port5
IRQ72
IRQ62
PIRQ72
PIRQ62
—
—
—
I
I
102
—
F13
F12
EVDD
EVDD
USBHOST_
VBUS_EN
IRQ52
PIRQ52
USBHOST_
VBUS_OC
—
I
—
F11
EVDD
IRQ42
IRQ32
IRQ22
IRQ12
PIRQ42
PIRQ32
PIRQ22
PIRQ12
SSI_MCLK
—
—
I
I
I
I
101
—
G14
G13
G12
G11
EVDD
EVDD
EVDD
EVDD
—
—
USB_CLKIN
DREQ12
—
SSI_CLKIN
100
FEC
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
FEC_MDC
FEC_MDIO
FEC_COL
PFECI2C3
PFECI2C2
PFECH7
PFECH6
PFECH5
PFECH4
PFECH[3:0]
PFECL7
I2C_SCL2
—
—
—
—
—
—
—
—
—
—
—
—
O
I/O
I
4
3
B1
I2C_SDA2
A1
—
—
—
—
—
—
—
—
—
—
144
B6
FEC_CRS
I
145
A6
FEC_RXCLK
FEC_RXDV
FEC_RXD[3:0]
FEC_RXER
FEC_TXCLK
FEC_TXEN
FEC_TXER
FEC_TXD[3:0]
I
146
A5
I
147
B5
I
148–151
152
C5, D5, A4, B4
I
C4
PFECL6
I
153
A3
PFECL5
O
O
O
154
B3
A2
PFECL4
155
PFECL[3:0]
157, 158, 1, 2
D4, C3, B2, C2
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
8
Freescale Semiconductor
Pin Assignments and Reset States
Table 3. MCF5372/3 Signal Information and Muxing (continued)
MCF5372L
MCF53721
MCF5373L
MCF5372
MCF5373
160 QFP
Signal Name
GPIO
Alternate 1
Alternate 2
196 MAPBGA
USB Host & USB On-the-Go
USB
VDD
USBOTG_M
USBOTG_P
USBHOST_M
USBHOST_P
—
—
—
—
—
—
—
—
—
—
—
—
I/O
I/O
I/O
I/O
—
—
—
—
H14
H13
J13
J12
USB
VDD
USB
VDD
USB
VDD
FlexCAN (MCF53721 only)
CANRX and CANTX do not have dedicated bond pads. Please refer to the following pins for muxing:
I2C_SDA for CANRX and I2C_SCL for CANTX.
PWM
EVDD
EVDD
EVDD
EVDD
PWM7
PWM5
PWM3
PWM1
PPWM7
PPWM5
PPWM3
PPWM1
—
—
I/O
I/O
I/O
I/O
—
—
—
—
E13
E12
E11
F14
—
—
DT3OUT
DT2OUT
DT3IN
DT2IN
SSI
The SSI signals do not have dedicated bond pads. Please refer to the following pins for muxing: IRQ4 for SSI_MCLK,
IRQ1 for SSI_CLKIN, U1CTS for SSI_BCLK, U1RTS for SSI_FS, U1RXD for SSI_RXD, and U1TXD for SSI_TXD
I2C
I2C_SCL2
I2C_SDA2
PFECI2C1
PFECI2C0
CANTX6
CANRX6
U2TXD
U2RXD
I/O
I/O
—
—
E3
E4
EVDD
EVDD
DMA
DACK[1:0] and DREQ[1:0] do not have dedicated bond pads. Please refer to the following pins for muxing:
TS for DACK0, DT0IN for DREQ0, DT1IN for DACK1, and IRQ1 for DREQ1.
QSPI
EVDD
EVDD
QSPI_CS2
QSPI_CS1
PQSPI5
PQSPI4
U2RTS
PWM7
—
O
O
78
—
N12
M12
USBOTG_
PU_EN
EVDD
EVDD
EVDD
EVDD
QSPI_CS0
QSPI_CLK
QSPI_DIN
PQSPI3
PQSPI2
PQSPI1
PQSPI0
PWM5
I2C_SCL2
U2CTS
—
—
—
—
O
O
I
—
77
75
76
M11
P12
P11
N11
QSPI_DOUT
I2C_SDA2
O
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
9
Pin Assignments and Reset States
Table 3. MCF5372/3 Signal Information and Muxing (continued)
MCF5372
MCF5372L
MCF53721
MCF5373L
Signal Name
GPIO
Alternate 1
Alternate 2
MCF5373
160 QFP
196 MAPBGA
UARTs
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
U1CTS
U1RTS
U1TXD
U1RXD
U0CTS
U0RTS
U0TXD
U0RXD
PUARTL7
PUARTL6
PUARTL5
PUARTL4
PUARTL3
PUARTL2
PUARTL1
PUARTL0
SSI_BCLK
SSI_FS
SSI_TXD2
SSI_RXD2
—
—
—
—
—
—
—
—
—
I
O
O
I
143
142
141
140
85
C6
D6
A7
B7
I
M14
M13
N14
P14
—
O
O
I
84
—
83
—
80
Note: The UART2 signals are multiplexed on the QSPI, DMA Timers, and I2C pins.
DMA Timers
EVDD
EVDD
EVDD
EVDD
DT3IN
DT2IN
DT1IN
DT0IN
PTIMER3
PTIMER2
PTIMER1
PTIMER0
DT3OUT
DT2OUT
DT1OUT
DT0OUT
U2RXD
U2TXD
DACK1
DREQ02
I
I
I
I
8
7
6
5
D1
C1
D2
D3
BDM/JTAG7
JTAG_EN8
DSCLK
PSTCLK
BKPT
—
—
—
—
—
—
—
—
—
TRST2
TCLK2
TMS2
TDI2
TDO
—
—
—
—
—
—
—
—
—
I
I
96
88
70
87
90
74
—
—
G10
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
K11
O
I
N8
L13
DSI
I
K12
DSO
O
O
O
L11
DDATA[3:0]
PST[3:0]
L9, M9, N9, P9
—
L10, M10, N10,
P10
EVDD
ALLPST
—
—
—
O
73
—
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
10
Freescale Semiconductor
Pin Assignments and Reset States
Table 3. MCF5372/3 Signal Information and Muxing (continued)
MCF5372L
MCF53721
MCF5373L
MCF5372
MCF5373
160 QFP
Signal Name
GPIO
Alternate 1
Alternate 2
196 MAPBGA
Test
TEST8
EVDD
IVDD
—
—
—
—
—
I
124
E10
EVDD
—
Power Supplies
—
—
—
—
—
9, 69, 71, 81, 94, E6, E7, F5–F7,
103, 139, 160
G5, H10, J8,
K8–K9
—
—
36, 79, 97, 125, E5, J9, K5, K10
156
PLL_VDD
SD_VDD
—
—
—
—
—
—
—
—
—
—
99
J10
11, 39, 41, 67, E8–E9, F8–F10,
105, 121, 137
—
J4–J7, H5, K6,
K7
USB_VDD
VSS
—
—
—
—
—
—
—
—
—
—
H12
10, 42, 68, 82, G6–G9, H6–H9
89, 104, 122,
138, 159
PLL_VSS
USB_VSS
—
—
—
—
—
—
—
—
—
—
98
—
H11
J14
1
2
3
Refers to pin’s primary function.
Pull-up enabled internally on this signal for this mode.
The SDRAM functions of these signals are not programmable by the user. They are dynamically switched by the processor
when accessing SDRAM memory space and are included here for completeness.
4
5
Primary functionality selected by asserting the DRAMSEL signal (SDR mode). Alternate functionality selected by negating the
DRAMSEL signal (DDR mode). The GPIO module is not responsible for assigning these pins.
GPIO functionality is determined by the edge port module. The GPIO module is only responsible for assigning the alternate
functions.
6
7
MCF53721 only.
If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not responsible for assigning
these pins.
8
Pull-down enabled internally on this signal for this mode.
NOTE
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
11
Pin Assignments and Reset States
4.2
Pinout—196 MAPBGA
The pinout for the MCF5373LCVM240, MCF5372LCVM240, and MCF53721CVM240 packages are shown below.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
B
C
D
E
F
A
B
C
D
E
F
FEC_
MDIO
FEC_
TXER
FEC_
TXCLK
FEC_
RXD1
FEC_
RXCLK
FEC_
CRS
U1TXD FB_CS2
U1RXD FB_CS3
A23
A19
A15
A12
A10
A9
FEC_
MDC
FEC_
TXD1
FEC_
TXEN
FEC_
RXD0
FEC_
RXDV
FEC_
COL
A22/
A21
A20
A18
A17
A14
A13
A11
A6
A7
A3
A8
A4
FEC_
TXD0
FEC_
TXD2
FEC_
RXER
FEC_
RXD3
DT2IN
DT3IN
SD_WE
D14
U1CTS FB_CS0 FB_CS4
U1RTS FB_CS1 FB_CS5
FEC_
TXD3
FEC_
RXD2
DT1IN
TS
DT0IN
A16
A5
A0
A1
A2
I2C_SCL I2C_SDA
IVDD
EVDD
EVDD
VSS
EVDD SD_VDD SD_VDD
TEST
PWM3
PWM5
IRQ6
IRQ2
PWM7
IRQ7
IRQ3
TA
D15
D11
SD_CS0 SD_CKE EVDD
EVDD SD_VDD SD_VDD SD_VDD IRQ5
JTAG_
PWM1
IRQ4
G
H
J
G
H
J
D10
D12
D8
D13
D9
EVDD
VSS
VSS
VSS
IRQ1
EN
SD_
DQS3
BE/
BWE1
PLL_
VSS
USBOTG
_VDD
USB
OTG_P
USB
OTG_M
SD_VDD
VSS
VSS
VSS
VSS
EVDD
BE/
BWE3
PLL_
VDD
DRAM
SEL
USB
USB
USBHOST
_VSS
D30
D26
D31
D27
SD_VDD SD_VDD SD_VDD SD_VDD EVDD
IVDD
HOST_P HOST_M
K
L
K
L
TRST/
DSCLK
D28
D24
D29
D25
IVDD SD_VDD SD_VDD EVDD
EVDD
DDATA3
DDATA2
DDATA1
IVDD
PST3
PST2
PST1
TDI/DSI RESET
XTAL
EXTAL
U0CTS
U0TXD
SD_DR_
DQS
TDO/
DSO
TMS/
RSTOUT
SD_CLK
D19
D7
D6
D5
D3
D2
D1
R/W
OE
BKPT
M
N
P
M
N
P
BE/
BWE2
QSPI_
CS0
QSPI_
U0RTS
CS1
SD_CLK SD_A10 SD_CAS SD_RAS
SD_
DQS2
TCLK/
PSTCLK
QSPI_
DOUT
QSPI_
CS2
XTAL
32K
FB_CLK
D23
D20
D17
BE/
BWE0
QSPI_
DIN
QSPI_
CLK
EXTAL
32K
D22
1
D21
2
D18
3
D16
4
D4
6
D0
7
RCON
8
DDATA0
9
PST0
10
U0RXD
14
5
11
12
13
Figure 4. MCF5373LCVM240, MCF5372LCVM240, and MCF53721CVM240 Pinout Top View (196 MAPBGA)
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
12
Freescale Semiconductor
Pin Assignments and Reset States
4.3
Pinout—160 QFP
The pinout for the MCF5372CAB180 and MCF5373CAB180 packages is shown below.
•
FEC_TXD1
FEC_TXD0
FEC_MDIO
FEC_MDC
DT0IN
DT1IN
DT2IN
DT3IN
EVDD
VSS 10
SD_VDD 11
TS 12
1
2
3
4
5
6
7
8
9
120 A13
119 A12
118 A11
117 A10
116 A9
115 A8
114 A7
113 A6
112 A5
111 A4
110 A3
109 A2
108 A1
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
SD_WE
SD_CKE
SD_CS0
D15
107 A0
106 TA
105 SD_VDD
104 VSS
D14
103 EVDD
102 IRQ7
101 IRQ4
100 IRQ1
99 PLL_VDD
98 PLL_VSS
97 IVDD
D13
D12
D11
D10
D9
D8
BE/BWE1
SD_DQS1/3
BE/BWE3
D31
96 JTAG_EN
95 RESET
94 EVDD
93 XTAL
D30
92 DRAMSEL
91 EXTAL
90 TDI/DSI
89 VSS
D29
D28
D27
D26
88 TRST/DSCLK
87 TMS/BKPT
86 RSTOUT
85 U0CTS
84 U0RTS
83 U0TXD
82 VSS
D25
D24
SD_DR_DQS
IVDD
SD_CLK
SD_CLK
SD_VDD
FB_CLK
81 EVDD
Figure 5. MCF5372CAB180 and MCF5373CAB180 Pinout Top View (160 QFP)
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
13
Electrical Characteristics
5
Electrical Characteristics
This document contains electrical specification tables and reference timing diagrams for the MCF5373 microcontroller unit.
This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing
specifications of MCF5373.
The electrical specifications are preliminary and are from previous designs or design simulations. These specifications may not
be fully tested or guaranteed at this early stage of the product life cycle. However, for production silicon, these specifications
will be met. Finalized specifications will be published after complete characterization and device qualifications have been
completed.
NOTE
The parameters specified in this MCU document supersede any values found in the module
specifications.
5.1
Maximum Ratings
1, 2
Table 4. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Core Supply Voltage
IVDD
EVDD
SDVDD
PLLVDD
VIN
– 0.5 to +2.0
– 0.3 to +4.0
– 0.3 to +4.0
– 0.3 to +2.0
– 0.3 to +3.6
V
V
V
V
V
CMOS Pad Supply Voltage
DDR/Memory Pad Supply Voltage
PLL Supply Voltage
Digital Input Voltage 3
Instantaneous Maximum Current
ID
25
mA
Single pin limit (applies to all pins) 3, 4, 5
Operating Temperature Range (Packaged)
TA
(TL - TH)
– 40 to +85
°C
°C
Storage Temperature Range
Tstg
– 55 to +150
1
2
Functional operating conditions are given in Section 5.4, “DC Electrical Specifications.”
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is
not guaranteed. Continued operation at these levels may affect device reliability or cause
permanent damage to the device.
This device contains circuitry protecting against damage due to high static voltage or electrical
fields; however, it is advised that normal precautions be taken to avoid application of any
voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an appropriate logic voltage level (VSS or
EVDD).
3
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive and negative clamp voltages,
and then use the larger of the two values.
4
5
All functional non-supply pins are internally clamped to VSS and EVDD
.
Power supply must maintain regulation within operating EVDD range during instantaneous and
operating maximum current conditions. If positive injection current (Vin > EVDD) is greater than
IDD, the injection current may flow out of EVDD and could result in external power supply going
out of regulation. Ensure external EVDD load shunts current greater than maximum injection
current. This is the greatest risk when the MCU is not consuming power (ex; no clock). Power
supply must maintain regulation within operating EVDD range during instantaneous and
operating maximum current conditions.
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
14
Freescale Semiconductor
Electrical Characteristics
5.2
Thermal Characteristics
Table 5. Thermal Characteristics
Characteristic
Symbol
256MBGA 196MBGA
160QFP
Unit
Junction to ambient, natural convection
Four layer board
(2s2p)
θJMA
371,2
341,2
421,2
381,2
491,2
°C/W
Junction to ambient (@200 ft/min)
Four layer board
(2s2p)
θJMA
441,2
°C/W
Junction to board
θJB
θJC
Ψjt
Tj
273
164
41,5
105
323
194
51,5
105
403
394
°C/W
°C/W
°C/W
oC
Junction to case
Junction to top of package
Maximum operating junction temperature
121,5
105
1
θ
JMA and Ψjt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale
recommends the use of θJmA and power dissipation specifications in the system design to prevent device junction
temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures
can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature
specification can be verified by physical measurement in the customer’s system using the Ψjt parameter, the device power
dissipation, and the method described in EIA/JESD Standard 51-2.
2
3
Per JEDEC JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board
temperature is measured on the top surface of the board near the package.
4
5
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is
written in conformance with Psi-JT.
The average chip-junction temperature (T ) in °C can be obtained from:
J
TJ = TA + (PD × ΘJMA
)
Eqn. 1
Where:
TA
= Ambient Temperature, °C
QJMA
PD
= Package Thermal Resistance, Junction-to-Ambient, °C/W
= PINT + PI/O
PINT
PI/O
= IDD × IVDD, Watts - Chip Internal Power
= Power Dissipation on Input and Output Pins — User Determined
For most applications P < P
and can be ignored. An approximate relationship between P and T (if P is neglected) is:
D J I/O
I/O
INT
K
--------------------------------
PD
=
Eqn. 2
(TJ + 273°C)
Solving equations 1 and 2 for K gives:
K = PD × (TA × 273°C) + QJMA × P2D
Eqn. 3
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring P (at equilibrium)
D
for a known T . Using this value of K, the values of P and T can be obtained by solving Equation 1 and Equation 2 iteratively
A
D
J
for any value of T .
A
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
15
Electrical Characteristics
5.3
ESD Protection
1, 2
Table 6. ESD Protection Characteristics
Characteristics
Symbol
Value
Units
ESD Target for Human Body Model
HBM
2000
V
1
2
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive
Grade Integrated Circuits.
A device is defined as a failure if after exposure to ESD pulses the device no longer meets
the device specification requirements. Complete DC parametric and functional testing is
performed per applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.
5.4
DC Electrical Specifications
Table 7. DC Electrical Specifications
Characteristic
Symbol
Min
Max
Unit
Core Supply Voltage
IVDD
PLLVDD
EVDD
1.4
1.4
3.0
1.6
1.6
3.6
V
V
V
V
PLL Supply Voltage
CMOS Pad Supply Voltage
SDRAM and FlexBus Supply Voltage
SDVDD
Mobile DDR/Bus Pad Supply Voltage (nominal 1.8V)
DDR/Bus Pad Supply Voltage (nominal 2.5V)
SDR/Bus Pad Supply Voltage (nominal 3.3V)
1.70
2.25
3.0
1.95
2.75
3.6
USB Supply Voltage
USBVDD
EVIH
3.0
2
3.6
EVDD + 0.3
0.8
V
V
V
V
CMOS Input High Voltage
CMOS Input Low Voltage
CMOS Output High Voltage
EVIL
VSS – 0.3
EVDD – 0.4
EVOH
—
IOH = –5.0 mA
CMOS Output Low Voltage
IOL = 5.0 mA
EVOL
—
0.4
V
V
SDRAM and FlexBus Input High Voltage
SDVIH
Mobile DDR/Bus Input High Voltage (nominal 1.8V)
DDR/Bus Pad Supply Voltage (nominal 2.5V)
SDR/Bus Pad Supply Voltage (nominal 3.3V)
1.35
1.7
2
SDVDD + 0.3
SDVDD + 0.3
SDVDD + 0.3
SDRAM and FlexBus Input Low Voltage
SDVIL
V
V
Mobile DDR/Bus Input High Voltage (nominal 1.8V)
DDR/Bus Pad Supply Voltage (nominal 2.5V)
SDR/Bus Pad Supply Voltage (nominal 3.3V)
VSS – 0.3
VSS – 0.3
0.45
0.8
0.8
VSS – 0.3
SDRAM and FlexBus Output High Voltage
Mobile DDR/Bus Input High Voltage (nominal 1.8V)
DDR/Bus Pad Supply Voltage (nominal 2.5V)
SDR/Bus Pad Supply Voltage (nominal 3.3V)
IOH = –5.0 mA for all modes
SDVOH
SDVDD – 0.35
—
—
—
2.1
2.4
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
16
Freescale Semiconductor
Electrical Characteristics
Table 7. DC Electrical Specifications (continued)
Characteristic
Symbol
Min
Max
Unit
SDRAM and FlexBus Output Low Voltage
Mobile DDR/Bus Input High Voltage (nominal 1.8V)
DDR/Bus Pad Supply Voltage (nominal 2.5V)
SDR/Bus Pad Supply Voltage (nominal 3.3V)
IOL = 5.0 mA for all modes
SDVOL
V
—
—
—
0.3
0.3
0.5
Input Leakage Current
Iin
−1.0
−10
1.0
μA
Vin = VDD or VSS, Input-only pins
Weak Internal Pull-Up Device Current, tested at VIL Max.1
IAPU
Cin
−130
μA
Input Capacitance 2
pF
All input-only pins
All input/output (three-state) pins
—
—
7
7
1
Refer to the signals section for pins having weak internal pull-up devices.
This parameter is characterized before qualification rather than 100% tested.
2
5.5
Oscillator and PLL Electrical Characteristics
Table 8. PLL Electrical Characteristics
Min.
Value
Max.
Value
Num
Characteristic
Symbol
Unit
PLL Reference Frequency Range
Crystal reference
1
fref_crystal
fref_ext
12
12
251
401
MHz
MHz
External reference
Core frequency
fsys
fsys/3
488 x 10−6
163 x 10−6
240
80
MHz
MHz
2
3
CLKOUT Frequency2
Crystal Start-up Time3, 4
tcst
—
10
ms
EXTAL Input High Voltage
Crystal Mode5
4
5
VIHEXT
VIHEXT
VXTAL + 0.4
EVDD/2 + 0.4
—
—
V
V
All other modes (External, Limp)
EXTAL Input Low Voltage
Crystal Mode5
VILEXT
VILEXT
—
—
VXTAL – 0.4
EVDD/2 – 0.4
V
V
All other modes (External, Limp)
7
8
PLL Lock Time 3, 6
tlpll
tdc
—
40
1
50000
60
CLKIN
%
Duty Cycle of reference 3
9
XTAL Current
IXTAL
3
mA
pF
10
11
Total on-chip stray capacitance on XTAL
Total on-chip stray capacitance on EXTAL
Crystal capacitive load
CS_XTAL
CS_EXTAL
CL
1.5
1.5
pF
See crystal
spec
12
13
Discrete load capacitance for XTAL
CL_XTAL
2*CL –
CS_XTAL
CPCB_XTAL
pF
–
7
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
17
Electrical Characteristics
Table 8. PLL Electrical Characteristics (continued)
Min.
Max.
Value
Num
Characteristic
Symbol
Unit
Value
Discrete load capacitance for EXTAL
CL_EXTAL
2*CL–-
pF
14
17
CS_EXTAL –
CPCB_EXTAL
7
CLKOUT Period Jitter, 3, 4, 7, 8, 9 Measured at fSYS Max
Peak-to-peak Jitter (Clock edge to clock edge)
Long Term Jitter
Cjitter
—
—
10
TBD
% fsys/3
% fsys/3
Frequency Modulation Range Limit 3, 10, 11
(fsysMax must not be exceeded)
Cmod
fvco
0.8
2.2
%fsys/3
18
19
VCO Frequency. fvco = (fref * PFD)/4
350
540
MHz
1
The maximum allowable input clock frequency when booting with the PLL enabled is 24MHz. For higher input clock
frequencies the processor must boot in LIMP mode to avoid violating the maximum allowable CPU frequency.
2
3
4
5
6
7
8
All internal registers retain data at 0 Hz.
This parameter is guaranteed by characterization before qualification rather than 100% tested.
Proper PC board layout procedures must be followed to achieve specifications.
This parameter is guaranteed by design rather than 100% tested.
This specification is the PLL lock time only and does not include oscillator start-up time.
CPCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively.
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal.
.
Noise injected into the PLL circuitry via PLL VDD, EVDD, and VSS and variation in crystal oscillator frequency increase
the Cjitter percentage for a given interval.
9
Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of Cjitter+Cmod.
10 Modulation percentage applies over an interval of 10 μs, or equivalently the modulation rate is 100 KHz.
11
Modulation range determined by hardware design.
5.6
External Interface Timing Characteristics
Table 9 lists processor bus input timings.
NOTE
All processor bus timings are synchronous; that is, input setup/hold and output delay with
respect to the rising edge of a reference clock. The reference clock is the FB_CLK output.
All other timing relationships can be derived from these values. Timings listed in Table 9
are shown in Figure 7 and Figure 8.
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
18
Freescale Semiconductor
Electrical Characteristics
* The timings are also valid for inputs sampled on the negative clock edge.
1.5V
FB_CLK (80MHz)
TSETUP
THOLD
Invalid
1.5V Valid 1.5V
Invalid
Input Setup And Hold
Input Rise Time
trise
Vh = VIH
Vl = VIL
tfall
Vh = VIH
Vl = VIL
Input Fall Time
FB_CLK
Inputs
B4
B5
Figure 6. General Input Timing Requirements
5.6.1
FlexBus
A multi-function external bus interface called FlexBus is provided with basic functionality to interface to slave-only devices up
to a maximum bus frequency of 80MHz. It can be directly connected to asynchronous or synchronous devices such as external
boot ROMs, flash memories, gate-array logic, or other simple target (slave) devices with little or no additional circuitry. For
asynchronous devices a simple chip-select based interface can be used. The FlexBus interface has six general purpose
chip-selects (FB_CS[5:0]) which can be configured to be distributed between the FlexBus or SDRAM memory interfaces.
Chip-select, FB_CS0 can be dedicated to boot ROM access and can be programmed to be byte (8 bits), word (16 bits), or
longword (32 bits) wide. Control signal timing is compatible with common ROM/flash memories.
5.6.1.1
FlexBus AC Timing Characteristics
The following timing numbers indicate when data is latched or driven onto the external bus, relative to the system clock.
Table 9. FlexBus AC Timing Specifications
Num
Characteristic
Symbol
Min
Max
Unit
—
Frequency of Operation
fsys/3
—
80
—
Mhz
ns
FB1 Clock Period (FB_CLK)
tFBCK ( cyc)
tFBCHDCV
tFBCHDCI
t
12.5
Address, Data, and Control Output Valid (A[23:0], D[31:0],
FB_CS[5:0], R/W, TS, BE/BWE[3:0] and OE)1
FB2
FB3
—
1
7.0
—
ns
ns
Address, Data, and Control Output Hold (A[23:0], D[31:0],
FB_CS[5:0], R/W, TS, BE/BWE[3:0], and OE)1, 2
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
19
Electrical Characteristics
Num
Table 9. FlexBus AC Timing Specifications (continued)
Characteristic
Symbol
Min
Max
Unit
FB4 Data Input Setup
FB5 Data Input Hold
tDVFBCH
tDIFBCH
tCVFBCH
tCIFBCH
3.5
0
—
—
—
—
ns
ns
ns
ns
FB6 Transfer Acknowledge (TA) Input Setup
FB7 Transfer Acknowledge (TA) Input Hold
4
0
1
2
Timing for chip selects only applies to the FB_CS[5:0] signals. Please see Section 5.7.2, “DDR SDRAM AC
Timing Characteristics” for SD_CS[3:0] timing.
The FlexBus supports programming an extension of the address hold. Please consult the Reference Manual
for more information.
NOTE
The processor drives the data lines during the first clock cycle of the transfer
with the full 32-bit address. This may be ignored by standard connected
devices using non-multiplexed address and data buses. However, some
applications may find this feature beneficial.
The address and data busses are muxed between the FlexBus and SDRAM
controller. At the end of the read and write bus cycles the address signals are
indeterminate.
S0
S1
S2
S3
FB_CLK
FB1
FB3
ADDR[23:0]
FB_A[23:0]
FB2
FB5
FB_D[31:X]
ADDR[31:X]
DATA
FB4
FB_R/W
FB_TS
FB_CSn, FB_OE,
FB_BE/BWEn
FB6
FB7
FB_TA
Figure 7. FlexBus Read Timing
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
20
Freescale Semiconductor
Electrical Characteristics
S0
S1
S2
S3
FB_CLK
FB1
FB3
ADDR[23:0]
FB_A[23:0]
FB2
ADDR[31:X]
FB_D[31:X]
DATA
FB_R/W
FB_TS
FB_CSn, FB_BE/BWEn
FB_OE
FB6
FB7
FB_TA
Figure 8. FlexBus Write Timing
5.7
SDRAM Bus
The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports standard SDRAM or
double data rate (DDR) SDRAM, but it does not support both at the same time.
5.7.1
SDR SDRAM AC Timing Characteristics
The following timing numbers indicate when data is latched or driven onto the external bus, relative to the memory bus clock,
when operating in SDR mode on write cycles and relative to SD_DQS on read cycles. The device’s SDRAM controller is a
DDR controller that has an SDR mode. Because it is designed to support DDR, a DQS pulse must remain supplied to the device
for each data beat of an SDR read. The processor accomplishes this by asserting a signal named SD_SDR_DQS during read
cycles. Care must be taken during board design to adhere to the following guidelines and specs with regard to the
SD_SDR_DQS signal and its usage.
Table 10. SDR Timing Specifications
Symbol
Characteristic
Frequency of Operation1
Symbol
Min
Max
Unit
•
•
60
80
MHz
ns
SD1 Clock Period2
tSDCK
tSDCKH
tSDCKH
12.5
0.45
0.45
16.67
0.55
0.55
SD3 Pulse Width High3
SD4 Pulse Width Low4
SD_CLK
SD_CLK
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA,
SD_CS[1:0] - Output Valid
0.5 × SD_CLK
SD5
tSDCHACV
—
ns
+ 1.0
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA,
SD_CS[1:0] - Output Hold
SD6
tSDCHACI
tDQSOV
2.0
—
—
ns
ns
ns
SD7 SD_SDR_DQS Output Valid5
Self timed
SD_DQS[3:0] input setup relative to SD_CLK6
SD8
0.25 ×
SD_CLK
tDQVSDCH
0.40 × SD_CLK
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
21
Electrical Characteristics
Symbol
Table 10. SDR Timing Specifications (continued)
Characteristic Symbol Min
Max
Unit
SD9 SD_DQS[3:2] input hold relative to SD_CLK7
tDQISDCH Does not apply. 0.5×SD_CLK fixed width.
0.25 ×
Data (D[31:0]) Input Setup relative to SD_CLK (reference
SD10
only)8
tDVSDCH
tDISDCH
tSDCHDMV
tSDCHDMI
—
ns
ns
ns
ns
SD_CLK
SD11 Data Input Hold relative to SD_CLK (reference only)
1.0
—
Data (D[31:0]) and Data Mask(SD_DQM[3:0]) Output Valid
SD12
0.75 × SD_CLK
+ 0.5
—
SD13 Data (D[31:0]) and Data Mask (SD_DQM[3:0]) Output Hold
1.5
—
1
The FlexBus and SDRAM clock operates at the same frequency of the internal bus clock. See the PLL chapter of the MCF5373
Reference Manual for more information on setting the SDRAM clock rate.
2
3
4
5
SD_CLK is one SDRAM clock in (ns).
Pulse width high plus pulse width low cannot exceed min and max clock period.
Pulse width high plus pulse width low cannot exceed min and max clock period.
SD_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This is a guideline only. Subtle variation
from this guideline is expected. SD_DQS only pulses during a read cycle and one pulse occurs for each data beat.
6
7
8
SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This spec is a guideline only. Subtle
variation from this guideline is expected. SDR_DQS only pulses during a read cycle and one pulse occurs for each data beat.
The SDR_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling edge
does not affect the memory controller.
Because a read cycle in SDR mode uses the DQS circuit within the device, it is most critical that the data valid window be
centered 1/4 clk after the rising edge of DQS. Ensuring that this happens results in successful SDR reads. The input setup
spec is provided as guidance.
SD2
SD1
SD_CLK
SD3
SD5
SD_CSn
SD_RAS
SD_CAS
SD_WE
CMD
ROW
SD4
A[23:0]
SD_BA[1:0]
COL
SD11
SDDM
D[31:0]
SD12
WD1
WD2
WD3
WD4
Figure 9. SDR Write Timing
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
22
Freescale Semiconductor
Electrical Characteristics
SD2
SD1
SD_CLK
SD5
SD_CSn,
SD_RAS,
SD_CAS,
SD_WE
SD3
CMD
ROW
3/4 MCLK
Reference
SD4
A[23:0],
SD_BA[1:0]
COL
tDQS
SDDM
SD6
SD_SDR_DQS (Measured at Output Pin)
SD_DQS[3:2] (Measured at Input Pin)
Board Delay
SD8
Board Delay
SD7
Delayed
SD_CLK
SD9
D[31:0]
from
WD1
WD2
WD3
WD4
Memories
NOTE: Data driven from memories relative
to delayed memory clock.
SD10
Figure 10. SDR Read Timing
5.7.2
DDR SDRAM AC Timing Characteristics
When using the SDRAM controller in DDR mode, the following timing numbers must be followed to properly latch or drive
data onto the memory bus. All timing numbers are relative to the four DQS byte lanes.
Table 11. DDR Timing Specifications
Num
Characteristic
Frequency of Operation
Symbol
Min
Max
Unit
•
tDDCK
tDDSK
tDDCKH
tDDCKL
60
80
Mhz
ns
DD1 Clock Period1
12.5
0.45
0.45
16.67
0.55
0.55
DD2 Pulse Width High2
DD3 Pulse Width Low3
SD_CLK
SD_CLK
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS[1:0] - Output Valid3
0.5 × SD_CLK
DD4
DD5
tSDCHACV
—
ns
+ 1.0
Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS[1:0] - Output Hold
tSDCHACI
tCMDVDQ
tDQDMV
2.0
—
—
1.25
—
ns
SD_CLK
ns
DD6 Write Command to first DQS Latching Transition
Data and Data Mask Output Setup (DQ-->DQS) Relative
DD7
1.5
to DQS (DDR Write Mode)4, 5
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
23
Electrical Characteristics
Num
Table 11. DDR Timing Specifications (continued)
Characteristic
Symbol
Min
Max
Unit
Data and Data Mask Output Hold (DQS-->DQ) Relative to
DQS (DDR Write Mode)6
tDQDMI
1.0
—
ns
DD8
DD9 Input Data Skew Relative to DQS (Input Setup)7
tDVDQ
tDIDQ
—
1
ns
ns
Input Data Hold Relative to DQS8
DD10
0.25 × SD_CLK
—
+ 0.5ns
DD11 DQS falling edge from SDCLK rising (output hold time)
DD12 DQS input read preamble width
tDQLSDCH
tDQRPRE
tDQRPST
tDQWPRE
tDQWPST
0.5
0.9
—
ns
1.1
0.6
SD_CLK
SD_CLK
SD_CLK
SD_CLK
DD13 DQS input read postamble width
DD14 DQS output write preamble width
DD15 DQS output write postamble width
SD_CLK is one SDRAM clock in (ns).
0.4
0.25
0.4
0.6
1
2
3
Pulse width high plus pulse width low cannot exceed min and max clock period.
Command output valid should be 1/2 the memory bus clock (SD_CLK) plus some minor adjustments for process, temperature,
and voltage variations.
4
This specification relates to the required input setup time of today’s DDR memories. The processor’s output setup should be
larger than the input setup of the DDR memories. If it is not larger, the input setup on the memory is in violation.
MEM_DATA[31:24] is relative to MEM_DQS[3], MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to
MEM_DQS[1], and MEM_[7:0] is relative MEM_DQS[0].
5
6
The first data beat is valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats are
valid for each subsequent DQS edge.
This specification relates to the required hold time of today’s DDR memories. MEM_DATA[31:24] is relative to MEM_DQS[3],
MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to MEM_DQS[1], and MEM_[7:0] is relative
MEM_DQS[0].
7
8
Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line
becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other
factors).
Data input hold is derived from each DQS clock edge. It begins with a DQS transition and ends when the first data line
becomes invalid.
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
24
Freescale Semiconductor
Electrical Characteristics
DD1
DD2
SD_CLK
DD3
SD_CLK
DD5
SD_CSn,SD_WE,
SD_RAS, SD_CAS
CMD
ROW
DD4
DD6
A[13:0]
COL
DD7
DM3/DM2
SD_DQS3/SD_DQS2
D[31:24]/D[23:16]
DD8
DD7
WD1 WD2 WD3 WD4
DD8
Figure 11. DDR Write Timing
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
25
Electrical Characteristics
DD1
DD2
SD_CLK
DD3
SD_CLK
DD5
CL=2
SD_CSn,SD_WE,
SD_RAS, SD_CAS
CMD
ROW
DD4
CL=2.5
A[13:0]
COL
DD9
DQS Read
Postamble
DQS Read
Preamble
SD_DQS3/SD_DQS2
D[31:24]/D[23:16]
DD10
WD1 WD2 WD3 WD4
DQS Read
Preamble
DQS Read
Postamble
SD_DQS3/SD_DQS2
D[31:24]/D[23:16]
WD1 WD2 WD3 WD4
Figure 12. DDR Read Timing
5.8
General Purpose I/O Timing
1
Table 12. GPIO Timing
Num
Characteristic
Symbol
Min
Max
Unit
G1
G2
G3
G4
FB_CLK High to GPIO Output Valid
FB_CLK High to GPIO Output Invalid
GPIO Input Valid to FB_CLK High
FB_CLK High to GPIO Input Invalid
tCHPOV
tCHPOI
tPVCH
tCHPI
—
1.5
9
10
—
—
—
ns
ns
ns
ns
1.5
1
GPIO pins include: IRQn, PWM, UART, FlexCAN, and Timer pins.
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
26
Freescale Semiconductor
Electrical Characteristics
FB_CLK
G2
G1
GPIO Outputs
G3
G4
GPIO Inputs
Figure 13. GPIO Timing
5.9
Reset and Configuration Override Timing
Table 13. Reset and Configuration Override Timing
Num
Characteristic
Symbol
Min
Max
Unit
R1 RESET Input valid to FB_CLK High
tRVCH
tCHRI
9
1.5
5
—
—
—
10
—
—
—
1
ns
ns
R2 FB_CLK High to RESET Input invalid
R3 RESET Input valid Time 1
tRIVT
tCYC
ns
R4 FB_CLK High to RSTOUT Valid
tCHROV
tROVCV
tCOS
—
0
R5 RSTOUT valid to Config. Overrides valid
R6 Configuration Override Setup Time to RSTOUT invalid
R7 Configuration Override Hold Time after RSTOUT invalid
R8 RSTOUT invalid to Configuration Override High Impedance
ns
20
0
tCYC
ns
tCOH
tROICZ
—
tCYC
1
During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously to
the system. Thus, RESET must be held a minimum of 100 ns.
FB_CLK
R1
R2
R3
RESET
R4
R4
RSTOUT
R8
R5
R6
R7
Configuration Overrides*:
(RCON, Override pins])
Figure 14. RESET and Configuration Override Timing
NOTE
Refer to the CCM chapter of the MCF5373 Reference Manual for more information.
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
27
Electrical Characteristics
5.10 USB On-The-Go
The MCF5373 device is compliant with industry standard USB 2.0 specification.
5.11 SSI Timing Specifications
This section provides the AC timings for the SSI in master (clocks driven) and slave modes (clocks input). All timings are given
for non-inverted serial clock polarity (SSI_TCR[TSCKP] = 0, SSI_RCR[RSCKP] = 0) and a non-inverted frame sync
(SSI_TCR[TFSI] = 0, SSI_RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings
remain valid by inverting the clock signal (SSI_BCLK) and/or the frame sync (SSI_FS) shown in the figures below.
1
Table 14. SSI Timing – Master Modes
Num
Description
SSI_MCLK cycle time2
Symbol
Min
Max
Units
S1
S2
S3
S4
S5
S6
S7
S8
S9
tMCLK 8 × tSYS
—
55%
—
ns
tMCLK
ns
SSI_MCLK pulse width high / low
SSI_BCLK cycle time3
45%
tBCLK 8 × tSYS
SSI_BCLK pulse width
45%
—
-2
55%
15
tBCLK
ns
SSI_BCLK to SSI_FS output valid
SSI_BCLK to SSI_FS output invalid
SSI_BCLK to SSI_TXD valid
—
ns
—
-4
15
ns
SSI_BCLK to SSI_TXD invalid / high impedence
SSI_RXD / SSI_FS input setup before SSI_BCLK
—
ns
15
0
—
ns
S10 SSI_RXD / SSI_FS input hold after SSI_BCLK
—
ns
1
2
All timings specified with a capactive load of 25pF.
SSI_MCLK can be generated from SSI_CLKIN or a divided version of the internal system clock
(SYSCLK).
3
SSI_BCLK can be derived from SSI_CLKIN or a divided version of SYSCLK. If the SYSCLK is used, the
minimum divider is 6. If the SSI_CLKIN input is used, the programmable dividers must be set to ensure
that SSI_BCLK does not exceed 4 x fSYS
Table 15. SSI Timing – Slave Modes
Description Symbol
.
1
Num
S11 SSI_BCLK cycle time
Min
Max
Units
tBCLK 8 × tSYS
—
55%
—
ns
tBCLK
ns
S12 SSI_BCLK pulse width high/low
45%
10
3
S13 SSI_FS input setup before SSI_BCLK
S14 SSI_FS input hold after SSI_BCLK
S15 SSI_BCLK to SSI_TXD/SSI_FS output valid
—
ns
—
15
ns
S16 SSI_BCLK to SSI_TXD/SSI_FS output invalid/high
impedence
-2
—
ns
S17 SSI_RXD setup before SSI_BCLK
S18 SSI_RXD hold after SSI_BCLK
10
3
—
—
ns
ns
1
All timings specified with a capactive load of 25pF.
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
28
Freescale Semiconductor
Electrical Characteristics
S1
S2
S2
SSI_MCLK
(Output)
S3
SSI_BCLK
(Output)
S4
S4
S5
S6
SSI_FS
(Output)
S9
S10
SSI_FS
(Input)
S7
S8
S7
S8
SSI_TXD
SSI_RXD
S9
S10
Figure 15. SSI Timing – Master Modes
S11
SSI_BCLK
(Input)
S12
S12
S15
S16
SSI_FS
(Output)
S13
S14
SSI_FS
(Input)
S15
S16
S16
S15
SSI_TXD
SSI_RXD
S17
S18
Figure 16. SSI Timing – Slave Modes
2
5.12 I C Input/Output Timing Specifications
2
Table 16 lists specifications for the I C input timing parameters shown in Figure 17.
2
Table 16. I C Input Timing Specifications between SCL and SDA
Num
Characteristic
Start condition hold time
Min
Max
Units
I1
I2
I3
I4
2
8
—
—
1
tcyc
tcyc
ms
ns
Clock low period
I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V)
Data hold time
—
0
—
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
29
Electrical Characteristics
Table 16. I C Input Timing Specifications between SCL and SDA (continued)
2
Num
Characteristic
Min
Max
Units
I5
I6
I7
I8
I9
I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
Clock high time
—
4
1
ms
tcyc
ns
—
—
—
—
Data setup time
0
Start condition setup time (for repeated start condition only)
Stop condition setup time
2
tcyc
tcyc
2
2
Table 17 lists specifications for the I C output timing parameters shown in Figure 17.
2
Table 17. I C Output Timing Specifications between SCL and SDA
Num
I11 Start condition hold time
I2 1 Clock low period
Characteristic
Min
Max
Units
6
10
—
7
—
—
—
—
3
tcyc
tcyc
µs
I3 2 I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V)
I4 1 Data hold time
tcyc
ns
I5 3 I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
I6 1 Clock high time
—
10
2
—
—
—
—
tcyc
tcyc
tcyc
tcyc
I7 1 Data setup time
I8 1 Start condition setup time (for repeated start condition only)
I9 1 Stop condition setup time
20
10
1
Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum
frequency (IFDR = 0x20) results in minimum output timings as shown in Table 17. The I2C interface is
designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual
position is affected by the prescale and division values programmed into the IFDR; however, the numbers
given in Table 17 are minimum values.
2
3
Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively drive
low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance and
pull-up resistor values.
Specified at a nominal 50-pF load.
Figure 17 shows timing for the values in Table 17 and Table 16.
I5
I6
I2
I2C_SCL
I2C_SDA
I7
I8
I1
I9
I4
I3
2
Figure 17. I C Input/Output Timings
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
30
Freescale Semiconductor
Electrical Characteristics
5.13 Fast Ethernet AC Timing Specifications
MII signals use TTL signal levels compatible with devices operating at 5.0 V or 3.3 V.
5.13.1 MII Receive Signal Timing
The receiver functions correctly up to a FEC_RXCLK maximum frequency of 25 MHz +1%. The processor clock frequency
must exceed twice the FEC_RXCLK frequency.
Table 18 lists MII receive channel timings.
Table 18. MII Receive Signal Timing
Num
Characteristic
Min
Max
Unit
M1
M2
M3
M4
FEC_RXD[3:0], FEC_RXDV, FEC_RXER to FEC_RXCLK setup
FEC_RXCLK to FEC_RXD[3:0], FEC_RXDV, FEC_RXER hold
FEC_RXCLK pulse width high
5
—
—
ns
5
ns
35%
35%
65%
65%
FEC_RXCLK period
FEC_RXCLK period
FEC_RXCLK pulse width low
Figure 18 shows MII receive signal timings listed in Table 18.
M3
FEC_RXCLK (input)
M4
FEC_RXD[3:0] (inputs)
FEC_RXDV
FEC_RXER
M1
M2
Figure 18. MII Receive Signal Timing Diagram
5.13.2 MII Transmit Signal Timing
Table 19 lists MII transmit channel timings.
The transmitter functions correctly up to a FEC_TXCLK maximum frequency of 25 MHz +1%. The processor clock frequency
must exceed twice the FEC_TXCLK frequency.
Table 19. MII Transmit Signal Timing
Num
Characteristic
Min
Max
Unit
M5
M6
M7
M8
FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER invalid
FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER valid
FEC_TXCLK pulse width high
5
—
ns
—
25
ns
35%
35%
65%
65%
FEC_TXCLK period
FEC_TXCLK period
FEC_TXCLK pulse width low
Figure 19 shows MII transmit signal timings listed in Table 19.
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
31
Electrical Characteristics
M7
FEC_TXCLK (input)
M5
M8
FEC_TXD[3:0] (outputs)
FEC_TXEN
FEC_TXER
M6
Figure 19. MII Transmit Signal Timing Diagram
5.13.3 MII Async Inputs Signal Timing
Table 20 lists MII asynchronous inputs signal timing.
Table 20. MII Async Inputs Signal Timing
Num
Characteristic
Min
Max
Unit
M9
FEC_CRS, FEC_COL minimum pulse width
1.5
—
FEC_TXCLK period
FEC_CRS
FEC_COL
M9
Figure 20. MII Async Inputs Timing Diagram
5.13.4 MII Serial Management Channel Timing
Table 21 lists MII serial management channel timings. The FEC functions correctly with a maximum MDC frequency of 2.5
MHz.
Table 21. MII Serial Management Channel Timing
Num
Characteristic
Min Max
Unit
M10 FEC_MDC falling edge to FEC_MDIO output invalid (minimum
propagation delay)
0
—
ns
M11 FEC_MDC falling edge to FEC_MDIO output valid (max prop delay)
M12 FEC_MDIO (input) to FEC_MDC rising edge setup
M13 FEC_MDIO (input) to FEC_MDC rising edge hold
M14 FEC_MDC pulse width high
—
10
0
25
—
—
ns
ns
ns
40% 60% FEC_MDC period
40% 60% FEC_MDC period
M15 FEC_MDC pulse width low
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
32
Freescale Semiconductor
Electrical Characteristics
M14
M15
FEC_MDC (output)
FEC_MDIO (output)
M10
M11
FEC_MDIO (input)
M12
M13
Figure 21. MII Serial Management Channel Timing Diagram
5.14 32-Bit Timer Module Timing Specifications
Table 22 lists timer module AC timings.
Table 22. Timer Module AC Timing Specifications
Name
Characteristic
Min
Max
Unit
T1
T2
DT0IN / DT1IN / DT2IN / DT3IN cycle time
DT0IN / DT1IN / DT2IN / DT3IN pulse width
3
1
—
—
tCYC
tCYC
5.15 QSPI Electrical Specifications
Table 23 lists QSPI timings.
Table 23. QSPI Modules AC Timing Specifications
Characteristic
Name
Min
Max
Unit
QS1
QS2
QS3
QS4
QS5
QSPI_CS[3:0] to QSPI_CLK
1
—
2
510
10
—
tCYC
ns
QSPI_CLK high to QSPI_DOUT valid.
QSPI_CLK high to QSPI_DOUT invalid. (Output hold)
QSPI_DIN to QSPI_CLK (Input setup)
QSPI_DIN to QSPI_CLK (Input hold)
ns
9
—
ns
9
—
ns
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
33
Electrical Characteristics
QS1
QSPI_CS[3:0]
QSPI_CLK
QS2
QSPI_DOUT
QSPI_DIN
QS3
QS4
QS5
Figure 22. QSPI Timing
5.16 JTAG and Boundary Scan Timing
Table 24. JTAG and Boundary Scan Timing
Num
Characteristics1
TCLK Frequency of Operation
Symbol
Min
Max
Unit
J1
J2
J3
J4
J5
J6
J7
J8
J9
fJCYC
tJCYC
DC
4
1/4
—
—
3
fsys/3
tCYC
ns
TCLK Cycle Period
TCLK Clock Pulse Width
tJCW
26
0
TCLK Rise and Fall Times
tJCRF
ns
Boundary Scan Input Data Setup Time to TCLK Rise
Boundary Scan Input Data Hold Time after TCLK Rise
TCLK Low to Boundary Scan Output Data Valid
TCLK Low to Boundary Scan Output High Z
TMS, TDI Input Data Setup Time to TCLK Rise
tBSDST
tBSDHT
tBSDV
4
—
—
33
33
—
—
26
8
ns
26
0
ns
ns
tBSDZ
0
ns
tTAPBST
tTAPBHT
tTDODV
tTDODZ
tTRSTAT
tTRSTST
4
ns
J10 TMS, TDI Input Data Hold Time after TCLK Rise
J11 TCLK Low to TDO Data Valid
10
0
ns
ns
J12 TCLK Low to TDO High Z
0
ns
J13 TRST Assert Time
100
10
—
—
ns
J14 TRST Setup Time (Negation) to TCLK High
ns
1
JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it.
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
34
Freescale Semiconductor
Electrical Characteristics
J2
J3
J3
VIH
TCLK
(input)
VIL
J4
J4
Figure 23. Test Clock Input Timing
TCLK
VIL
VIH
J5
J6
Data Inputs
Input Data Valid
J7
J8
Data Outputs
Output Data Valid
Data Outputs
Data Outputs
J7
Output Data Valid
Figure 24. Boundary Scan (JTAG) Timing
TCLK
VIL
VIH
J9
Input Data Valid
J10
TDI
TMS
J11
TDO
Output Data Valid
J12
J11
TDO
TDO
Output Data Valid
Figure 25. Test Access Port Timing
TCLK
TRST
J14
J13
Figure 26. TRST Timing
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
35
Current Consumption
5.17 Debug AC Timing Specifications
Table 25 lists specifications for the debug AC timing parameters shown in Figure 27.
Table 25. Debug AC Timing Specification
Num
Characteristic
PSTCLK cycle time
Min
Max
Units
D0
D1
D2
D3
D41
D5
D6
2
—
1.5
1
2
3.0
—
—
—
—
—
t
SYS = 1/fSYS
ns
PSTCLK rising to PSTDDATA valid
PSTCLK rising to PSTDDATA invalid
DSI-to-DSCLK setup
ns
PSTCLK
PSTCLK
PSTCLK
PSTCLK
DSCLK-to-DSO hold
4
DSCLK cycle time
5
BKPT assertion time
1
1
DSCLK and DSI are synchronized internally. D4 is measured from the synchronized
DSCLK input relative to the rising edge of PSTCLK.
D0
PSTCLK
D2
D1
PSTDDATA[7:0]
Figure 27. Real-Time Trace AC Timing
D5
DSCLK
DSI
D3
Current
D4
Next
DSO
Past
Current
Figure 28. BDM Serial Port AC Timing
6
Current Consumption
All current consumption data is lab data measured on a single device using an evaluation board. Table 26 shows the typical
power consumption in low-power modes. These current measurements are taken after executing a STOP instruction.
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
36
Freescale Semiconductor
Current Consumption
1,2
Table 26. Current Consumption in Low-Power Modes
58 MHz
(Typ)3
64 MHz
(Typ)3
72 MHz
(Typ)3
80 MHz
(Typ)3
80 MHz
Units
Mode
Voltage
(Peak)4
3.3 V
1.5 V
3.3 V
1.5 V
3.3 V
1.5 V
3.3 V
1.5 V
3.3 V
1.5 V
3.3 V
1.5 V
3.9
3.92
1.04
4.0
1.04
4.8
4.0
1.04
4.8
4.0
1.08
4.8
Stop Mode 3 (Stop 11)5
Stop Mode 2 (Stop 10)4
Stop Mode 1(Stop 01)4
Stop Mode 0 (Stop 00)4
Wait/Doze
1.04
4.69
4.72
2.69
2.69
2.70
4.81
17.85
24.33
18.06
25.21
30.81
42.3
65.4
2.70
4.81
19.91
26.13
20.12
27.03
34.47
50.5
73.4
2.75
4.81
4.72
4.73
15.28
21.65
15.47
22.49
26.79
33.61
56.3
16.44
21.68
16.63
22.52
28.85
33.61
60.7
20.42
mA
26.16
20.67
39.8
97.4
62.6
Run
132.3
1
2
3
All values are measured with a 3.30V EVDD, 3.30V SDVDD and 1.5V IVDD power supplies. Tests performed at room
temperature with pins configured for high drive strength.
Refer to the Power Management chapter in the MCF537x Reference Manual for more information on low-power
modes.
All peripheral clocks except UART0, FlexBus, INTC0, reset controller, PLL, and edge port off before entering low
power mode. All code executed from flash.
4
5
All peripheral clocks on before entering low power mode. All code is executed from flash.
See the description of the low-power control register (LCPR) in the MCF537x Reference Manual for more
information on stop modes 0–3.
450
400
350
300
250
200
150
100
50
Stop 0 - Flash
Stop 1 - Flash
Stop 2 - Flash
Stop 3 - Flash
Wait/Doze - Flash
Run - Flash
0
58
64
72
80
80(peak)
fsys/3 (MHz)
Figure 29. Current Consumption in Low-Power Modes
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
37
Current Consumption
1
Table 27. Typical Active Current Consumption Specifications
Typical2 Active
fsys/3 Frequency
1.333 MHz
2.666 MHz
58 MHz
Voltage
Peak3
Unit
(Flash)
3.3V
1.5V
3.3V
1.5V
3.3V
1.5V
3.3V
1.5V
3.3V
1.5V
3.3V
1.5V
7.73
2.87
7.74
3.56
8.60
5.52
49.3
91.70
54.0
97.0
63.7
104.7
73.7
112.9
8.57
4.37
40.10
65.90
44.40
69.50
53.6
mA
64 MHz
72 MHz
74.6
63.0
80 MHz
79.6
1
All values are measured with a 3.30 V EVDD, 3.30 V SDVDD and 1.5 V IVDD power
supplies. Tests performed at room temperature with pins configured for high drive
strength.
2
3
CPU polling a status register. All peripheral clocks except UART0, FlexBus,
INTC0, reset controller, PLL, and edge port disabled.
Peak current measured while running a while(1) loop with all modules active.
Figure 30 shows the estimated maximum power consumption.
Estimated Power Consumption vs. Core Frequency
300
250
200
150
100
50
0
0
40
80
120
160
200
240
Core Frequency (MHz)
Figure 30. Estimated Maximum Power Consumption
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
38
Freescale Semiconductor
Package Information
7
Package Information
This section contains drawings showing the pinout and the packaging and mechanical characteristics of the MCF537x devices.
NOTE
The mechanical drawings are the latest revisions at the time of publication of this
document. The most up-to-date mechanical drawings can be found at the product summary
page located at http://www.freescale.com/coldfire.
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
39
Package Information
7.1
Package Dimensions—196 MAPBGA
Figure 31 shows the MCF5373LCVM240, MCF5372LCVM240, and MCF53721CVM240 package dimensions.
NOTES:
D
X
Y
1. Dimensions are in millimeters.
2. Interpretdimensionsandtolerances
per ASME Y14.5M, 1994.
Laser mark for pin 1
identification in
this area
3. Dimension B is measured at the
maximum solder ball diameter,
parallel to datum plane Z.
4. Datum Z (seating plane) is defined
bythesphericalcrownsofthesolder
balls.
M
K
5. Parallelism measurement shall
exclude any effect of mark on top
surface of package.
Millimeters
DIM Min Max
A 1.32 1.75
A1 0.27 0.47
A2 1.18 REF
E
b
D
E
e
0.35 0.65
15.00 BSC
15.00 BSC
1.00 BSC
0.50 BSC
S
M
Top View
0.20
13X e
S
Metalized mark for
pin 1 identification
in this area
14 13 12 11 10
9
6
5
4
3
2
1
A
B
C
D
E
F
5
S
0.30 Z
13X e
A2
A
G
H
J
A1
0.15 Z
4
Z
K
L
Detail K
Rotated 90 Clockwise
°
M
N
P
3
196X
b
Bottom View
0.30 Z X Y
0.10 Z
View M-M
Figure 31. 196 MAPBGA Package Dimensions (Case No. 1128A-01)
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
40
Freescale Semiconductor
Package Information
7.2
Package Dimensions—160 QFP
Figure 32 and Figure 33 show the MCF5372CAB180 and MCF5373CAB180 package dimensions.
Top View
Figure 32. 160QFP Package Dimensions (Sheet 1 of 2)
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
41
Package Information
Figure 33. 160QFP Package Dimensions (Sheet 2 of 2)
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
42
Freescale Semiconductor
Revision History
8
Revision History
Table 28. MCF5373DS Document Revision History
Rev. No.
Substantive Changes
Date of Release
0
• Initial release
11/2005
12/2005
0.1
• Swapped pin locations PLL_VSS (J11->H11) and DRAMSEL
(H11->J11) in Table 1. Figure 4 is correct.
0.2
0.3
1
• Added not to Section 7, “Package Information.”
• Added “top view” and “bottom view” where appropriate in mechanical
drawings and pinout figures.
3/2006
4/2006
7/2007
• Figure 6: Corrected “FB_CLK (75MHz)” label to “FB_CLK (80MHz)”
• Changed 160QFP pinouts in Figure 5 and Table 2: Removed IRQ3
pin, shifted pins 89–99 up one pin to 90–100. Pin 89 is now VSS.
• Table 2: Rearranged GPIO signal names for FEC pins.
• Removed ULPI specifications as the device does not support ULPI.
• Updated thermal characteristic values in Table 7.
• Updated DC electricals values in Table 7.
• Updated Section 3.3, “Supply Voltage Sequencing and Separation
Cautions” and subsections.
• Updated and added Oscillator/PLL characteristics in Table 8.
• Table 9: Swapped min/max for FB1; Removed FB8 & FB9.
• Updated SDRAM write timing diagram, Figure 9.
• Table 11: Added values for frequency of operation and DD1.
• Replaced figure & table Section 5.11, “SSI Timing Specifications,”
with slave & master mode versions.
• Removed second sentence from Section 5.13.2, “MII Transmit Signal
Timing,” regarding no minimum frequency requirement for TXCLK.
• Removed third and fourth paragraphs from Section 5.13.2, “MII
Transmit Signal Timing,” as this feature is not supported on this
device.
• Updated figure & table Section 5.17, “Debug AC Timing
Specifications.”
• Renamed & moved previous version’s Section 5.5 “Power
Consumption” to Section 6, “Current Consumption.” Added additional
real-world data to this section as well.
2
• Added MCF53721 device information throughout: features list, family
configuration table, ordering information table, signals description
table, and relevant package diagram titles
8/2007
• Remove Footnote 1 from Table 11.
• Changed document type from Advance Information to Technical Data.
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
43
Revision History
Table 28. MCF5373DS Document Revision History (continued)
Substantive Changes
Rev. No.
3
Date of Release
• Removed cryptography from Table 1 for the MCF53721 device.
• Corrected D0 spec in Table 25 from 1.5 x tsys to 2 x tsys for min and
max balues.
4/2008
• Updated FlexBus read and write timing diagrams in Figure 7 and
Figure 8.
• Corrected package information in Table 2 for MCF5373LCVM240
device from “256 MAPBGA” to “196 MAPBGA”.
• Removed footnote 2 from the IRQ[7:1] alternate functions USBHOST
VBUS_EN, USBHOST VBUS_OC, SSI_MCLK, USB_CLKIN, and
SSI_CLKIN signals in Table 6.
4
Changed the following specs in Table 10 and Table 11:
• Minimum frequency of operation from TBD to 60MHz
• Maximum clock period from TBD to 16.67 ns
11/2008
Added FlexCAN for the MCF53721 device in features list, block diagram,
Signal Information and Muxing table, and GPIO timing diagram
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
44
Freescale Semiconductor
Revision History
MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4
Freescale Semiconductor
45
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Document Number: MCF5373DS
Rev. 4
11/2008
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