MC9328MXLDVM15R2 [NXP]
32-BIT, 150MHz, RISC PROCESSOR, PBGA256, 14 X 14 MM, 1.30 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, MAPBGA-256;型号: | MC9328MXLDVM15R2 |
厂家: | NXP |
描述: | 32-BIT, 150MHz, RISC PROCESSOR, PBGA256, 14 X 14 MM, 1.30 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, MAPBGA-256 时钟 外围集成电路 |
文件: | 总90页 (文件大小:1439K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Document Number: MC9328MXL
Rev. 8, 12/2006
Freescale Semiconductor
Data Sheet: Technical Data
MC9328MXL
Package Information
Plastic Package
Case 1304B-01
MC9328MXL
(MAPBGA–225)
Ordering Information
See Table 1 on page 3
Contents
1 Introduction
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Signals and Connections . . . . . . . . . . . . . . . 4
3 Electrical Characteristics . . . . . . . . . . . . . . 17
The i.MX Family of applications processors provides a
leap in performance with an ARM9™ microprocessor
core and highly integrated system functions. The i.MX
family specifically addresses the requirements of the
personal, portable product market by providing
intelligent integrated peripherals, an advanced processor
core, and power management capabilities.
4 Functional Description and Application
Information . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5 Pin-Out and Package Information . . . . . . . . 84
6 Product Documentation . . . . . . . . . . . . . . . . 88
Contact Information . . . . . . . . . . . . . . . Last Page
The MC9328MXL (i.MXL) processor features the
advanced and power-efficient ARM920T™ core that
operates at speeds up to 200 MHz. Integrated modules,
which include a USB device, an LCD controller, and an
MMC/SD host controller, support a suite of peripherals
to enhance portable products seeking to provide a rich
multimedia experience. It is packaged in either a
256-contact Mold Array Process-Ball Grid Array
(MAPBGA) or 225-contact MAPBGA package.
Figure 1 shows the functional block diagram of the
i.MXL processor.
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its
products.
© Freescale Semiconductor, Inc., 2004, 2005, 2006. All rights reserved.
Introduction
Standard
System I/O
System Control
Power
Control
CGM
(PLLx2)
JTAG/ICE
Bootstrap
GPIO
PWM
Connectivity
MC9328MXL
CPU Complex
ARM9TDMI™
MMC/SD
Timer 1 & 2
RTC
Memory Stick®
Host Controller
Watchdog
SPI 1 and
SPI 2
I Cache
D Cache
Multimedia
UART 1
UART 2
Multimedia
Accelerator
Interrupt
Controller
AIPI 1
AIPI 2
VMMU
Video Port
2
SSI/I S
DMAC
Bus
Human Interface
2
I C
(11 Chnl)
Control
LCD Controller
EIM &
SDRAMC
USB Device
Figure 1. i.MXL Functional Block Diagram
1.1
Features
To support a wide variety of applications, the processor offers a robust array of features, including the following:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
ARM920T™ Microprocessor Core
AHB to IP Bus Interfaces (AIPIs)
External Interface Module (EIM)
SDRAM Controller (SDRAMC)
DPLL Clock and Power Control Module
Two Universal Asynchronous Receiver/Transmitters (UART 1 and UART 2)
Serial Peripheral Interface (SPI)
Two General-Purpose 32-bit Counters/Timers
Watchdog Timer
Real-Time Clock/Sampling Timer (RTC)
LCD Controller (LCDC)
Pulse-Width Modulation (PWM) Module
Universal Serial Bus (USB) Device
Multimedia Card and Secure Digital (MMC/SD) Host Controller Module
Memory Stick® Host Controller (MSHC)
Direct Memory Access Controller (DMAC)
2
Synchronous Serial Interface and an Inter-IC Sound (SSI/I S) Module
2
Inter-IC (I C) Bus Module
MC9328MXL Technical Data, Rev. 8
2
Freescale Semiconductor
Introduction
•
•
•
•
•
•
•
•
Video Port
General-Purpose I/O (GPIO) Ports
Bootstrap Mode
Multimedia Accelerator (MMA)
Power Management Features
Operating Voltage Range: 1.7 V to 1.9 V core, 1.7 V to 3.3 V I/O
256-pin MAPBGA Package
225-contact MAPBGA Package
1.2
Target Applications
The i.MXL processor is targeted for advanced information appliances, smart phones, Web browsers,
digital MP3 audio players, handheld computers, and messaging applications.
1.3
Ordering Information
Table 1 provides ordering information.
Table 1. i.MXL Ordering Information
Package Type
Frequency
Temperature
Solderball Type
Order Number
256-lead MAPBGA
200 MHz
0OC to 70OC
-30OC to 70OC
0OC to 70OC
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
MC9328MXLVM20(R2)
MC9328MXLDVM20(R2)
MC9328MXLVM15(R2)
MC9328MXLDVM15(R2)
MC9328MXLCVM15(R2)
MC9328MXLVP20(R2)
MC9328MXLDVP20(R2)
MC9328MXLVP15(R2)
MC9328MXLDVP15(R2)
MC9328MXLCVP15(R2)
150 MHz
-30OC to 70OC
-40OC to 85OC
0OC to 70OC
225-lead MAPBGA
200 MHz
150 MHz
-30OC to 70OC
0°C to 70°C
-30OC to 70OC
-40OC to 85OC
1.4
Conventions
This document uses the following conventions:
•
•
•
•
•
•
OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET.
Logic level one is a voltage that corresponds to Boolean true (1) state.
Logic level zero is a voltage that corresponds to Boolean false (0) state.
To set a bit or bits means to establish logic level one.
To clear a bit or bits means to establish logic level zero.
A signal is an electronic construct whose state conveys or changes in state convey information.
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
3
Signals and Connections
•
•
A pin is an external physical connection. The same pin can be used to connect a number of signals.
Asserted means that a discrete signal is in active logic state.
— Active low signals change from logic level one to logic level zero.
— Active high signals change from logic level zero to logic level one.
Negated means that an asserted discrete signal changes logic state.
— Active low signals change from logic level zero to logic level one.
— Active high signals change from logic level one to logic level zero.
•
•
•
LSB means least significant bit or bits, and MSB means most significant bit or bits. References to
low and high bytes or words are spelled out.
Numbers preceded by a percent sign (%) are binary. Numbers preceded by a dollar sign ($) or 0x
are hexadecimal.
2 Signals and Connections
Table 2 identifies and describes the i.MXL processor signals that are assigned to package pins. The signals
are grouped by the internal module that they are connected to.
Table 2. i.MXL Signal Descriptions
Signal Name
Function/Notes
External Bus/Chip-Select (EIM)
A[24:0]
Address bus signals
Data bus signals
D[31:0]
EB0
MSB Byte Strobe—Active low external enable byte signal that controls D [31:24].
Byte Strobe—Active low external enable byte signal that controls D [23:16].
Byte Strobe—Active low external enable byte signal that controls D [15:8].
LSB Byte Strobe—Active low external enable byte signal that controls D [7:0].
Memory Output Enable—Active low output enables external data bus.
EB1
EB2
EB3
OE
CS [5:0]
Chip-Select—The chip-select signals CS [3:2] are multiplexed with CSD [1:0] and are selected by the
Function Multiplexing Control Register (FMCR). By default CSD [1:0] is selected.
ECB
LBA
Active low input signal sent by a flash device to the EIM whenever the flash device must terminate an
on-going burst sequence and initiate a new (long first access) burst sequence.
Active low signal sent by a flash device causing the external burst device to latch the starting burst
address.
BCLK (burst clock)
RW
Clock signal sent to external synchronous memories (such as burst flash) during burst mode.
RW signal—Indicates whether external access is a read (high) or write (low) cycle. Used as a WE input
signal by external DRAM.
DTACK
DTACK signal—The external input data acknowledge signal. When using the external DTACK signal
as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not
terminated by the external DTACK signal after 1022 clock counts have elapsed.
MC9328MXL Technical Data, Rev. 8
4
Freescale Semiconductor
Signals and Connections
Table 2. i.MXL Signal Descriptions (Continued)
Signal Name
Function/Notes
Bootstrap
BOOT [3:0]
System Boot Mode Select—The operational system boot mode of the i.MXL processor upon system
reset is determined by the settings of these pins.
SDRAM Controller
SDBA [4:0]
SDIBA [3:0]
SDRAM non-interleave mode bank address multiplexed with address signals A [15:11]. These signals
are logically equivalent to core address p_addr [25:21] in SDRAM cycles.
SDRAM interleave addressing mode bank address multiplexed with address signals A [19:16]. These
signals are logically equivalent to core address p_addr [12:9] in SDRAM cycles.
MA [11:10]
MA [9:0]
SDRAM address signals
SDRAM address signals which are multiplexed with address signals A [10:1]. MA [9:0] are selected on
SDRAM cycles.
DQM [3:0]
CSD0
SDRAM data enable
SDRAM Chip-select signal which is multiplexed with the CS2 signal. These two signals are selectable
by programming the system control register.
CSD1
SDRAM Chip-select signal which is multiplexed with CS3 signal. These two signals are selectable by
programming the system control register. By default, CSD1 is selected, so it can be used as boot
chip-select by properly configuring BOOT [3:0] input pins.
RAS
SDRAM Row Address Select signal
SDRAM Column Address Select signal
SDRAM Write Enable signal
SDRAM Clock Enable 0
SDRAM Clock Enable 1
SDRAM Clock
CAS
SDWE
SDCKE0
SDCKE1
SDCLK
RESET_SF
Not Used
Clocks and Resets
EXTAL16M
Crystal input (4 MHz to 16 MHz), or a 16 MHz oscillator input when the internal oscillator circuit is shut
down.
XTAL16M
EXTAL32K
XTAL32K
CLKO
Crystal output
32 kHz crystal input
32 kHz crystal output
Clock Out signal selected from internal clock signals.
RESET_IN
Master Reset—External active low Schmitt trigger input signal. When this signal goes active, all
modules (except the reset module and the clock control module) are reset.
RESET_OUT
POR
Reset Out—Internal active low output signal from the Watchdog Timer module and is asserted from the
following sources: Power-on reset, External reset (RESET_IN), and Watchdog time-out.
Power On Reset—Internal active high Schmitt trigger input signal. The POR signal is normally
generated by an external RC circuit designed to detect a power-up event.
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
5
Signals and Connections
Signal Name
Table 2. i.MXL Signal Descriptions (Continued)
Function/Notes
JTAG
TRST
TDO
TDI
Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller.
Serial Output for test instructions and data. Changes on the falling edge of TCK.
Serial Input for test instructions and data. Sampled on the rising edge of TCK.
Test Clock to synchronize test logic and control register access through the JTAG port.
TCK
TMS
Test Mode Select to sequence the JTAG test controller’s state machine. Sampled on the rising edge of
TCK.
DMA
DMA_REQ
DMA Request—external DMA request signal. Multiplexed with SPI1_SPI_RDY.
BIG_ENDIAN
Big Endian—Input signal that determines the configuration of the external chip-select space. If it is
driven logic-high at reset, the external chip-select space will be configured to big endian. If it is driven
logic-low at reset, the external chip-select space will be configured to little endian. This input must not
change state after power-on reset negates or during chip operation.
ETM
ETMTRACESYNC
ETMTRACECLK
ETM sync signal which is multiplexed with A24. ETMTRACESYNC is selected in ETM mode.
ETM clock signal which is multiplexed with A23. ETMTRACECLK is selected in ETM mode.
ETMPIPESTAT [2:0] ETM status signals which are multiplexed with A [22:20]. ETMPIPESTAT [2:0] are selected in ETM
mode.
ETMTRACEPKT [7:0] ETM packet signals which are multiplexed with ECB, LBA, BCLK (burst clock), PA17, A [19:16].
ETMTRACEPKT [7:0] are selected in ETM mode.
CMOS Sensor Interface
CSI_D [7:0]
CSI_MCLK
CSI_VSYNC
CSI_HSYNC
CSI_PIXCLK
Sensor port data
Sensor port master clock
Sensor port vertical sync
Sensor port horizontal sync
Sensor port data latch clock
LCD Controller
LD [15:0]
LCD Data Bus—All LCD signals are driven low after reset and when LCD is off.
FLM/VSYNC
Frame Sync or Vsync—This signal also serves as the clock signal output for the gate
driver (dedicated signal SPS for Sharp panel HR-TFT).
LP/HSYNC
LSCLK
Line pulse or H sync
Shift clock
ACD/OE
CONTRAST
SPL_SPR
PS
Alternate crystal direction/output enable.
This signal is used to control the LCD bias voltage as contrast control.
Program horizontal scan direction (Sharp panel dedicated signal).
Control signal output for source driver (Sharp panel dedicated signal).
MC9328MXL Technical Data, Rev. 8
6
Freescale Semiconductor
Signals and Connections
Table 2. i.MXL Signal Descriptions (Continued)
Function/Notes
Signal Name
CLS
Start signal output for gate driver. This signal is an inverted version of PS (Sharp panel dedicated
signal).
REV
Signal for common electrode driving signal preparation (Sharp panel dedicated signal).
SPI 1 and SPI 2
SPI1_MOSI
SPI1_MISO
SPI1_SS
Master Out/Slave In
Slave In/Master Out
Slave Select (Selectable polarity)
Serial Clock
SPI1_SCLK
SPI1_SPI_RDY
SPI2_TXD
Serial Data Ready
SPI2 Master TxData Output—This signal is multiplexed with a GPI/O pin yet shows up as a primary or
alternative signal in the signal multiplex scheme table. Please refer to the SPI and GPIO chapters in
the MC9328MXL Reference Manual for information about how to bring this signal to the assigned pin.
SPI2_RXD
SPI2_SS
SPI2 Master RxData Input—This signal is multiplexed with a GPI/O pin yet shows up as a primary or
alternative signal in the signal multiplex scheme table. Please refer to the SPI and GPIO chapters in
the MC9328MXL Reference Manual for information about how to bring this signal to the assigned pin.
SPI2 Slave Select—This signal is multiplexed with a GPI/O pin yet shows up as a primary or alternative
signal in the signal multiplex scheme table. Please refer to the SPI and GPIO chapters in the
MC9328MXL Reference Manual for information about how to bring this signal to the assigned pin.
SPI2_SCLK
SPI2 Serial Clock—This signal is multiplexed with a GPI/O pin yet shows up as a primary or alternative
signal in the signal multiplex scheme table. Please refer to the SPI and GPIO chapters in the
MC9328MXL Reference Manual for information about how to bring this signal to the assigned pin.
General Purpose Timers
TIN
Timer Input Capture or Timer Input Clock—The signal on this input is applied to both timers
simultaneously.
TMR2OUT
Timer 2 Output
USB Device
USBD_VMO
USBD_VPO
USBD_VM
USB Minus Output
USB Plus Output
USB Minus Input
USB Plus Input
USBD_VP
USBD_SUSPND
USBD_RCV
USBD_ROE
USBD_AFE
USB Suspend Output
USB Receive Data
USB OE
USB Analog Front End Enable
Secure Digital Interface
SD_CMD
SD_CLK
SD Command—If the system designer does not wish to make use of the internal pull-up, via the Pull-up
enable register, a 4.7K–69K external pull up resistor must be added.
MMC Output Clock
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
7
Signals and Connections
Table 2. i.MXL Signal Descriptions (Continued)
Function/Notes
Signal Name
SD_DAT [3:0]
Data—If the system designer does not wish to make use of the internal pull-up, via the Pull-up enable
register, a 50K–69K external pull up resistor must be added.
Memory Stick Interface
MS_BS
Memory Stick Bus State (Output)—Serial bus control signal
Memory Stick Serial Data (Input/Output)
MS_SDIO
MS_SCLKO
MS_SCLKI
Memory Stick Serial Clock (Input)—Serial protocol clock source for SCLK Divider
Memory Stick External Clock (Output)—Test clock input pin for SCLK divider. This pin is only for test
purposes, not for use in application mode.
MS_PI0
MS_PI1
General purpose Input0—Can be used for Memory Stick Insertion/Extraction detect
General purpose Input1—Can be used for Memory Stick Insertion/Extraction detect
UARTs – IrDA/Auto-Bauding
UART1_RXD
UART1_TXD
UART1_RTS
UART1_CTS
UART2_RXD
UART2_TXD
UART2_RTS
UART2_CTS
UART2_DSR
UART2_RI
Receive Data
Transmit Data
Request to Send
Clear to Send
Receive Data
Transmit Data
Request to Send
Clear to Send
Data Set Ready
Ring Indicator
UART2_DCD
UART2_DTR
Data Carrier Detect
Data Terminal Ready
Serial Audio Port – SSI (configurable to I2S protocol)
SSI_TXDAT
SSI_RXDAT
SSI_TXCLK
SSI_RXCLK
SSI_TXFS
Transmit Data
Receive Data
Transmit Serial Clock
Receive Serial Clock
Transmit Frame Sync
Receive Frame Sync
SSI_RXFS
I2C
I2C_SCL
I2C_SDA
I2C Clock
I2C Data
MC9328MXL Technical Data, Rev. 8
8
Freescale Semiconductor
Signals and Connections
Table 2. i.MXL Signal Descriptions (Continued)
Signal Name
Function/Notes
PWM
PWMO
PWM Output
Test Function
TRISTATE
Forces all I/O signals to high impedance for test purposes. For normal operation, terminate this input
with a 1 k ohm resistor to ground. (TRI-STATE® is a registered trademark of National Semiconductor.)
Digital Supply Pins
NVDD
NVSS
Digital Supply for the I/O pins
Digital Ground for the I/O pins
Supply Pins – Analog Modules
Supply for analog blocks
AVDD
Internal Power Supply
QVDD
QVSS
Power supply pins for silicon internal circuitry
Ground pins for silicon internal circuitry
2.1
I/O Pads Power Supply and Signal Multiplexing Scheme
This section describes detailed information about both the power supply for each I/O pin and its function
multiplexing scheme. The user can reference information provided in Table 6 on page 18 to configure the
power supply scheme for each device in the system (memory and external peripherals). The function
multiplexing information also shown in Table 6 allows the user to select the function of each pin by
configuring the appropriate GPIO registers when those pins are multiplexed to provide different functions.
Table 3. MC9328MXLMC9328MXS Signal Multiplexing Scheme
Primary
Alternate
GPIO
225
BGA
Ball
256
BGA
Ball
I/O Supply
Voltage
AIN
BIN
AOUT
Default
Pull-
Up
Pull
-Up
Signal
Dir
Signal
Dir
Mux
NVDD1
D2
B1
A24
O
ETMTRAC
ESYNC
O
PA0
69K SPI2_
SCLK
A24
NVDD1
NVDD1
C1
D1
C2
C1
D31
A23
I/O
O
69K
69K
69K
69K
ETMTRAC
ECLK
O
O
O
PA31
PA30
PA29
69K
69K
69K
A23
A22
A21
NVDD1
NVDD1
E3
E2
D2
D1
D30
A22
I/O
O
ETMPIPE
STAT2
NVDD1
NVDD1
E4
E1
D3
E2
D29
A21
I/O
O
ETMPIPE
STAT1
NVDD1
F3
E3
D28
I/O
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
9
Signals and Connections
Table 3. MC9328MXLMC9328MXS Signal Multiplexing Scheme (Continued)
Primary
Alternate
GPIO
225
I/O Supply
BGA
256
BGA
Ball
AIN
BIN
AOUT
Default
Pull-
Up
Pull
Voltage
Signal
Dir
Signal
Dir
Mux
Ball
-Up
NVDD1
F1
E1
A20
O
ETMPIPE
STAT0
O
PA28
69K
A20
NVDD1
NVDD1
F4
F2
F2
F4
D27
A19
I/O
O
69K
69K
69K
69K
ETMTRAC
EPKT3
O
O
O
O
PA27
PA26
PA25
PA24
69K
69K
69K
69K
A19
A18
A17
A16
NVDD1
NVDD1
G3
G2
E4
F1
D26
A18
I/O
O
ETMTRAC
EPKT2
NVDD1
NVDD1
G4
G1
F3
D25
A17
I/O
O
G2
ETMTRAC
EPKT1
NVDD1
NVDD1
H4
H2
G3
F5
D24
A16
I/O
O
ETMTRAC
EPKT0
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
H3
H1
H5
J1
G4
G1
H2
H3
G5
H1
H4
J1
D23
A15
D22
A14
D21
A13
D20
A12
D19
A11
D18
A10
D17
A9
I/O
O
69K
69K
69K
69K
69K
69K
69K
69K
69K
69K
69K
69K
69K
I/O
O
J3
I/O
O
K1
J4
I/O
O
J2
K4
K2
L4
L1
L3
L2
M1
N1
M2
N2
P1
R1
M3
P2
N3
P3
R2
J4
I/O
O
J2
J3
I/O
O
K1
K4
K3
K2
L1
I/O
O
D16
A8
I/O
O
L4
D15
A7
I/O
O
L2
L5
D14
A6
I/O
O
M4
L3
D13
A5
I/O
O
M1
M2
N1
M3
D12
A4
I/O
O
D11
I/O
MC9328MXL Technical Data, Rev. 8
10
Freescale Semiconductor
Signals and Connections
Table 3. MC9328MXLMC9328MXS Signal Multiplexing Scheme (Continued)
Primary
Dir
Alternate
Signal Dir
GPIO
225
BGA
Ball
256
BGA
Ball
I/O Supply
Voltage
AIN
BIN
AOUT
Default
Pull-
Up
Pull
Signal
Mux
-Up
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
N4
M4
P4
R3
N5
R4
P5
M5
N6
R5
P6
L7
P3
N3
P1
N2
P2
R1
T2
R2
R5
T3
R3
T4
N4
R4
N5
P4
P5
T5
M5
T6
T7
R6
P6
EB0
D10
A3
O
I/O
O
69K
69K
EB1
D9
O
I/O
O
EB2
A2
O
EB3
D8
O
I/O
O
69K
69K
69K
OE
A1
O
CS5
D7
O
PA23
69K
PA23
R6
M7
R7
N7
P7
K3
R8
M8
N8
P8
L9
I/O
O
CS4
A0
PA22
PA21
69K
69K
PA22
A0
O
CS3
D6
O
CSD1
CSD0
CSD1
I/O
O
CS2
SDCLK
CS1
CS0
D5
CSD0
O
O
O
I/O
I
69K
69K
69K
69K
69K
ECB
ETMTRAC
EPKT7
PA20
PA19
PA18
PA17
69K
69K
69K
ECB
LBA
NVDD1
NVDD1
R9
N6
R7
D4
I/O
O
R10
LBA
ETMTRAC
EPKT6
NVDD1
NVDD1
R11
M9
P8
R8
D3
I/O
I/O
I/O
BCLK
ETMTRAC
EPKT5
BCLK
PA17
NVDD1
NVDD1
L8
P7
N7
D2
N9
PA17
ETMTRAC
EPKT4
69K SPI2_
SS
DTACK
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
K10
M10
P10
P9
N8
M7
T8
D1
RW
MA11
MA10
D0
O
O
M8
R9
P9
N10
R12
I/O
O
69K
DQM3
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
11
Signals and Connections
Table 3. MC9328MXLMC9328MXS Signal Multiplexing Scheme (Continued)
Primary
Dir
Alternate
Signal Dir
GPIO
225
I/O Supply
BGA
256
BGA
Ball
AIN
BIN
AOUT
Default
Pull-
Up
Pull
Voltage
Signal
Mux
Ball
-Up
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
N11
P11
N12
P12
R13
R14
N13
P13
P15
T9
N9
DQM2
DQM1
DQM0
RAS
O
O
O
O
O
O
R10
M9
L8
CAS
T10
R11
P10
N10
SDWE
SDCKE0
SDCKE1
O
O
O
RESET_S
F
NVDD1
AVDD1
QVDD2
AVDD1
AVDD1
P14
R15
M13
N15
N14
T11
T12
R15
P13
CLKO
O
AVDD1 Static
QVDD2 Static
TRST
I
I
69K
T13 TRISTATE
1
AVDD1
M15
T14
EXTAL16
M
I
AVDD1
AVDD1
L14
L15
T15
R16
XTAL16M
O
I
EXTAL32
K
AVDD1
AVDD1
K15
M14
P16
M10
XTAL32K
O
I
RESET_I
N2
69K
AVDD1
K14
N11
R12
RESET_O
UT
O
POR2
AVDD1
AVDD1
L12
K13
I
I
M11 BIG_ENDI
AN3
BOOT33
P11
AVDD1
AVDD1
AVDD1
AVDD1
NVDD2
M12
K11
J14
J15
J13
I
I
BOOT23
N12
BOOT13
R13
I
BOOT03
P12
I
TDO4
R14
O
NVDD2
NVDD2
NVDD2
NVDD2
NVDD2
H15
J12
K12
J11
H14
N15
L9
TMS
TCK
I
I
69K
69K
69K
N16
P14
P15
TDI
I
I2C_SCL
O
PA16
PA15
69K
69K
PA16
PA15
I2C_SDA I/O
MC9328MXL Technical Data, Rev. 8
12
Freescale Semiconductor
Signals and Connections
Table 3. MC9328MXLMC9328MXS Signal Multiplexing Scheme (Continued)
Primary
Dir
Alternate
Signal Dir
GPIO
225
BGA
Ball
256
BGA
Ball
I/O Supply
Voltage
AIN
BIN
AOUT
Default
Pull-
Up
Pull
Signal
Mux
-Up
NVDD2
NVDD2
NVDD2
H13
G14
H12
N13
M13
M14
CSI_PIXC
LK
I
I
I
PA14
69K
PA14
PA13
PA12
CSI_HSY
NC
PA13
PA12
69K
69K
CSI_VSY
NC
NVDD2
NVDD2
NVDD2
NVDD2
NVDD2
NVDD2
NVDD2
NVDD2
NVDD2
G13
J10
N14
M15
M16
M12
L16
L15
L14
L13
L12
CSI_D7
CSI_D6
CSI_D5
CSI_D4
CSI_D3
CSI_D2
CSI_D1
CSI_D0
I
I
PA11
PA10
PA9
PA8
PA7
PA6
PA5
PA4
PA3
69K
69K
69K
69K
69K
69K
69K
69K
69K
PA11
PA10
PA9
PA8
PA7
PA6
PA5
PA4
PA3
G15
F15
G12
F14
H11
E14
E15
I
I
I
I
I
I
CSI_MCL
K
O
NVDD2
NVDD2
G11
E13
L11
L10
PWMO
TIN
O
I
PA2
PA1
69K
69K
PA2
PA1
SPI2_
RXD_0
NVDD2
D14
K15 TMR2OUT
O
PD31
69K
SPI2_
TXD
PD31
NVDD2
NVDD2
NVDD2
NVDD2
NVDD2
NVDD2
NVDD2
NVDD2
NVDD2
NVDD2
NVDD2
NVDD2
NVDD2
NVDD2
NVDD2
NVDD2
NVDD2
F13
F12
D15
C14
D13
E12
C13
C12
B15
B14
A15
A14
B13
A13
D12
B12
C11
K16
K14
K13
K12
J14
LD15
LD14
LD13
LD12
LD11
LD10
LD9
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
PD30
PD29
PD28
PD27
PD26
PD25
PD24
PD23
PD22
PD21
PD20
PD19
PD18
PD17
PD16
PD15
PD14
69K
69K
69K
69K
69K
69K
69K
69K
69K
69K
69K
69K
69K
69K
69K
69K
69K
PD30
PD29
PD28
PD27
PD26
PD25
PD24
PD23
PD22
PD21
PD20
PD19
PD18
PD17
PD16
PD15
PD14
K11
H15
J13
LD8
J12
LD7
J11
LD6
H14
H13
H16
H12
G16
H11
G15
LD5
LD4
LD3
LD2
LD1
LD0
FLM/VSY
NC
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
13
Signals and Connections
Table 3. MC9328MXLMC9328MXS Signal Multiplexing Scheme (Continued)
Primary
Dir
Alternate
GPIO
225
I/O Supply
BGA
256
BGA
Ball
AIN
BIN
AOUT
Default
Pull-
Up
Pull
Voltage
Signal
Signal
Dir
Mux
Ball
-Up
NVDD2
D11
G14
LP/HSYN
C
O
PD13
69K
PD13
NVDD2
NVDD2
E11
C10
G13
G12
ACD/OE
O
O
PD12
PD11
69K
69K
PD12
PD11
CONTRA
ST
NVDD2
NVDD2
NVDD2
NVDD2
B11
A12
F10
A11
F16
H10
G11
F12
SPL_SPR
O
O
O
O
O
UART2_D
SR
O
O
O
I
PD10
PD9
PD8
PD7
69K SPI2_
TXD
PD10
PD9
PD8
PD7
PS
UART2_RI
69K
SPI2_
RXD_1
CLS
UART2_D
CD
69K SPI2_
SS
REV
UART2_D
TR
69K SPI2_
SCLK
NVDD2
NVDD3
B10
D10
F15
G9
LSCLK
PD6
69K
69K
PD6
SPI1_MO I/O
SI
PC17
PC17
NVDD3
E10
F9
SPI1_MIS I/O
O
PC16
69K
PC16
NVDD3
NVDD3
B9
E9
B9
SPI1_SS
I/O
PC15
PC14
69K
69K
PC15
PC14
A10
SPI1_SCL I/O
K
DMA_REQ
NVDD3
NVDD3
NVDD3
NVDD3
NVDD3
NVDD3
A9
E8
B8
C9
E9
A8
D9
A9
C9
A8
G8
B8
SPI1_SPI I/O
_RDY
PC13
PC12
PC11
PC10
PC9
69K
69K
69K
69K
69K
69K
PC13
PC12
PC11
PC10
PC9
UART1_R
XD
I
UART1_T
XD
O
I
UART1_R
TS
UART1_C
TS
O
SSI_TXCL I/O
K
PC8
PC8
NVDD3
NVDD3
C8
F9
F8
E8
SSI_TXFS I/O
PC7
PC6
69K
69K
PC7
PC6
SSI_TXDA
T
O
NVDD3
NVDD3
B7
F8
D8
B7
SSI_RXD
AT
I
PC5
PC4
69K
69K
PC5
PC4
SSI_RXCL
K
I
NVDD3
NVDD4
A7
C7
C8
C7
SSI_RXFS
I
I
PC3
69K
69K
PC3
UART2_R
XD
PB31
PB31
MC9328MXL Technical Data, Rev. 8
14
Freescale Semiconductor
Signals and Connections
Table 3. MC9328MXLMC9328MXS Signal Multiplexing Scheme (Continued)
Primary
Dir
Alternate
Signal Dir
GPIO
225
BGA
Ball
256
BGA
Ball
I/O Supply
Voltage
AIN
BIN
AOUT
Default
Pull-
Up
Pull
Signal
Mux
-Up
NVDD4
NVDD4
NVDD4
NVDD4
NVDD4
D8
E7
F7
B6
C6
F7
E7
C6
D7
D6
UART2_T
XD
O
I
PB30
69K
PB30
PB29
PB28
PB27
PB26
UART2_R
TS
PB29
PB28
PB27
PB26
69K
69K
69K
69K
UART2_C
TS
O
O
O
USBD_VM
O
USBD_VP
O
NVDD4
NVDD4
NVDD4
A6
D6
A5
E6
B6
D5
USBD_VM
USBD_VP
I
I
PB25
PB24
PB23
69K
69K
69K
PB25
PB24
PB23
USBD_SU
SPND
O
NVDD4
NVDD4
NVDD4
B5
A4
B4
C5
B5
A5
USBD_RC I/O
V
PB22
PB21
PB20
69K
69K
69K
PB22
PB21
PB20
USBD_RO
E
O
USBD_AF
E
O
NVDD4
NVDD4
NVDD4
NVDD4
NVDD4
NVDD4
NVDD4
NVDD4
A3
C4
D4
B3
A2
C3
A1
B2
G7
F6
G6
B4
C4
D4
B3
A3
PB19
PB18
PB17
PB16
PB15
PB14
I/O
69K
69K
69K
69K
69K
69K
69K
69K
PB19
PB18
PB17
PB16
PB15
PB14
PB13
PB12
I/O
O
I
I
I
SD_CMD I/O
SD_CLK
MS_BS
PB13
PB12
O
MS_SCLK
O
NVDD4
NVDD4
B1
C5
A2
E5
SD_DAT3 I/O
SD_DAT2 I/O
MS_SDIO
PB11
PB10
69K
(pull
down)
PB11
PB10
MS_SCLK
I
69K
NVDD4
NVDD4
NVDD1
D3
C2
D5
G6
E5
H6
J8
B2
C3
K8
A1
H5
T1
H9
H8
SD_DAT1 I/O
SD_DAT0 I/O
NVDD1 Static
MS_PI1
MS_PI0
PB9
PB8
69K
69K
PB9
PB8
NVSS
NVDD1 Static
NVSS Static
QVDD1 Static
QVSS Static
Static
NVDD1
QVDD1
E6
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
15
Signals and Connections
Table 3. MC9328MXLMC9328MXS Signal Multiplexing Scheme (Continued)
Primary
Dir
Alternate
Signal Dir
GPIO
225
I/O Supply
BGA
256
BGA
Ball
AIN
BIN
AOUT
Default
Pull-
Up
Pull
-Up
Voltage
Signal
Mux
Ball
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
NVDD1
F5
J6
J5
K6
NVDD
NVSS
Static
Static
G5
K6
K5
NVDD1 Static
NVSS Static
NVDD1 Static
NVSS Static
NVDD1 Static
NVSS Static
NVDD1 Static
NVSS Static
NVDD1 Static
M6
H6
J7
J5
H7
K5
L6
J7
J7
L5
L6
G8
L5
K7
J8
H8
K7
L7
NVSS
QVSS
Static
Static
T16
K10
J10
J15
J16
K9
NVDD2
QVDD3
NVDD2
QVDD4
NVDD3
H10
G9
F11
G10
C15
H9
D7
L13
D9
J9
NVDD2 Static
NVSS Static
QVDD3 Static
QVSS Static
NVDD2 Static
NVSS Static
QVDD4 Static
QVSS Static
NVDD3 Static
J9
A13
B13
A10
A7
NVSS
NVSS
Static
Static
K9
A4
NVDD4
NVDD1
NVDD1
NVDD1
NVDD1
G7
F6
A6
NVDD4 Static
NVDD1 Static
NVDD1 Static
NVDD1 Static
NVDD1 Static
L6
M6
K8
L10
L11
M11
NVSS
NVSS
NVSS
Static
Static
Static
1
2
3
4
Pull down this input with 1KΩ resistor to GND.
External circuit required to drive this input.
Tie this input high (to AVDD) or pull down with 1KΩ resistor to GND.
Pull up this output with a resistor to NVDD2.
MC9328MXL Technical Data, Rev. 8
16
Freescale Semiconductor
Electrical Characteristics
3 Electrical Characteristics
This section contains the electrical specifications and timing diagrams for the i.MXL processor.
3.1
Maximum Ratings
Table 4 provides information on maximum ratings which are those values beyond which damage to the
device may occur. Functional operation should be restricted to the limits listed in Recommended Operating
Range Table 5 on page 18 or the DC Characteristics table.
Table 4. Maximum Ratings
Symbol
NVDD
Rating
Minimum
-0.3
Maximum
3.3
Unit
V
DC I/O Supply Voltage
QVDD
DC Internal (core = 150 MHz) Supply Voltage
DC Internal (core = 200 MHz) Supply Voltage
DC Analog Supply Voltage
-0.3
1.9
V
QVDD
-0.3
2.0
V
AVDD
-0.3
3.3
V
BTRFVDD
DC Bluetooth Supply Voltage
-0.3
3.3
V
VESD_HBM
VESD_MM
ILatchup
Test
ESD immunity with HBM (human body model)
ESD immunity with MM (machine model)
Latch-up immunity
–
–
2000
100
200
150
V
V
–
mA
°C
Storage temperature
-55
8001
13002
Pmax
Power Consumption
mW
A typical application with 30 pads simultaneously switching assumes the GPIO toggling and instruction fetches from the ARM®
core-that is, 7x GPIO, 15x Data bus, and 8x Address bus.
1
2
A worst-case application with 70 pads simultaneously switching assumes the GPIO toggling and instruction fetches from the
ARM core-that is, 32x GPIO, 30x Data bus, 8x Address bus. These calculations are based on the core running its heaviest OS
application at 200MHz, and where the whole image is running out of SDRAM. QVDD at 2.0V, NVDD and AVDD at 3.3V,
therefore, 180mA is the worst measurement recorded in the factory environment, max 5mA is consumed for OSC pads, with
each toggle GPIO consuming 4mA.
3.2
Recommended Operating Range
Table 5 provides the recommended operating ranges for the supply voltages and temperatures. The i.MXL
processor has multiple pairs of VDD and VSS power supply and return pins. QVDD and QVSS pins are
used for internal logic. All other VDD and VSS pins are for the I/O pads voltage supply, and each pair of
VDD and VSS provides power to the enclosed I/O pads. This design allows different peripheral supply
voltage levels in a system.
Because AVDD pins are supply voltages to the analog pads, it is recommended to isolate and noise-filter
the AVDD pins from other VDD pins.
For more information about I/O pads grouping per VDD, please refer to Table 2 on page 4.
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
17
Electrical Characteristics
Symbol
Table 5. Recommended Operating Range
Rating
Minimum Maximum
Unit
TA
Operating temperature range
MC9328MXLVM20/MC9328MXLVM15
0
70
°C
MC9328MXLVP20/MC9328MXLVP15
TA
Operating temperature range
MC9328MXLDVM20/MC9328MXLDVM15
MC9328MXLDVP20/MC9328MXLDVP15
-30
-40
2.70
70
°C
°C
V
TA
Operating temperature range
MC9328MXLCVM15/
MC9328MXLCVP15
85
NVDD
I/O supply voltage (if using MSHC, CSI, SPI, LCD, and USBd which are
only 3 V interfaces)
3.30
NVDD
QVDD
QVDD
AVDD
I/O supply voltage (if not using the peripherals listed above)
Internal supply voltage (Core = 150 MHz)
Internal supply voltage (Core = 200 MHz)
Analog supply voltage
1.70
1.70
1.80
1.70
3.30
1.90
2.00
3.30
V
V
V
V
3.3
Power Sequence Requirements
For required power-up and power-down sequencing, please refer to the “Power-Up Sequence” section of
application note AN2537 on the i.MX applications processor website.
3.4
DC Electrical Characteristics
Table 6 contains both maximum and minimum DC characteristics of the i.MXL processor.
Table 6. Maximum and Minimum DC Characteristics
Number or
Symbol
Parameter
Min
Typical
Max
Unit
Iop
Full running operating current at 1.8V for QVDD, 3.3V for
NVDD/AVDD (Core = 96 MHz, System = 96 MHz, MPEG4
decoding playback from external memory card to both
external SSI audio decoder and driving TFT display panel,
and OS with MMU enabled memory system is running on
external SDRAM).
–
QVDD at
–
mA
1.8V = 120mA;
NVDD+AVDD at
3.0V = 30mA
Sidd1
Sidd2
Sidd3
Sidd4
Standby current
(Core = 150 MHz, QVDD = 1.8V, temp = 25°C)
–
–
–
–
25
45
35
60
–
–
–
–
μA
μA
μA
μA
Standby current
(Core = 150 MHz, QVDD = 1.8V, temp = 55°C)
Standby current
(Core = 150 MHz, QVDD = 2.0V, temp = 25°C)
Standby current
(Core = 150 MHz, QVDD = 2.0V, temp = 55°C)
MC9328MXL Technical Data, Rev. 8
18
Freescale Semiconductor
Electrical Characteristics
Table 6. Maximum and Minimum DC Characteristics (Continued)
Number or
Symbol
Parameter
Min
0.7V
Typical
Max
Unit
V
Input high voltage
Input low voltage
–
–
–
–
–
Vdd+0.2
0.4
V
V
IH
DD
V
–
0.7V
–
IL
V
Output high voltage (I
= 2.0 mA)
Vdd
0.4
V
OH
OH
DD
V
Output low voltage (I = -2.5 mA)
OL
V
OL
IL
I
Input low leakage current
(V = GND, no pull-up or pull-down)
–
1
μA
IN
I
Input high leakage current
–
–
–
–
–
1
–
μA
mA
mA
μA
IH
(V = V , no pull-up or pull-down)
IN
DD
I
Output high current
(V = 0.8VDD, VDD = 1.8V)
4.0
-4.0
–
OH
OH
I
Output low current
–
OL
OZ
(V = 0.4V, VDD = 1.8V)
OL
I
Output leakage current
5
(V = V , output is high impedance)
out
DD
C
Input capacitance
Output capacitance
–
–
–
–
5
5
pF
pF
i
C
o
3.5
AC Electrical Characteristics
The AC characteristics consist of output delays, input setup and hold times, and signal skew times. All
signals are specified relative to an appropriate edge of other signals. All timing specifications are specified
at a system operating frequency from 0 MHz to 96 MHz (core operating frequency 150 MHz) with an
operating supply voltage from V
timing is measured at 30 pF loading.
to V
under an operating temperature from T to T . All
L H
DD max
DD min
Table 7. Tristate Signal Timing
Pin
Parameter
Minimum
Maximum
Unit
TRISTATE Time from TRISTATE activate until I/O becomes Hi-Z
Table 8. 32k/16M Oscillator Signal Timing
–
20.8
ns
Parameter
Minimum
RMS
Maximum
Unit
EXTAL32k input jitter (peak to peak)
EXTAL32k startup time
–
800
–
5
–
20
–
ns
ms
–
EXTAL16M input jitter (peak to peak) 1
EXTAL16M startup time 1
TBD
–
TBD
–
TBD
–
1
The 16 MHz oscillator is not recommended for use in new designs.
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
19
Functional Description and Application Information
4 Functional Description and Application Information
This section provides the electrical information including and timing diagrams for the individual modules
of the i.MXL.
4.1
Embedded Trace Macrocell
All registers in the ETM9 are programmed through a JTAG interface. The interface is an extension of the
ARM920T processor’s TAP controller, and is assigned scan chain 6. The scan chain consists of a 40-bit
shift register comprised of the following:
•
•
•
32-bit data field
7-bit address field
A read/write bit
The data to be written is scanned into the 32-bit data field, the address of the register into the 7-bit address
field, and a 1 into the read/write bit.
A register is read by scanning its address into the address field and a 0 into the read/write bit. The 32-bit
data field is ignored. A read or a write takes place when the TAP controller enters the UPDATE-DR state.
The timing diagram for the ETM9 is shown in Figure 2. See Table 9 for the ETM9 timing parameters used
in Figure 2.
2a
1
2b
3a
TRACECLK
3b
TRACECLK
(Half-Rate Clocking Mode)
Output Trace Port
Valid Data
Valid Data
4a
Figure 2. Trace Port Timing Diagram
4b
Table 9. Trace Port Timing Diagram Parameter Table
1.8 0.1 V 3.0 0.3 V
Ref No.
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
1
CLK frequency
0
1.3
3
85
–
0
2
2
–
–
100
–
MHz
ns
2a
2b
3a
3b
Clock high time
Clock low time
Clock rise time
Clock fall time
–
–
ns
–
4
3
ns
–
3
3
ns
MC9328MXL Technical Data, Rev. 8
20
Freescale Semiconductor
Functional Description and Application Information
Table 9. Trace Port Timing Diagram Parameter Table (Continued)
1.8 0.1 V 3.0 0.3 V
Ref No.
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
4a
4b
Output hold time
Output setup time
2.28
3.42
–
–
2
3
–
–
ns
ns
4.2
DPLL Timing Specifications
Parameters of the DPLL are given in Table 10. In this table, T is a reference clock period after the
ref
Table 10. DPLL Specifications
Test Conditions
pre-divider and T is the output double clock period.
dck
Parameter
Minimum Typical Maximum
Unit
DPLL input clock freq range
Vcc = 1.8V
Vcc = 1.8V
5
5
–
–
100
30
MHz
Pre-divider output clock
freq range
MHz
DPLL output clock freq range
Pre-divider factor (PD)
Vcc = 1.8V
–
80
1
–
–
–
–
–
–
–
220
16
MHz
–
–
Total multiplication factor (MF) Includes both integer and fractional parts
5
15
MF integer part
–
5
15
–
MF numerator
Should be less than the denominator
0
1022
1023
312.5
–
MF denominator
Pre-multiplier lock-in time
–
–
1
–
–
μsec
Freq lock-in time after
full reset
FOL mode for non-integer MF
(does not include pre-multi lock-in time)
280
(56 μs)
Tref
Tref
250
220
300
270
–
300
270
400
370
0.01
Freq lock-in time after
partial reset
FOL mode for non-integer MF (does not
include pre-multi lock-in time)
250
(50 μs)
Phase lock-in time after
full reset
FPL mode and integer MF (does not include
pre-multi lock-in time)
350
(70 μs)
Tref
Phase lock-in time after
partial reset
FPL mode and integer MF (does not include
pre-multi lock-in time)
320
(64 μs)
Tref
Freq jitter (p-p)
–
0.005
(0.01%)
2•Tdck
Phase jitter (p-p)
Integer MF, FPL mode, Vcc=1.8V
–
1.0
(10%)
–
1.7
–
1.5
2.5
4
ns
V
Power supply voltage
Power dissipation
–
–
FOL mode, integer MF,
fdck = 200 MHz, Vcc = 1.8V
mW
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
21
Functional Description and Application Information
4.3
Reset Module
The timing relationships of the Reset module with the POR and RESET_IN are shown in Figure 3 and
Figure 4.
NOTE
Be aware that NVDD must ramp up to at least 1.8V before QVDD is powered up
to prevent forward biasing.
90% AVDD
1
10% AVDD
POR
2
RESET_POR
Exact 300ms
3
7 cycles @ CLK32
RESET_DRAM
4
14 cycles @ CLK32
HRESET
RESET_OUT
CLK32
HCLK
Figure 3. Timing Relationship with POR
5
RESET_IN
14 cycles @ CLK32
HRESET
4
RESET_OUT
6
CLK32
HCLK
Figure 4. Timing Relationship with RESET_IN
MC9328MXL Technical Data, Rev. 8
22
Freescale Semiconductor
Functional Description and Application Information
Table 11. Reset Module Timing Parameter Table
1.8 0.1 V
3.0 0.3 V
Min Max
Ref
No.
Parameter
Unit
Min
Max
note1
300
note1
300
1
2
Width of input POWER_ON_RESET
–
–
–
Width of internal POWER_ON_RESET
(CLK32 at 32 kHz)
300
300
ms
3
4
5
6
7K to 32K-cycle stretcher for SDRAM reset
7
14
4
7
14
–
7
14
4
7
14
–
Cycles of
CLK32
14K to 32K-cycle stretcher for internal system reset
HRESERT and output reset at pin RESET_OUT
Cycles of
CLK32
Width of external hard-reset RESET_IN
Cycles of
CLK32
4K to 32K-cycle qualifier
4
4
4
4
Cycles of
CLK32
1
POR width is dependent on the 32 or 32.768 kHz crystal oscillator start-up time. Design margin should allow for crystal
tolerance, i.MX chip variations, temperature impact, and supply voltage influence. Through the process of supplying crystals
for use with CMOS oscillators, crystal manufacturers have developed a working knowledge of start-up time of their crystals.
Typically, start-up times range from 400 ms to 1.2 seconds for this type of crystal.
If an external stable clock source (already running) is used instead of a crystal, the width of POR should be ignored in
calculating timing for the start-up process.
4.4
External Interface Module
The External Interface Module (EIM) handles the interface to devices external to the i.MXL processor,
including the generation of chip-selects for external peripherals and memory. The timing diagram for the
EIM is shown in Figure 5, and Table 12 defines the parameters of signals.
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
23
Functional Description and Application Information
(HCLK) Bus Clock
1a
1b
2b
3b
Address
2a
Chip-select
3a
Read (Write)
4a
5a
4b
5b
OE (rising edge)
OE (falling edge)
EB (rising edge)
EB (falling edge)
4c
5c
4d
5d
6b
6a
LBA (negated falling edge)
6a
6c
LBA (negated rising edge)
7a
7b
BCLK (burst clock) - rising edge
7c
7d
BCLK (burst clock) - falling edge
Read Data
8b
9a
9a
8a
9b
Write Data (negated falling)
9c
Write Data (negated rising)
DTACK_B
10a
10a
Figure 5. EIM Bus Timing Diagram
Table 12. EIM Bus Timing Parameter Table
1.8 0.1 V
3.0 0.3 V
Ref No.
Parameter
Unit
Min
Typical Max
Min
Typical Max
1a
1b
2a
2b
3a
3b
Clock fall to address valid
2.48
1.55
2.69
1.55
1.35
1.86
3.31
2.48
3.31
2.48
2.79
2.59
9.11
5.69
7.87
6.31
6.52
6.11
2.4
1.5
2.6
1.5
1.3
1.8
3.2
2.4
3.2
2.4
2.7
2.5
8.8
5.5
7.6
6.1
6.3
5.9
ns
ns
ns
ns
ns
ns
Clock fall to address invalid
Clock fall to chip-select valid
Clock fall to chip-select invalid
Clock fall to Read (Write) Valid
Clock fall to Read (Write) Invalid
MC9328MXL Technical Data, Rev. 8
24
Freescale Semiconductor
Functional Description and Application Information
Table 12. EIM Bus Timing Parameter Table (Continued)
1.8 0.1 V
3.0 0.3 V
Ref No.
Parameter
Unit
Min
Typical Max
Min
Typical Max
4a
4b
4c
4d
5a
5b
5c
5d
6a
6b
6c
7a
7b
7c
7d
8a
8b
9a
9b
9c
10a
Clock1 rise to Output Enable Valid
Clock1 rise to Output Enable Invalid
Clock1 fall to Output Enable Valid
Clock1 fall to Output Enable Invalid
Clock1 rise to Enable Bytes Valid
Clock1 rise to Enable Bytes Invalid
Clock1 fall to Enable Bytes Valid
Clock1 fall to Enable Bytes Invalid
Clock1 fall to Load Burst Address Valid
Clock1 fall to Load Burst Address Invalid
Clock1 rise to Load Burst Address Invalid
Clock1 rise to Burst Clock rise
Clock1rise to Burst Clock fall
2.32
2.11
2.38
2.17
1.91
1.81
1.97
1.76
2.07
1.97
1.91
1.61
1.61
1.55
1.55
5.54
0
2.62
2.52
2.69
2.59
2.52
2.42
2.59
2.48
2.79
2.79
2.62
2.62
2.62
2.48
2.59
–
6.85
6.55
7.04
6.73
5.54
5.24
5.69
5.38
6.73
6.83
6.45
5.64
5.84
5.59
5.80
–
2.3
2.1
2.3
2.1
1.9
1.8
1.9
1.7
2.0
1.9
1.9
1.6
1.6
1.5
1.5
5.5
0
2.6
2.5
2.6
2.5
2.5
2.4
2.5
2.4
2.7
2.7
2.6
2.6
2.6
2.4
2.5
–
6.8
6.5
6.8
6.5
5.5
5.2
5.5
5.2
6.5
6.6
6.4
5.6
5.8
5.4
5.6
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock1 fall to Burst Clock rise
Clock1 fall to Burst Clock fall
Read Data setup time
Read Data hold time
–
–
–
–
Clock1 rise to Write Data Valid
Clock1 fall to Write Data Invalid
Clock1 rise to Write Data Invalid
DTACK setup time
1.81
1.45
1.63
2.52
2.72
2.48
–
6.85
5.69
–
1.8
1.4
1.62
2.5
2.7
2.4
–
6.8
5.5
–
–
–
–
–
1
Clock refers to the system clock signal, HCLK, generated from the System DPLL
4.4.1
DTACK Signal Description
The DTACK signal is the external input data acknowledge signal. When using the external DTACK signal
as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not
terminated by the external DTACK signal after 1022 HCLK counts have elapsed. Only the CS5 group
supports DTACK signal function when the external DTACK signal is used for data acknowledgement.
4.4.2
DTACK Signal Timing
Figure 6 through Figure 9 show the access cycle timing used by chip-select 5. The signal values and units
of measure for this figure are found in the associated tables.
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
25
Functional Description and Application Information
4.4.2.1
WAIT Read Cycle without DMA
3
Address
2
CS5
EB
8
1
9
programmable
min 0ns
5
OE
4
WAIT
7
6
DATABUS
10
11
XL
Figure 6. WAIT Read Cycle without DMA
Table 13. WAIT Read Cycle without DMA: WSC = 111111, DTACK_SEL=1, HCLK=96MHz
3.0 0.3 V
Number
Characteristic
Unit
Minimum
Maximum
1
OE and EB assertion time
CS5 pulse width
See note 2
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
3T
56.81
–
3
OE negated to address inactive
Wait asserted after OE asserted
Wait asserted to OE negated
Data hold timing after OE negated
Data ready after wait asserted
OE negated to CS negated
OE negated after EB negated
Become low after CS5 asserted
Wait pulse width
57.28
1020T
3T+7.33
–
4
5
2T+1.57
T-1.49
0
6
7
T
8
9
1.5T-0.68
0.06
0
1.5T-0.06
0.18
10
1019T
1020T
11
1T
Note:
1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
2. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only when
EBC bit in CS5L register is clear.
3. Address becomes valid and CS asserts at the start of read access cycle.
4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.
MC9328MXL Technical Data, Rev. 8
26
Freescale Semiconductor
Functional Description and Application Information
4.4.2.2
WAIT Read Cycle DMA Enabled
4
Address
2
9
CS5
1
10
programmable
min 0ns
EB
3
6
OE
(logic high)
RW
5
WAIT
7
11
8
DATABUS
12
L
Figure 7. DTACK WAIT Read Cycle DMA Enabled
Table 14. DTACK WAIT Read Cycle DMA Enabled: WSC = 111111, DTACK_SEL=1, HCLK=96MHz
3.0 0.3 V
Number
Characteristic
Unit
Minimum
Maximum
1
2
OE and EB assertion time
See note 2
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CS pulse width
3T
3
OE negated before CS5 is negated
Address inactived before CS negated
Wait asserted after CS5 asserted
Wait asserted to OE negated
Data hold timing after OE negated
Data ready after wait is asserted
CS deactive to next CS active
OE negate after EB negate
1.5T-0.68
1.5T-0.06
0.05
1020T
3T+7.33
–
4
–
5
–
6
2T+1.57
7
T-1.49
8
–
T
T
9
–
10
11
0.06
0
0.18
1019T
Wait becomes low after CS5 asserted
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
27
Functional Description and Application Information
Table 14. DTACK WAIT Read Cycle DMA Enabled: WSC = 111111, DTACK_SEL=1, HCLK=96MHz (Continued)
3.0 0.3 V
Number
Characteristic
Unit
Minimum
Maximum
12
Wait pulse width
1T
1020T
ns
Note:
1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
2. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only when
EBC bit in CS5L register is clear.
3. Address becomes valid and CS asserts at the start of read access cycle.
4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.
4.4.2.3
WAIT Write Cycle without DMA
5
Address
3
1
programmable
min 0ns
CS5
2
10
programmable
min 0ns
EB
4
7
RW
(logic high)
WAIT
OE
6
11
8
9
12
DATABUS
from i.MXL
Figure 8. WAIT Write Cycle without DMA
Table 15. WAIT Write Cycle without DMA: WSC = 111111, DTACK_SEL=1, HCLK=96MHz
3.0 0.3 V
Number
Characteristic
Unit
Minimum
Maximum
1
2
3
4
5
6
CS5 assertion time
See note 2
See note 2
3T
–
ns
ns
ns
ns
ns
ns
EB assertion time
–
CS5 pulse width
–
2.5T-1.16
–
RW negated before CS5 is negated
RW negated to Address inactive
Wait asserted after CS5 asserted
2.5T-3.63
64.22
–
1020T
MC9328MXL Technical Data, Rev. 8
28
Freescale Semiconductor
Functional Description and Application Information
Table 15. WAIT Write Cycle without DMA: WSC = 111111, DTACK_SEL=1, HCLK=96MHz (Continued)
3.0 0.3 V
Number
Characteristic
Unit
Minimum
Maximum
7
8
Wait asserted to RW negated
Data hold timing after RW negated
Data ready after CS5 is asserted
EB negated after CS5 is negated
Wait becomes low after CS5 asserted
Wait pulse width
T+2.66
2T+7.96
–
ns
ns
ns
ns
ns
ns
2T+0.03
9
–
0.5T
0
T
10
11
12
0.5T+0.5
1019T
1020T
1T
Note:
1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
2. CS5 assertion can be controlled by CSA bits. EB assertion can also be programmable by WEA bits in CS5L register.
3. Address becomes valid and RW asserts at the start of write access cycle.
4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.
4.4.2.4
WAIT Write Cycle DMA Enabled
5
Address
1
3
10
programmable
min 0ns
CS5
2
11
programmable
min 0ns
EB
4
7
RW
OE (logic high)
WAIT
6
12
9
8
13
DATABUS
Figure 9. WAIT Write Cycle DMA Enabled
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
29
Functional Description and Application Information
Table 16. WAIT Write Cycle DMA Enabled: WSC = 111111, DTACK_SEL=1, HCLK=96MHz
3.0 0.3 V
Number
Characteristic
Unit
Minimum
Maximum
1
2
CS5 assertion time
See note 2
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
EB assertion time
See note 2
3
CS5 pulse width
3T
–
4
RW negated before CS5 is negated
Address inactived after CS negated
Wait asserted after CS5 asserted
Wait asserted to RW negated
Data hold timing after RW negated
Data ready after CS5 is asserted
CS deactive to next CS active
EB negate after CS negate
Wait becomes low after CS5 asserted
Wait pulse width
2.5T-3.63
2.5T-1.16
0.09
1020T
2T+7.96
–
5
–
6
–
7
T+2.66
8
2T+0.03
9
–
T
T
10
11
12
13
–
0.5T
0
0.5T+0.5
1019T
1020T
ns
ns
1T
Note:
1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
2. CS5 assertion can be controlled by CSA bits. EB assertion also can be programmable by WEA bits in CS5L register.
3. Address becomes valid and RW asserts at the start of write access cycle.
4.The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.
4.4.3
EIM External Bus Timing
The External Interface Module (EIM) is the interface to devices external to the i.MXL, including
generation of chip-selects for external peripherals and memory. The timing diagram for the EIM is shown
in Figure 5, and Table 12 defines the parameters of signals.
MC9328MXL Technical Data, Rev. 8
30
Freescale Semiconductor
Functional Description and Application Information
hclk
hsel_weim_cs[0]
htrans
Seq/Nonseq
Read
hwrite
haddr
hready
V1
weim_hrdata
weim_hready
Last Valid Data
V1
BCLK (burst clock)
ADDR
Last Valid Address
V1
CS2
R/W
Read
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
DATA
V1
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 10. WSC = 1, A.HALF/E.HALF
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
31
Functional Description and Application Information
hclk
hsel_weim_cs[0]
htrans
hwrite
haddr
Nonseq
Write
V1
hready
hwdata
Last Valid Data
Write Data (V1)
Unknown
weim_hrdata
Last Valid Data
weim_hready
BCLK (burst clock)
ADDR
Last Valid Address
V1
CS0
R/W
Write
LBA
OE
EB
DATA
Last Valid Data
Write Data (V1)
Figure 11. WSC = 1, WEA = 1, WEN = 1, A.HALF/E.HALF
MC9328MXL Technical Data, Rev. 8
32
Freescale Semiconductor
Functional Description and Application Information
hclk
hsel_weim_cs[0]
htrans
Nonseq
Read
V1
hwrite
haddr
hready
weim_hrdata
Last Valid Data
V1 Word
weim_hready
BCLK (burst clock)
ADDR
Last Valid Addr
Address V1
Address V1 + 2
CS0
Read
R/W
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
1/2 Half Word
2/2 Half Word
DATA
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 12. WSC = 1, OEA = 1, A.WORD/E.HALF
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
33
Functional Description and Application Information
hclk
hsel_weim_cs[0]
Nonseq
Write
V1
htrans
hwrite
haddr
hready
hwdata
Last Valid Data
Write Data (V1 Word)
Last Valid Data
weim_hrdata
weim_hready
BCLK (burst clock)
ADDR
Last Valid Addr
Address V1
Address V1 + 2
CS0
R/W
LBA
Write
OE
EB
DATA
1/2 Half Word
2/2 Half Word
Figure 13. WSC = 1, WEA = 1, WEN = 2, A.WORD/E.HALF
MC9328MXL Technical Data, Rev. 8
34
Freescale Semiconductor
Functional Description and Application Information
hclk
hsel_weim_cs[3]
htrans
Nonseq
hwrite
Read
V1
haddr
hready
weim_hrdata
Last Valid Data
V1 Word
weim_hready
BCLK (burst clock)
ADDR
Last Valid Addr
Address V1
Address V1 + 2
CS[3]
R/W
LBA
Read
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
DATA
Note 1: x = 0, 1, 2 or 3
1/2 Half Word
2/2 Half Word
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 14. WSC = 3, OEA = 2, A.WORD/E.HALF
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
35
Functional Description and Application Information
hclk
hsel_weim_cs[3]
htrans
hwrite
haddr
Nonseq
Write
V1
hready
hwdata Last Valid
Data
Write Data (V1 Word)
Last Valid Data
weim_hrdata
weim_hready
BCLK (burst clock)
ADDR
Last Valid Addr
Address V1
Address V1 + 2
CS3
R/W
LBA
OE
Write
EB
DATA
Last Valid Data
1/2 Half Word
2/2 Half Word
Figure 15. WSC = 3, WEA = 1, WEN = 3, A.WORD/E.HALF
MC9328MXL Technical Data, Rev. 8
36
Freescale Semiconductor
Functional Description and Application Information
hclk
hsel_weim_cs[2]
htrans
Nonseq
Read
V1
hwrite
haddr
hready
weim_hrdata
Last Valid Data
V1 Word
weim_hready
BCLK (burst clock)
ADDR
Last Valid Addr
Address V1
Address V1 + 2
CS2
R/W
Read
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
weim_data_in
1/2 Half Word
2/2 Half Word
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 16. WSC = 3, OEA = 4, A.WORD/E.HALF
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
37
Functional Description and Application Information
hclk
hsel_weim_cs[2]
htrans
Nonseq
Write
V1
hwrite
haddr
hready
hwdata
Last Valid
Data
Write Data (V1 Word)
Last Valid Data
weim_hrdata
weim_hready
BCLK (burst clock)
ADDR Last Valid Addr
Address V1
Address V1 + 2
CS2
R/W
Write
LBA
OE
EB
DATA
Last Valid Data
1/2 Half Word
2/2 Half Word
Figure 17. WSC = 3, WEA = 2, WEN = 3, A.WORD/E.HALF
MC9328MXL Technical Data, Rev. 8
38
Freescale Semiconductor
Functional Description and Application Information
hclk
hsel_weim_cs[2]
htrans
Nonseq
Read
V1
hwrite
haddr
hready
weim_hrdata
Last Valid Data
V1 Word
weim_hready
BCLK (burst clock)
ADDR
Last Valid Addr
Address V1
Address V1 + 2
CS2
R/W
LBA
Read
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
DATA
Note 1: x = 0, 1, 2 or 3
1/2 Half Word
2/2 Half Word
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 18. WSC = 3, OEN = 2, A.WORD/E.HALF
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
39
Functional Description and Application Information
hclk
hsel_weim_cs[2]
htrans
Nonseq
Read
V1
hwrite
haddr
hready
weim_hrdata
Last Valid Data
V1 Word
weim_hready
BCLK (burst clock)
ADDR
Last Valid Addr
Address V1
Address V1 + 2
CS2
R/W
LBA
Read
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
DATA
Note 1: x = 0, 1, 2 or 3
1/2 Half Word
2/2 Half Word
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 19. WSC = 3, OEA = 2, OEN = 2, A.WORD/E.HALF
MC9328MXL Technical Data, Rev. 8
40
Freescale Semiconductor
Functional Description and Application Information
hclk
hsel_weim_cs[2]
htrans
Nonseq
Write
V1
hwrite
haddr
hready
hwdata
Last Valid
Data
Write Data (V1 Word)
Unknown
weim_hrdata
Last Valid Data
weim_hready
BCLK (burst clock)
ADDR Last Valid Addr
Address V1
Address V1 + 2
CS2
R/W
Write
LBA
OE
EB
DATA
Last Valid Data
1/2 Half Word
2/2 Half Word
Figure 20. WSC = 2, WWS = 1, WEA = 1, WEN = 2, A.WORD/E.HALF
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
41
Functional Description and Application Information
hclk
hsel_weim_cs[2]
htrans
Nonseq
Write
V1
hwrite
haddr
hready
hwdata
Last Valid
Data
Write Data (V1 Word)
Last Valid Data
Unknown
weim_hrdata
weim_hready
BCLK (burst clock)
ADDR
Last Valid Addr
Address V1
Address V1 + 2
CS2
R/W
LBA
OE
Write
EB
DATA
Last Valid Data
1/2 Half Word
2/2 Half Word
Figure 21. WSC = 1, WWS = 2, WEA = 1, WEN = 2, A.WORD/E.HALF
MC9328MXL Technical Data, Rev. 8
42
Freescale Semiconductor
Functional Description and Application Information
hclk
hsel_weim_cs[2]
htrans
Nonseq
Read
V1
Nonseq
Write
V8
hwrite
haddr
hready
hwdata
Last Valid Data
Write Data
Read Data
weim_hrdata
weim_hready
Last Valid Data
BCLK (burst clock)
ADDR
Last Valid Addr
Address V1
Address V8
Write
CS2
R/W
LBA
Read
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
DATA
DATA
Read Data
Last Valid Data
Write Data
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 22. WSC = 2, WWS = 2, WEA = 1, WEN = 2, A.HALF/E.HALF
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
43
Functional Description and Application Information
Read
Idle
Write
hclk
hsel_weim_cs[2]
htrans
Nonseq
Read
V1
Nonseq
Write
V8
hwrite
haddr
hready
hwdata
Last Valid Data
Write Data
weim_hrdata
weim_hready
Last Valid Data
Read Data
BCLK (burst clock)
ADDR
Last Valid Addr
Address V1
Address V8
Write
CS2
R/W
LBA
Read
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
DATA
DATA
Read Data
Last Valid Data
Write Data
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 23. WSC = 2, WWS = 1, WEA = 1, WEN = 2, EDC = 1, A.HALF/E.HALF
MC9328MXL Technical Data, Rev. 8
44
Freescale Semiconductor
Functional Description and Application Information
hclk
hsel_weim_cs[4]
htrans
Nonseq
Write
V1
hwrite
haddr
hready
hwdata
Last Valid
Data
Write Data (Word)
weim_hrdata
Last Valid Data
weim_hready
BCLK (burst clock)
ADDR
Last Valid Addr
Address V1
Address V1 + 2
CS
R/W
Write
LBA
OE
EB
DATA
Last Valid Data
Write Data (1/2 Half Word)
Write Data (2/2 Half Word)
Figure 24. WSC = 2, CSA = 1, WWS = 1, A.WORD/E.HALF
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
45
Functional Description and Application Information
hclk
hsel_weim_cs[4]
htrans
Nonseq
Read
V1
Nonseq
Write
V8
hwrite
haddr
hready
hwdata
weim_hrdata
weim_hready
Last Valid Data
Write Data
Read Data
Last Valid Data
BCLK (burst clock)
ADDR Last Valid Addr
Address V1
Address V8
CS4
R/W
LBA
OE
Read
Write
EBx1 (EBC2=0)
EBx1 (EBC2=1)
Read Data
DATA
DATA
Last Valid Data
Write Data
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 25. WSC = 3, CSA = 1, A.HALF/E.HALF
MC9328MXL Technical Data, Rev. 8
46
Freescale Semiconductor
Functional Description and Application Information
hclk
hsel_weim_cs[4]
htrans
Nonseq
Read
V1
Idle
Seq
Read
V2
hwrite
haddr
hready
weim_hrdata
weim_hready
Last Valid Data
Read Data (V1)
Read Data (V2)
BCLK (burst clock)
ADDR
Last Valid
Address V1
Address V2
CNC
CS4
R/W
LBA
Read
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
Read Data
(V1)
Read Data
(V2)
DATA
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 26. WSC = 2, OEA = 2, CNC = 3, BCM = 1, A.HALF/E.HALF
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
47
Functional Description and Application Information
hclk
hsel_weim_cs[4]
htrans
Nonseq
Read
V1
Idle Nonseq
hwrite
haddr
Write
V8
hready
hwdata
Last Valid Data
Write Data
weim_hrdata
Last Valid Data
Read Data
weim_hready
BCLK (burst clock)
ADDR
Last Valid Addr
Address V1
Address V8
CNC
CS4
R/W
LBA
OE
Read
Write
EBx1 (EBC2=0)
EBx1 (EBC2=1)
DATA
DATA
Read Data
Last Valid Data
Write Data
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 27. WSC = 2, OEA = 2, WEA = 1, WEN = 2, CNC = 3, A.HALF/E.HALF
MC9328MXL Technical Data, Rev. 8
48
Freescale Semiconductor
Functional Description and Application Information
hclk
hsel_weim_cs[2]
htrans
Idle
Nonseq
Read
V1
Nonse
Read
V5
hwrite
haddr
hready
weim_hrdata
weim_hready
BCLK (burst clock)
ADDR
Last Valid Addr
Address V1
Address V5
CS2
Read
R/W
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
ECB
DATA
V1 Word V2 Word
V5 Word V6 Word
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 28. WSC = 3, SYNC = 1, A.HALF/E.HALF
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
49
Functional Description and Application Information
hclk
hsel_weim_cs[2]
htrans
Idle
Nonseq
Seq
Read
V2
Seq
Read
V3
Seq
Read
V4
hwrite
haddr
Read
V1
hready
weim_hrdata
weim_hready
BCLK (burst clock)
ADDR
Last Valid Data
V1 Word
V2 Word
V3 Word
V4 Word
Last Valid Addr
Address V1
CS2
R/W
LBA
Read
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
ECB
DATA
V1 Word
V2 Word
V3 Word
V4 Word
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 29. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.WORD
MC9328MXL Technical Data, Rev. 8
50
Freescale Semiconductor
Functional Description and Application Information
hclk
hsel_weim_cs[2]
htrans
Idle
Seq
Nonseq
hwrite
Read
V1
Read
V2
haddr
hready
weim_hrdata
Last Valid Data
V1 Word
V2 Word
weim_hready
BCLK (burst clock)
ADDR
CS2
Last Valid
Address V1
Address V2
Read
R/W
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
ECB
DATA
V1 1/2
V1 2/2
V2 1/2
V2 2/2
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 30. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.HALF
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
51
Functional Description and Application Information
hclk
hsel_weim_cs[2]
Non
seq
Idle
htrans
Seq
Read
V2
hwrite
haddr
Read
V1
hready
weim_hrdata
Last Valid Data
V1 Word
V2 Word
weim_hready
BCLK (burst clock)
Last
ADDR
CS2
Address V1
Read
R/W
LBA
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
ECB
DATA
V1 1/2
V1 2/2
V2 1/2
V2 2/2
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 31. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 2, A.WORD/E.HALF
MC9328MXL Technical Data, Rev. 8
52
Freescale Semiconductor
Functional Description and Application Information
hclk
hsel_weim_cs[2]
htrans
Non
seq
Idle
Seq
Read
V2
hwrite
Read
V1
haddr
hready
weim_hrdata
Last Valid Data
V1 Word
V2 Word
weim_hready
BCLK (burst clock)
ADDR
Last
Address V1
CS2
R/W
LBA
Read
OE
EBx1 (EBC2=0)
EBx1 (EBC2=1)
ECB
DATA
V1 1/2
V1 2/2
V2 1/2
V2 2/2
Note 1: x = 0, 1, 2 or 3
Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register
Figure 32. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 1, A.WORD/E.HALF
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
53
Functional Description and Application Information
4.4.4
Non-TFT Panel Timing
T1
T1
VSYN
T3
T4
T2
T2
XMAX
HSYN
SCLK
Ts
LD[15:0]
Figure 33. Non-TFT Panel Timing
Table 17. Non TFT Panel Timing Diagram
Allowed Register
Symbol
Parameter
Actual Value
Unit
Minimum Value1, 2
Tpix4
Tpix
–
T1
HSYN to VSYN delay3
0
HWAIT2+2
HWIDTH+1
T2
T3
HSYN pulse width
VSYN to SCLK
0
–
0 ≤ T3 ≤ Ts5
T4
SCLK to HSYN
0
HWAIT1+1
Tpix
1
Maximum frequency of LCDC_CLK is 48 MHz, which is controlled by Peripheral Clock Divider Register.
Maximum frequency of SCLK is HCLK / 5, otherwise LD output will be wrong.
2
3
VSYN, HSYN and SCLK can be programmed as active high or active low. In the above timing diagram, all
these 3 signals are active high.
4
5
Tpix is the pixel clock period which equals LCDC_CLK period * (PCD + 1).
Ts is the shift clock period. Ts = Tpix * (panel data bus width).
4.5
SPI Timing Diagrams
To use the internal transmit (TX) and receive (RX) data FIFOs when the SPI 1 module is configured as a
master, two control signals are used for data transfer rate control: the SS signal (output) and the SPI_RDY
signal (input). The SPI1 Sample Period Control Register (PERIODREG1) and the SPI2 Sample Period
Control Register (PERIODREG2) can also be programmed to a fixed data transfer rate for either SPI 1 or
SPI 2. When the SPI 1 module is configured as a slave, the user can configure the SPI1 Control Register
(CONTROLREG1) to match the external SPI master’s timing. In this configuration, SS becomes an input
signal, and is used to latch data into or load data out to the internal data shift registers, as well as to
increment the data FIFO. Figure 34 through Figure 38 show the timing relationship of the master SPI using
different triggering mechanisms.
MC9328MXL Technical Data, Rev. 8
54
Freescale Semiconductor
Functional Description and Application Information
2
5
3
SS
1
4
SPIRDY
SCLK, MOSI, MISO
Figure 34. Master SPI Timing Diagram Using SPI_RDY Edge Trigger
SS
SPIRDY
SCLK, MOSI, MISO
Figure 35. Master SPI Timing Diagram Using SPI_RDY Level Trigger
SS (output)
SCLK, MOSI, MISO
Figure 36. Master SPI Timing Diagram Ignore SPI_RDY Level Trigger
SS (input)
SCLK, MOSI, MISO
Figure 37. Slave SPI Timing Diagram FIFO Advanced by BIT COUNT
SS (input)
6
7
SCLK, MOSI, MISO
Figure 38. Slave SPI Timing Diagram FIFO Advanced by SS Rising Edge
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
55
Functional Description and Application Information
Table 18. Timing Parameter Table for Figure 34 through Figure 38
3.0 0.3 V
Ref No.
Parameter
Unit
Minimum
Maximum
2T1
1
2
SPI_RDY to SS output low
–
–
ns
ns
3 • Tsclk2
2 • Tsclk
0
SS output low to first SCLK edge
3
4
5
Last SCLK edge to SS output high
SS output high to SPI_RDY low
SS output pulse width
–
–
–
ns
ns
ns
Tsclk + WAIT 3
6
7
SS input low to first SCLK edge
SS input pulse width
T
T
–
–
ns
ns
1
2
3
T = CSPI system clock period (PERCLK2).
Tsclk = Period of SCLK.
WAIT = Number of bit clocks (SCLK) or 32.768 kHz clocks per Sample Period Control Register.
8
SCLK
9
9
Figure 39. SPI SCLK Timing Diagram
Table 19. Timing Parameter Table for SPI SCLK
3.0 0.3 V
Ref No.
Parameter
Unit
Minimum
Maximum
8
9
SCLK frequency
SCLK pulse width
0
10
–
MHz
ns
100
4.6
LCD Controller
This section includes timing diagrams for the LCD controller. For detailed timing diagrams of the LCD
controller with various display configurations, refer to the LCD controller chapter of the MC9328MXL
Reference Manual.
LSCLK
1
LD[15:0]
Figure 40. SCLK to LD Timing Diagram
MC9328MXL Technical Data, Rev. 8
56
Freescale Semiconductor
Functional Description and Application Information
Table 20. LCDC SCLK Timing Parameter Table
3.0 0.3 V
Ref No.
Parameter
Minimum
Maximum
Unit
1
SCLK to LD valid
–
2
ns
Non-display
Display region
T3
T1
T4
VSYN
T2
HSYN
OE
Line Y
Line 1
Line Y
LD[15:0]
T6
T7
T5
XMAX
HSYN
SCLK
OE
T8
(1,1)
(1,2)
LD[15:0]
VSYN
(1,X)
T9
T10
Figure 41. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing
Table 21. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing
Symbol
Description
Minimum
Corresponding Register Value
Unit
T1
End of OE to beginning of VSYN
T5+T6
(VWAIT1·T2)+T5+T6+T7+T9
Ts
+T7+T9
T2
T3
T4
T5
T6
T7
HSYN period
XMAX+5
XMAX+T5+T6+T7+T9+T10
VWIDTH·(T2)
VWAIT2·(T2)
Ts
Ts
Ts
Ts
Ts
Ts
VSYN pulse width
T2
2
End of VSYN to beginning of OE
HSYN pulse width
1
HWIDTH+1
End of HSYN to beginning to T9
End of OE to beginning of HSYN
1
HWAIT2+1
1
HWAIT1+1
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
57
Functional Description and Application Information
Table 21. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing (Continued)
Symbol
Description
SCLK to valid LD data
Minimum
Corresponding Register Value
Unit
T8
T9
-3
2
3
2
ns
Ts
End of HSYN idle2 to VSYN edge
(for non-display region)
T9
End of HSYN idle2 to VSYN edge
(for Display region)
1
1
Ts
T10
T10
VSYN to OE active (Sharp = 0) when VWAIT2 = 0
VSYN to OE active (Sharp = 1) when VWAIT2 = 0
1
2
1
2
Ts
Ts
Note:
•
•
Ts is the SCLK period which equals LCDC_CLK / (PCD + 1). Normally LCDC_CLK = 15ns.
VSYN, HSYN and OE can be programmed as active high or active low. In Figure 41, all 3 signals
are active low.
•
•
The polarity of SCLK and LD[15:0] can also be programmed.
SCLK can be programmed to be deactivated during the VSYN pulse or the OE deasserted period.
In Figure 41, SCLK is always active.
•
•
For T9 non-display region, VSYN is non-active. It is used as an reference.
XMAX is defined in pixels.
4.7
Multimedia Card/Secure Digital Host Controller
The DMA interface block controls all data routing between the external data bus (DMA access), internal
MMC/SD module data bus, and internal system FIFO access through a dedicated state machine that
monitors the status of FIFO content (empty or full), FIFO address, and byte/block counters for the
MMC/SD module (inner system) and the application (user programming).
3a
1
2
4b
3b
Bus Clock
4a
5b
5a
Valid Data
CMD_DAT Input
Valid Data
7
CMD_DAT Output
Valid Data
Valid Data
6a
Figure 42. Chip-Select Read Cycle Timing Diagram
6b
MC9328MXL Technical Data, Rev. 8
58
Freescale Semiconductor
Functional Description and Application Information
Table 22. SDHC Bus Timing Parameter Table
1.8 0.1 V
3.0 0.3 V
Ref
No.
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
1
CLK frequency at Data transfer Mode
(PP)1—10/30 cards
0
25/5
0
25/5
MHz
2
CLK frequency at Identification Mode2
Clock high time1—10/30 cards
Clock low time1—10/30 cards
Clock fall time1—10/30 cards
0
6/33
15/75
–
400
–
0
400
–
kHz
ns
3a
3b
4a
10/50
10/50
–
–
–
ns
10/50
10/50
ns
(5.00)3
4b
Clock rise time1—10/30 cards
–
14/67
(6.67)3
–
10/50
ns
5a
5b
6a
6b
7
Input hold time3—10/30 cards
Input setup time3—10/30 cards
Output hold time3—10/30 cards
Output setup time3—10/30 cards
Output delay time3
10.3/10.3
10.3/10.3
5.7/5.7
5.7/5.7
0
–
–
9/9
9/9
5/5
5/5
0
–
–
ns
ns
ns
ns
ns
–
–
–
–
16
14
1
2
3
CL ≤ 100 pF / 250 pF (10/30 cards)
CL ≤ 250 pF (21 cards)
CL ≤ 25 pF (1 card)
4.7.1
Command Response Timing on MMC/SD Bus
The card identification and card operation conditions timing are processed in open-drain mode. The card
response to the host command starts after exactly N clock cycles. For the card address assignment,
ID
SET_RCA is also processed in the open-drain mode. The minimum delay between the host command and
card response is NCR clock cycles as illustrated in Figure 43. The symbols for Figure 43 through
Figure 47 are defined in Table 23.
Table 23. State Signal Parameters for Figure 43 through Figure 47
Card Active
Definition
Host Active
Definition
Symbol
Symbol
Z
D
High impedance state
Data bits
S
T
P
E
Start bit (0)
Transmitter bit (Host = 1, Card = 0)
One-cycle pull-up (1)
End bit (1)
*
Repetition
CRC
Cyclic redundancy check bits (7 bits)
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
59
Functional Description and Application Information
N
ID cycles
Host Command
Content
CRC
CID/OCR
Content
CMD
CMD
******
ST
E Z
Z S T
Z Z Z
Identification Timing
NCR cycles
Host Command
Content
CRC
CID/OCR
******
Content
SET_RCA Timing
ST
E Z
Z S T
Z Z Z
Figure 43. Timing Diagrams at Identification Mode
After a card receives its RCA, it switches to data transfer mode. As shown on the first diagram in
Figure 44, SD_CMD lines in this mode are driven with push-pull drivers. The command is followed by a
period of two Z bits (allowing time for direction switching on the bus) and then by P bits pushed up by the
responding card. The other two diagrams show the separating periods N and N
.
RC
CC
NCR cycles
Host Command
Response
Content
CRC
E Z Z Z
CMD
Content
CRC
******
ST
E Z Z P
P S T
Command response timing (data transfer mode)
NRC cycles
Response
Content
Host Command
Content
CRC
E Z Z Z
CMD
CRC
******
ST
E Z
Z S T
Timing response end to next CMD start (data transfer mode)
NCC cycles
Host Command
Host Command
Content
CRC
E Z Z Z
CMD
Content
CRC
E Z
******
ST
Z S T
Timing of command sequences (all modes)
Figure 44. Timing Diagrams at Data Transfer Mode
Figure 45 shows basic read operation timing. In a read operation, the sequence starts with a single block
read command (which specifies the start address in the argument field). The response is sent on the
SD_CMD lines as usual. Data transmission from the card starts after the access time delay N , beginning
AC
from the last bit of the read command. If the system is in multiple block read mode, the card sends a
continuous flow of data blocks with distance N until the card sees a stop transmission command. The
AC
data stops two clock cycles after the end bit of the stop command.
MC9328MXL Technical Data, Rev. 8
60
Freescale Semiconductor
Functional Description and Application Information
NCR cycles
Host Command
Response
CMD
DAT
Content
CRC
******
******
Content
CRC
E Z
ST
E Z Z P
P S T
Z****Z
*****
Z Z P
P S DDDD
Read Data
Timing of single block read
NAC cycles
NCR cycles
Host Command
Response
Content
CRC
E Z
CMD
DAT
Content
CRC
******
ST
E Z Z P
Z Z P
P S T
Z****Z
******
*****
Read Data
*****
*****
Read Data
P S DDDD
P
P S DDDD
NAC cycles
NAC cycles
Timing of multiple block read
NCR cycles
Host Command
Response
CMD
Content
CRC
******
Content
CRC
E Z
ST
E Z Z P
P S T
NST
DAT
*****
*****
DDDD
DDDD E Z Z Z
Timing of stop command
(CMD12, data transfer mode)
Valid Read Data
Figure 45. Timing Diagrams at Data Read
Figure 46 shows the basic write operation timing. As with the read operation, after the card response, the
data transfer starts after N cycles. The data is suffixed with CRC check bits to allow the card to check
WR
for transmission errors. The card sends back the CRC check result as a CC status token on the data line. If
there was a transmission error, the card sends a negative CRC status (101); otherwise, a positive CRC
status (010) is returned. The card expects a continuous flow of data blocks if it is configured to multiple
block mode, with the flow terminated by a stop transmission command.
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
61
Functional Description and Application Information
Figure 46. Timing Diagrams at Data Write
The stop transmission command may occur when the card is in different states. Figure 47 shows the
different scenarios on the bus.
MC9328MXL Technical Data, Rev. 8
62
Freescale Semiconductor
Functional Description and Application Information
Figure 47. Stop Transmission During Different Scenarios
Table 24. Timing Values for Figure 43 through Figure 47
Parameter Symbol Minimum Maximum
MMC/SD bus clock, CLK (All values are referred to minimum (VIH) and maximum (VIL)
Unit
Command response cycle
Identification response cycle
Access time delay cycle
NCR
NID
2
5
2
64
Clock cycles
Clock cycles
Clock cycles
5
NAC
TAAC + NSAC
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
63
Functional Description and Application Information
Table 24. Timing Values for Figure 43 through Figure 47 (Continued)
Parameter
Command read cycle
Symbol
Minimum
Maximum
Unit
NRC
NCC
NWR
NST
8
8
2
2
–
–
–
2
Clock cycles
Clock cycles
Clock cycles
Clock cycles
Command-command cycle
Command write cycle
Stop transmission cycle
TAAC: Data read access time -1 defined in CSD register bit[119:112]
NSAC: Data read access time -2 in CLK cycles (NSAC·100) defined in CSD register bit[111:104]
4.7.2
SDIO-IRQ and ReadWait Service Handling
In SDIO, there is a 1-bit or 4-bit interrupt response from the SDIO peripheral card. In 1-bit mode, the
interrupt response is simply that the SD_DAT[1] line is held low. The SD_DAT[1] line is not used as data
in this mode. The memory controller generates an interrupt according to this low and the system interrupt
continues until the source is removed (SD_DAT[1] returns to its high level).
In 4-bit mode, the interrupt is less simple. The interrupt triggers at a particular period called the “Interrupt
Period” during the data access, and the controller must sample SD_DAT[1] during this short period to
determine the IRQ status of the attached card. The interrupt period only happens at the boundary of each
block (512 bytes).
CMD
Content
CRC
Response
******
S
ST
E Z Z P S
E Z Z Z
Z Z Z
DAT[1]
Interrupt Period
IRQ
IRQ
Block Data
Block Data
S
E
E
For 4-bit
L H
DAT[1]
Interrupt Period
For 1-bit
Figure 48. SDIO IRQ Timing Diagram
ReadWait is another feature in SDIO that allows the user to submit commands during the data transfer. In
this mode, the block temporarily pauses the data transfer operation counter and related status, yet keeps
the clock running, and allows the user to submit commands as normal. After all commands are submitted,
the user can switch back to the data transfer operation and all counter and status values are resumed as
access continues.
MC9328MXL Technical Data, Rev. 8
64
Freescale Semiconductor
Functional Description and Application Information
CMD
******
CMD52 CRC
******
P S T
E Z Z Z
DAT[1]
Block Data
Block Data
Block Data
S
S
E Z Z L H
S
E
E
For 4-bit
DAT[2]
Block Data
E Z Z L L L L L L L L L L L L L L L L L L L L L H Z S
For 4-bit
Figure 49. SDIO ReadWait Timing Diagram
4.8
Memory Stick Host Controller
The Memory Stick protocol requires three interface signal line connections for data transfers: MS_BS,
MS_SDIO, and MS_SCLKO. Communication is always initiated by the MSHC and operates the bus in
either four-state or two-state access mode.
The MS_BS signal classifies data on the SDIO into one of four states (BS0, BS1, BS2, or BS3) according
to its attribute and transfer direction. BS0 is the INT transfer state, and during this state no packet
transmissions occur. During the BS1, BS2, and BS3 states, packet communications are executed. The BS1,
BS2, and BS3 states are regarded as one packet length and one communication transfer is always
completed within one packet length (in four-state access mode).
The Memory Stick usually operates in four state access mode and in BS1, BS2, and BS3 bus states. When
an error occurs during packet communication, the mode is shifted to two-state access mode, and the BS0
and BS1 bus states are automatically repeated to avoid a bus collision on the SDIO.
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
65
Functional Description and Application Information
2
3
5
1
4
MS_SCLKI
6
8
7
MS_SCLKO
MS_BS
9
10
11
12
11
12
MS_SDIO(output)
14
13
MS_SDIO (input)
(RED bit = 0)
15
16
MS_SDIO (input)
(RED bit = 1)
Figure 50. MSHC Signal Timing Diagram
Table 25. MSHC Signal Timing Parameter Table
Parameter
3.0 0.3 V
Minimum Maximum
Ref
No.
Unit
1
2
MS_SCLKI frequency
–
20
20
–
25
–
MHz
ns
MS_SCLKI high pulse width
MS_SCLKI low pulse width
MS_SCLKI rise time
3
–
ns
4
3
ns
5
MS_SCLKI fall time
–
3
ns
6
MS_SCLKO frequency1
MS_SCLKO high pulse width1
MS_SCLKO low pulse width1
MS_SCLKO rise time1
MS_SCLKO fall time1
–
25
–
MHz
ns
7
20
15
–
8
–
ns
9
5
ns
10
11
–
5
ns
MS_BS delay time1
–
3
ns
MC9328MXL Technical Data, Rev. 8
66
Freescale Semiconductor
Functional Description and Application Information
Table 25. MSHC Signal Timing Parameter Table (Continued)
3.0 0.3 V
Ref
No.
Parameter
MS_SDIO output delay time1,2
Unit
Minimum Maximum
12
13
14
15
16
–
18
0
3
–
–
–
–
ns
ns
ns
ns
ns
MS_SDIO input setup time for MS_SCLKO rising edge (RED bit = 0)3
MS_SDIO input hold time for MS_SCLKO rising edge (RED bit = 0)3
MS_SDIO input setup time for MS_SCLKO falling edge (RED bit = 1)4
MS_SDIO input hold time for MS_SCLKO falling edge (RED bit = 1)4
23
0
1
2
Loading capacitor condition is less than or equal to 30pF.
An external resistor (100 ~ 200 ohm) should be inserted in series to provide current control on the MS_SDIO pin,
because of a possibility of signal conflict between the MS_SDIO pin and Memory Stick SDIO pin when the pin
direction changes.
3
4
If the MSC2[RED] bit = 0, MSHC samples MS_SDIO input data at MS_SCLKO rising edge.
If the MSC2[RED] bit = 1, MSHC samples MS_SDIO input data at MS_SCLKO falling edge.
4.9
Pulse-Width Modulator
The PWM can be programmed to select one of two clock signals as its source frequency. The selected
clock signal is passed through a divider and a prescaler before being input to the counter. The output is
available at the pulse-width modulator output (PWMO) external pin. Its timing diagram is shown in
Figure 51 and the parameters are listed in Table 26.
1
2a
3b
System Clock
2b
4b
3a
4a
PWM Output
Figure 51. PWM Output Timing Diagram
Table 26. PWM Output Timing Parameter Table
1.8 0.1 V
3.0 0.3 V
Ref No.
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
1
System CLK frequency1
Clock high time1
Clock low time1
0
87
–
0
100
–
MHz
ns
2a
2b
3a
3.3
7.5
–
5/10
5/10
–
–
–
ns
Clock fall time1
5
5/10
ns
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
67
Functional Description and Application Information
Table 26. PWM Output Timing Parameter Table (Continued)
1.8 0.1 V 3.0 0.3 V
Ref No.
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
3b
4a
4b
Clock rise time1
–
6.67
–
–
5
5
5/10
–
ns
ns
ns
Output delay time1
Output setup time1
5.7
5.7
–
–
1
CL of PWMO = 30 pF
4.10 SDRAM Controller
This section shows timing diagrams and parameters associated with the SDRAM (synchronous dynamic
random access memory) Controller.
1
SDCLK
2
3S
3
CS
RAS
CAS
3H
3S
3S
3H
3S
3H
3H
4H
WE
ADDR
DQ
4S
ROW/BA
COL/BA
5
8
6
Data
7
3S
DQM
3H
Note: CKE is high during the read/write cycle.
Figure 52. SDRAM Read Cycle Timing Diagram
MC9328MXL Technical Data, Rev. 8
68
Freescale Semiconductor
Functional Description and Application Information
Table 27. SDRAM Read Timing Parameter Table
1.8 0.1 V
3.0 0.3 V
Ref
No.
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
1
2
3
SDRAM clock high-level width
SDRAM clock low-level width
SDRAM clock cycle time
2.67
6
–
–
4
4
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11.4
3.42
2.28
3.42
2.28
–
–
10
3
–
3S CS, RAS, CAS, WE, DQM setup time
3H CS, RAS, CAS, WE, DQM hold time
4S Address setup time
–
–
–
2
–
–
3
–
4H Address hold time
–
2
–
5
5
5
6
7
7
7
8
SDRAM access time (CL = 3)
6.84
6.84
22
–
–
6
SDRAM access time (CL = 2)
–
–
6
SDRAM access time (CL = 1)
–
–
22
–
Data out hold time
2.85
–
2.5
–
Data out high-impedance time (CL = 3)
Data out high-impedance time (CL = 2)
Data out high-impedance time (CL = 1)
Active to read/write command period (RC = 1)
6.84
6.84
22
–
6
–
–
6
–
–
22
–
1
tRCD1
tRCD
1
tRCD = SDRAM clock cycle time. This settings can be found in the MC9328MXL reference manual.
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
69
Functional Description and Application Information
SDCLK
1
3
2
CS
RAS
6
CAS
WE
ADDR
DQ
5
7
4
/ BA
ROW/BA
COL/BA
DATA
8
9
DQM
Figure 53. SDRAM Write Cycle Timing Diagram
Table 28. SDRAM Write Timing Parameter Table
1.8 0.1 V
3.0 0.3 V
Ref No.
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
1
2
3
4
5
6
SDRAM clock high-level width
SDRAM clock low-level width
SDRAM clock cycle time
Address setup time
2.67
6
–
–
–
–
–
–
4
4
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
11.4
3.42
2.28
10
3
Address hold time
Precharge cycle period1
2
2
tRP2
tRP
7
Active to read/write command delay
tRCD2
–
tRCD2
–
ns
8
9
Data setup time
Data hold time
4.0
–
–
2
2
–
–
ns
ns
2.28
1
Precharge cycle timing is included in the write timing diagram.
2
tRP and tRCD = SDRAM clock cycle time. These settings can be found in the MC9328MXL reference manual.
MC9328MXL Technical Data, Rev. 8
70
Freescale Semiconductor
Functional Description and Application Information
SDCLK
CS
1
3
2
RAS
CAS
6
7
7
WE
ADDR
DQ
4
5
BA
ROW/BA
DQM
Figure 54. SDRAM Refresh Timing Diagram
Table 29. SDRAM Refresh Timing Parameter Table
1.8 0.1 V
3.0 0.3 V
Ref No.
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
1
2
3
4
5
6
SDRAM clock high-level width
SDRAM clock low-level width
SDRAM clock cycle time
Address setup time
2.67
6
–
–
–
–
–
–
4
4
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
11.4
3.42
2.28
10
3
Address hold time
2
1
Precharge cycle period
tRP1
tRP
7
Auto precharge command period
tRC1
–
tRC1
–
ns
1
tRP and tRC = SDRAM clock cycle time. These settings can be found in the MC9328MXL reference manual.
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
71
Functional Description and Application Information
SDCLK
CS
RAS
CAS
WE
ADDR
DQ
BA
DQM
CKE
Figure 55. SDRAM Self-Refresh Cycle Timing Diagram
4.11 USB Device Port
Four types of data transfer modes exist for the USB module: control transfers, bulk transfers, isochronous
transfers, and interrupt transfers. From the perspective of the USB module, the interrupt transfer type is
identical to the bulk data transfer mode, and no additional hardware is supplied to support it. This section
covers the transfer modes and how they work from the ground up.
Data moves across the USB in packets. Groups of packets are combined to form data transfers. The same
packet transfer mechanism applies to bulk, interrupt, and control transfers. Isochronous data is also moved
in the form of packets, however, because isochronous pipes are given a fixed portion of the USB
bandwidth at all times, there is no end-of-transfer.
MC9328MXL Technical Data, Rev. 8
72
Freescale Semiconductor
Functional Description and Application Information
USBD_AFE
(Output)
t VMO_ROE
4
t ROE_VPO
1
USBD_ROE
(Output)
6
3
tPERIOD
tVPO_ROE
USBD_VPO
(Output)
USBD_VMO
(Output)
tROE_VMO
tFEOPT
USBD_SUSPND
(Output)
2
5
USBD_RCV
(Input)
USBD_VP
(Input)
USBD_VM
(Input)
Figure 56. USB Device Timing Diagram for Data Transfer to USB Transceiver (TX)
Table 30. USB Device Timing Parameters for Data Transfer to USB Transceiver (TX)
3.0 0.3 V
Ref
No.
Parameter
Unit
Minimum
Maximum
1
2
3
4
5
6
t
ROE_VPO; USBD_ROE active to USBD_VPO low
83.14
81.55
83.54
248.90
160.00
11.97
83.47
81.98
83.80
249.13
175.00
12.03
ns
ns
tROE_VMO; USBD_ROE active to USBD_VMO high
tVPO_ROE; USBD_VPO high to USBD_ROE deactivated
tVMO_ROE; USBD_VMO low to USBD_ROE deactivated (includes SE0)
tFEOPT; SE0 interval of EOP
ns
ns
ns
tPERIOD; Data transfer rate
Mb/s
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
73
Functional Description and Application Information
USBD_AFE
(Output)
USBD_ROE
(Output)
USBD_VPO
(Output)
USBD_VMO
(Output)
USBD_SUSPND
(Output)
USBD_RCV
(Input)
1
tFEOPR
USBD_VP
(Input)
USBD_VM
(Input)
Figure 57. USB Device Timing Diagram for Data Transfer from USB Transceiver (RX)
Table 31. USB Device Timing Parameter Table for Data Transfer from USB Transceiver (RX)
3.0 0.3 V
Ref No.
Parameter
Unit
Minimum
Maximum
1
tFEOPR; Receiver SE0 interval of EOP
82
–
ns
2
4.12 I C Module
2
The I C communication protocol consists of seven elements: START, Data Source/Recipient, Data
Direction, Slave Acknowledge, Data, Data Acknowledge, and STOP.
SDA
5
3
4
SCL
2
6
1
2
Figure 58. Definition of Bus Timing for I C
MC9328MXL Technical Data, Rev. 8
74
Freescale Semiconductor
Functional Description and Application Information
2
Table 32. I C Bus Timing Parameter Table
1.8 0.1 V
3.0 0.3 V
Ref No.
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
1
2
3
4
5
6
Hold time (repeated) START condition
Data hold time
182
0
–
171
–
160
0
–
150
–
ns
ns
ns
ns
ns
ns
Data setup time
11.4
80
10
HIGH period of the SCL clock
LOW period of the SCL clock
Setup time for STOP condition
–
120
320
160
–
480
182.4
–
–
–
–
4.13 Synchronous Serial Interface
The transmit and receive sections of the SSI can be synchronous or asynchronous. In synchronous mode,
the transmitter and the receiver use a common clock and frame synchronization signal. In asynchronous
mode, the transmitter and receiver each have their own clock and frame synchronization signals.
Continuous or gated clock mode can be selected. In continuous mode, the clock runs continuously. In gated
clock mode, the clock functions only during transmission. The internal and external clock timing diagrams
are shown in Figure 60 through Figure 62.
Normal or network mode can also be selected. In normal mode, the SSI functions with one data word of
I/O per frame. In network mode, a frame can contain between 2 and 32 data words. Network mode is
typically used in star or ring-time division multiplex networks with other processors or codecs, allowing
interface to time division multiplexed networks without additional logic. Use of the gated clock is not
allowed in network mode. These distinctions result in the basic operating modes that allow the SSI to
communicate with a wide variety of devices.
1
STCK Output
4
2
STFS (bl) Output
STFS (wl) Output
6
8
12
11
32
10
STXD Output
SRXD Input
31
Note: SRXD input in synchronous mode only.
Figure 59. SSI Transmitter Internal Clock Timing Diagram
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
75
Functional Description and Application Information
1
SRCK Output
3
5
SRFS (bl) Output
SRFS (wl) Output
7
9
13
14
SRXD Input
Figure 60. SSI Receiver Internal Clock Timing Diagram
15
16
17
STCK Input
18
20
STFS (bl) Input
STFS (wl) Input
24
22
28
27
34
26
STXD Output
SRXD Input
33
Note: SRXD Input in Synchronous mode only
Figure 61. SSI Transmitter External Clock Timing Diagram
MC9328MXL Technical Data, Rev. 8
76
Freescale Semiconductor
Functional Description and Application Information
15
16
17
SRCK Input
19
21
SRFS (bl) Input
SRFS (wl) Input
25
23
30
29
SRXD Input
Figure 62. SSI Receiver External Clock Timing Diagram
Table 33. SSI (Port C Primary Function) Timing Parameter Table
1.8 0.1 V
3.0 0.3 V
Ref No.
Parameter
Unit
Minimum Maximum Minimum Maximum
Internal Clock Operation1 (Port C Primary Function2)
1
2
STCK/SRCK clock period1
95
1.5
–
4.5
83.3
1.3
-1.1
2.2
0.1
1.3
-1.1
2.2
0.1
12.5
0.8
0.5
11.3
18.5
0
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
STCK high to STFS (bl) high3
SRCK high to SRFS (bl) high3
STCK high to STFS (bl) low3
SRCK high to SRFS (bl) low3
STCK high to STFS (wl) high3
SRCK high to SRFS (wl) high3
STCK high to STFS (wl) low3
SRCK high to SRFS (wl) low3
STCK high to STXD valid from high impedance
STCK high to STXD high
3.9
-1.5
3.8
-0.8
3.9
-1.5
3.8
-0.8
13.8
2.7
2.8
11.9
–
3
-1.2
2.5
-1.7
4.3
4
5
0.1
-0.8
4.45
-1.5
4.33
-0.8
15.73
3.08
3.19
13.57
–
6
1.48
-1.1
2.51
0.1
7
8
9
10
11a
11b
12
13
14
14.25
0.91
0.57
12.88
21.1
0
STCK high to STXD low
STCK high to STXD high impedance
SRXD setup time before SRCK low
SRXD hold time after SRCK low
–
–
External Clock Operation (Port C Primary Function2)
15
16
17
STCK/SRCK clock period1
STCK/SRCK clock high period
STCK/SRCK clock low period
92.8
27.1
61.1
–
–
–
81.4
40.7
40.7
–
–
–
ns
ns
ns
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
77
Functional Description and Application Information
Table 33. SSI (Port C Primary Function) Timing Parameter Table (Continued)
1.8 0.1 V 3.0 0.3 V
Minimum Maximum Minimum Maximum
Ref No.
Parameter
Unit
18
19
20
21
22
23
24
25
26
27a
27b
28
29
30
STCK high to STFS (bl) high3
SRCK high to SRFS (bl) high3
STCK high to STFS (bl) low3
SRCK high to SRFS (bl) low3
STCK high to STFS (wl) high3
SRCK high to SRFS (wl) high3
STCK high to STFS (wl) low3
SRCK high to SRFS (wl) low3
STCK high to STXD valid from high impedance
STCK high to STXD high
–
–
92.8
92.8
92.8
92.8
92.8
92.8
92.8
92.8
28.16
18.13
18.24
28.5
–
0
0
81.4
81.4
81.4
81.4
81.4
81.4
81.4
81.4
24.7
15.9
16.0
25.0
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
0
–
0
–
0
–
0
–
0
–
0
18.01
8.98
9.12
18.47
1.14
0
15.8
7.0
8.0
16.2
1.0
0
STCK high to STXD low
STCK high to STXD high impedance
SRXD setup time before SRCK low
SRXD hole time after SRCK low
–
–
Synchronous Internal Clock Operation (Port C Primary Function2)
31
32
SRXD setup before STCK falling
SRXD hold after STCK falling
15.4
0
–
–
13.5
0
–
–
ns
ns
Synchronous External Clock Operation (Port C Primary Function2)
33
34
SRXD setup before STCK falling
SRXD hold after STCK falling
1.14
0
–
–
1.0
0
–
–
ns
ns
1
2
All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting
the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.
There are 2 sets of I/O signals for the SSI module. They are from Port C primary function (pad 257 to pad 261) and Port B
alternate function (pad 283 to pad 288). When SSI signals are configured as outputs, they can be viewed both at Port C primary
function and Port B alternate function. When SSI signals are configured as input, the SSI module selects the input based on
status of the FMCR register bits in the Clock controller module (CRM). By default, the input are selected from Port C primary
function.
3
bl = bit length; wl = word length.
MC9328MXL Technical Data, Rev. 8
78
Freescale Semiconductor
Functional Description and Application Information
Table 34. SSI (Port B Alternate Function) Timing Parameter Table
1.8 0.1 V 3.0 0.3 V
Minimum Maximum Minimum Maximum
Internal Clock Operation1 (Port B Alternate Function2)
Ref
No.
Parameter
Unit
1
2
3
4
5
6
7
8
9
STCK/SRCK clock period1
95
1.7
–
83.3
1.5
-0.1
2.7
–
4.2
1.0
4.6
2.0
4.2
1.0
4.6
2.0
14.2
3.0
3.5
12.8
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
STCK high to STFS (bl) high3
SRCK high to SRFS (bl) high3
STCK high to STFS (bl) low3
SRCK high to SRFS (bl) low3
STCK high to STFS (wl) high3
SRCK high to SRFS (wl) high3
STCK high to STFS (wl) low3
SRCK high to SRFS (wl) low3
4.8
-0.1
3.08
1.25
1.71
-0.1
3.08
1.25
14.93
1.25
2.51
12.43
20
1.0
5.24
2.28
4.79
1.0
1.1
1.5
-0.1
2.7
5.24
2.28
16.19
3.42
3.99
14.59
–
1.1
10 STCK high to STXD valid from high impedance
11a STCK high to STXD high
13.1
1.1
11b STCK high to STXD low
2.2
10.9
17.5
0
12 STCK high to STXD high impedance
13 SRXD setup time before SRCK low
14 SRXD hold time after SRCK low
0
–
–
External Clock Operation (Port B Alternate Function2)
15 STCK/SRCK clock period1
16 STCK/SRCK clock high period
17 STCK/SRCK clock low period
18 STCK high to STFS (bl) high3
19 SRCK high to SRFS (bl) high3
20 STCK high to STFS (bl) low3
21 SRCK high to SRFS (bl) low3
22 STCK high to STFS (wl) high3
23 SRCK high to SRFS (wl) high3
24 STCK high to STFS (wl) low3
25 SRCK high to SRFS (wl) low3
26 STCK high to STXD valid from high impedance
27a STCK high to STXD high
92.8
27.1
61.1
–
–
81.4
40.7
40.7
0
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
–
–
–
92.8
92.8
92.8
92.8
92.8
92.8
92.8
92.8
29.07
20.75
21.32
81.4
81.4
81.4
81.4
81.4
81.4
81.4
81.4
25.5
18.2
18.7
–
0
–
0
–
0
–
0
–
0
–
0
–
0
18.9
9.23
10.60
16.6
8.1
9.3
27b STCK high to STXD low
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
79
Functional Description and Application Information
Table 34. SSI (Port B Alternate Function) Timing Parameter Table (Continued)
1.8 0.1 V 3.0 0.3 V
Ref
No.
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
28 STCK high to STXD high impedance
29 SRXD setup time before SRCK low
30 SRXD hold time after SRCK low
17.90
1.14
0
29.75
15.7
1.0
0
26.1
–
ns
ns
ns
–
–
–
Synchronous Internal Clock Operation (Port B Alternate Function2)
31 SRXD setup before STCK falling
32 SRXD hold after STCK falling
18.81
0
–
–
16.5
0
–
–
ns
ns
Synchronous External Clock Operation (Port B Alternate Function2)
33 SRXD setup before STCK falling
34 SRXD hold after STCK falling
1.14
0
–
–
1.0
0
–
–
ns
ns
1
2
All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting
the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.
There are 2 set of I/O signals for the SSI module. They are from Port C primary function (pad 257 to pad 261) and Port B
alternate function (pad 283 to pad 288). When SSI signals are configured as outputs, they can be viewed both at Port C primary
function and Port B alternate function. When SSI signals are configured as inputs, the SSI module selects the input based on
FMCR register bits in the Clock controller module (CRM). By default, the input are selected from Port C primary function.
3
bl = bit length; wl = word length.
4.14 CMOS Sensor Interface
The CMOS Sensor Interface (CSI) module consists of a control register to configure the interface timing,
a control register for statistic data generation, a status register, interface logic, a 32 × 32 image data receive
FIFO, and a 16 × 32 statistic data FIFO.
4.14.1 Gated Clock Mode
Figure 63 shows the timing diagram when the CMOS sensor output data is configured for negative edge
and the CSI is programmed to received data on the positive edge. Figure 64 shows the timing diagram
when the CMOS sensor output data is configured for positive edge and the CSI is programmed to received
data in negative edge. The parameters for the timing diagrams are listed in Table 35.
MC9328MXL Technical Data, Rev. 8
80
Freescale Semiconductor
Functional Description and Application Information
1
VSYNC
HSYNC
7
5
6
2
PIXCLK
Valid Data
Valid Data
Valid Data
DATA[7:0]
3
4
Figure 63. Sensor Output Data on Pixel Clock Falling Edge
CSI Latches Data on Pixel Clock Rising Edge
1
VSYNC
HSYNC
7
6
5
2
PIXCLK
Valid Data
Valid Data
Valid Data
DATA[7:0]
3
4
Figure 64. Sensor Output Data on Pixel Clock Rising Edge
CSI Latches Data on Pixel Clock Falling Edge
Table 35. Gated Clock Mode Timing Parameters
Ref No.
Parameter
Min
Max
Unit
1
2
3
4
5
6
7
csi_vsync to csi_hsync
csi_hsync to csi_pixclk
csi_d setup time
180
–
–
ns
ns
1
1
–
ns
csi_d hold time
1
–
ns
csi_pixclk high time
csi_pixclk low time
csi_pixclk frequency
10.42
10.42
0
–
ns
–
ns
48
MHz
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
81
Functional Description and Application Information
The limitation on pixel clock rise time / fall time are not specified. It should be calculated from the hold
time and setup time, according to:
Rising-edge latch data
max rise time allowed = (positive duty cycle - hold time)
max fall time allowed = (negative duty cycle - setup time)
In most of case, duty cycle is 50 / 50, therefore
max rise time = (period / 2 - hold time)
max fall time = (period / 2 - setup time)
For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns.
positive duty cycle = 10 / 2 = 5ns
=> max rise time allowed = 5 - 1 = 4ns
negative duty cycle = 10 / 2 = 5ns
=> max fall time allowed = 5 - 1 = 4ns
Falling-edge latch data
max fall time allowed = (negative duty cycle - hold time)
max rise time allowed = (positive duty cycle - setup time)
4.14.2 Non-Gated Clock Mode
Figure 65 shows the timing diagram when the CMOS sensor output data is configured for negative edge
and the CSI is programmed to received data on the positive edge. Figure 66 shows the timing diagram
when the CMOS sensor output data is configured for positive edge and the CSI is programmed to received
data in negative edge. The parameters for the timing diagrams are listed in Table 36.
1
VSYNC
6
4
5
PIXCLK
Valid Data
Valid Data
Valid Data
DATA[7:0]
2
3
Figure 65. Sensor Output Data on Pixel Clock Falling Edge
CSI Latches Data on Pixel Clock Rising Edge
MC9328MXL Technical Data, Rev. 8
82
Freescale Semiconductor
Functional Description and Application Information
1
VSYNC
6
4
5
PIXCLK
Valid Data
Valid Data
Valid Data
DATA[7:0]
2
3
Figure 66. Sensor Output Data on Pixel Clock Rising Edge
CSI Latches Data on Pixel Clock Falling Edge
Table 36. Non-Gated Clock Mode Parameters
Ref No.
Parameter
Min
Max
Unit
1
2
3
4
5
6
csi_vsync to csi_pixclk
csi_d setup time
180
1
–
–
ns
ns
csi_d hold time
1
–
ns
csi_pixclk high time
csi_pixclk low time
csi_pixclk frequency
10.42
10.42
0
–
ns
–
ns
48
MHz
The limitation on pixel clock rise time / fall time are not specified. It should be calculated from the hold
time and setup time, according to:
max rise time allowed = (positive duty cycle - hold time)
max fall time allowed = (negative duty cycle - setup time)
In most of case, duty cycle is 50 / 50, therefore:
max rise time = (period / 2 - hold time)
max fall time = (period / 2 - setup time)
For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns.
positive duty cycle = 10 / 2 = 5ns
=> max rise time allowed = 5 - 1 = 4ns
negative duty cycle = 10 / 2 = 5ns
=> max fall time allowed = 5 - 1 = 4ns
Falling-edge latch data
max fall time allowed = (negative duty cycle - hold time)
max rise time allowed = (positive duty cycle - setup time)
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
83
5 Pin-Out and Package Information
Table 37 illustrates the package pin assignments for the 256-pin MAPBGA package. For a complete listing of signals, see the Signal
Multiplexing Table 3 on page 9.
Table 37. i.MXL 256 MAPBGA Pin Assignments
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
USBD_
AFE
UART1_
RTS
UART1_
RXD
A
B
C
D
E
F
NVSS
SD_DAT3
SD_CLK
NVSS
NVDD4
NVSS
NVDD3
N.C.
N.C.
QVDD4
N.C.
N.C.
N.C.
A
B
C
D
E
F
USBD_
ROE
SSI_
RXCLK
SSI_
TXCLK
SPI1_
SCLK
A24
A23
A22
A20
A18
A15
SD_DAT1
D31
SD_CMD
SD_DAT0
D29
PB16
PB15
PB14
D26
USBD_VP
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
CLS
N.C.
N.C.
QVSS
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
USBD_
RCV
UART2_
CTS
UART2_
RXD
SSI_
RXFS
UART1_
TXD
USBD_
SUSPND
USBD_
VPO
USBD_
VMO
SSI_
RXDAT
SPI1_
SPI_RDY
D30
N.C.
N.C.
N.C.
N.C.
N.C.
UART2_
RTS
SSI_
TXDAT
A21
D28
SD_DAT2
A16
USBD_VM
PB18
SPI1_SS
N.C.
N.C.
N.C.
UART2_
TXD
SSI_
TXFS
SPI1_
MISO
D27
D25
A19
REV
N.C.
LSCLK
SPL_SPR
LD1
UART1_
CTS
SPI1_
MOSI
LP/
HSYNC
FLM/
VSYNC
G
A17
D24
D23
D21
PB17
PB19
CONTRAST
ACD/OE
G
H
J
A13
A12
A10
A8
D22
A11
D16
A7
A14
D18
A9
D20
D19
D17
D15
NVDD1
NVDD1
NVDD1
D14
NVDD1
NVDD1
NVSS
NVSS
NVSS
NVSS
NVSS
QVSS
NVDD1
NVDD1
CAS
QVDD1
NVSS
NVDD2
TCK
PS
NVSS
NVDD2
TIN
LD0
LD6
LD2
LD7
LD4
LD8
LD5
LD11
LD9
LD3
QVSS
LD15
H
J
QVDD3
TMR2OUT
CSI_D2
K
L
LD10
PWMO
LD12
LD13
CSI_D0
LD14
K
L
D13
NVDD1
CSI_MCLK
CSI_D1
CSI_D3
BIG_
ENDIAN
CSI_
HSYNC
M
N
A5
A4
D12
EB1
D11
D10
A6
D7
SDCLK
A0
NVSS
D4
RW
MA10
RAS
RESET_IN
CSI_D4
BOOT2
CSI_VSYNC
CSI_D7
CSI_D6
TMS
CSI_D5
TDI
M
N
RESET_
OUT
CSI_
PIXCLK
1
PA17
D1
D3
DQM1
RESET_SF
SDCKE1
DQM0
P
R
T
A3
EB2
NVSS
1
D9
EB3
A2
2
EB0
A1
OE
3
CS3
CS4
CS5
4
D6
D8
CS2
5
ECB
D5
D2
LBA
CS0
7
DQM3
D0
BOOT3
SDCKE0
CLKO
11
BOOT0
POR
TRST
I2C_SCL
TDO
I2C_SDA
QVDD2
XTAL32K
EXTAL32K
QVSS
P
R
T
2
BOOT1
BCLK
CS1
6
MA11
DQM2
9
SDWE
10
AVDD1
12
TRISTATE EXTAL16M XTAL16M
13 14 15
8
16
1
2
This signal is not used and should be floated in an actual application.
burst clock
Table 38 illustrates the package pin assignments for the 225-contact MAPBGA package. For a complete listing of signals, see the
Signal Multiplexing Table 3 on page 9.
Table 38. i.MXL 225 MAPBGA Pin Assignments
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
USBD_
ROE
USBD_
SUSPND
SSI_
RXFS
SSI_
TXCLK
SPI1_SPI_
RDY
SPI1_
SCLK
A
B
C
D
E
SD_CMD
PB15
PB19
USBD_VM
REV
PS
LD2
LD4
LD5
A
B
C
D
E
USBD_
AFE
USBD_
RCV
USBD_
VMO
SSI_
RXDAT
UART1_
TXD
SPL_
SPR
SD_DAT3
D31
SD_CLK
SD_DAT0
A24
PB16
PB14
SPI1_SS
LSCLK
LD0
LD8
LD3
LD9
LD6
LD12
LD7
NVDD2
LD13
USBD_
VPO
UART2_
RXD
SSI_
TXFS
UART1_
RTS
PB18
PB17
D29
SD_DAT2
NVDD1
CONTRAST FLM/VSYNC
USBD_
VP
UART2_
TXD
SPI1_
A23
SD_DAT1
D30
QVDD4
NVDD3
LP/HSYNC
MOSI
LD1
LD11
TIN
TMR2OUT
CSI_D0
CSI_D2
UART2_
RTS
UART1_
RXD
UART1_
CTS
SPI1_
CSI_
MCLK
A21
A22
NVDD1
QVSS
ACD/OE
MISO
LD10
UART2_
CTS
SSI_
RXCLK
SSI_
TXDAT
F
G
H
J
A20
A17
A15
A14
A13
A19
A18
A16
A12
A11
D28
D26
D23
D21
CS2
D27
D25
D24
D20
D19
NVDD1
NVDD1
D22
NVDD1
NVSS
NVSS
NVSS
NVSS
CLS
QVSS
NVDD2
CSI_D6
D1
QVDD3
PWMO
LD14
LD15
CSI_D4
CSI_D5
TMS
F
G
H
J
NVDD4
NVSS
NVSS
QVSS
NVSS
NVSS
NVSS
NVSS
NVSS
NVSS
ECB
CSI_D3
CSI_D7 CSI_HSYNC
CSI_
VSYNC
CSI_
CSI_D1
I2C_SCL
BOOT2
I2C_SDA
PIXCLK
NVDD1
NVDD1
QVDD1
NVDD1
TCK
TDI
TDO
BOOT1
BOOT0
XTAL32K
BIG_
ENDIAN
RESET_
OUT
K
K
L
M
N
P
R
A10
D16
A8
A9
D15
A7
D17
D13
D12
A4
D18
D10
EB0
A3
NVDD1
EB3
D9
NVDD1
NVDD1
D8
CS5
CS4
CS3
D6
D2
CS1
CS0
D5
NVSS
RW
NVSS
NVSS
DQM2
DQM1
D3
POR
BOOT3
DQM0
RAS
QVSS
XTAL16M EXTAL32K
RESET_IN EXTAL16M
L
M
N
P
R
1
QVDD2
BCLK
PA17
MA10
D4
D0
SDCKE0 TRISTATE
TRST
2
D14
A6
A5
A2
A1
MA11
LBA
10
SDCKE1
CAS
CLKO
SDWE
14
RESET_SF
AVDD1
15
D11
2
EB1
3
EB2
4
OE
D7
A0
SDCLK
8
DQM3
12
1
5
6
7
9
11
13
1
2
Burst Clock
This signal is not used and should be floated in an actual application.
Pin-Out and Package Information
5.1
MAPBGA 256 Package Dimensions
Figure 67 illustrates the 256 MAPBGA 14 mm × 14 mm × 1.30 mm package, with an 0.8 mm pad pitch.
The device designator for the MAPBGA package is VH.
Case Outline 1367
TOP VIEW
SIDE VIEW
BOTTOM VIEW
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2.INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14 5M-1994.
3.MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A.
4. DATUM A, THE SEATING PLANE IS DEFINED BY SPHERICAL CROWNS OF THE SOLDER BALLS.
Figure 67. i.MXL 256 MAPBGA Mechanical Drawing
MC9328MXL Technical Data, Rev. 8
86
Freescale Semiconductor
Pin-Out and Package Information
5.2
MAPBGA 225 Package Dimensions
Figure 68 illustrates the 225 MAPBGA 13 mm × 13 mm package.
Case Outline 1304B
TOP VIEW
BOTTOM VIEW
SIDE VIEW
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2.DIMENSIONS AND TOLERANCES PER ASME Y14 5M-1994.
3.MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A.
4. DATUM A, THE SEATING PLANE IS DEFINED BY SPHERICAL CROWNS OF THE SOLDER
BALLS.
5.PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE
Figure 68. i.MXL 225 MAPBGA Mechanical Drawing
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
87
Product Documentation
6 Product Documentation
6.1
Revision History
Table 39 provides revision history for this release. This history includes technical content revisions only
and not stylistic or grammatical changes.
Table 39. i.MXL Data Sheet Revision History Rev. 8
Location
Table 2 on page 4
Revision
• Added the DMA_REQ signal to table.
Signal Names and
Descriptions
• Corrected signal name from USBD_OE to USBD_ROE
Table 3 on page 9
Signal Multiplex Table i.MXL
Added Signal Multiplex table from Reference Manual with the following changes:
• Changed I/O Supply Voltage,PB31–20, from NVDD3 to NVDD4
• Added 225 BGA column.
• Removed 69K pull-up resistor from EB1, EB2, and added to D9
Table 10 on page 21
Table 3 on page 9
Changed first and second parameters descriptions:
From: Reference Clock freq range, To: DPLL input clock freq range
From: Double clock freq range, To: DPLL output freq range
Added Signal Multiplex table.
6.2
Reference Documents
The following documents are required for a complete description of the MC9328MXL and are necessary
to design properly with the device. Especially for those not familiar with the ARM920T processor or
previous i.MX processor products, the following documents are helpful when used in conjunction with this
document.
ARM Architecture Reference Manual (ARM Ltd., order number ARM DDI 0100)
ARM9DT1 Data Sheet Manual (ARM Ltd., order number ARM DDI 0029)
ARM Technical Reference Manual (ARM Ltd., order number ARM DDI 0151C)
EMT9 Technical Reference Manual (ARM Ltd., order number DDI O157E)
MC9328MXL Product Brief (order number MC9328MXLP)
MC9328MXL Reference Manual (order number MC9328MXLRM)
The Freescale manuals are available on the Freescale Semiconductors Web site at
http://www.freescale.com/imx. These documents may be downloaded directly from the Freescale Web
site, or printed versions may be ordered. The ARM Ltd. documentation is available from
http://www.arm.com.
MC9328MXL Technical Data, Rev. 8
88
Freescale Semiconductor
NOTES
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
89
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Document Number: MC9328MXL
Rev. 8
12/2006
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NXP
MC9328MXLDVP15R2
32-BIT, 150MHz, RISC PROCESSOR, PBGA225, 13 X 13 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, MAPBGA-225
NXP
MC9328MXLDVP20
200 MHz, RISC PROCESSOR, PBGA225, 13 X 13 MM, 0.80 MM PITCH, LEAD FREE, PLASTIC, BGA-225
MOTOROLA
MC9328MXLDVP20R2
32-BIT, 200MHz, RISC PROCESSOR, PBGA225, 13 X 13 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, MAPBGA-225
NXP
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