MC9328MX21SVKR2_技术文档

Document Number: MC9328MX21S

Rev. 1.3, 06/2008

Freescale Semiconductor

Data Sheet: Technical Data

MC9328MX21S

Package Information

(MAPBGA–289)

MC9328MX21S

266 MHz

Ordering Information: See Table 1 on page 3

Contents

1 Introduction

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

2 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . .4

3 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .12

4 Pin Assignment and Package Information . . .84

5 Document Revision History . . . . . . . . . . . . . . .87

Freescale’s i.MX family of microprocessors has

demonstrated leadership in the portable handheld

market. Building on the success of the MX (Media

Extensions) series, the i.MX21S (MC9328MX21S)

provides a leap in performance with an ARM926EJ-S

microprocessor core that provides accelerated Java

™

supportinaddition tohighlyintegrated systemfunctions.

The i.MX21S device addresses the needs of multiple

markets with intelligent integrated peripherals, advanced

®

ARM processor core, and power management

capabilities.

The i.MX21S features the advanced and power-efficient

ARM926EJ-S core operating at speeds up to 266 MHz

and is part of a growing family of Smart Speed products

that offer high performance processing optimized for

lowest power consumption. On-chip modules such as an

®

LCD controller, USB On-The-Go, 1-Wire interface,

and synchronous serial interfaces offer designers a rich

suite of peripherals that can enhance many products.

For cost sensitive applications, the NAND Flash

controller allows the use of low-cost NAND Flash

This document contains information on a new product. Specifications and information herein are subject to change

without notice.

Introduction

devices to be used as primary or secondary non-volatile storage. The on-chip error correction code (ECC)

and parity checking circuitry of the NAND Flash controller frees the CPU for other tasks. WLAN,

Bluetooth and expansion options are provided through PCMCIA/CF, USB, and MMC/SD host controllers.

The device is packaged in a 289-pin MAPBGA.

System Control

Connectivity

®

CSPI x 2

SSI x 2

i.MX21S

JTAG/Multi-ICE

System Boot

ARM9 Platform

2

I C

Clock Management

MAX

ARM926EJ-S

Audio Mux

UART 1, 3, & 4

1-Wire

MMU

I Cache

D Cache

Standard System I/O

Timers x 3

Bus Control

Memory Control

FIRI

Internal Control

USB OTG/ 1 Host

PWM

WDOG

RTC

Memory Expansion

Memory Interface

Human Interface

SDRAMC

WEIM

LCD Controller

SLCD Controller

Keypad

GPIO

DMAC

MMC/SD x 2

PCMCIA/CF

NFC

Figure 1. i.MX21S Functional Block Diagram

1.1

Conventions

This document uses the following conventions:

•

OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET.

Logic level one is a voltage that corresponds to Boolean true (1) state.

Logic level zero is a voltage that corresponds to Boolean false (0) state.

To set a bit or bits means to establish logic level one.

To clear a bit or bits means to establish logic level zero.

A signal is an electronic construct whose state conveys or changes in state convey information.

A pin is an external physical connection. The same pin can be used to connect a number of signals.

Asserted means that a discrete signal is in active logic state.

— Active low signals change from logic level one to logic level zero.

— Active high signals change from logic level zero to logic level one.

Negated means that an asserted discrete signal changes logic state.

— Active low signals change from logic level zero to logic level one.

— Active high signals change from logic level one to logic level zero.

•

MC9328MX21S Technical Data, Rev. 1.3

2

Freescale Semiconductor

Introduction

•

LSB means least significant bit or bits, and MSB means most significant bit or bits. References to low and

high bytes or words are spelled out.

Numbers preceded by a percent sign (%) are binary. Numbers preceded by a dollar sign ($) or 0x are

hexadecimal.

1.2

Reference Documentation

The following documents are required for a complete description of the i.MX21S and are necessary to

design properly with the device. Especially for those not familiar with the ARM926EJ-S processor the

following documents are helpful when used in conjunction with this manual.

ARM Architecture Reference Manual (ARM Ltd., order number ARM DDI 0100)

ARM7TDMI Data Sheet (ARM Ltd., order number ARM DDI 0029)

ARM920T Technical Reference Manual (ARM Ltd., order number ARM DDI 0151C)

MC9328MX21S Product Brief (order number MC9328MX21SPB)

The Freescale manuals are available on the Freescale Semiconductor Web site at http://

www.freescale.com. These documents may be downloaded directly from the Freescale Web site, or printed

versions may be ordered. The ARM Ltd. documentation is available from http://www.arm.com.

1.3

Ordering Information

Table 1 provides ordering information for the device.

Table 1. Ordering Information

Part Order Number

Package Size

Package Type

Operating Range

MC9328MX21SVK

289-lead MAPBGA

0.65mm, 14mm x 14mm

Lead-free

⁰°C–70°C

MC9328MX21SCVK

MC9328MX21SVM

MC9328MX21SCVM

289-lead MAPBGA

0.65mm, 14mm x 14mm

Lead-free

^-40°C–85°C

⁰°C–70°C

289-lead MAPBGA

0.8mm, 17mm x 17mm

289-lead MAPBGA

0.8mm, 17mm x 17mm

^-40°C–85°C

1.4

Features

The i.MX21S boasts a robust array of features that can support a wide variety of applications. Below is a

brief description of i.MX21S features.

•

ARM926EJ-S Core Complex

Display and Video Modules

— LCD Controller (LCDC)

— Smart LCD Controller (SLCDC)

Wireless Connectivity

•

— Fast Infra-Red Interface (FIRI)

Wired Connectivity

— USB On-The-Go (USBOTG) Controller

MC9328MX21S Technical Data, Rev. 1.3

Freescale Semiconductor

3

Signal Descriptions

— Three Universal Asynchronous Receiver/Transmitters (UARTx)

— Two Configurable Serial Peripheral Interfaces (CSPIx) for High Speed Data Transfer

2

— Inter-IC (I C) Bus Module

— Two Synchronous Serial Interfaces (SSI) with Inter-IC Sound (I S)

2

— Digital Audio Mux

— One-Wire Controller

— Keypad Interface

•

Memory Expansion and I/O Card Support

— Two Multimedia Card and Secure Digital (MMC/SD) Host Controller Modules

Memory Interface

— External Interface Module (EIM)

— SDRAM Controller (SDRAMC)

— NAND Flash Controller (NFC)

— PCMCIA/CF Interface

•

Standard System Resources

— Clock Generation Module (CGM) and Power Control Module

— Three General-Purpose 32-Bit Counters/Timers

— Watchdog Timer

— Real-Time Clock/Sampling Timer (RTC)

— Pulse-Width Modulator (PWM) Module

— Direct Memory Access Controller (DMAC)

— General-Purpose I/O (GPIO) Ports

— Debug Capability

2 Signal Descriptions

Table 2 identifies and describes the i.MX21S signals. Pin assignment is provided in Section 4, “Pin

Assignment and Package Information” and in the “Signal Multiplexing Scheme” table within the reference

manual.

The connections of the pins in Table 2 depends solely upon the user application, however there are a few

factory test signals that are not used in a normal application. Following is a list of these signals and how

they are to be terminated for proper operation of the i.MX21S processor:

•

CLKMODE[1:0]: To ensure proper operation, leave these signals as no connects.

OSC26M_TEST: To ensure proper operation, leave this signal as no connect.

EXT_48M: To ensure proper operation, connect this signal to ground.

EXT_266M: To ensure proper operation, connect this signal to ground.

TEST_WB[2:0]: These signals are also multiplexed with GPIO PORT E as well as alternate

keypad signals. If not utilizing these signals for GPIO functionality or for their other multiplexed

function, then configure as GPIO input with pull up enabled, and leave as a no connect.

•

TEST_WB[4:3]: To ensure proper operation, leave these signals as no connects.

MC9328MX21S Technical Data, Rev. 1.3

4

Freescale Semiconductor

Signal Descriptions

Table 2. i.MX21S Signal Descriptions

Signal Name

Function/Notes

External Bus/Chip Select (EIM)

A [25:0]

D [31:0]

EB0

Address bus signals

Data bus signals

MSB Byte Strobe—Active low external enable byte signal that controls D [31:24], shared with SDRAM

DQM0.

EB1

EB2

Byte Strobe—Active low external enable byte signal that controls D [23:16], shared with SDRAM DQM1.

Byte Strobe—Active low external enable byte signal that controls D [15:8], shared with SDRAM DQM2

and PCMCIA PC_REG.

EB3

LSB Byte Strobe—Active low external enable byte signal that controls D [7:0], shared with SDRAM

DQM3 and PCMCIA PC_IORD.

OE

Memory Output Enable—Active low output enables external data bus, shared with PCMCIA PC_IOWR.

CS [5:0]

Chip Select—The chip select signals CS [3:2] are multiplexed with CSD [1:0] and are selected by the

Function Multiplexing Control Register (FMCR) in the System Control chapter. By default CSD [1:0] is

selected. DTACK is multiplexed with CS4.

ECB

LBA

Active low input signal sent by flash device to the EIM whenever the flash device must terminate an on-

going burst sequence and initiate a new (long first access) burst sequence.

Active low signal sent by flash device causing the external burst device to latch the starting burst

address.

BCLK

RW

Clock signal sent to external synchronous memories (such as burst flash) during burst mode.

RW signal—Indicates whether external access is a read (high) or write (low) cycle. This signal is also

shared with the PCMCIA PC_WE.

DTACK

DTACK signal—External input data acknowledge signal, multiplexed with CS4.

Bootstrap

BOOT [3:0]

System Boot Mode Select—The operational system boot mode upon system reset is determined by the

settings of these pins. To hardwire these inputs low, terminate with a 1 KΩ resister to ground. For a logic

high, terminate with a 1 KΩ resistor to VDDA. Do not change the state of these inputs after power-up.

Boot 3 should always be tied to logic low.

SDRAM Controller

SDBA [4:0]

SDIBA [3:0]

SDRAM non-interleave mode bank address signals. These signals are multiplexed with address signals

A[20:16].

SDRAM interleave addressing mode bank address signals. These signals are multiplexed with address

signals A[24:21].

MA [11:0]

DQM [3:0]

SDRAM address signals. MA[9:0] are multiplexed with address signals A[10:1].

SDRAM data qualifier mask multiplexed with EB[3:0]. DQM3 corresponds to D[31:24], DQM2

corresponds to D[23:16], DQM1 corresponds to D[15:8], and DQM0 corresponds to D[7:0].

CSD0

CSD1

RAS

SDRAM Chip Select signal. This signal is multiplexed with the CS2 signal. This signal is selectable by

programming the Function Multiplexing Control Register in the System Control chapter.

SDRAM Chip Select signal. This signal is multiplexed with the CS3 signal. This signal is selectable by

programming the Function Multiplexing Control Register in the System Control chapter.

SDRAM Row Address Select signal.

MC9328MX21S Technical Data, Rev. 1.3

Freescale Semiconductor

5

Signal Descriptions

Signal Name

Table 2. i.MX21S Signal Descriptions (Continued)

Function/Notes

CAS

SDRAM Column Address Select signal

SDWE

SDRAM Write Enable signal

SDRAM Clock Enable 0

SDRAM Clock Enable 1

SDRAM Clock

SDCKE0

SDCKE1

SDCLK

Clocks and Resets

EXTAL26M

Crystal input (26MHz), or a 16 MHz to 32 MHz oscillator (or square-wave) input when the internal

oscillator circuit is shut down. When using an external signal source, feed this input with a square wave

signal switching from GND to VDDA.

XTAL26M

Oscillator output to external crystal. When using an external signal source, float this output.

EXTAL32K

32 kHz or 32.768 kHz crystal input. When using an external signal source, feed this input with a square

wave signal switching from GND to QVDD5.

XTAL32K

CLKO

Oscillator output to external crystal. When using an external signal source, float this output.

Clock Out signal selected from internal clock signals. Please refer to clock controller for internal clock

selection.

EXT_48M

EXT_266M

RESET_IN

This is a special factory test signal. To ensure proper operation, connect this signal to ground.

Master Reset—External active low Schmitt trigger input signal. When this signal goes active, all modules

(except the reset module, SDRAMC module, and the clock control module) are reset.

RESET_OUT

POR

Reset Out—Internal active low output signal from the Watchdog Timer module and is asserted from the

following sources: Power-on reset, External reset (RESET_IN), and Watchdog time-out.

Power On Reset—Active low Schmitt trigger input signal. The POR signal is normally generated by an

external RC circuit designed to detect a power-up event.

CLKMODE[1:0]

OSC26M_TEST

TEST_WB[2:0]

These are special factory test signals. To ensure proper operation, leave these signals as no connects.

This is a special factory test signal. To ensure proper operation, leave this signal as a no connect.

These are special factory test signals. However, these signals are also multiplexed with GPIO PORT E

as well as alternate keypad signals. If not using these signals for GPIO functions or for other multiplexed

functions, then configure as GPIO input with pull-up enabled, and leave as a no connect.

TEST_WB[4:3]

WKGD

These are special factory test signals. To ensure proper operation, leave these signals as no connects.

Battery indicator input used to qualify the walk-up process. Also multiplexed with TIN.

JTAG

®

For termination recommendations, see the Table “JTAG pinouts” in the Multi-ICE User Guide from ARM Limited.

TRST

TDO

TDI

Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller.

Serial Output for test instructions and data. Changes on the falling edge of TCK.

Serial Input for test instructions and data. Sampled on the rising edge of TCK.

Test Clock to synchronize test logic and control register access through the JTAG port.

TCK

TMS

Test Mode Select to sequence the JTAG test controller’s state machine. Sampled on the rising edge of

TCK.

JTAG_CTRL

JTAG Controller select signal—JTAG_CTRL is sampled during the rising edge of TRST. Must be pulled

to logic high for proper JTAG interface to debugger. Pulling JTAG_CRTL low is for internal test purposes

only.

MC9328MX21S Technical Data, Rev. 1.3

6

Freescale Semiconductor

Signal Descriptions

Table 2. i.MX21S Signal Descriptions (Continued)

Function/Notes

Signal Name

RTCK

JTAG Return Clock used to enhance stability of JTAG debug interface devices. This signal is multiplexed

with 1-Wire, therefore using 1-Wire renders RTCK unusable and vice versa.

LCD Controller

LD [17:0]

LCD Data Bus—All LCD signals are driven low after reset and when LCD is off. LD[15:0] signals are

multiplexed with SLCDC1_DAT[15:0] from SLCDC1. LD[16] is multiplexed with EXT_DMAGRANT.

FLM_VSYNC

(or simply referred

to as VSYNC)

Frame Sync or Vsync—This signal also serves as the clock signal output for gate

driver (dedicated signal SPS for Sharp panel HR-TFT).

LP_HSYNC (or simply Line Pulse or HSync

referred to as HSYNC)

LSCLK

OE_ACD

CONTRAST

SPL_SPR

PS

Shift Clock.

Alternate Crystal Direction/Output Enable.

This signal is used to control the LCD bias voltage as contrast control.

Sampling start signal for left and right scanning. This signal is multiplexed with the SLCDC1_CLK.

Control signal output for source driver (Sharp panel dedicated signal). This signal is multiplexed with the

SLCDC1_CS.

CLS

REV

Start signal output for gate driver. This signal is invert version of PS (Sharp panel dedicated signal). This

signal is multiplexed with the SLCDC1_RS.

Signal for common electrode driving signal preparation (Sharp panel dedicated signal). This signal is

multiplexed with SLCDC1_D0.

Smart LCD Controller

SLCDC1_CLK

SLCDC1_CS

SLCDC1_RS

SLCDC1_D0

SLCDC Clock output signal. This signal is multiplexed and available at 2 alternate locations. These are

SPL_SPR and SD2_CLK signals of LCDC and SD2, respectively.

SLCDC Chip Select output signal. This signal is multiplexed and available at 2 alternate signal locations.

These are PS and SD2_CMD signals of LCDC and SD2, respectively.

SLCDC Register Select output signal. This signal is multiplexed and available at 2 alternate signal

locations. These are CLS and SD2_D3 signals of LCDC and SD2, respectively.

SLCDC serial data output signal. This signal is multiplexed and available at 2 alternate signal locations.

These are and REV and SD2_D2 signals of LCDC and SD2, respectively. This signal is inactive when a

parallel data interface is used.

SLCDC1_DAT[15:0] SLCDC Data output signals for connection to a parallel SLCD panel interface. These signals are

multiplexed with LD[15:0] while an alternate 8-bit SLCD muxing is available on LD[15:8]. Further

alternate muxing of these signals are available on some of the USB OTG and USBH1 signals.

SLCDC2_CLK

SLCDC2_CS

SLCDC2_RS

SLCDC2_D0

SLCDC Clock input signal for pass through to SLCD device. This signal is multiplexed with SSI3_CLK

signal from SSI3.

SLCDC Chip Select input signal for pass through to SLCD device. This signal is multiplexed with

SSI3_TXD signal from SSI3.

SLCDC Register Select input signal for pass through to SLCD device. This signal is multiplexed with

SSI3_RXD signal from SSI3.

SLCD Data input signal for pass through to SLCD device. This signal is multiplexed with SSI3_FS signal

from SSI3.

MC9328MX21S Technical Data, Rev. 1.3

Freescale Semiconductor

7

Signal Descriptions

Table 2. i.MX21S Signal Descriptions (Continued)

Function/Notes

Signal Name

External DMA

EXT_DMAREQ

External DMA Request input signal. This signal is multiplexed with CSPI1_RDY.

EXT_DMAGRANT External DMA Grant output signal. This signal is multiplexed with LD[16] of LCDC and CSPI1_SS1 of

CSPI1.

NAND Flash Controller

NF_CLE

NF_CE

NAND Flash Command Latch Enable output signal. Multiplexed with PC_POE of PCMCIA.

NAND Flash Chip Enable output signal. This signal is multiplexed with PC_CE1 of PCMCIA.

NAND Flash Write Protect output signal. This signal is multiplexed with PC_CE2 of PCMCIA.

NAND Flash Address Latch Enable output signal. This signal is multiplexed with PC_OE of PCMCIA.

NAND Flash Read Enable output signal. This signal is multiplexed with PC_RW of PCMCIA.

NAND Flash Write Enable output signal. This signal is multiplexed with and PC_BVD2 of PCMCIA.

NAND Flash Ready Busy input signal. This signal is multiplexed with PC_RST of PCMCIA.

NF_WP

NF_ALE

NF_RE

NF_WE

NF_RB

NF_IO[15:0]

NAND Flash Data input and output signals. NF_IO[15:7] signals are multiplexed with A[25:21] and

A[15:13]. NF_IO[7:0] signals are multiplexed with several PCMCIA signals.

PCMCIA Controller

PC_A[25:0]

PC_D[15:0]

PC_CD1

PCMCIA Address signals. These signals are multiplexed with A[25:0].

PCMCIA Data input and output signals. These signals are multiplexed with D[15:0].

PCMCIA Card Detect1 input signal. This signal is multiplexed with NFIO[7] signal of NF.

PCMCIA Card Detect2 input signal. This signal is multiplexed with NFIO[6] signal of NF.

PCMCIA Wait input signal to extend current access. This signal is multiplexed with NFIO[5] signal of NF.

PCMCIA Ready input signal indicates card is ready for access. Multiplexed with NFIO[4] signal of NF.

PCMCIA Reset output signal. This signal is multiplexed with NFRB signal of NF.

PC_CD2

PC_WAIT

PC_READY

PC_RST

PC_OE

PCMCIA Memory Read Enable output signal asserted during common or attribute memory read cycles.

This signal is multiplexed with NFALE signal of NF.

PC_WE

PCMCIA Memory Write Enable output signal asserted during common or attribute memory cycles. This

signal is shared with RW of the EIM.

PC_VS1

PC_VS2

PCMCIA Voltage Sense1 input signal. This signal is multiplexed with NFIO[2] signal of NF.

PCMCIA Voltage Sense2 input signal. This signal is multiplexed with NFIO[1] signal of NF.

PCMCIA Battery Voltage Detect1 input signal. This signal is multiplexed with NFIO[0] signal of NF.

PCMCIA Battery Voltage Detect2 input signal. This signal is multiplexed with NF_WE signal of NF.

PCMCIA Speaker Out output signal. This signal is multiplexed with PWMO signal.

PCMCIA Register Select output signal. This signal is shared with EB2 of EIM.

PC_BVD1

PC_BVD2

PC_SPKOUT

PC_REG

PC_CE1

PCMCIA Card Enable1 output signal. This signal is multiplexed with NFCE signal of NF.

PCMCIA Card Enable2 output signal. This signal is multiplexed with NFWP signal of NF.

PCMCIA IO Read output signal. This signal is shared with EB3 of EIM.

PC_CE2

PC_IORD

PC_IOWR

PC_WP

PCMCIA IO Write output signal. This signal is shared with OE signal of EIM.

PCMCIA Write Protect input signal. This signal is multiplexed with NFIO[3] signal of NF.

MC9328MX21S Technical Data, Rev. 1.3

8

Freescale Semiconductor

Signal Descriptions

Table 2. i.MX21S Signal Descriptions (Continued)

Function/Notes

Signal Name

PC_POE

PCMCIA Output Enable signal to enable voltage translation buffers and transceivers. This signal is

multiplexed with NFCLE signal of NF.

PC_RW

PCMCIA Read Write output signal to control external transceiver direction. Asserted high for read

access and negated low for write access. This signal is multiplexed with NFRE signal of NF.

PC_PWRON

PCMCIA input signal to indicate that the card power has been applied and stabilized.

CSPI

CSPI1_MOSI

CSPI1_MISO

CSPI1_SS[2:0]

Master Out/Slave In signal

Master In/Slave Out signal

Slave Select (Selectable polarity) signal. CSPI1_SS2 is also multiplexed with USBG_RXDAT and

CSPI1_SS1 is multiplexed with EXT_DMAGRANT.

CSPI1_SCLK

CSPI1_RDY

Serial Clock signal

Serial Data Ready signal. Also multiplexed with EXT_DMAREQ.

Master Out/Slave In signal. This signal is multiplexed with USBH2_TXDP signal of USB OTG.

Master In/Slave Out signal. This signal is multiplexed with USBH2_TXDM signal of USB OTG.

CSPI2_MOSI

CSPI2_MISO

CSPI2_SS[2:0]

Slave Select (Selectable polarity) signals. These signals are multiplexed with USBH2_FS,

USBH2_RXDP and USBH2_RXDM signal of USB OTG

CSPI2_SCLK

TIN

Serial Clock signal. This signal is multiplexed with USBH2_OE signal of USB OTG

General Purpose Timers

Timer Input Capture or Timer Input Clock—The signal on this input is applied to all 3 timers

simultaneously. This signal is muxed with the Walk-up Guard Mode WKGD signal in the PLL, Clock, and

Reset Controller module.

TOUT1

(or simply TOUT)

Timer Output signal from General Purpose Timer1 (GPT1). This signal is multiplexed with SYS_CLK1

and SYS_CLK2 signal of SSI1 and SSI2. The pin name of this signal is simply TOUT.

TOUT2

TOUT3

Timer Output signal from General Purpose Timer1 (GPT2). This signal is multiplexed with PWMO.

Timer Output signal from General Purpose Timer1 (GPT3). This signal is multiplexed with PWMO.

USB On-The-Go

USB_BYP

USB_PWR

USB Bypass input active low signal. This signal can only be used for USB function, not for GPIO.

USB Power output signal

USB_OC

USB Over current input signal. This signal can only be used for USB function, not for GPIO.

USB OTG Receive Data Plus input signal. This signal is muxed with SLCDC1_DAT15.

USB OTG Receive Data Minus input signal. This signal is muxed with SLCDC1_DAT14.

USB OTG Transmit Data Plus output signal. This signal is muxed with SLCDC1_DAT13.

USB OTG Transmit Data Minus output signal. This signal is muxed with SLCDC1_DAT12.

USB OTG Transceiver differential data receive signal. Multiplexed with CSPI1_SS2.

USB OTG Output Enable signal. This signal is muxed with SLCDC1_DAT11.

USB OTG Transceiver ON output signal. This signal is muxed with SLCDC1_DAT9.

USBG_RXDP

USBG_RXDM

USBG_TXDP

USBG_TXDM

USBG_RXDAT

USBG_OE

USBG_ON

USBG_FS

USB OTG Full Speed output signal. This signal is multiplexed with external transceiver USBG_TXR_INT

signal of USB OTG. This signal is muxed with SLCDC1_DAT10.

MC9328MX21S Technical Data, Rev. 1.3

Freescale Semiconductor

9

Signal Descriptions

Table 2. i.MX21S Signal Descriptions (Continued)

Function/Notes

Signal Name

USBH1_RXDP

USB Host1 Receive Data Plus input signal. This signal is multiplexed with UART4_RXD and

SLCDC1_DAT6. It also provides an alternative multiplex for UART4_RTS, where this signal is selectable

by programming the Function Multiplexing Control Register in the System Control chapter.

USBH1_RXDM

USBH1_TXDP

USB Host1 Receive Data Minus input signal. This signal is muxed with SLCDC1_DAT5. It also provides

an alternative multiplex for UART4_CTS.

USB Host1 Transmit Data Plus output signal. This signal is multiplexed with UART4_CTS and

SLCDC1_DAT4. It also provides an alternative multiplex for UART4_RXD, where this signal is selectable

by programming the Function Multiplexing Control Register in the System Control chapter.

USBH1_TXDM

USBH1_RXDAT

USBH1_OE

USB Host1 Transmit Data Minus output signal. Multiplexed with UART4_TXD and SLCDC1_DAT3.

USB Host1 Transceiver differential data receive signal. Multiplexed with USBH1_FS.

USB Host1 Output Enable signal. This signal is muxed with SLCDC1_DAT2.

USBH1_FS

USB Host1 Full Speed output signal. Multiplexed with UART4_RTS and SLCDC1_DAT1 and

USBH1_RXDAT.

USBH_ON

USBG_SCL

USB Host transceiver ON output signal. This signal is muxed with SLCDC1_DAT0.

2

USB OTG I C Clock input/output signal. This signal is multiplexed with SLCDC1_DAT8.

2

USBG_SDA

USB OTG I C Data input/output signal. This signal is multiplexed with SLCDC1_DAT7.

USBG_TXR_INT

USB OTG transceiver interrupt input. Multiplexed with USBG_FS.

Secure Digital Interface

SD1_CMD

SD Command bidirectional signal—If the system designer does not want to make use of the internal pull-

up, via the Pull-up enable register, a 4.7k–69k external pull-up resistor must be added.

SD1_CLK

SD Output Clock.

SD1_D[3:0]

SD Data bidirectional signals—If the system designer does not want to make use of the internal pull-up,

via the Pull-up enable register, a 50k–69k external pull-up resistor must be added.

SD2_CMD

SD2_CLK

SD2_D[3:0]

SD Command bidirectional signal. This signal is multiplexed with SLCDC1_CS signal from SLCDC1.

SD Output Clock signal. This signal is multiplexed with SLCDC1_CLK signal from SLCDC1.

SD Data bidirectional signals. SD2_D[3:2] are multiplexed with SLCDC1_RS and SLCDC_D0 signals

from SLCDC1.

UARTs – IrDA/Auto-Bauding

(Note: UART2 is not used in the MC9328MX21S)

UART1_RXD

UART1_TXD

UART1_RTS

UART1_CTS

UART3_RXD

UART3_TXD

UART3_RTS

UART3_CTS

UART4_RXD

UART4_TXD

UART4_RTS

Receive Data input signal

Transmit Data output signal

Request to Send input signal

Clear to Send output signal

Receive Data input signal. This signal is multiplexed with IR_RXD from FIRI.

Transmit Data output signal. This signal is multiplexed with IR_TXD from FIRI.

Request to Send input signal

Clear to Send output signal

Receive Data input signal which is multiplexed with USBH1_RXDP and USBH1_TXDP.

Transmit Data output signal which is multiplexed with USBH1_TXDM.

Request to Send input signal which is multiplexed with USBH1_FS and USBH1_RXDP.

MC9328MX21S Technical Data, Rev. 1.3

10

Freescale Semiconductor

Signal Descriptions

Table 2. i.MX21S Signal Descriptions (Continued)

Function/Notes

Signal Name

UART4_CTS

Clear to Send output signal which is multiplexed with USBH1_TXDP and USBH1_RXDM.

2

Serial Audio Port – SSI (configurable to I S protocol and AC97)

SSI1_CLK

SSI1_TXD

SSI1_RXD

SSI1_FS

Serial clock signal which is output in master or input in slave

Transmit serial data

Receive serial data

Frame Sync signal which is output in master and input in slave

SSI1 master clock. Multiplexed with TOUT.

SYS_CLK1

SSI2_CLK

SSI2_TXD

SSI2_RXD

SSI2_FS

Serial clock signal which is output in master or input in slave.

Transmit serial data signal

Receive serial data

Frame Sync signal which is output in master and input in slave.

SSI2 master clock. Multiplexed with TOUT.

SYS_CLK2

SSI3_CLK

SSI3_TXD

SSI3_RXD

SSI3_FS

Serial clock signal which is output in master or input in slave. Multiplexed with SLCDC2_CLK

Transmit serial data signal which is multiplexed with SLCDC2_CS

Receive serial data which is multiplexed with SLCDC2_RS

Frame Sync signal which is output in master and input in slave. Multiplexed with SLCDC2_D0.

Serial clock signal which is output in master or input in slave.

Transmit serial data

SAP_CLK

SAP_TXD

SAP_RXD

SAP_FS

Receive serial data

Frame Sync signal which is output in master and input in slave.

2

I C

2

I2C_CLK

I C Clock

2

I2C_DATA

I C Data

1-Wire

OWIRE

PWMO

1-Wire input and output signal. This signal is multiplexed with JTAG RTCK.

PWM

PWM Output. This signal is multiplexed with PC_SPKOUT of PCMCIA, as well as TOUT2 and TOUT3

of the General Purpose Timer module.

General Purpose Input/Output

PB[10:21], PF[16]

KP_COL[7:0]

Dedicated GPIO. When unused, program this signal as an input with the on-chip pull-up resistor enabled.

Keypad

Keypad Column selection signals. KP_COL[7:6] are multiplexed with UART2_CTS and UART2_TXD

respectively. Alternatively, KP_COL6 is also available on the internal factory test signal TEST_WB2. The

Function Multiplexing Control Register in the System Control chapter must be used in conjunction with

programming the GPIO multiplexing (to select the alternate signal multiplexing) to choose which signal

KP_COL6 is available.

MC9328MX21S Technical Data, Rev. 1.3

Freescale Semiconductor

11

Specifications

Table 2. i.MX21S Signal Descriptions (Continued)

Function/Notes

Signal Name

KP_ROW[7:0]

Keypad Row selection signals. KP_ROW[7:6] are multiplexed with UART2_RTS and UART2_RXD

signals respectively. Alternatively, KP_ROW7 and KP_ROW6 are available on the internal factory test

signals TEST_WB0 and TEST_WB1 respectively. The Function Multiplexing Control Register in the

System Control chapter must be used in conjunction with programming the GPIO multiplexing (to select

the alternate signal multiplexing) to choose which signals KP_ROW6 and KP_ROW7 are available.

Noisy Supply Pins

NVDD

NVSS

Noisy Supply for the I/O pins. There are six (6) I/O voltages, NVDD1 through NVDD6.

Noisy Ground for the I/O pins

Supply Pins – Analog Modules

VDDA

Supply for analog blocks

QVSS (internally

Quiet GND for analog blocks (QVSS and AVSS are synonymous)

connected to AVSS)

Internal Power Supplies

QVDD

QVSS

Power supply pins for silicon internal circuitry

Quiet GND pins for silicon internal circuitry

QVDDX

Power supply pin for the ARM core. Externally connect directly to QVDD

3 Specifications

This section contains the electrical specifications and timing diagrams for the i.MX21S processor.

3.1

Maximum Ratings

Table 3 provides the maximum ratings.

CAUTION

Stresses beyond those listed under “Maximum Ratings,” (Table 3) may cause

permanent damage to the device. These are stress ratings only. Functional operation

of the device at these or any other conditions beyond those indicated under

“266 MHz Recommended Operating Range” (Table 4) is not implied. Exposure to

maximum-rated conditions for extended periods may affect device reliability.

Table 3. Maximum Ratings

Ref. Num

Parameter

Symbol

QVDDX

Min

Max

Units

1

Supply Voltage

QVDD

-0.3

-55

2.1

3.3

V

max,

max

NVDD

VDDA

max

max,

1

2

3

Input Voltage Range

V

VDD + 0.3

150

Imax

o

Storage Temperature Range

T

C

storage

1. VDD is the supply voltage associated with the input. See Signal Multiplexing Scheme table in the reference manual.

MC9328MX21S Technical Data, Rev. 1.3

12

Freescale Semiconductor

Specifications

3.2

Recommended Operating Range

Table 4 provides the recommended operating ranges. The device has multiple pairs of VDD and VSS

power supply and return pins. QVDD, QVDDx, and QVSS pins are used for internal logic. All other VDD

and VSS pins are for the I/O pads voltage supply, and each pair of VDD and VSS provides power to the

enclosed I/O pads. This design allows different peripheral supply voltage levels in a system.

Because VDDA pins are supply voltages to the analog pads, it is recommended to isolate and noise-filter

the VDDA pins from other VDD pins.

For more information about I/O pads grouping per VDD, please refer to Table 4.

Table 4. 266 MHz Recommended Operating Range

Rating

Symbol

Minimum

Maximum

Unit

Operating temperature range

Part No. Suffix

VK/VM

T

0

70

85

°C

V

A

CVK/CVM

T

- 40

1.70

1.45

1.70

A

I/O supply voltage NVDD 1–6

NVDD

3.30

1.65

3.30

x

Internal supply voltage (Core = 266 MHz)

Analog supply voltage

QVDD, QVDDx

VDDA

V

3.3

DC Electrical Characteristics

Table 5 contains the DC characteristics of the i.MX21S.

Table 5. DC Characteristics

1

Parameter

Symbol

Test Conditions

Min

Typ

Max

Units

High-level input voltage

V

–

0.7NVDD

–

NVDD

IH

Low-level Input voltage

V

O

0.8NVDD

–

0.3NVDD

IL

High-level output voltage

Low-level output voltage

High-level output current, slow I/O

V

I

= spec’ed Drive

–

0.2NVDD

–

V

OH

V

I

OL

I

V

=0.8NVDD

mA

OH_S

out

2

DSCR = 000

DSCR = 001

DSCR = 011

DSCR = 111

-2

-4

-8

-12

High-level output current, fast I/O

Low-level output current, slow I/O

I

V

=0.8NVDD1

–

mA

OH_F

out

2

DSCR = 000

DSCR = 001

DSCR = 011

DSCR = 111

-3.5

-4.5

-5.5

-6.5

I

V

=0.2NVDD

OL_S

out

2

DSCR = 000

DSCR = 001

DSCR = 011

DSCR = 111

2

4

8

12

MC9328MX21S Technical Data, Rev. 1.3

Freescale Semiconductor

13

Specifications

Table 5. DC Characteristics (Continued)

1

Parameter

Symbol

Test Conditions

=0.2NVDD1

DSCR = 000

DSCR = 001

DSCR = 011

DSCR = 111

Min

Typ

Max

Units

Low-level output current, fast I/O

I

V

–

mA

OL_F

out

2

3.5

4.5

5.5

6.5

Schmitt trigger Positive–input threshold

Schmitt trigger Negative–input threshold

Hysteresis

V +

–

0.75

–

2.15

V

T

V -

–

1

T

V

–

0.3

–

V

HYS

Input leakage current (no pull-up or pull-

down)

I

V

= 0 or NVDD

= NVDD or 0

–

μA

in

I/O leakage current

I

V

–

5

μA

OZ

I/O

I/O = High impedance

state

1. Data labeled Typical is not guaranteed, but is intended as an indication of the IC's potential performance.

2. For DSCR definition refer to the System Control chapter in the reference manual.

Table 6 shows the input and output capacitance for the device.

Table 6. Input/Output Capacitance

Parameter

Input capacitance

Output capacitance

Symbol

Min

Typ

Max

5

Units

pF

C

i

–

5

pF

o

Table 7 shows the power consumption for the device.

Table 7. Power Consumption

ID Parameter

Conditions

Symbol

Typ Max Units

1

Run Current QVDD = QVDDX = 1.65 V, NVDD1 = 1.8 V.

NVDD2 through NVDD6 = VDDA = 3.1V.

Core = 266 MHz, System = 133 MHz.

MPEG4 Playback (QVGA) from MMC/SD card, 30fps,

44.1kHz audio.

I

+ I

120

8

–

mA

QVDD

QVDDX

I

NVDD1

I

through I

+ I

6.6

NVDD2

NVDD6

VDDA

2

Sleep Current Standby current with Well Biasing System enabled.

I

STBY

1

Well Bias Control Register (WBCR) must be set as

follows:

WBCR:

CRM_WBS bits = 01

CRM_WBFA bit = 1

CRM_WBM bits = 001

CRM_SPA_SEL bit = 1

FMCR bit = 1

QVDD = QVDDX = 1.65V, TA

–

3.0

700

–

mA

μA

^{QVDD = QVDDX = 1.65V, 25}°

^{QVDD = QVDDX = 1.55V, 25}° 320

For WBCR definition refer to System Control Chapter

in the reference manual.

1. TA = 70°C for suffixes VK, VM, DVK, DVM, and SVK. TA = 85°C for suffixes CVK, CVM, and SCVK.

MC9328MX21S Technical Data, Rev. 1.3

14

Freescale Semiconductor

Specifications

3.4

AC Electrical Characteristics

The AC characteristics consist of output delays, input setup and hold times, and signal skew times. All

signals are specified relative to an appropriate edge of other signals. All timing specifications are specified

at a system operating frequency (HCLK) from 0 MHz to 133 MHz (core operating frequency 266 MHz)

with an operating supply voltage from V

All timing is measured at 30 pF loading with the exception of fast I/O signals as discussed below. Refer

to the reference manual’s System Control Chapter for details on drive strength settings.

to V

under an operating temperature from T to T .

L H

DD max

DD min

Table 8 provides the maximum loading guidelines that can be tolerated on a memory I/O signal (also

known as Fast I/O) to achieve 133 MHz operation. These critical signals include the SDRAM Clock

(SDCLK), Data Bus signals (D[31:0]), lower order address signals such as A0-A10, MA10, MA11, and

other signals required to meet 133 MHz timing.

The values shown in Table 8 apply over the recommended operating temperature range. Care must be

taken to minimize parasitic capacitance of associated printed circuit board traces.

Table 8. Loading Guidelines for Fast IO Signals to Achieve 133 MHz Operation

Drive Strength Setting (DSCR2–DSCR12)

Maximum I/O Loading at 1.8 V

Maximum I/O Loading at 3.0 V

000: 3.5 mA

001: 4.5 mA

011: 5.5 mA

111: 6.5 mA

9 pF

12 pF

15 pF

19 pF

12 pF

16 pF

21 pF

26 pF

Table 9. 32k/26M Oscillator Signal Timing

Parameter

Minimum

RMS

Maximum

Unit

EXTAL32k input jitter (peak to peak) for both System PLL and MCUPLL

EXTAL32k input jitter (peak to peak) for MCUPLL only

EXTAL32k startup time

–

5

–

20

100

–

ns

800

ms

Table 10. CLKO Rise/Fall Time (at 30pF Loaded)

Best Case Typical Worst Case Units

Rise Time

Fall Time

0.80

0.74

1.00

1.08

1.40

1.67

ns

MC9328MX21S Technical Data, Rev. 1.3

Freescale Semiconductor

15

Specifications

3.5

DPLL Timing Specifications

Parameters of the DPLL are given in Table 11. In this table, T is a reference clock period after the

ref

predivider and T is the output double clock period.

dck

Table 11. DPLL Specifications

Parameter

Test Conditions

Minimum Typical Maximum

Unit

Reference clock frequency range

Vcc = 1.5V

16

–

320

32

MHz

Pre-divider output clock frequency Vcc = 1.5V

range

Double clock frequency range

Pre-divider factor (PD)

Total multiplication factor (MF)

MF integer part

Vcc = 1.5V

220

1

–

560

16

MHz

–

Includes both integer and fractional parts

5

–

15

–

5

–

15

MF numerator

Should be less than the denominator

–

0

–

1022

1023

450

MF denominator

1

–

Frequency lock-in time after

full reset

FOL mode for non-integer MF

(does not include pre-multi lock-in time)

350

400

T

ref

Frequency lock-in time after

partial reset

FOL mode for non-integer MF

(does not include pre-multi lock-in time)

220

480

360

280

530

410

330

580

460

T

ref

Phase lock-in time after

full reset

FPL mode and integer MF

(does not include pre-multi lock-in time)

T

ref

Phase lock-in time after

partial reset

FPL mode and integer MF

(does not include pre-multi lock-in time)

T

ref

Frequency jitter (p-p)

Phase jitter (p-p)

–

0.02

1.0

0.03

1.5

–

2•T

dck

Integer MF, FPL mode, Vcc=1.7V

FOL mode, integer MF,

ns

Power dissipation

1.5

mW

f

= 560 MHz, Vcc = 1.5V

(Avg)

dck

MC9328MX21S Technical Data, Rev. 1.3

16

Freescale Semiconductor

Specifications

3.6

Reset Module

The timing relationships of the Reset module with the POR and RESET_IN are shown in Figure 2 and

Figure 3. Be aware that NVDD must ramp up to at least 1.7V for NVDD1 and 2.7V for NVDD2-6 before

QVDD is powered up to prevent forward biasing.

1

POR

Can be adjusted depending on the crystal

start-up time 32kHz or 32.768kHz

2

RESET_POR

Exact 300ms

3

7 cycles @ CLK32

RESET_DRAM

4

14 cycles @ CLK32

HRESET

RESET_OUT

CLK32

HCLK

Figure 2. Timing Relationship with POR

5

RESET_IN

14 cycles @ CLK32

4

HRESET

RESET_OUT

6

CLK32

HCLK

Figure 3. Timing Relationship with RESET_IN

MC9328MX21S Technical Data, Rev. 1.3

Freescale Semiconductor

17

Specifications

Table 12. Reset Module Timing Parameters

1.8 V 0.10 V 3.0 V 0.30 V

Ref

No.

Parameter

Unit

Min

Max

Min

Max

1

2

Width of input POWER_ON_RESET

800

300

–

800

300

–

ms

Width of internal POWER_ON_RESET

(CLK32 at 32 kHz)

300

3

4

7k to 32k-cycle stretcher for SDRAM reset

7

Cycles of CLK32

14k to 32k-cycle stretcher for internal system reset HRESERT

and output reset at pin RESET_OUT

14

5

6

Width of external hard-reset RESET_IN

4k to 32k-cycle qualifier

4

–

4

–

4

Cycles of CLK32

3.7

External DMA Request and Grant

The External DMA request is an active low signal to be used by devices external to i.MX21 processor to

request the DMAC for data transfer.

After assertion of External DMA request the DMA burst will start when the channel on which the External

request is the source (as per the RSSR settings) becomes the current highest priority channel. The external

device using the External DMA request should keep its request asserted until it is serviced by the DMAC.

One External DMA request will initiate one DMA burst.

The output External Grant signal from the DMAC is an active-low signal.When the following conditions

are true, the External DMA Grant signal is asserted with the initiation of the DMA burst.

•

The DMA channel for which the DMA burst is ongoing has request source as external DMA Request

(as per source select register setting).

•

REN and CEN bit of this channel are set.

External DMA Request is asserted.

After the grant is asserted, the External DMA request will not be sampled until completion of the DMA

burst. As the external request is synchronized, the request synchronization will not be done during this

period. The priority of the external request becomes low for the next consecutive burst, if another DMA

request signal is asserted.

Worst case—that is, the smallest burst (1 byte read/write) timing diagrams are shown in Figure 4 and

Figure 5. Minimum and maximum timings for the External request and External grant signals are present

in Table 13.

Figure 4 shows the minimum time for which the External Grant signal remains asserted when an External

DMA request is de-asserted immediately after sensing grant signal active.

MC9328MX21S Technical Data, Rev. 1.3

18

Freescale Semiconductor

Specifications

Ext_DMAReq

Ext_DMAGrant

t_{min_assert}

Figure 4. Assertion of DMA External Grant Signal

Figure 5 shows the safe maximum time for which External DMA request can be kept asserted, after

sensing grant signal active such that a new burst is not initiated.

Ext_DMAReq

Ext_DMAGrant

t_{max_req_assert}

Data read from

External device

t_{max_read}

Data written to

External device

t_{max_write}

NOTE: Assuming in worst case the data is read/written from/to External device as per the above waveform.

Figure 5. Safe Maximum Timings for External Request De-Assertion

Table 13. DMA External Request and Grant Timing Parameters

3.0 V

1.8 V

Parameter

Description

Unit

WCS

BCS

WCS

BCS

t

Minimum assertion time of External Grant 8 hclk + 8.6 8 hclk + 2.74 8 hclk + 7.17 8 hclk + 3.25 ns

signal

min_assert

t

Maximum External request assertion time 9 hclk - 20.66 9 hclk - 6.7 9 hclk - 17.96 9 hclk - 8.16

after assertion of Grant signal

ns

max_req_assert

t

Maximum External request assertion time 8 hclk - 6.21 8 hclk - 0.77 8 hclk - 5.84 8 hclk - 0.66

after first read completion

max_read

t

Maximum External request assertion time 3 hclk - 15.87 3 hclk - 8.83 3 hclk - 15.9 3 hclk - 9.12

after completion of first write

max_write

3.8

CSPI Timing Diagrams

To use the internal transmit (TX) and receive (RX) data FIFOs when the CSPI1 module is configured as a

master, two control signals are used for data transfer rate control: the SS signal (output) and the SPI_RDY

signal (input). The SPI 1 Sample Period Control Register (PERIODREG1) and the SPI 2 Sample Period

Control Register (PERIODREG2) can also be programmed to a fixed data transfer rate for either CSPI1

or CSPI2. When the CSPI1 module is configured as a slave, the user can configure the SPI 1 Control

Register (CONTROLREG1) to match the external CSPI master’s timing. In this configuration, SS

MC9328MX21S Technical Data, Rev. 1.3

Freescale Semiconductor

19

Specifications

becomes an input signal, and is used to latch data into or load data out to the internal data shift registers,

as well as to increment the data FIFO.

2

5

3

SS

1

4

SPIRDY

SCLK, MOSI, MISO

Figure 6. Master CSPI Timing Diagram Using SPI_RDY Edge Trigger

SS

SPIRDY

SCLK, MOSI, MISO

Figure 7. Master CSPI Timing Diagram Using SPI_RDY Level Trigger

SS (output)

SCLK, MOSI, MISO

Figure 8. Master CSPI Timing Diagram Ignore SPI_RDY Level Trigger

SS (input)

SCLK, MOSI, MISO

Figure 9. Slave CSPI Timing Diagram FIFO Advanced by BIT COUNT

SS (input)

6

7

SCLK, MOSI, MISO

Figure 10. Slave CSPI Timing Diagram FIFO Advanced by SS Rising Edge

MC9328MX21S Technical Data, Rev. 1.3

20

Freescale Semiconductor

Specifications

Table 14. Timing Parameters for Figure 6 through Figure 10

Ref No.

Parameter

Minimum

Maximum

Unit

1

2

3

4

5

6

7

SPI_RDY to SS output low

SS output low to first SCLK edge

Last SCLK edge to SS output high

SS output high to SPI_RDY low

SS output pulse width

2T

–

ns

2

3·Tsclk

2·Tsclk

0

3

Tsclk + WAIT

SS input low to first SCLK edge

SS input pulse width

T

1. T = CSPI system clock period (PERCLK2).

2. Tsclk = Period of SCLK.

3. WAIT = Number of bit clocks (SCLK) or 32.768 kHz clocks per Sample Period Control

Register.

3.9

LCD Controller

This section includes timing diagrams for the LCD controller. For detailed timing diagrams of the LCD

controller with various display configurations, refer to the LCD controller chapter of the i.MX21S

Reference Manual.

T1

LSCLK

LD[17:0]

T2

T3

Figure 11. SCLK to LD Timing Diagram

Table 15. LCDC SCLK Timing Parameters

3.0 0.3V

Symbol

Parameter

Unit

Minimum

Maximum

T1

T2

T3

SCLK period

23

11

2000

ns

Pixel data setup time

Pixel data up time

–

The pixel clock is equal to LCDC_CLK / (PCD + 1).

When it is in CSTN, TFT or monochrome mode with bus width = 1, SCLK is equal to the pixel clock.

When it is in monochrome with other bus width settings, SCLK is equal to the pixel clock divided by bus width.

The polarity of SCLK and LD can also be programmed.

Maximum frequency of SCLK is HCLK / 3 for TFT and CSTN, otherwise LD output will be incorrect.

MC9328MX21S Technical Data, Rev. 1.3

Freescale Semiconductor

21

Specifications

Display region

Non-display region

T3

T1

T4

VSYN

T2

HSYN

OE

Line Y

Line 1

Line Y

LD[17:0]

T6

T5

XMAX

T7

HSYN

SCLK

OE

(0,1)

(0,2)

LD[15:0]

(0,X-1)

Figure 12. 4/8/12/16/18 Bit/Pixel TFT Color Mode Panel Timing

Table 16. 4/8/12/16/18 Bit/Pixel TFT Color Mode Panel Timing

Symbol

Description

Minimum

Value

Unit

T1

T2

T3

T4

T5

T6

T7

End of OE to beginning of VSYN

HSYN period

T5+T6+T7-1

(VWAIT1·T2)+T5+T6+T7-1

XMAX+T5+T6+T7

VWIDTH·T2

Ts

–

T2

1

VSYN pulse width

End of VSYN to beginning of OE

HSYN pulse width

(VWAIT2·T2)+1

HWIDTH+1

1

End of HSYN to beginning to OE

End of OE to beginning of HSYN

3

HWAIT2+3

1

HWAIT1+1

Note:

• Ts is the SCLK period.

• VSYN, HSYN and OE can be programmed as active high or active low. In Figure 12, all 3 signals are active low.

• SCLK can be programmed to be deactivated during the VSYN pulse or the OE deasserted period. In Figure 12, SCLK is

always active.

• XMAX is defined in number of pixels in one line.

MC9328MX21S Technical Data, Rev. 1.3

22

Freescale Semiconductor

Specifications

XMAX

SCLK

D1

LD

D2

D320

SPL_SPR

HSYN

T1

T3

T2

T4

CLS

PS

T5

T6

T7

REV

Figure 13. Sharp TFT Panel Timing

Table 17. Sharp TFT Panel Timing

Symbol

Description

Minimum

Value

Unit

T1

T2

T3

T4

T5

T6

T7

SPL/SPR pulse width

–

1

4

3

1

0

1

Ts

End of LD of line to beginning of HSYN

End of HSYN to beginning of LD of line

CLS rise delay from end of LD of line

CLS pulse width

HWAIT1+1

HWAIT2 + 4

CLS_RISE_DELAY+1

CLS_HI_WIDTH+1

PS rise delay from CLS negation

REV toggle delay from last LD of line

PS_RISE_DELAY

REV_TOGGLE_DELAY+1

Note:

•

Falling of SPL/SPR aligns with first LD of line.

Falling of PS aligns with rising edge of CLS.

REV toggles in every HSYN period.

MC9328MX21S Technical Data, Rev. 1.3

Freescale Semiconductor

23

Specifications

T1

VSYN

T3

T4

T2

XMAX

HSYN

SCLK

Ts

LD[15:0]

Figure 14. Non-TFT Mode Panel Timing

Table 18. Non-TFT Mode Panel Timing

Symbol

Description

Minimum

Value

Unit

T1

T2

T3

T4

HSYN to VSYN delay

HSYN pulse width

VSYN to SCLK

2

1

–

1

HWAIT2+2

HWIDTH+1

⁰≤ T3 ≤ Ts

HWAIT1+1

Tpix

–

SCLK to HSYN

Tpix

Note:

• Ts is the SCLK period while Tpix is the pixel clock period.

• VSYN, HSYN and SCLK can be programmed as active high or active low. In Figure 59, all these 3 signals are

active high.

• When it is in CSTN mode or monochrome mode with bus width = 1, T3 = Tpix = Ts.

• When it is in monochrome mode with bus width = 2, 4, and 8, T3 = 1, 2 and 4 Tpix respectively.

MC9328MX21S Technical Data, Rev. 1.3

24

Freescale Semiconductor

Specifications

3.10 Smart LCD Controller

T2

T3

T1

LCD_CS

LCD_CLK (LCD_DATA[6])

T4

T5

T7

LSB

SDATA (LCD_DATA[7])

RS

MSB

T6

RS=0 ≥ command data, RS=1≥ display data

SCKPOL = 1, CSPOL = 0

T2

T3

T1

LCD_CS

LCD_CLK (LCD_DATA[6])

T4

T5

T7

LSB

SDATA (LCD_DATA[7])

RS

MSB

T6

RS=0 ≥ command data, RS=1≥ display data

SCKPOL = 0, CSPOL = 0

T2

T3

LCD_CS

T1

LCD_CLK (LCD_DATA[6])

T4

T5

T7

LSB

SDATA (LCD_DATA[7])

RS

MSB

T6

RS=0 ≥ command data, RS=1≥ display data

SCKPOL = 1, CSPOL = 1

T2

T3

LCD_CS

T1

LCD_CLK (LCD_DATA[6])

T4

T5

T7

LSB

SDATA (LCD_DATA[7])

RS

MSB

T6

RS=0 ≥ command data, RS=1≥ display data

SCKPOL = 0, CSPOL = 1

Figure 15. SLCDC Serial Transfer Timing

MC9328MX21S Technical Data, Rev. 1.3

Freescale Semiconductor

25

Specifications

Table 19. SLCDC Serial Transfer Timing

Symbol

Description

Pixel clock period

Minimum

Maximum

Unit

T1

T2

T3

T4

T6

T7

42

5

962

–

ns

Chip select setup time

Chip select hold time

Data setup time

5

–

5

–

Data hold time

5

–

Register select setup time

Register select hold time

5

–

5

–

LCD_CLK

LCD_RS

LCD_CS

T4

T2

T5

T1

T3

command data

display data

LCD_DATA[15:0]

CSPOL = 0

LCD_CLK

T5

T4

LCD_RS

LCD_CS

T1

T2

T3

command data

display data

LCD_DATA[15:0]

CSPOL = 1

Figure 16. SLCDC Parallel Transfers Timing

Table 20. SLCDC Parallel Transfers Timing

Symbol

Description

Pixel clock period

Minimum

Maximum

Unit

T1

T2

T3

T4

T5

23

5

962

–

ns

Data setup time

Data hold time

5

–

Register select setup time

Register select hold time

5

–

5

–

MC9328MX21S Technical Data, Rev. 1.3

26

Freescale Semiconductor

Specifications

3.11 Multimedia Card/Secure Digital Host Controller

The DMA interface block controls all data routing between the external data bus (DMA access), internal

MMC/SD module data bus, and internal system FIFO access through a dedicated state machine that

monitors the status of FIFO content (empty or full), FIFO address, and byte/block counters for the MMC/

SD module (inner system) and the application (user programming).

3a

1

2

4b

3b

Bus Clock

4a

5b

5a

Valid Data

CMD_DAT Input

Valid Data

7

CMD_DAT Output

Valid Data

6b

6a

Figure 17. Chip-Select Read Cycle Timing Diagram

Table 21. SDHC Bus Timing Parameters

1.8 V 0.1 V

3.0 V 0.3 V

Ref

No.

Parameter

Unit

Min

Max

Min

Max

1

CLK frequency at Data transfer Mode (PP) —10/30 cards

0

25/5

0

25/5

MHz

kHz

ns

2

CLK frequency at Identification Mode

400

1

3a

3b

4a

4b

5a

5b

6a

6b

7

Clock high time —10/30 cards

6/33

15/75

–

10/50

–

1

Clock low time —10/30 cards

–

ns

1

3

Clock fall time —10/30 cards

10/50 (5.00)

10/50

ns

1

Clock rise time —10/30 cards

–

14/67 (6.67)

–

10/50

ns

3

Input hold time —10/30 cards

5.7/5.7

0

–

5/5

0

–

ns

3

Input setup time —10/30 cards

ns

3

Output hold time —10/30 cards

–

ns

3

Output setup time —10/30 cards

–

ns

3

Output delay time

16

14

ns

^{1. C}≤ 100 pF / 250 pF (10/30 cards)

L

2. C ≤ 250 pF (21 cards)

L

^{3. C}≤ 25 pF (1 card)

L

MC9328MX21S Technical Data, Rev. 1.3

Freescale Semiconductor

27

Specifications

3.11.1 Command Response Timing on MMC/SD Bus

The card identification and card operation conditions timing are processed in open-drain mode. The card

response to the host command starts after exactly N clock cycles. For the card address assignment,

ID

SET_RCA is also processed in the open-drain mode. The minimum delay between the host command and

card response is NCR clock cycles as illustrated in Figure 18. The symbols for Figure 18 through

Figure 22 are defined in Table 22.

Table 22. State Signal Parameters for Figure 18 through Figure 22

Card Active

Definition

Host Active

Definition

Symbol

Z

High impedance state

Data bits

S

T

Start bit (0)

D

Transmitter bit

(Host = 1, Card = 0)

*

Repetition

P

E

One-cycle pull-up (1)

End bit (1)

CRC

Cyclic redundancy check bits (7 bits)

N_IDcycles

Host Command

CID/OCR

Content

CMD

Content

******

CRC

S T

E Z

Z S T

Z Z Z

Identification Timing

N

_CRcycles

Host Command

Content CRC

CID/OCR

******

Content

SET_RCA Timing

S T

E Z

Z S T

Z Z Z

Figure 18. Timing Diagrams at Identification Mode

After a card receives its RCA, it switches to data transfer mode. As shown on the first diagram in

Figure 19, SD_CMD lines in this mode are driven with push-pull drivers. The command is followed by a

period of two Z bits (allowing time for direction switching on the bus) and then by P bits pushed up by the

responding card. The other two diagrams show the separating periods N and N .

RC

CC

MC9328MX21S Technical Data, Rev. 1.3

28

Freescale Semiconductor

Specifications

N

_CRcycles

******

Host Command

Response

Content CRC

E Z Z Z

CMD

Content

CRC

ST

E Z Z P

P S T

Command response timing (data transfer mode)

N_RCcycles

Response

Content

Host Command

CMD

******

Content

CRC

E Z Z Z

ST

E Z

Z S T

Timing response end to next CMD start (data transfer mode)

N_CCcycles

Host Command

Content

Host Command

CMD

******

Content

CRC

E Z Z Z

ST

E Z

Z S T

Timing of command sequences (all modes)

Figure 19. Timing Diagrams at Data Transfer Mode

Figure 20 shows basic read operation timing. In a read operation, the sequence starts with a single block

read command (which specifies the start address in the argument field). The response is sent on the

SD_CMD lines as usual. Data transmission from the card starts after the access time delay N , beginning

AC

from the last bit of the read command. If the system is in multiple block read mode, the card sends a

continuous flow of data blocks with distance N until the card sees a stop transmission command. The

AC

data stops two clock cycles after the end bit of the stop command.

MC9328MX21S Technical Data, Rev. 1.3

Freescale Semiconductor

29

Specifications

N

_CRcycles

Host Command

Response

Content CRC

E Z

CMD

DAT

Content

CRC

******

ST

E Z Z P

P S T

Z****Z

*****

Z Z P

P S DDDD

Read Data

Timing of single block read

N_ACcycles

N_CRcycles

******

Host Command

Response

Content

CMD

DAT

Content

CRC

E Z

ST

E Z Z P

P S T

Z****Z

******

*****

Read Data

*****

Read Data

Z Z P

P S DDDD

P

P S DDDD

N_ACcycles

N

_ACcycles

Timing of multiple block read

N

_CRcycles

Host Command

Content CRC

Response

Content

CMD

******

CRC

E Z

ST

E Z Z P

P S T

N_ST

DAT

*****

DDDD

DDDDE Z Z Z

Timing of stop command

(CMD12, data transfer mode)

Valid Read Data

Figure 20. Timing Diagrams at Data Read

Figure 21 shows the basic write operation timing. As with the read operation, after the card response, the

data transfer starts after N cycles. The data is suffixed with CRC check bits to allow the card to check

WR

for transmission errors. The card sends back the CRC check result as a CC status token on the data line. If

there was a transmission error, the card sends a negative CRC status (101); otherwise, a positive CRC

status (010) is returned. The card expects a continuous flow of data blocks if it is configured to multiple

block mode, with the flow terminated by a stop transmission command.

MC9328MX21S Technical Data, Rev. 1.3

30

Freescale Semiconductor

Specifications

Figure 21. Timing Diagrams at Data Write

The stop transmission command may occur when the card is in different states. Figure 22 shows the

different scenarios on the bus.

MC9328MX21S Technical Data, Rev. 1.3

Freescale Semiconductor

31

Specifications

Figure 22. Stop Transmission During Different Scenarios

Table 23. Timing Values for Figure 18 through Figure 22

Parameter

Symbol

Minimum

Maximum

Unit

MMC/SD bus clock, CLK (All values are referred to minimum (VIH) and maximum (VIL)

Command response cycle

Identification response cycle

Access time delay cycle

NCR

NID

2

5

2

64

Clock cycles

5

NAC

TAAC + NSAC

MC9328MX21S Technical Data, Rev. 1.3

32

Freescale Semiconductor

Specifications

Unit

Table 23. Timing Values for Figure 18 through Figure 22 (Continued)

Parameter

Command read cycle

Symbol

Minimum

Maximum

NRC

NCC

NWR

NST

8

2

–

2

Clock cycles

Command-command cycle

Command write cycle

Stop transmission cycle

TAAC: Data read access time -1 defined in CSD register bit[119:112]

NSAC: Data read access time -2 in CLK cycles (NSAC·100) defined in CSD register bit[111:104]

3.11.2 SDIO-IRQ and ReadWait Service Handling

In SDIO, there is a 1-bit or 4-bit interrupt response from the SDIO peripheral card. In 1-bit mode, the

interrupt response is simply that the SD_DAT[1] line is held low. The SD_DAT[1] line is not used as data

in this mode. The memory controller generates an interrupt according to this low and the system interrupt

continues until the source is removed (SD_DAT[1] returns to its high level).

In 4-bit mode, the interrupt is less simple. The interrupt triggers at a particular period called the Interrupt

Period during the data access, and the controller must sample SD_DAT[1] during this short period to

determine the IRQ status of the attached card. The interrupt period only happens at the boundary of each

block (512 bytes).

CMD

Content

CRC

Response

******

S

ST

E Z Z P S

E Z Z Z

Z Z Z

DAT[1]

For 4-bit

Interrupt Period

IRQ

Block Data

S

E

L H

Interrupt Period

DAT[1]

For 1-bit

Figure 23. SDIO IRQ Timing Diagram

ReadWait is another feature in SDIO that allows the user to submit commands during the data transfer. In

this mode, the block temporarily pauses the data transfer operation counter and related status, yet keeps

the clock running, and allows the user to submit commands as normal. After all commands are submitted,

the user can switch back to the data transfer operation and all counter and status values are resumed as

access continues.

CMD

******

CMD52 CRC

******

P S T

E Z Z Z

DAT[1]

For 4-bit

Block Data

S

E Z Z L H

S

E

DAT[2]

For 4-bit

Block Data

E Z Z L L L L L L L L L L L L L L L L L L L L L H Z S

Figure 24. SDIO ReadWait Timing Diagram

MC9328MX21S Technical Data, Rev. 1.3

Freescale Semiconductor

33

Specifications

3.12 External Memory Interface (EMI) Electricals

3.12.1 NAND-Flash Controller (NFC) Interface

Figure 25, Figure 26, Figure 27, and Figure 28 depict the relative timing requirements among different

signals of the NFC at module level, and Table 24 lists the timing parameters. The NAND Flash Controller

(NFC) timing parameters are based on the internal NFC clock generated by the Clock Controller module,

where time T is the period of the NFC clock in ns. Per the i.MX21S Reference Manual, specifically the

Phase-Locked (PLL), Clock, and Reset Controller chapter, the NFC clock is derived from the same clock

which drives the CPU clock (FCLK) that is fed through the NFCDIV block to generate the NFC clock.

The relationship between the NFC clock and the external timing parameters of the NFC is provided in

Table 24.

Table 24 also provides two examples of external timing parameters with NFC clock frequencies of

22.17 MHz and 33.25 MHz. For example, assuming a 266 MHz FCLK (CPU clock), NFCDIV should be

set to divide-by-12 to generate a 22.17 MHz NFC clock and divide-by-8 to generate a 33.25 MHz NFC

clock. The user should compare the parameters of the selected NAND Flash memory with the NFC

external timing parameters to determine the proper NFC clock. The maximum NFC clock allowed is

66 MHz. It should also be noted that the default NFC clock on power up is 16.63 MHz.

NFCLE

NF1

NF3

NF2

NF4

NFCE

NF5

NFWE

NF6

NF7

NF9

NFALE

NF8

command

NFIO[7:0]

Figure 25. Command Latch Cycle Timing DIagram

MC9328MX21S Technical Data, Rev. 1.3

34

Freescale Semiconductor

Specifications

NFCLE

NFCE

NF1

NF3

NF4

NF5

NFWE

NF6

NF7

NF9

NFALE

NF8

NFIO[7:0]

Address

Time it takes for SW to issue the next address command

Figure 26. Address Latch Cycle Timing DIagram

NFCLE

NFCE

NF1

NF3

NF4

NF10

NF11

NF5

NF8

NFWE

NFALE

NF6

NF9

NFIO[15:0]

Data to Flash

Figure 27. Write Data Latch Timing DIagram

NFCLE

NFCE

NF14

NF3

NF13

NF15

NFRE

NF16

NF17

NFRB

Data from Flash

NFIO[15:0]

NF12

Figure 28. Read Data Latch Timing Diagram

MC9328MX21S Technical Data, Rev. 1.3

Freescale Semiconductor

35

Specifications

1 2

Table 24. NFC Target Timing Parameters ,

Relationshipto NFC

Clock Period

(T)

NFC Clock

22.17 MHz

T = 45 ns

NFC Clock

33.25 MHz

T = 30 ns

ID

Parameter

Symbol

Unit

Min

Max

Min

Max

Min

Max

NF1 NFCLE Setup Time

NF2 NFCLE Hold Time

NF3 NFCE Setup Time

NF4 NFCE Hold Time

NF5 NF_WP Pulse Width

NF6 NFALE Setup Time

NF7 NFALE Hold Time

NF8 Data Setup Time

NF9 Data Hold Time

tCLS

tCLH

tCS

T

–

45

–

30

60

30

120

45

60

15

0

–

ns

T

45

tCH

T

45

tWP

tALS

tALH

tDS

T

45

T

45

T

45

T

45

tDH

T

45

NF10 Write Cycle Time

NF11 NFWE Hold Time

NF12 Ready to NFRE Low

NF13 NFRE Pulse Width

NF14 READ Cycle Time

NF15 NFRE High Hold Time

NF16 Data Setup on READ

NF17 Data Hold on READ

tWC

tWH

tRR

2T

T

90

45

4T

1.5T

2T

0.5T

15

0

180

67.5

90

tRP

tRC

tREH

tDSR

tDHR

22.5

15

0

1. High is defined as 80% of signal value and low is defined as 20% of signal value. All timings are listed according to this NFC

clock frequency (multiples of NFC clock period) except NF16, which is not NFC clock related.

2. The read data is generated by the NAND Flash device and sampled with the internal NFC clock.

MC9328MX21S Technical Data, Rev. 1.3

36

Freescale Semiconductor

Specifications

3.13 Pulse-Width Modulator

The PWM can be programmed to select one of two clock signals as its source frequency. The selected

clock signal is passed through a divider and a prescaler before being input to the counter. The output is

available at the pulse-width modulator output (PWMO) external pin.

1

2a

3b

System Clock

2b

4b

3a

4a

PWM Output

Figure 29. PWM Output Timing Diagram

Table 25. PWM Output Timing Parameters

1.8 V 0.1 V

3.0 V 0.3 V

Ref No.

Parameter

Unit

Minimum

Maximum

Minimum

Maximum

1

System CLK frequency

0

12.29

9.91

–

45

–

0

12.29

9.91

–

45

–

MHz

ns

1

2a

2b

3a

3b

4a

4b

Clock high time

1

Clock low time

–

ns

1

Clock fall time

0.5

–

0.5

–

ns

1

Clock rise time

–

ns

1

Output delay time

9.37

8.71

3.61

3.03

ns

1

Output setup time

–

ns

1. C_Lof PWMO = TBD

MC9328MX21S Technical Data, Rev. 1.3

Freescale Semiconductor

37

Specifications

3.14 SDRAM Memory Controller

The following figures (Figure 30 through Figure 33) and their associated tables specify the timings related

to the SDRAMC module in the i.MX21S.

1

SDCLK

2

3S

3

CS

RAS

CAS

3H

3S

3H

3S

3H

4H

WE

ADDR

DQ

4S

ROW/BA

COL/BA

5

8

6

Data

7

3S

DQM

3H

Note: CKE is high during the read/write cycle.

Figure 30. SDRAM Read Cycle Timing Diagram

Table 26. SDRAM Read Cycle Timing Parameter

1.8 V 0.1 V

3.0 V 0.3 V

Ref

No.

Parameter

Unit

Minimum

Maximum

Minimum

Maximum

1

2

3

SDRAM clock high-level width

SDRAM clock low-level width

SDRAM clock cycle time

3.00

7.5

–

3

–

ns

7.5

3

3S CS, RAS, CAS, WE, DQM setup time

3H CS, RAS, CAS, WE, DQM hold time

4.78

3.03

2

MC9328MX21S Technical Data, Rev. 1.3

38

Freescale Semiconductor

Specifications

Table 26. SDRAM Read Cycle Timing Parameter (Continued)

1.8 V 0.1 V

3.0 V 0.3 V

Minimum Maximum

Ref

No.

Parameter

Unit

Minimum

Maximum

4S Address setup time

4H Address hold time

3.67

2.95

–

2

–

ns

–

5

6

7

8

SDRAM access time (CL = 3)

5.4

SDRAM access time (CL = 2)

–

6.0

SDRAM access time (CL = 1)

–

Data out hold time

–

2

1

Data out high-impedance time (CL = 3)

Data out high-impedance time (CL = 2)

Data out high-impedance time (CL = 1)

Active to read/write command period (RC = 1)

–

t

–

t

HZ

1

–

HZ

–

2

t

–

t

–

RCD

1. t = SDRAM data out high-impedance time, external SDRAM memory device dependent parameter.

HZ

2. t

= SDRAM clock cycle time. The t

SDCLK

setting can be found in the i.MX21S reference manual.

RCD

1

3

2

CS

RAS

6

CAS

WE

4

5

7

ADDR

/ BA

ROW/BA

COL/BA

DATA

8

9

DQ

DQM

Figure 31. SDRAM Write Cycle Timing Diagram

MC9328MX21S Technical Data, Rev. 1.3

Freescale Semiconductor

39

Specifications

Table 27. SDRAM Write Cycle Timing Parameter

1.8 V 0.1 V

3.0 V 0.3 V

Ref

No.

Parameter

Unit

Minimum

Maximum

Minimum

Maximum

1

2

3

4

5

6

7

8

9

SDRAM clock high-level width

SDRAM clock low-level width

SDRAM clock cycle time

Address setup time

3.00

7.5

–

3

–

ns

7.5

2

3.67

Address hold time

2.95

2

1

2

Precharge cycle period

t

RP

2

Active to read/write command delay

Data setup time

t

RCD

3.41

2

Data hold time

2.45

2

1. Precharge cycle timing is included in the write timing diagram.

2. t and t

= SDRAM clock cycle time. These settings can be found in the i.MX21 reference manual.

RCD

RP

SDCLK

CS

1

3

2

RAS

CAS

6

7

WE

ADDR

DQ

4

5

BA

ROW/BA

DQM

Figure 32. SDRAM Refresh Timing Diagram

MC9328MX21S Technical Data, Rev. 1.3

40

Freescale Semiconductor

Specifications

Table 28. SDRAM Refresh Timing Parameters

1.8 V 0.1 V

3.0 V 0.3 V

Ref

No.

Parameter

Unit

Minimum

Maximum

Minimum

Maximum

1

2

3

4

5

6

7

SDRAM clock high-level width

SDRAM clock low-level width

SDRAM clock cycle time

Address setup time

3.00

7.5

–

3

–

ns

7.5

2

3.67

Address hold time

2.95

2

1

Precharge cycle period

Auto precharge command period

t

RP

1

t

RC

1. t and t = SDRAM clock cycle time. These settings can be found in the i.MX21 reference manual.

RP

RC

SDCLK

CS

RAS

CAS

WE

ADDR

DQ

BA

DQM

CKE

Figure 33. SDRAM Self-Refresh Cycle Timing Diagram

MC9328MX21S Technical Data, Rev. 1.3

Freescale Semiconductor

41

Specifications

3.15 Synchronous Serial Interface

The transmit and receive sections of the SSI can be synchronous or asynchronous. In synchronous mode,

the transmitter and the receiver use a common clock and frame synchronization signal. In asynchronous

mode, the transmitter and receiver each have their own clock and frame synchronization signals.

Continuous or gated clock mode can be selected. In continuous mode, the clock runs continuously. In gated

clock mode, the clock functions only during transmission. The internal and external clock timing diagrams

are shown in Figure 34 through Figure 37.

Normal or network mode can also be selected. In normal mode, the SSI functions with one data word of

I/O per frame. In network mode, a frame can contain between 2 and 32 data words. Network mode is

typically used in star or ring-time division multiplex networks with other processors or codecs, allowing

interface to time division multiplexed networks without additional logic. Use of the gated clock is not

allowed in network mode. These distinctions result in the basic operating modes that allow the SSI to

communicate with a wide variety of devices.

The SSI can be connected to 4 set of ports, SAP, SSI1, SSI2 and SSI3.

1

CK Output

4

2

FS (bl) Output

FS (wl) Output

6

8

12

10

11

32

STXD Output

SRXD Input

31

Note: SRXD input in synchronous mode only.

Figure 34. SSI Transmitter Internal Clock Timing Diagram

MC9328MX21S Technical Data, Rev. 1.3

42

Freescale Semiconductor

Specifications

1

CK Output

3

5

FS (bl) Output

FS (wl) Output

7

9

13

14

SRXD Input

Figure 35. SSI Receiver Internal Clock Timing Diagram

15

16

17

CK Input

18

20

FS (bl) Input

FS (wl) Input

24

22

28

27

34

26

STXD Output

SRXD Input

33

Note: SRXD Input in Synchronous mode only

Figure 36. SSI Transmitter External Clock Timing Diagram

15

16

17

CK Input

19

21

FS (bl) Input

FS (wl) Input

25

23

30

29

SRXD Input

Figure 37. SSI Receiver External Clock Timing Diagram

MC9328MX21S Technical Data, Rev. 1.3

Freescale Semiconductor

43

Specifications

Table 29. SSI to SAP Ports Timing Parameters

1.8 V 0.1 V

3.0 V 0.3 V

Ref

No.

Parameter

Unit

Minimum

Maximum

Minimum

Maximum

1

Internal Clock Operation (SAP Ports)

1

2

(Tx/Rx) CK clock period

90.91

-3.30

-3.93

-3.30

-3.93

-3.30

-3.93

-3.30

-3.93

-2.44

-2.67

23.68

0

–

90.91

-2.98

-4.18

-2.98

-4.18

-2.98

-4.18

-2.98

-4.18

-2.65

22.09

0

–

ns

(Tx) CK high to FS (bl) high

-1.16

-1.34

-1.16

-1.34

-1.16

-1.34

-1.16

-1.34

-0.60

-0.99

–

-1.10

-1.43

-1.10

-1.43

-1.10

-1.43

-1.10

-1.43

-0.98

–

3

(Rx) CK high to FS (bl) high

(Tx) CK high to FS (bl) low

4

5

(Rx) CK high to FS (bl) low

6

(Tx) CK high to FS (wl) high

(Rx) CK high to FS (wl) high

(Tx) CK high to FS (wl) low

7

8

9

(Rx) CK high to FS (wl) low

10

(Tx) CK high to STXD valid from high impedance

11a (Tx) CK high to STXD high

11b (Tx) CK high to STXD low

12

13

14

(Tx) CK high to STXD high impedance

SRXD setup time before (Rx) CK low

SRXD hold time after (Rx) CK low

–

External Clock Operation (SAP Ports)

1

15

16

17

18

19

20

21

22

23

24

25

26

(Tx/Rx) CK clock period

90.91

36.36

10.24

10.89

10.24

10.89

10.24

10.89

10.24

10.89

12.08

10.80

12.08

0.37

–

90.91

36.36

7.16

7.63

7.16

7.63

7.16

7.63

7.16

7.63

7.71

0.42

0

–

ns

(Tx/Rx) CK clock high period

(Tx/Rx) CK clock low period

(Tx) CK high to FS (bl) high

(Rx) CK high to FS (bl) high

(Tx) CK high to FS (bl) low

–

19.50

21.27

19.50

21.27

19.50

21.27

19.50

21.27

19.36

–

8.65

9.12

8.65

9.12

8.65

9.12

8.65

9.12

9.20

–

(Rx) CK high to FS (bl) low

(Tx) CK high to FS (wl) high

(Rx) CK high to FS (wl) high

(Tx) CK high to FS (wl) low

(Rx) CK high to FS (wl) low

(Tx) CK high to STXD valid from high impedance

27a (Tx) CK high to STXD high

27b (Tx) CK high to STXD low

28

29

30

(Tx) CK high to STXD high impedance

SRXD setup time before (Rx) CK low

SRXD hole time after (Rx) CK low

0

–

MC9328MX21S Technical Data, Rev. 1.3

44

Freescale Semiconductor

Specifications

Unit

Table 29. SSI to SAP Ports Timing Parameters (Continued)

1.8 V 0.1 V

Minimum Maximum

Synchronous Internal Clock Operation (SAP Ports)

3.0 V 0.3 V

Minimum

Ref

No.

Parameter

Maximum

31

32

SRXD setup before (Tx) CK falling

SRXD hold after (Tx) CK falling

23.00

0

–

21.41

0

–

ns

Synchronous External Clock Operation (SAP Ports)

33

34

SRXD setup before (Tx) CK falling

SRXD hold after (Tx) CK falling

1.20

0

–

0.88

0

–

ns

1. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting

the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.

Table 30. SSI to SSI1 Ports Timing Parameters

1.8 V 0.1 V

Minimum Maximum

Internal Clock Operation (SSI1 Ports)

3.0 V 0.3 V

Ref

No.

Parameter

Unit

Minimum

Maximum

1

2

(Tx/Rx) CK clock period

90.91

-0.68

-0.96

-0.68

-0.96

-0.68

-0.96

-0.68

-0.96

-1.68

-1.58

20.41

0

–

90.91

-0.68

-0.96

-0.68

-0.96

-0.68

-0.96

-0.68

-0.96

-1.68

-1.58

20.41

0

–

ns

(Tx) CK high to FS (bl) high

(Rx) CK high to FS (bl) high

(Tx) CK high to FS (bl) low

-0.15

-0.27

-0.15

-0.27

-0.15

-0.27

-0.15

-0.27

-0.36

-0.31

–

-0.15

-0.27

-0.15

-0.27

-0.15

-0.27

-0.15

-0.27

-0.36

-0.31

–

3

4

5

(Rx) CK high to FS (bl) low

6

(Tx) CK high to FS (wl) high

(Rx) CK high to FS (wl) high

(Tx) CK high to FS (wl) low

7

8

9

(Rx) CK high to FS (wl) low

(Tx) CK high to STXD valid from high impedance

10

11a (Tx) CK high to STXD high

11b (Tx) CK high to STXD low

12

13

14

(Tx) CK high to STXD high impedance

SRXD setup time before (Rx) CK low

SRXD hold time after (Rx) CK low

–

External Clock Operation (SSI1 Ports)

1

15

16

17

18

19

(Tx/Rx) CK clock period

90.91

36.36

10.22

10.79

–

90.91

36.36

8.82

–

ns

(Tx/Rx) CK clock high period

(Tx/Rx) CK clock low period

(Tx) CK high to FS (bl) high

(Rx) CK high to FS (bl) high

–

17.63

19.67

16.24

18.28

9.39

MC9328MX21S Technical Data, Rev. 1.3

Freescale Semiconductor

45

Specifications

Table 30. SSI to SSI1 Ports Timing Parameters (Continued)

1.8 V 0.1 V

3.0 V 0.3 V

Ref

No.

Parameter

(Tx) CK high to FS (bl) low

Unit

Minimum

Maximum

Minimum

Maximum

20

21

22

23

24

25

26

10.22

10.79

10.22

10.79

10.22

10.79

10.05

10.00

10.05

0.78

17.63

19.67

17.63

19.67

17.63

19.67

15.75

15.63

15.75

–

8.82

9.39

8.82

9.39

8.82

9.39

8.66

8.61

8.66

0.47

0

16.24

18.28

16.24

18.28

16.24

18.28

14.36

14.24

14.36

–

ns

(Rx) CK high to FS (bl) low

(Tx) CK high to FS (wl) high

(Rx) CK high to FS (wl) high

(Tx) CK high to FS (wl) low

(Rx) CK high to FS (wl) low

(Tx) CK high to STXD valid from high impedance

27a (Tx) CK high to STXD high

27b (Tx) CK high to STXD low

28

29

30

(Tx) CK high to STXD high impedance

SRXD setup time before (Rx) CK low

SRXD hole time after (Rx) CK low

0

–

Synchronous Internal Clock Operation (SSI1 Ports)

31

32

SRXD setup before (Tx) CK falling

SRXD hold after (Tx) CK falling

19.90

0

–

19.90

0

–

ns

Synchronous External Clock Operation (SSI1 Ports)

33

34

SRXD setup before (Tx) CK falling

SRXD hold after (Tx) CK falling

2.59

0

–

2.28

0

–

ns

1. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting

the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.

Table 31. SSI to SSI2 Ports Timing Parameters

1.8 V 0.1 V

Minimum Maximum

Internal Clock Operation (SSI2 Ports)

3.0 V 0.3 V

Ref

No.

Parameter

Unit

Minimum

Maximum

1

2

(Tx/Rx) CK clock period

90.91

0.01

-0.21

0.01

-0.21

0.01

-0.21

0.01

-0.21

0.34

–

90.91

0.01

-0.21

0.01

-0.21

0.01

-0.21

0.01

-0.21

0.34

–

ns

(Tx) CK high to FS (bl) high

(Rx) CK high to FS (bl) high

(Tx) CK high to FS (bl) low

0.15

0.05

0.15

0.05

0.15

0.05

0.15

0.05

0.72

0.15

0.05

0.15

0.05

0.15

0.05

0.15

0.05

0.72

3

4

5

(Rx) CK high to FS (bl) low

6

(Tx) CK high to FS (wl) high

(Rx) CK high to FS (wl) high

(Tx) CK high to FS (wl) low

7

8

9

(Rx) CK high to FS (wl) low

(Tx) CK high to STXD valid from high impedance

10

MC9328MX21S Technical Data, Rev. 1.3

46

Freescale Semiconductor

Specifications

Unit

Table 31. SSI to SSI2 Ports Timing Parameters (Continued)

1.8 V 0.1 V

3.0 V 0.3 V

Minimum

Ref

No.

Parameter

Minimum

Maximum

11a (Tx) CK high to STXD high

11b (Tx) CK high to STXD low

0.34

21.50

0

0.72

0.48

–

0.34

21.50

0

0.72

0.48

–

ns

12

13

14

(Tx) CK high to STXD high impedance

SRXD setup time before (Rx) CK low

SRXD hold time after (Rx) CK low

–

External Clock Operation (SSI2 Ports)

1

15

16

17

18

19

20

21

22

23

24

25

26

(Tx/Rx) CK clock period

90.91

36.36

10.40

11.00

10.40

11.00

10.40

11.00

10.40

11.00

9.59

–

90.91

36.36

8.67

9.28

8.67

9.28

8.67

9.28

8.67

9.28

7.86

2.52

0

–

ns

(Tx/Rx) CK clock high period

(Tx/Rx) CK clock low period

(Tx) CK high to FS (bl) high

(Rx) CK high to FS (bl) high

(Tx) CK high to FS (bl) low

–

17.37

19.70

17.37

19.70

17.37

19.70

17.37

19.70

17.08

16.84

–

15.88

18.21

15.88

18.21

15.88

18.21

15.88

18.21

15.59

15.35

–

(Rx) CK high to FS (bl) low

(Tx) CK high to FS (wl) high

(Rx) CK high to FS (wl) high

(Tx) CK high to FS (wl) low

(Rx) CK high to FS (wl) low

(Tx) CK high to STXD valid from high impedance

27a (Tx) CK high to STXD high

27b (Tx) CK high to STXD low

9.59

28

29

30

(Tx) CK high to STXD high impedance

SRXD setup time before (Rx) CK low

SRXD hole time after (Rx) CK low

9.59

2.52

0

–

Synchronous Internal Clock Operation (SSI2 Ports)

31

32

SRXD setup before (Tx) CK falling

SRXD hold after (Tx) CK falling

20.78

0

–

20.78

0

–

ns

Synchronous External Clock Operation (SSI2 Ports)

33

34

SRXD setup before (Tx) CK falling

SRXD hold after (Tx) CK falling

4.42

0

–

4.42

0

–

ns

1. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting

the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.

MC9328MX21S Technical Data, Rev. 1.3

Freescale Semiconductor

47

Specifications

Table 32. SSI to SSI3 Ports Timing Parameters

1.8 V 0.1 V

3.0 V 0.3 V

Ref

No.

Parameter

Unit

Minimum

Maximum

Minimum

Maximum

1

Internal Clock Operation (SSI3 Ports)

1

2

(Tx/Rx) CK clock period

90.91

-2.09

-2.74

-2.09

-2.74

-2.09

-2.74

-2.09

-2.74

-1.73

-2.87

-1.73

22.77

0

–

90.91

-2.09

-2.74

-2.09

-2.74

-2.09

-2.74

-2.09

-2.74

-1.73

-2.87

-1.73

22.77

0

–

ns

(Tx) CK high to FS (bl) high

-0.66

-0.84

-0.66

-0.84

-0.66

-0.84

-0.66

-0.84

-0.26

-0.80

-0.26

–

-0.66

-0.84

-0.66

-0.84

-0.66

-0.84

-0.66

-0.84

-0.26

-0.80

-0.26

–

3

(Rx) CK high to FS (bl) high

(Tx) CK high to FS (bl) low

4

5

(Rx) CK high to FS (bl) low

6

(Tx) CK high to FS (wl) high

(Rx) CK high to FS (wl) high

(Tx) CK high to FS (wl) low

7

8

9

(Rx) CK high to FS (wl) low

10

(Tx) CK high to STXD valid from high impedance

11a (Tx) CK high to STXD high

11b (Tx) CK high to STXD low

12

13

14

(Tx) CK high to STXD high impedance

SRXD setup time before (Rx) CK low

SRXD hold time after (Rx) CK low

–

External Clock Operation (SSI3 Ports)

1

15

16

17

18

19

20

21

22

23

24

25

26

(Tx/Rx) CK clock period

90.91

36.36

9.62

–

90.91

36.36

7.90

8.58

7.90

8.58

7.90

8.58

7.90

8.58

7.29

6.75

–

ns

(Tx/Rx) CK clock high period

(Tx/Rx) CK clock low period

(Tx) CK high to FS (bl) high

(Rx) CK high to FS (bl) high

(Tx) CK high to FS (bl) low

–

17.10

19.54

17.10

19.54

17.10

19.54

17.10

19.54

16.46

15.32

15.61

18.05

15.61

18.05

15.61

18.05

15.61

18.05

14.97

13.83

10.30

9.62

(Rx) CK high to FS (bl) low

10.30

9.62

(Tx) CK high to FS (wl) high

(Rx) CK high to FS (wl) high

(Tx) CK high to FS (wl) low

(Rx) CK high to FS (wl) low

(Tx) CK high to STXD valid from high impedance

10.30

9.62

10.30

9.02

27a (Tx) CK high to STXD high

27b (Tx) CK high to STXD low

8.48

MC9328MX21S Technical Data, Rev. 1.3

48

Freescale Semiconductor

Specifications

Table 32. SSI to SSI3 Ports Timing Parameters (Continued)

1.8 V 0.1 V

3.0 V 0.3 V

Minimum Maximum

Ref

No.

Parameter

Unit

Minimum

Maximum

28

29

30

(Tx) CK high to STXD high impedance

SRXD setup time before (Rx) CK low

SRXD hole time after (Rx) CK low

9.02

1.49

0

16.46

7.29

1.49

0

14.97

ns

–

Synchronous Internal Clock Operation (SSI3 Ports)

31

32

SRXD setup before (Tx) CK falling

SRXD hold after (Tx) CK falling

21.99

0

–

21.99

0

–

ns

Synchronous External Clock Operation (SSI3 Ports)

33

34

SRXD setup before (Tx) CK falling

SRXD hold after (Tx) CK falling

3.80

0

–

3.80

0

–

ns

1. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting

the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.

3.16 1-Wire Interface Timing

3.16.1 Reset Sequence with Reset Pulse Presence Pulse

To begin any communications with the DS2502, it is required that an initialization procedure be issued. A

reset pulse must be generated and then a presence pulse must be detected. The minimum reset pulse length

is 480 us. The bus master (one-wire) will generate this pulse, then after the DS2502 detects a rising edge

on the one-wire bus, it will wait 15-60 us before it will transmit back a presence pulse. The presence pulse

will exist for 60-240 us.

The timing diagram for this sequence is shown in Figure 38.

Reset and Presence Pulses

AutoClear RPP

Control Bit

DS2502

Set RPP

waits

DS2502 Tx

“presence pulse”

60-240us

511 us

15-60us

one-wire

BUS

512us

One-Wire samples (set PST)

68us

Figure 38. 1-Wire Initialization

The reset pulse begins the initialization sequence and it is initiated when the RPP control register bit is set.

When the presence pulse is detected, this bit will be cleared. The presence pulse is used by the bus master

to determine if at least one DS2502 is connected. Software will determine if more than one DS2502 exists.

The one-wire will sample for the DS2502 presence pulse. The presence pulse is latched in the one-wire

MC9328MX21S Technical Data, Rev. 1.3

Freescale Semiconductor

49

Specifications

control register PST. When the PST bit is set to a one, it means that a DS2502 is present; if the bit is set to

a zero, then no device was found.

3.16.2 Write 0

The Write 0 function simply writes a zero bit to the DS2502. The sequence takes 117 us. The one-wire bus

is held low for 100us.

AutoClear WR0

Set WR0

Write 0 Slot 128us

17us

100us

one-wire

BUS

Figure 39. Write 0 Timing

The Write 0 pulse sequence is initiated when the WR0 control bit register is set. When the write is

complete, the WR0 register will be auto cleared.

3.16.3 Write 1/Read Data

The Write 1 and Read timing is identical. The time slot is first driven low. According to the DS2502

documentation, the DS2502 has a delay circuit which is used to synchronize the DS2502 with the bus

master (one-wire). This delay circuit is triggered by the falling edge of the data line and is used to decide

when the DS2502 should sample the line. In the case of a write 1 or read 1, after a delay, a 1 will be

transmitted / received. When a read 0 slot is issued, the delay circuit will hold the data line low to override

the 1 generated by the bus master (one-wire).

For the Write 1 or Read, the control register WR1/RD is set and auto-cleared when the sequence has been

completed. After a Read, the control register RDST bit is set to the value of the read.

Auto Clear WR1/R

Set WR1/RD

Write “1” Slot 117us

5us

Figure 40. Write 1 Timing

MC9328MX21S Technical Data, Rev. 1.3

50

Freescale Semiconductor

Specifications

Set WR1/RD

Auto Clear WR1/RD Set WR1/RD

Auto Clear WR1/R

Read Timing

Read “0” Slot 117us

60us

Read “1” Slot 117us

one-wire

BUS

5us

13us

5us

13us

One-Wire samples

(set RDST)

One-Wire samples

(set RDST)

Figure 41. Read Timing

The precision of the generated clock is very important to get a proper behavior of the one-wire module.

This module is based on a state machine which undertakes actions at defined times.

Table 33. System Timing Requirements

Values

(Microsec)

Minimum

(Microsec)

Maximum

(microsec)

Absolute

Precision

Relative

Precision

Times

RSTL

PST

511

68

480

60

480

60

1

–

75

–

31

7

0.0645

0.1

RSTH

512

100

5

32

20

4

0.0645

0.2

LOW0

120

15

LOWR

0.8

READ_sample

13

–

2

0.15

The most stringent constraint is 0.0645 as a relative time imprecision.

The time relative precision is directly derived from the frequency of the derivative clock (f):

Time relative precision = 1/f -1 = divider/clock (MHz) - 1

The Figure 34 gathers relative time precision for different main clock frequencies.

Table 34. System Clock Requirements

Main Clock Frequency (MHz)

13

16.8

19.44

Clock divide ratio

13

1

17

19

Generated frequency (MHz)

Relative time imprecision

0.9882

0.0117

1.023

0.023

0

This shows that the user should take care of the main clock frequency when using the one-wire module. If

the main clock is an exact integer multiple of 1 MHz, then the generated frequency will be exactly 1 MHz.

NOTE:

A main clock frequency below 10 MHz might cause a misbehavior of the module.

MC9328MX21S Technical Data, Rev. 1.3

Freescale Semiconductor

51

Specifications

3.17 USB On-The-Go

Four types of data transfer modes exist for the USB module: control transfers, bulk transfers, isochronous

transfers and interrupt transfers. From the perspective of the USB module, the interrupt transfer type is

identical to the bulk data transfer mode, and no additional hardware is supplied to support it. This section

covers the transfer modes and how they work from the ground up.

Data moves across the USB in packets. Groups of packets are combined to form data transfers. The same

packet transfer mechanism applies to bulk, interrupt, and control transfers. Isochronous data is also moved

in the form of packets, but because isochronous pipes are given a fixed portion of the USB bandwidth at

all times, there is no end-of-transfer.

USB_ON

(Output)

t

TXDM_OEB

4

t

1

OEB_TXDP

USB_OE

(Output)

6

3

t

PERIOD

TXDP_OEB

USB_TXDP

(Output)

USB_TXDM

(Output)

t

OEB_TXDM

t

FEOPT

2

5

USB_VP

(Input)

USB_VM

(Input)

Figure 42. USB Timing Diagram for Data Transfer to USB Transceiver (TX)

Table 35. USB Timing Parameters for Data Transfer to USB Transceiver (TX)

3.0 V 0.3 V

Ref

No.

Parameter

Unit

Minimum

Maximum

1

2

3

4

5

6

t_OEB

; USBD_OE active to USBD_TXDP low

; USBD_OE active to USBD_TXDM high

83.14

81.55

83.54

248.9

160

83.47

81.98

83.8

ns

_TXDP

t_OEB

_TXDM

t

_OEB; USBD_TXDP high to USBD_OE deactivated

ns

TXDP_

TXDM_

FEOPT

PERIOD

_OEB; USBD_TXDM low to USBD_OE deactivated (includes SE0)

; SE0 interval of EOP

249.13

175

ns

; Data transfer rate

11.97

12.03

Mb/s

MC9328MX21S Technical Data, Rev. 1.3

52

Freescale Semiconductor

Specifications

USB_ON

(Output)

USB_OE

(Output)

USB_TXDP

(Output)

USB_TXDM

(Output)

1

t

FEOPR

USB_RXDP

(Input)

USB_RXDM

(Input)

Figure 43. USB Timing Diagram for Data Transfer from USB Transceiver (RX)

Table 36. USB Timing Parameters for Data Transfer from USB Transceiver (RX)

3.0 V 0.3 V

Ref No.

Parameter

Unit

Minimum

Maximum

1

t

; Receiver SE0 interval of EOP

82

–

ns

FEOPR

2

The USBOTG I C communication protocol consists of six components: START, Data Source/Recipient,

Data Direction, Slave Acknowledge, Data, Data Acknowledge, and STOP.

USBG_SDA

5

3

4

USBG_SCL

1

2

6

2

Figure 44. USB Timing Diagram for Data Transfer from USB Transceiver (I C)

2

Table 37. USB Timing Parameters for Data Transfer from USB Transceiver (I C)

1.8 V 0.1 V

Ref No.

Parameter

Unit

Minimum

Maximum

1

2

3

4

5

6

Hold time (repeated) START condition

Data hold time

188

0

–

188

–

ns

Data setup time

88

HIGH period of the SCL clock

LOW period of the SCL clock

Setup time for STOP condition

500

185

–

MC9328MX21S Technical Data, Rev. 1.3

Freescale Semiconductor

53

Specifications

3.18 External Interface Module (EIM)

The External Interface Module (EIM) handles the interface to devices external to the i.MX21S, including

generation of chip-selects for external peripherals and memory. The timing diagram for the EIM is shown

in Figure 45, and Table 38 defines the parameters of signals.

(HCLK) Bus Clock

1a

2a

3a

1b

2b

3b

Address

Chip-select

Read (Write)

4a

5a

4b

5b

OE (rising edge)

4c

5c

4d

OE (falling edge)

EB (rising edge)

EB (falling edge)

5d

6b

6a

LBA (negated falling edge)

LBA (negated rising edge)

6c

7a

7b

11

Burst Clock (rising edge)

7c

7d

Burst Clock (falling edge)

Read Data

8b

9a

8a

9b

Write Data (negated falling)

9c

Write Data (negated rising)

DTACK

10a

Figure 45. EIM Bus Timing Diagram

MC9328MX21S Technical Data, Rev. 1.3

54

Freescale Semiconductor

Specifications

Table 38. EIM Bus Timing Parameters

1.8 V 0.1 V 3.0 V 0.3 V

1.8 V

0.1 V

Ref No.

Parameter

Unit

Min

Typical

Max

Min

Typical

Max

1a

1b

2a

2b

3a

3b

4a

4b

4c

4d

5a

5b

5c

5d

6a

6b

6c

7a

7b

7c

7d

8a

8b

9a

9b

9c

10a

11

Clock fall to address valid

3.97

3.93

3.47

3.39

3.51

3.59

3.62

3.70

3.60

3.69

4.64

3.52

3.50

3.65

3.66

3.50

3.49

3.50

3.49

4.54

0.5

6.02

6.00

5.59

5.09

5.56

5.37

5.49

5.61

5.48

5.62

5.46

5.47

5.06

5.05

5.28

5.67

5.69

5.22

5.19

5.22

5.19

–

9.89

9.86

8.62

8.27

8.79

9.14

8.98

9.26

8.77

9.12

8.71

8.70

8.39

8.27

8.69

9.36

9.48

8.42

8.30

8.39

8.29

–

3.83

3.81

3.30

3.15

3.39

3.36

3.46

3.44

3.42

3.46

3.41

3.30

3.41

3.33

3.26

3.31

3.26

3.31

4.54

0.5

5.89

5.86

5.09

4.85

5.39

5.20

5.33

5.37

5.30

5.36

5.25

5.18

5.23

5.43

5.47

4.99

5.03

4.98

5.02

–

9.79

9.76

8.45

8.03

8.51

8.50

9.02

8.81

8.88

8.60

8.54

8.36

8.81

9.13

9.25

8.19

8.17

8.15

8.12

–

ns

Clock fall to address invalid

Clock fall to chip-select valid

Clock fall to chip-select invalid

Clock fall to Read (Write) Valid

Clock fall to Read (Write) Invalid

1

Clock rise to Output Enable Valid

1

Clock rise to Output Enable Invalid

1

Clock fall to Output Enable Valid

1

Clock fall to Output Enable Invalid

1

Clock rise to Enable Bytes Valid

1

Clock rise to Enable Bytes Invalid

1

Clock fall to Enable Bytes Valid

1

Clock fall to Enable Bytes Invalid

1

Clock fall to Load Burst Address Valid

1

Clock fall to Load Burst Address Invalid

1

Clock rise to Load Burst Address Invalid

1

Clock rise to Burst Clock rise

1

Clock rise to Burst Clock fall

1

Clock fall to Burst Clock rise

1

Clock fall to Burst Clock fall

Read Data setup time

Read Data hold time

–

1

Clock rise to Write Data Valid

4.13

4.10

4.02

2.65

15

5.86

5.79

5.81

4.63

–

9.16

9.15

9.37

8.40

–

3.95

4.04

4.22

2.64

15

6.36

6.27

5.29

4.61

–

10.31

9.16

9.24

8.41

–

1

Clock fall to Write Data Invalid

1

Clock rise to Write Data Invalid

DTACK setup time

Burst Clock (BCLK) cycle time

1. Clock refers to the system clock signal, HCLK, generated from the System DPLL

MC9328MX21S Technical Data, Rev. 1.3

Freescale Semiconductor

55

Specifications

3.18.1 EIM External Bus Timing Diagrams

The following timing diagrams show the timing of accesses to memory or a peripheral.

Note: Signals listed with lower case letters are internal to the device.

hclk

hselm_weim_cs[0]

htrans

hwrite

Seq/Nonseq

Read

haddr

hready

V1

weim_hrdata

weim_hready

Last Valid Data

V1

BCLK

A[24:0]

Last Valid Address

V1

CS[0]

R/W

Read

LBA

OE

EB (EBC=0)

EB (EBC=1)

DATA_IN

V1

Figure 46. WSC = 1, A.HALF/E.HALF

MC9328MX21S Technical Data, Rev. 1.3

56

Freescale Semiconductor

Specifications

Note: Signals listed with lower case letters are internal to the device.

hclk

hselm_weim_cs[0]

htrans

hwrite

haddr

Nonseq

Write

V1

hready

hwdata

Last Valid Data

Write Data (V1)

Unknown

weim_hrdata

Last Valid Data

weim_hready

BCLK

A[24:0]

Last Valid Address

V1

CS[0]

R/W

LBA

Write

OE

EB

D[31:0]

Last Valid Data

Write Data (V1)

Figure 47. WSC = 1, WEA = 1, WEN = 1, A.HALF/E.HALF

MC9328MX21S Technical Data, Rev. 1.3

Freescale Semiconductor

57

Specifications

Note: Signals listed with lower case letters are internal to the device.

hclk

hselm_weim_cs[0]

htrans

hwrite

haddr

Nonseq

Read

V1

hready

weim_hrdata

Last Valid Data

V1 Word

weim_hready

BCLK

A[24:0]

Last Valid Addr

Address V1

Address V1 + 2

CS[0]

R/W

LBA

OE

Read

EB (EBC=0)

EB (EBC=1)

DATA_IN

1/2 Half Word

2/2 Half Word

Figure 48. WSC = 1, OEA = 1, A.WORD/E.HALF

MC9328MX21S Technical Data, Rev. 1.3

58

Freescale Semiconductor

Specifications

Note: Signals listed with lower case letters are internal to the device.

hclk

hselm_weim_cs[0]

Nonseq

Write

V1

htrans

hwrite

haddr

hready

hwdata

Last Valid Data

Write Data (V1 Word)

Last Valid Data

weim_hrdata

weim_hready

BCLK

A[24:0]

Last Valid Addr

Address V1

Address V1 + 2

CS[0]

R/W

LBA

Write

OE

EB

D[31:0]

1/2 Half Word

2/2 Half Word

Figure 49. WSC = 1, WEA = 1, WEN = 1, A.WORD/E.HALF

MC9328MX21S Technical Data, Rev. 1.3

Freescale Semiconductor

59

Specifications

Note: Signals listed with lower case letters are internal to the device.

hclk

hselm_weim_cs[3]

htrans

Nonseq

hwrite

Read

V1

haddr

hready

weim_hrdata

Last Valid Data

V1 Word

weim_hready

BCLK

A[24:0]

Last Valid Addr

Address V1

Read

Address V1 + 2

CS[3]

R/W

LBA

OE

EB (EBC=0)

EB (EBC=1)

DATA_IN

1/2 Half Word

2/2 Half Word

Figure 50. WSC = 3, OEA = 2, A.WORD/E.HALF

MC9328MX21S Technical Data, Rev. 1.3

60

Freescale Semiconductor

Specifications

Note: Signals listed with lower case letters are internal to the device.

hclk

hselm_weim_cs[3]

Nonseq

htrans

hwrite

Write

V1

haddr

hready

hwdata

Last Valid

Data

Write Data (V1 Word)

Last Valid Data

weim_hrdata

weim_hready

BCLK

A[24:0]

Last Valid Addr

Address V1

Address V1 + 2

CS[3]

R/W

Write

LBA

OE

EB

D[31:0]

Last Valid Data

1/2 Half Word

2/2 Half Word

Figure 51. WSC = 3, WEA = 1, WEN = 3, A.WORD/E.HALF

MC9328MX21S Technical Data, Rev. 1.3

Freescale Semiconductor

61

Specifications

Note: Signals listed with lower case letters are internal to the device.

hclk

hselm_weim_cs[2]

htrans

Nonseq

Read

V1

hwrite

haddr

hready

weim_hrdata

Last Valid Data

V1 Word

weim_hready

BCLK

A[24:0]

Last Valid Addr

Address V1

Read

Address V1 + 2

CS[2]

R/W

LBA

OE

EB (EBC=0)

EB (EBC=1)

DATA_IN

1/2 Half Word

2/2 Half Word

Figure 52. WSC = 3, OEA = 4, A.WORD/E.HALF

MC9328MX21S Technical Data, Rev. 1.3

62

Freescale Semiconductor

Specifications

Note: Signals listed with lower case letters are internal to the device.

hclk

hselm_weim_cs[2]

htrans

Nonseq

hwrite

haddr

Write

V1

hready

hwdata

Last Valid

Data

Write Data (V1 Word)

Last Valid Data

weim_hrdata

weim_hready

BCLK

A[24:0] Last Valid Addr

Address V1

Address V1 + 2

CS[2]

R/W

Write

LBA

OE

EB

D[31:0]

Last Valid Data

1/2 Half Word

2/2 Half Word

Figure 53. WSC = 3, WEA = 2, WEN = 3, A.WORD/E.HALF

MC9328MX21S Technical Data, Rev. 1.3

Freescale Semiconductor

63

Specifications

Note: Signals listed with lower case letters are internal to the device.

hclk

hselm_weim_cs[2]

htrans

Nonseq

Read

V1

hwrite

haddr

hready

weim_hrdata

Last Valid Data

V1 Word

weim_hready

BCLK

A[24:0]

Last Valid Addr

Address V1

Read

Address V1 + 2

CS[2]

R/W

LBA

OE

EB (EBC=0)

EB (EBC=1)

DATA_IN

1/2 Half Word

2/2 Half Word

Figure 54. WSC = 3, OEN = 2, A.WORD/E.HALF

MC9328MX21S Technical Data, Rev. 1.3

64

Freescale Semiconductor

Specifications

Note: Signals listed with lower case letters are internal to the device.

hclk

hselm_weim_cs[2]

htrans

Nonseq

Read

V1

hwrite

haddr

hready

weim_hrdata

Last Valid Data

V1 Word

weim_hready

BCLK

Last Valid Addr

Address V1

Read

Address V1 + 2

A[24:0]

CS[2]

R/W

LBA

OE

EB (EBC=0)

EB (EBC=1)

DATA_IN

1/2 Half Word

2/2 Half Word

Figure 55. WSC = 3, OEA = 2, OEN = 2, A.WORD/E.HALF

MC9328MX21S Technical Data, Rev. 1.3

Freescale Semiconductor

65

Specifications

Note: Signals listed with lower case letters are internal to the device.

hclk

hselm_weim_cs[2]

htrans

Nonseq

Write

V1

hwrite

haddr

hready

hwdata

Last Valid

Data

Write Data (V1 Word)

Last Valid Data

Unknown

weim_hrdata

weim_hready

BCLK

A[24:0] Last Valid Addr

CS[2]

Address V1

Address V1 + 2

R/W

Write

LBA

OE

EB

D[31:0]

1/2 Half Word

2/2 Half Word

Last Valid Data

Figure 56. WSC = 2, WWS = 1, WEA = 1, WEN = 2, A.WORD/E.HALF

MC9328MX21S Technical Data, Rev. 1.3

66

Freescale Semiconductor

Specifications

Note: Signals listed with lower case letters are internal to the device.

hclk

hselm_weim_cs[2]

Nonseq

Write

V1

htrans

hwrite

haddr

hready

hwdata

Last Valid

Data

Write Data (V1 Word)

Last Valid Data

Unknown

weim_hrdata

weim_hready

BCLK

A[24:0]

Last Valid Addr

Address V1

Address V1 + 2

CS[2]

R/W

LBA

Write

OE

EB

D[31:0]

1/2 Half Word

2/2 Half Word

Last Valid Data

Figure 57. WSC = 1, WWS = 2, WEA = 1, WEN = 2, A.WORD/E.HALF

MC9328MX21S Technical Data, Rev. 1.3

Freescale Semiconductor

67

Specifications

Note: Signals listed with lower case letters are internal to the device.

hclk

hselm_weim_cs[2]

htrans

Nonseq

Read

V1

Nonseq

Write

V8

hwrite

haddr

hready

hwdata

Last Valid Data

Write Data

Read Data

weim_hrdata

Last Valid Data

weim_hready

BCLK

A[24:0]

Last Valid Addr

Address V1

Address V8

CS[2]

R/W

LBA

Read

Write

OE

EB (EBC=0)

EB (EBC=1)

DATA_IN

D[31:0]

Read Data

Last Valid Data

Write Data

Figure 58. WSC = 2, WWS = 2, WEA = 1, WEN = 2, A.HALF/E.HALF

MC9328MX21S Technical Data, Rev. 1.3

68

Freescale Semiconductor

Specifications

Note: Signals listed with lower case letters are internal to the device.

Read Idle

Write

hclk

hselm_weim_cs[2]

htrans

Nonseq

Read

V1

Nonseq

Write

V8

hwrite

haddr

hready

hwdata

Last Valid Data

Write Data

weim_hrdata

weim_hready

Last Valid Data

Read Data

BCLK

A[24:0]

Last Valid Addr

Address V1

Address V8

Write

CS[2]

R/W

LBA

Read

OE

EB (EBC=0)

EB (EBC=1)

DATA_IN

D[31:0]

Read Data

Last Valid Data

Write Data

Figure 59. WSC = 2, WWS = 1, WEA = 1, WEN = 2, EDC = 1, A.HALF/E.HALF

MC9328MX21S Technical Data, Rev. 1.3

Freescale Semiconductor

69

Specifications

Note: Signals listed with lower case letters are internal to the device.

hclk

hselm_weim_cs[4]

htrans

Nonseq

Write

V1

hwrite

haddr

hready

hwdata

Last Valid

Data

Write Data (Word)

Last Valid Data

weim_hrdata

weim_hready

BCLK

A[24:0]

Last Valid Addr

Address V1

Address V1 + 2

CS[3:0]

R/W

Write

LBA

OE

EB

D[31:0]

Write Data (1/2 Half Word)

Write Data (2/2 Half Word)

Last Valid Data

Figure 60. WSC = 2, CSA = 1, WWS = 1, A.WORD/E.HALF

MC9328MX21S Technical Data, Rev. 1.3

70

Freescale Semiconductor

Specifications

Note: Signals listed with lower case letters are internal to the device.

hclk

hselm_weim_cs[4]

Nonseq

Read

V1

Nonseq

Write

V8

htrans

hwrite

haddr

hready

hwdata

weim_hrdata

weim_hready

Last Valid Data

Write Data

Read Data

Last Valid Data

BCLK

A[24:0] Last Valid Addr

Address V1

Address V8

CS[4]

R/W

LBA

OE

Read

Write

EB (EBC=0)

EB (EBC=1)

Read Data

DATA_IN

D[31:0]

Last Valid Data

Write Data

Figure 61. WSC = 3, CSA = 1, A.HALF/E.HALF

MC9328MX21S Technical Data, Rev. 1.3

Freescale Semiconductor

71

Specifications

Note: Signals listed with lower case letters are internal to the device.

hclk

hselm_weim_cs[4]

htrans

Nonseq

Read

V1

Idle

Seq

Read

V2

hwrite

haddr

hready

weim_hrdata

weim_hready

Last Valid Data

Read Data (V1)

Read Data (V2)

BCLK

A[24:0]

Last Valid Addr

Address V1

Address V2

CNC

CS[4]

R/W

LBA

Read

OE

EB (EBC=0)

EB (EBC=1)

DATA_IN

Read Data

(V1)

Read Data

(V2)

Figure 62. WSC = 2, OEA = 2, CNC = 3, BCM = 1, A.HALF/E.HALF

MC9328MX21S Technical Data, Rev. 1.3

72

Freescale Semiconductor

Specifications

Note: Signals listed with lower case letters are internal to the device.

hclk

hselm_weim_cs[4]

htrans

Nonseq

Read

V1

Idle

Nonseq

Write

V8

hwrite

haddr

hready

hwdata

Last Valid Data

Write Data

weim_hrdata

Last Valid Data

Read Data

weim_hready

BCLK

A[24:0]

Last Valid Addr

Address V1

Address V8

CNC

CS[4]

R/W

Read

Write

LBA

OE

EB (EBC=0)

EB (EBC=1)

DATA_IN

D[31:0]

Read Data

Last Valid Data

Write Data

Figure 63. WSC = 2, OEA = 2, WEA = 1, WEN = 2, CNC = 3, A.HALF/E.HALF

MC9328MX21S Technical Data, Rev. 1.3

Freescale Semiconductor

73

Specifications

Note: Signals listed with lower case letters are internal to the device.

hclk

hselm_weim_cs[2]

htrans

Idle

Nonseq

Read

V1

Nonseq

Read

V5

hwrite

haddr

hready

weim_hrdata

weim_hready

BCLK

A[24:0]

Last Valid Addr

Address V1

Address V5

CS[2]

Read

R/W

LBA

OE

EB (EBC=0)

EB (EBC=1)

ECB

V5 Word

DATA_IN

V6 Word

V1 Word V2 Word

Figure 64. WSC = 3, SYNC = 1, A.HALF/E.HALF

MC9328MX21S Technical Data, Rev. 1.3

74

Freescale Semiconductor

Specifications

Note: Signals listed with lower case letters are internal to the device.

hclk

hselm_weim_cs[2]

htrans

hwrite

haddr

Nonseq

Idle

Seq

Read

V2

Seq

Read

V3

Seq

Read

V4

Read

V1

hready

weim_hrdata

weim_hready

BCLK

Last Valid Data

V1 Word

V2 Word

V3 Word

V4 Word

A[24:0]

Last Valid Addr

Address V1

CS[2]

R/W

Read

LBA

OE

EB (EBC=0)

EB (EBC=1)

ECB

DATA_IN

V1 Word

V2 Word

V3 Word

V4 Word

Figure 65. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.WORD

MC9328MX21S Technical Data, Rev. 1.3

Freescale Semiconductor

75

Specifications

Note: Signals listed with lower case letters are internal to the device.

hclk

hselm_weim_cs[2]

htrans

Nonseq

Seq

Idle

hwrite

haddr

Read

V1

Read

V2

hready

weim_hrdata

Last Valid Data

V1 Word

V2 Word

weim_hready

BCLK

A[24:0]

CS[2]

R/W

Last Valid Addr

Address V1

Address V2

Read

LBA

OE

EB (EBC=0)

EB (EBC=1)

ECB

DATA_IN

V1 1/2

V1 2/2

V2 1/2

V2 2/2

Figure 66. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.HALF

MC9328MX21S Technical Data, Rev. 1.3

76

Freescale Semiconductor

Specifications

Note: Signals listed with lower case letters are internal to the device.

hclk

hselm_weim_cs[2]

Non

htrans

Seq

Read

V2

Idle

seq

Read

V1

hwrite

haddr

hready

weim_hrdata

Last Valid Data

V1 Word

V2 Word

weim_hready

BCLK

Last Valid

Addr

Address V1

A[24:0]

CS[2]

Read

R/W

LBA

OE

EB (EBC=0)

EB (EBC=1)

ECB

DATA_IN

V1 1/2

V1 2/2

V2 1/2

V2 2/2

Figure 67. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 2, A.WORD/E.HALF

MC9328MX21S Technical Data, Rev. 1.3

Freescale Semiconductor

77

Specifications

Note: Signals listed with lower case letters are internal to the device.

hclk

hselm_weim_cs[2]

htrans

Non

seq

Seq

Idle

hwrite

haddr

Read

V1

Read

V2

hready

weim_hrdata

Last Valid Data

V1 Word

V2 Word

weim_hready

BCLK

A[24:0]

CS[2]

Last Valid

Addr

Address V1

R/W

LBA

Read

OE

EB (EBC=0)

EB (EBC=1)

ECB

DATA_IN

V1 1/2

V1 2/2

V2 1/2

V2 2/2

Figure 68. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 1, A.WORD/E.HALF

MC9328MX21S Technical Data, Rev. 1.3

78

Freescale Semiconductor

Specifications

3.19 DTACK Mode Memory Access Timing Diagrams

When enabled, the DTACK input signal is used to externally terminate a data transfer. For DTACK

enabled operations, a bus time-out monitor generates a bus error when an external bus cycle is not

terminated by the DTACK input signal after 1024 HCLK clock cycles have elapsed, where HCLK is the

internal system clock driven from the PLL module. For a 133 MHz HCLK setting, this time equates to

7.7 μs. Refer to the Section 3.5, “DPLL Timing Specifications” for more information on how to generate

different HCLK frequencies.

There are two modes of operation for the DTACK input signal: rising edge detection or level sensitive

detection with a programmable insensitivity time. DTACK is only used during external asynchronous data

transfers, thus the SYNC bit in the chip select control registers must be cleared.

During edge detection mode, the EIM will terminate an external data transfer following the detection of

the DTACK signal’s rising edge, so long as it occurs within the 1024 HCLK cycle time. Edge detection

mode is used for devices that follow the PCMCIA standard. Note that DTACK rising edge detection mode

can only be used for CS[5] operations. To configure CS[5] for DTACK rising edge detection, the following

bits must be programmed in the Chip Select 5 Control Register and EIM Configuration Register:

•

WSC bit field set to 0x3F and CSA (or CSN) set to 1 or greater in the Chip Select 5 Control Register

AGE bit set in the EIM Configuration Register

Other bits such as DSZ, OEA, OEN, and so on, may be set according to system and timing requirements

of the external device. The requirement of setting CSA or CSN is required to allow the EIM to wait for the

rising edge of DTACK during back-to-back external transfers, such as during DMA transfers or an internal

32-bit access through an external 16-bit data port.

During level sensitive detection, the EIM will first hold off sampling the DTACK signal for at least 2

HCLK cycles, and up to 5 HCLK cycles as programmed by the DCT bits in the Chip Select Control

Register. After this insensitivity time, the EIM will sample DTACK and if it detects that DTACK is logic

high, it will continue the data transfer at the programmed number of wait states. However, if the EIM

detects that DTACK is logic low, it will wait until DTACK goes to logic high to continue the access, so

long as this occurs within the 1024 HCLK cycle time. If at anytime during an external data transfer

DTACK goes to logic low, the EIM will wait until DTACK returns to logic high to resume the data transfer.

Level detection is often used for asynchronous devices such graphic controller chips. Level detection may

be used with any chip select except CS[4] as it is multiplexed with the DTACK signal. To configure a chip

select for DTACK level sensitive detection, the following bits must be programmed in the Chip Select

Control Register and EIM Configuration Register:

•

EW bit set, WSC set to > 1, and CSN set to < 3 in the Chip Select Control Register

BCD/DCT set to desired “insensitivity time” in the Chip Select Control Register. The “insensitivity time”

is dictated by the external device’s timing requirements.

•

AGE bit cleared in the EIM Configuration Register

Other bits such as DSZ, OEA, OEN, and so on, may be set according to system and timing requirements

of the external device.

The waveforms in the following section provide examples of the DTACK signal operation.

MC9328MX21S Technical Data, Rev. 1.3

Freescale Semiconductor

79

Specifications

3.19.1 DTACK Example Waveforms: Internal ARM AHB Word Accesses to

Word-Width (32-bit) Memory

HCLK

BCLK

Last Valid

Addr

V1

ADDR

CS[5]

Read

RW

LBA

OE

EB (EBC=0)

EB (EBC=1)

DTACK

DATA_IN

V1 Data

Figure 69. DTACK Edge Triggered Read Access, WSC=3F, OEA=8, OEN=5, AGE=1.

MC9328MX21S Technical Data, Rev. 1.3

80

Freescale Semiconductor

Specifications

HCLK

BCLK

Last Valid Addr

Address V1

V1+8

V1+4

ADDR

CS[0]

Read

RW

LBA

OE

EB (EBC=0)

EB (EBC=1)

DCT

DTACK

DATA_IN

V1 Word

V1+4 Word

V1+8 Word

Figure 70. DTACK Level Sensitive Sequential Read Accesses, WSC=2, EW=1, DCT=1, AGE=0 (Example of

DTACK Remaining High)

MC9328MX21S Technical Data, Rev. 1.3

Freescale Semiconductor

81

Specifications

HCLK

BCLK

ADDR

CS[0]

Address V1

V1+4

V1+8

Last Valid Addr

RWA

RWN

Write

RW

LBA

OE

EB

DCT

DTACK

V1 Word

V1+4 Word

V1+8

DATA_OUT

Figure 71. DTACK Level Sensitive Sequential Write Accesses, WSC=2, EW=1, RWA=1, RWN=1, DCT=1,

AGE=0 (Example of DTACK Asserting)

MC9328MX21S Technical Data, Rev. 1.3

82

Freescale Semiconductor

Specifications

2

3.20 I C Module

2

The I C communication protocol consists of seven elements: START, Data Source/Recipient, Data

Direction, Slave Acknowledge, Data, Data Acknowledge, and STOP.

SDA

3

4

5

SCL

1

6

2

Figure 72. Definition of Bus Timing for I C

2

Table 39. I C Bus Timing Parameters

1.8 V 0.1 V

3.0 V 0.3 V

Ref

No.

Parameter

Unit

Minimum

Maximum

Minimum

Maximum

SCL Clock Frequency

0

100

–

0

100

–

kHz

ns

1

2

3

4

5

6

Hold time (repeated) START condition

Data hold time

114.8

0

111.1

0

69.7

–

72.3

–

Data setup time

3.1

1.76

68.3

335.1

111.1

HIGH period of the SCL clock

LOW period of the SCL clock

Setup time for STOP condition

69.7

336.4

110.5

–

MC9328MX21S Technical Data, Rev. 1.3

Freescale Semiconductor

83

Pin Assignment and Package Information

4.1

MAPBGA Package Dimensions

Figure 73 illustrates the MAPBGA 14 mm × 14 mm × 1.41 mm package, which has 0.65 mm ball pitch.

Figure 73. i.MX21 MAPBGA Mechanical Drawing

MC9328MX21S Technical Data, Rev. 1.3

Freescale Semiconductor

85

Pin Assignment and Package Information

4.2

MAPBGA Package Dimensions

Figure 74 illustrates the MAPBGA 17 mm × 17 mm × 1.45 mm package, which has 0.8 mm spacing

between the pads.

Figure 74. i.MX21 MAPBGA Mechanical Drawing

MC9328MX21S Technical Data, Rev. 1.3

86

Freescale Semiconductor

Document Revision History

5 Document Revision History

Table 41 provides the document changes for the MC9328MX21S Rev. 1.3.

Table 41. Document Revision History

Location

Description of Change

Table 1 on page 3

Table 7 on page 14

Table 40 on page 84

Added VM and CVM devices.

Updated Sleep Current values..

Added Package Drawing for the 17mm x 17mm package.

MC9328MX21S Technical Data, Rev. 1.3

Freescale Semiconductor

87

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Document Number: MC9328MX21S

Rev. 1.3

06/2008


型号：	MC9328MX21SVKR2
厂家：	NXP
描述：	32-BIT, 266 MHz, MICROPROCESSOR, PBGA289, 14 X 14 MM, 1.41 MM HEIGHT, 0.65 MM PITCH, LEAD FREE, MAPBGA-289 时钟外围集成电路
文件：	总88页 (文件大小：905K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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