MC56F81XXX [NXP]
DSC based on 32-bit 56800EX core;型号: | MC56F81XXX |
厂家: | NXP |
描述: | DSC based on 32-bit 56800EX core |
文件: | 总73页 (文件大小:1117K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Document Number MC56F81XXX
Rev. 1.1, 12/2020
NXP Semiconductors
Data Sheet: Technical Data
MC56F81XXX
MC56F81xxx
Supports MC56F81xxx
Features
• One high resolution eFlexPWM module with up to 12
PWM outputs, including 8 channels with 312ps
resolution NanoEdge placement
• This family of digital signal controllers (DSCs) is
based on the 32-bit 56800EX core. On a single chip,
each device combines the processing power of a DSP
and the functionality of an MCU, with a flexible set of
peripherals to support many target applications:
– Industrial control
• Communication interfaces
– Up to two high-speed queued SCI (QSCI) modules
with LIN slave functionality
– One queued SPI (QSPI) modules
– Motion control
– Up to two LPI2C modules (Support Full PMBus)
– Home appliances
– General-purpose inverters
• Timers
– One 16-bit quad timer (1 x 4 16-bit timer)
– Two 32-bit Periodic Interval Timers (PITs)
– One Quadrature Decoder (QDC)
– Smart sensors, fire and security systems
– Wireless charging
– Switched-mode power supply and power
management
• Security and integrity
– Uninterruptible power supplies (UPS)
– Solar inverter
– Medical monitoring applications
– Cyclic Redundancy Check (CRC) generator
– Windowed Computer operating properly (COP)
watchdog
– External Watchdog Monitor (EWM)
• DSC based on 32-bit 56800EX core
– Up to 100 MIPS at 100 MHz core frequency in fast
mode
• Clocks
– On-chip oscillators: 200 kHz, and 8/2MHz IRC
– Crystal / resonator oscillator
– DSP and MCU functionality in a unified, C-efficient
architecture
• System
• On-chip memory
– 4-channel enhanced DMA controller, supporting up
to 63 request sources
– Up to 128 KB flash memory
– Up to 20 KB data/program RAM
– Both on-chip flash memory and RAM can be
mapped into both program and data memory spaces
– Boot ROM (supports boot from SCI, I2C)
– Integrated power-on reset (POR) and low-voltage
interrupt (LVI) and brown-out reset module
– Inter-Module Crossbar and Event Generator
– JTAG/enhanced on-chip emulation (EOnCE) for
unobtrusive, real-time debugging
• Analog
– Two high-speed, 12-bit ADCs with dynamic x1, x2,
and x4 programmable amplifier
– Two operational amplifiers, programmable gain up
to x16
• Operating characteristics
– Single supply: 2.7 V to 3.6 V
– Operation ambient temperature (V): -40 to 105°C
– Operation ambient temperature (M): -40 to 125°C
– Up to four analog comparators with integrated 8-bit
DAC references
– One 12-bit digital-to-analog converters (DAC)
– On-chip temperature sensors
• 64-pin LQFP, 48-pin LQFP, 32-pin LQFP and QFN
packages
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Table of Contents
1
Overview............................................................................................3
8.8 Definition: Typical value........................................................ 37
8.9 Typical value conditions......................................................... 38
Ratings................................................................................................38
9.1 Thermal handling ratings........................................................ 38
9.2 Moisture handling ratings........................................................38
9.3 ESD handling ratings.............................................................. 38
9.4 Voltage and current operating ratings..................................... 39
1.1 Product Family........................................................................ 3
1.2 56800EX 32-bit Digital Signal Controller (DSC) core...........4
1.3 Operation Parameters.............................................................. 4
1.4 Interrupt Controller................................................................. 5
1.5 Peripheral highlights............................................................... 5
1.6 System Block Diagram............................................................13
MC56F81xxx signal and pin descriptions..........................................15
Signal groups......................................................................................25
Pinout................................................................................................. 26
4.1 Signal Multiplexing and Pin Assignments..............................26
4.2 Pinout diagrams.......................................................................28
Ordering parts.....................................................................................31
5.1 Determining valid orderable parts...........................................31
5.2 Part number list....................................................................... 31
Part identification...............................................................................32
6.1 Description.............................................................................. 32
6.2 Format..................................................................................... 32
6.3 Fields....................................................................................... 32
6.4 Example...................................................................................33
Package marking information............................................................ 33
Terminology and guidelines...............................................................34
8.1 Definition: Operating requirement..........................................34
8.2 Definition: Operating behavior............................................... 34
8.3 Definition: Attribute................................................................35
8.4 Definition: Rating....................................................................35
8.5 Result of exceeding a rating....................................................35
8.6 Relationship between ratings and operating requirements......36
8.7 Guidelines for ratings and operating requirements................. 36
9
2
3
4
10 General............................................................................................... 39
10.1 General characteristics............................................................ 39
10.2 AC electrical characteristics....................................................40
10.3 Nonswitching electrical specifications....................................41
10.4 Switching specifications..........................................................47
10.5 Thermal specifications............................................................ 47
11 Peripheral operating requirements and behaviors..............................49
11.1 Core modules...........................................................................49
11.2 System modules.......................................................................50
11.3 Clock modules.........................................................................50
11.4 Memories and memory interfaces...........................................53
11.5 Analog..................................................................................... 55
11.6 PWMs and timers....................................................................61
11.7 Communication interfaces.......................................................62
12 Design Considerations....................................................................... 67
12.1 Thermal design considerations................................................67
12.2 Electrical design considerations..............................................69
12.3 Power-on Reset design considerations....................................70
13 Obtaining package dimensions.......................................................... 71
14 Product documentation.......................................................................72
15 Revision history................................................................................. 72
5
6
7
8
MC56F81xxx, Rev. 1.1, 12/2020
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NXP Semiconductors
Overview
1 Overview
1.1 Product Family
Table 1. MC56F81xxx Family
Feature
MC56F81
768
748
766
746
763
743
668
648
666
646
663
643
Core frequency (MHz)
Flash memory (KB)
RAM (KB)
100 / 50
128
20
64
12
128
20
64
12
128
20
64
12
128
20
64
12
128
20
64
12
128
20
64
12
Boot ROM
Yes (supports SCI, I2C)
Inter Module Xbar
Event Generator
Yes
4
Windowed Watchdog
External Watchdog Monitor
eDMA
1
1
4CH
Internal OSC
8 MHz / 200 KHz
External Crystal Oscillator
Comparator + 8bit DAC
Operational Amplifier
12-bit Cyclic ADC channels
NanoEdge PWM: high-resolution
Standard PWM with Input capture
QTimers
Yes (4 MHz ~ 16 MHz)
4
2
3
1
4
2
3
1
2 x 8-ch
2 x 5-ch
2 x 3-ch
2 x 8-ch
2 x 5-ch
2 x 3-ch
6-ch 1
—
8-ch
4-ch
6-ch 1
—
2-ch
—
8-ch + 4-ch 6-ch + 2-ch1
4 x 16bit
Quadrature Decoder
Periodic Interval Timers
12bit DAC
1
—
1
2 x 32bit
1
—
LPI2C (supports Full PMBus)
QSCI
2
2
1
2
1
1
QSPI
1
—
GPIO
54
39
26
54
39
26
Operating Temperature
-40℃ to 105℃ (V temperature)
-40℃ to 125℃ (M temperature)
-40℃ to 105℃ (V temperature)
Package
64 LQFP
48 LQFP
32
LQFP/QFN 2
64 LQFP
48 LQFP
32
LQFP/QFN 2
1. Only include the PWM channels with output pins. All internal 8 channels PWM are available through the on-chip inter-
module crossbar.
2. The 32 LQFP and 32 QFN packages for this product are not yet available. However, the pin-out and pricing information of
these packages are readily available. These devices are then committed for sampling and production based on customer
demand.
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Overview
1.2 56800EX 32-bit Digital Signal Controller (DSC) core
• Efficient 32-bit 56800EX Digital Signal Processor (DSP) engine with modified dual
Harvard architecture:
• Three internal address buses
• Four internal data buses: two 32-bit primary buses, one 16-bit secondary data
bus, and one 16-bit instruction bus
• 32-bit data accesses
• Supports concurrent instruction fetches in the same cycle, and dual data accesses
in the same cycle
• 20 addressing modes
• 162 basic instructions
• Instruction set supports both fractional arithmetic and integer arithmetic
• 32-bit internal primary data buses support 8-bit, 16-bit, and 32-bit data movement,
plus addition, subtraction, and logical operations
• Single-cycle 16 × 16-bit -> 32-bit and 32 x 32-bit -> 64-bit multiplier-accumulator
(MAC) with dual parallel moves
• 32-bit arithmetic and logic multi-bit shifter
• Four 36-bit accumulators, including extension bits
• Parallel instruction set with unique DSP addressing modes
• Hardware DO and REP loops
• Bit reverse address mode, which effectively supports DSP and Fast Fourier
Transform algorithms
• Full shadowing of the register stack for zero-overhead context saves and restores:
nine shadow registers correspond to nine address registers (R0, R1, R2, R3, R4, R5,
N, N3, M01)
• Instruction set supports both DSP and controller functions
• Controller-style addressing modes and instructions enable compact code
• Enhanced bit manipulation instruction set
• Efficient C compiler and local variable support
• Software subroutine and interrupt stack, with the stack's depth limited only by
memory
• Priority level setting for interrupt levels
• JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, real-time debugging
that is independent of processor speed
1.3 Operation Parameters
• 50 MHz core frequency in normal mode, 100 MHz core frequency in fast mode.
• Operation ambient temperature:
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Peripheral highlights
V Temperature option:-40 oC to 105oC
M Temperature option:-40 oC to 125oC
• Single 3.3 V power supply
• Supply range: VDD - VSS = 2.7 V to 3.6 V, VDDA - VSSA = 2.7 V to 3.6 V
1.4 Interrupt Controller
• Five interrupt priority levels
• Three user-programmable priority levels for each interrupt source: level 0, level
1, level 2
• Unmaskable level 3 interrupts include illegal instruction, hardware stack
overflow, misaligned data access, SWI3 instruction
• Interrupt level 3 is highest priority and non-maskable. Its sources include:
• Illegal instructions
• Hardware stack overflow
• SWI instruction
• EOnce interrupts
• Misaligned data accesses
• Lowest-priority software interrupt: level LP
• Support for nested interrupts, so that a higher priority level interrupt request can
interrupt lower priority interrupt subroutine
• Masking of interrupt priority level is managed by the 56800EX core
• Two programmable fast interrupts that can be assigned to any interrupt source
• Notification to System Integration Module (SIM) to restart clock when in wait and
stop states
• Ability to relocate interrupt vector table
1.5 Peripheral highlights
1.5.1 Enhanced Flex Pulse Width Modulator (eFlexPWM)
• 16 bits of resolution for center, edge-aligned, and asymmetrical PWMs
• PWMA with NanoEdge high resolution
• Fractional delay for enhanced resolution of the PWM period and edge placement
• Arbitrary PWM edge placement
• 312 ps PWM frequency and duty-cycle resolution when NanoEdge functionality
is enabled.
• PWM outputs can be configured as complementary output pairs or independent
outputs
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Peripheral highlights
• Dedicated time-base counter with period and frequency control per submodule
• Independent top and bottom deadtime insertion for each complementary pair
• Independent control of both edges of each PWM output
• Enhanced input capture and output compare functionality on each input:
• Channels not used for PWM generation can be used for buffered output compare
functions.
• Channels not used for PWM generation can be used for input capture functions.
• Enhanced dual edge capture functionality
• Synchronization of submodule to external hardware (or other PWM) is supported.
• Double-buffered PWM registers
• Integral reload rates from 1 to 16
• Half-cycle reload capability
• Multiple output trigger events can be generated per PWM cycle via hardware.
• Support for double-switching PWM outputs
• Up to eight fault inputs can be assigned to control multiple PWM outputs
• Programmable filters for fault inputs
• Independently programmable PWM output polarity
• Individual software control of each PWM output
• All outputs can be programmed to change simultaneously via a FORCE_OUT event.
• PWMX pin can optionally output a third PWM signal from each submodule
• Option to supply the source for each complementary PWM signal pair from any of
the following:
• Crossbar module outputs
• External ADC input, taking into account values set in ADC high and low limit
registers
• 312 ps resolution can be enabled for period, duty and deadtime related registers
• Direct phase shift controls among each submodule
• Trigger signal can share the same load frequency as reload signal in each submodule
1.5.2 12-bit Analog-to-Digital Converter (Cyclic type)
• Two independent 12-bit analog-to-digital converters (ADCs):
• 2 x 8-channel external inputs
• Built-in x1, x2, x4 programmable gain pre-amplifier
• Maximum ADC clock frequency up to 12.5 MHz, having period as low as 80 ns
• Single conversion time of 10 ADC clock cycles
• Additional conversion time of 8 ADC clock cycles
• Support of analog inputs for single-ended and differential (including unipolar
differential) conversions
• Sequential and parallel scan modes. Parallel mode includes simultaneous and
independent scan modes.
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Peripheral highlights
• Samples of each ADC have offset, limit and zero-crossing calculation supported
• ADC conversions can be synchronized by any module connected to the internal
crossbar module, such as PWM, timer, GPIO, and comparator modules.
• Support for hardware-triggering and software-triggering conversions
• Support for a multi-triggering mode with a programmable number of conversions on
each trigger
• Each ADC has ability to scan and store up to 8 conversion results.
• Current injection protection
1.5.3 Operational Amplifier (OPAMP)
• Up to four sets for rotation configuration
• Configurable gain through internal channels
• Obtain gain through external channels
• Optional clocks for counter
• Low power technology
• Optimize transient response
1.5.4 12-bit Digital-to-Analog Converter
• 12-bit resolution
• Powerdown mode
• Automatic mode allows the DAC to automatically generate pre-programmed output
waveforms, including square, triangle, and sawtooth waveforms (for applications like
slope compensation)
• Programmable period, update rate, and range
• Output can be routed to an internal comparator, or optionally to an off-chip
destination
1.5.5 Comparator
• Full rail-to-rail comparison range
• Support for high and low speed modes
• Selectable input source includes external pins and internal DACs
• Programmable output polarity
• 8-bit programmable DAC as a voltage reference per comparator
• Three programmable hysteresis levels
• Selectable interrupt on rising-edge, falling-edge, or toggle of a comparator output
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Peripheral highlights
1.5.6 Periodic Interrupt Timer (PIT) Modules
• 32-bit counter with programmable count modulo
• PIT0 is master and PIT1 is slave (if synchronizing both PITs)
• The output signals of both PIT0 and PIT1 are internally connected to a peripheral
crossbar module
• Can run when the CPU is in Wait/Stop modes. Can also wake up the CPU from
Wait/Stop modes.
• In addition to its existing bus clock (up to 50 MHz), 3 alternate clock sources for the
counter clock are available:
• Crystal oscillator output
• 8 MHz / 2 MHz internal RC output
• On-chip low-power 200 kHz oscillator
1.5.7 Quadrature Decoder (QDC)
• Includes logic to decode quadrature signals
• Inputs can be connected to a general purpose timer to make low speed velocity
measurements
• Configurable digital filter for inputs
• Quadrature decoder filter can be bypassed
• 32-bit position counter capable of modulo counting
• Position counter can be initialized by software or external events
• 16-bit position difference register
• Compare function can indicate when shaft has reached a defined position
• A watchdog timer can detect a non-rotating shaft condition
• Preloadable 16-bit revolution counter
• Maximum count frequency equals the peripheral clock rate
• Optional interrupt when both PHASEA and PHASEB inputs change in the same
cycle
1.5.8 Inter-Module Crossbar and Event Generator (EVTG) logic
• Provides generalized connections between and among on-chip peripherals: ADCs,
12-bit DAC, comparators, quad-timers, eFlexPWMs, EWM, quadrature decoder, and
select I/O pins
• User-defined input/output pins for all modules connected to the crossbar
• DMA request and interrupt generation from the crossbar
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Peripheral highlights
• Write-once protection for all registers
• The EVTG module mainly includes two parts: Two AND/OR/INVERT (known
simply as the AOI) modules and one configurable Flip-Flop. It supports the
generation of a configurable number of EVENT signals. The inputs are from crossbar
(XBAR) outputs, and the outputs feed to XBAR inputs.
1.5.9 Quad Timer
• Four 16-bit up/down counters, with a programmable prescaler for each counter
• Operation modes: edge count, gated count, signed count, capture, compare, PWM,
signal shot, single pulse, pulse string, cascaded, quadrature decode
• Programmable input filter
• Counting start can be synchronized across counters
1.5.10 Queued Serial Communications Interface (QSCI) modules with
LIN Slave Functionality
• Operating clock can be up to two times the CPU operating frequency
• Four-word-deep FIFOs available on both transmit and receive buffers
• Standard mark/space non-return-to-zero (NRZ) format
• 16-bit integer and 3-bit fractional baud rate selection
• Full-duplex or single-wire operation
• Programmable 8-bit or 9-bit data format
• Error detection capability
• Two receiver wakeup methods:
• Idle line
• Address mark
• 1/16 bit-time noise detection
• Support for Local Interconnect Network (LIN) slave operation
1.5.11 Queued Serial Peripheral Interface (QSPI) modules
• Maximum 25 Mbit/s baud rate
• Selectable baud rate clock sources for low baud rate communication
• Baud rate as low as the maximum Baud rate / 4096
• Full-duplex operation
• Master and slave modes
• Double-buffered operation with separate transmit and receive registers
• Four-word-deep FIFOs available on transmit and receive buffers
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Peripheral highlights
• Programmable length transmissions (2 bits to 16 bits)
• Programmable transmit and receive shift order (MSB or LSB as first bit transmitted)
1.5.12 Low Power Inter-Integrated Circuit (LPI2C)
The LPI2C supports:
• Standard, Fast, Fast+ and Ultra Fast modes are supported
• High speed mode (HS) in slave mode
• High speed mode (HS) in master mode, if SCL pin implements current source pull-
up (device-specific)
• Multi-master support, including synchronization and arbitration. Multi-master means
any number of master nodes can be present. Additionally, master and slave roles may
be changed between messages (after a STOP is sent).
• Clock stretching: Sometimes multiple I2C nodes may be driving the lines at the same
time. If any I2C node is driving a line low, then that line will be low. I2C nodes that
are starting to transmit a logical one (by letting the line float high) can detect that the
line is low, and thereby know that another I2C node is active at the same time.
• When node detection is used on the SCL line, it is called clock stretching, and
clock stretching is used as a I2C flow control mechanism for multiple laves.
• When node detection is used on the SDA line, it is called arbitration, and
arbitration ensures that there is only one I2C node transmitter at a time.
• General call, 7-bit and 10-bit addressing
• Software reset, START byte and Device ID (also require software support)
The LPI2C master supports:
• Command/transmit FIFO of 4words.
• Receive FIFO of 4words.
• Command FIFO will wait for idle I2C bus before initiating transfer
• Command FIFO can initiate (repeated) START and STOP conditions and one or
more master-receiver transfers
• STOP condition can be generated from command FIFO, or generated automatically
when the transmit FIFO is empty
• Host request input to control the start time of an I2C bus transfer
• Flexible receive data match can generate interrupt on data match and/or discard
unwanted data
• Flag and optional interrupt to signal Repeated START condition, STOP condition,
loss of arbitration, unexpected NACK, and command word errors
• Supports configurable bus idle timeout and pin-stuck-low timeout
The LPI2C slave supports:
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Peripheral highlights
• Separate I2C slave registers to minimize software overhead because of master/slave
switching
• Support for 7-bit or 10-bit addressing, address range, SMBus alert and general call
address
• Transmit data register that supports interrupt or DMA requests
• Receive data register that supports interrupt or DMA requests
• Software-controllable ACK or NACK, with optional clock stretching on ACK/
NACK bit
• Configurable clock stretching, to avoid transmit FIFO underrun and receive FIFO
overrun errors
• Flag and optional interrupt at end of packet, STOP condition, or bit error detection
1.5.13 Windowed Computer Operating Properly (COP) watchdog
• Programmable windowed timeout period
• Support for operation in all power modes: run mode, wait mode, stop mode
• Causes loss of reference reset 128 cycles after loss of reference clock to the PLL is
detected
• Selectable reference clock source in support of EN60730 and IEC61508
• Selectable clock sources:
• External crystal oscillator
• On-chip low-power 200 kHz oscillator
• System bus (IPBus up to 50 MHz)
• 8 MHz / 2 MHz IRC
• Support for interrupt generation
1.5.14 External Watchdog Monitor (EWM)
• Monitors external circuit as well as the software flow
• Programmable timeout period
• Interrupt capability prior to timeout
• Independent output (EWM_OUT_b) that places external circuit (but not CPU and
peripheral) in a safe mode when EWM timeout occurs
• Selectable reference clock source in support of EN60730 and IEC61508
• Wait mode and Stop mode operation is not supported.
• Selectable clock sources:
• External crystal oscillator
• On-chip low-power 200 kHz oscillator
• System bus (IPBus up to 50 MHz)
• 8 MHz / 2 MHz IRC
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Clock sources
1.5.15 Power supervisor
• Power-on reset (POR) is released after VDD > 2.7 V during supply is ramped up;
CPU, peripherals, and JTAG/EOnCE controllers exit RESET state
• Brownout reset (VDD < 2.0 V)
• Critical warn low-voltage interrupt (LVI 2.2 V)
• Peripheral low-voltage warning interrupt (LVI 2.7 V)
1.5.16 Phase-locked loop
• Output frequency range is optimized from 200 MHz to 550 MHz
• Input reference clock frequency: 8 MHz to 16 MHz
• Detection of loss of lock and loss of reference clock
• Ability to power down
1.5.17 Clock sources
1.5.17.1 On-chip oscillators
• Tunable 8 MHz RC oscillator with 2 MHz at standby mode
• 200 kHz low frequency clock as secondary clock source for COP, EWM, PIT
1.5.17.2 Crystal oscillator
• Support for both high ESR crystal oscillator (ESR greater than 100 Ω) and ceramic
resonator
• Operating frequency: 4–16 MHz
1.5.18 Cyclic Redundancy Check (CRC) generator
• Hardware 16/32-bit CRC generator
• High-speed hardware CRC calculation
• Programmable initial seed value
• Programmable 16/32-bit polynomial
• Error detection for all single, double, odd, and most multi-bit errors
• Option to transpose input data or output data (CRC result) bitwise or bytewise,1
which is required for certain CRC standards
• Option for inversion of final CRC result
1. A bytewise transposition is not possible when accessing the CRC data register via 8-bit accesses. In this case, user
software must perform the bytewise transposition.
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Clock sources
1.5.19 General Purpose I/O (GPIO)
• Individual control of peripheral mode or GPIO mode for each pin
• Programmable push-pull or open drain output
• Configurable pullup or pulldown on all input pins
• All pins (except JTAG, RESET_B ) default to be GPIO inputs
• Controllable output slew rate
1.6 System Block Diagram
NOTE
The following figure shows the maximum memory
configurations supported.
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Clock sources
ROM Patch
Controller
Boot ROM
32 KB
JTAG
Program Bus
Core Data Bus
EOnCE
56800EX CPU
M0
M1
Program
Controller
(PC)
Address
Generation
Unit (AGU)
Program/Data Flash
Up to 128 KB
S0
Secondary Data Bus
4
M2
M3
Arithmetic
Logic Unit
(ALU)
Bit
Manipulation
Unit
Data/Program RAM
Up to 20 KB
S1
S3 S2
eDMA Controller
Watchdog (COP)
Interrupt Controller
Crystal OSC
Internal IRC
2 MHz/ 8 MHz
Power Management
Controller (PMC)
Internal IRC
200 kHz
System Integration
Module (SIM)
Periodic Interrupt
Timer (PIT32) 0,1
PLL
CRC
Peripheral Bus
QSCI
0,1
eFlexPWM
NanoEdge
LPI2C
0,1
Quad Timer
4ch
Quadrature
Decoder
QSPI
Inter Module Crossbar Inputs Inter Module connction
Inter Module Crossbar Outputs
Event
Generator
GPIO & Peripheral MUX
Inter-Module
Crossbar
Inter Module Crossbar Outputs
Inter Module Crossbar Inputs
Package
Pins
Compartors With
8bit DAC A,B,C,D
ADCB
12Bit
DAC
12Bit
ADCA
12Bit
Op-Amp
0.1
EWM
Peripheral Bus
Figure 1. System block diagram
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MC56F81xxx signal and pin descriptions
2 MC56F81xxx signal and pin descriptions
After reset, each pin is configured for its primary function (listed first). Any alternative
functionality, shown in parentheses, must be programmed through the GPIO module
peripheral enable registers (GPIOx_PER) and the SIM module GPIO peripheral select
(GPSx) registers. All GPIO ports can be individually programmed as an input or output
(using bit manipulation).
For the MC56F81xxx products, which use 64-pin LQFP, 48-pin LQFP and 32-pin LQFP
packages:
Table 2. Signal descriptions
Signal Name
64
48
32
State
Type
Signal Description
LQFP LQFP LQFP/ During
QFN
Reset
VDD
29
44
60
30
43
61
22
—
32
44
22
31
45
15
—
Supply
Supply
I/O Power — Supplies 3.3 V power to the chip I/O
interface.
—
28
14
—
29
9
VSS
Supply
Supply
I/O Ground — Provide ground for the device I/O
interface.
VDDA
VSSA
VCAP
Supply
Supply
Supply
Supply
Analog Power — Supplies 3.3 V power to the analog
modules. It must be connected to a clean analog power
supply.
23
16
10
Analog Ground — Supplies an analog ground to the
analog modules. It must be connected to a clean power
supply.
26
57
19
43
—
On-chip On-chip Connect a 2.2 µF or greater bypass capacitor between
regulator regulator this pin and VSS to stabilize the core voltage regulator
output
27
output
output required for proper device operation.
NOTE: The total bypass capacitor value between all
VCAP pins and VSS recommends between
4.0uF ~ 5.0uF.
TDI
64
62
48
46
32
30
Input,
internal
pullup
Input
Test Data Input — Provides a serial input data stream
to the JTAG/EOnCE port. It is sampled on the rising
edge of TCK and has an internal pullup resistor. After
reset, the default state is TDI.
enabled
(GPIOD0)
Input/
Output
GPIO Port D0.
TDO
Output
Output
Test Data Output — This tri-state-able pin provides a
serial output data stream from the JTAG/EOnCE port. It
is driven in the shift-IR and shift-DR controller states,
and it changes on the falling edge of TCK. After reset,
the default state is TDO.
(GPIOD1)
Input/
GPIO Port D1.
Output
Table continues on the next page...
MC56F81xxx, Rev. 1.1, 12/2020
NXP Semiconductors
15
MC56F81xxx signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
64
LQFP LQFP LQFP/ During
QFN Reset
48
32
State
Type
Signal Description
TCK
1
1
1
Input,
Input
Test Clock Input — This input pin provides a gated
clock to synchronize the test logic and shift serial data
to the JTAG/EOnCE port.The pin is connected
internally to a pulldown resistor. A Schmitt-trigger input
is used for noise immunity. After reset, the default state
is TCK.
internal
pulldown
enabled
(GPIOD2)
Input/
GPIO Port D2.
Output
TMS
63
47
31
Input,
internal
pullup
Input
Test Mode Select Input — Used to sequence the JTAG
TAP controller state machine. It is sampled on the
rising edge of TCK and has an internal pullup resistor.
After reset, the default state is TMS.
enabled
NOTE: Always tie the TMS pin to VDD through a 2.2
kΩ resistor if need to keep on-board debug
capability. Otherwise, directly tie to VDD
Except being configured as GPIO.
.
(GPIOD3)
Input/
GPIO Port D3.
Output
RESET
2
2
2
Input,
internal
pullup
Input
Reset — A direct hardware reset on the processor.
When RESET is asserted low, the device is initialized
and placed in the reset state. A Schmitt-trigger input is
used for noise immunity. The internal reset signal is
deasserted synchronously with the internal clocks after
a fixed number of internal clocks. After reset, the
default state is RESET. Recommended a capacitor of
0.1 µF for filtering noise and up to 22 µF for time delay
if required.
enabled
(GPIOD4)
Input/
Open-
drain
GPIO Port D4 — Can be individually programmed as
an input or open-drain output pin. RESET functionality
is disabled in this mode and the device can be reset
only through Power-On Reset (POR), COP reset, or
software reset.
Output
GPIOA0
13
9
6
Input
Input/
Output
GPIO Port A0 — After reset, the default state is
GPIOA0.
(ANA0
Input
ANA0 — ADCA input channel 0.
&
CMPA_IN3 — Analog comparator A input 3
OPAMPA_IN3 — Operational amplifier A input 3
CMPA_IN3
&
When used as an analog input, the signal goes to
ANA0 and CMPA_IN3 and OPAMPA_IN3. 1
OPAMPA_IN3)
(CMPC_O)
GPIOA1
Output
Analog comparator C output.
14
10
7
Input
Input/
Output
GPIO Port A1 — After reset, the default state is
GPIOA1.
(ANA1
&
Input
ANA1 — ADCA input channel 1.
CMPA_IN0 — Analog comparator A input 0.
OPAMPA_IN0 — Operational amplifier A input 0.
CMPA_IN0
Table continues on the next page...
MC56F81xxx, Rev. 1.1, 12/2020
16
NXP Semiconductors
MC56F81xxx signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
64
LQFP LQFP LQFP/ During
QFN Reset
48
32
State
Type
Signal Description
&
When used as an analog input, the signal goes to
ANA1 and CMPA_IN0 and OPAMPA_IN0.1
OPAMPA_IN0)
GPIOA2
15
11
8
Input
Input/
Output
GPIO Port A2 — After reset, the default state is
GPIOA2.
(ANA2
Input
ANA2 — ADCA input channel 2.
&
VREFHA — ADCA analog reference high.
CMPA_IN1 — Analog comparator A input 1.
OPAMPA_IN1 — Operational amplifier A input 1.
VREFHA
&
CMPA_IN1
&
When used as an analog input, the signal goes to
ANA2 (or VREFHA) and CMPA_IN1 and
OPAMPA_IN1. 1
OPAMPA_IN1)
NOTE: ADC input can be configured as either ANA2
or VREFHA in the ADC Calibration Register.
GPIOA3
16
12
—
Input
Input/
Output
GPIO Port A3 — After reset, the default state is
GPIOA3.
(ANA3
Input
ANA3 — ADCA input channel 3.
&
VREFLA — ADCA analog reference low.
CMPA_IN2 — Analog comparator A input 2.
OPAMPA_IN2 — Operational amplifier A input 2.
VREFLA
&
CMPA_IN2
&
When used as an analog input, the signal goes to
ANA3 (or VREFLA) and CMPA_IN2 and
OPAMPA_IN2.1
OPAMPA_IN2)
NOTE: ADC input can be configured as either ANA3
or VREFLA in the ADC Calibration Register.
GPIOA4
12
11
10
8
—
—
—
Input
Input
Input
Input/
Output
GPIO Port A4 — After reset, the default state is
GPIOA4.
(ANA4
&
Input
ANA4 — ADCA input channel 4.
CMPD_IN0 — Analog comparator D input 0.
CMPD_IN0)
When used as an analog input, the signal goes to
ANA4 and CMPD_IN0.1
GPIOA5
—
—
Input/
Output
GPIO Port A5 — After reset, the default state is
GPIOA5.
(ANA5
&
Input
ANA5 — ADCA input channel 5.
CMPD_IN1 — Analog comparator D input 1.
CMPD_IN1)
When used as an analog input, the signal goes to
ANA5 and CMPD_IN1.1
GPIOA6
Input/
Output
GPIO Port A6 — After reset, the default state is
GPIOA6.
(ANA6
&
Input
ANA6 — ADCA input channel 6.
CMPD_IN2 — Analog comparator D input 2.
CMPD_IN2)
Table continues on the next page...
MC56F81xxx, Rev. 1.1, 12/2020
NXP Semiconductors
17
MC56F81xxx signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
64
LQFP LQFP LQFP/ During
QFN Reset
48
32
State
Type
Signal Description
When used as an analog input, the signal goes to
ANA6 and CMPD_IN2.1
GPIOA7
9
—
—
Input
Input/
Output
GPIO Port A7 — After reset, the default state is
GPIOA7.
(ANA7
&
Input
ANA7 — ADCA input channel 7.
CMPD_IN3 — Analog comparator D input 3.
CMPD_IN3)
When used as an analog input, the signal goes to
ANA7 and CMPD_IN3.1
GPIOB0
24
17
11
12
13
Input
Input
Input
Input/
Output
GPIO Port B0 — After reset, the default state is
GPIOB0.
(ANB0
Input
ANB0 — ADCB input channel 0.
&
CMPB_IN3 — Analog comparator B input 3.
OPAMPB_IN3 — Operational amplifier B input 3.
CMPB_IN3
&
When used as an analog input, the signal goes to
ANB0 and CMPB_IN3 and OPAMPB_IN3.1
OPAMPB_IN3)
GPIOB1
25
18
Input/
Output
GPIO Port B1 — After reset, the default state is
GPIOB1.
(ANB1
Input
ANB1 — ADCB input channel 1.
&
CMPB_IN0 —Analog comparator B input 0.
OPAMPB_IN0 — Operational amplifier B input 0.
CMPB_IN0
&
When used as an analog input, the signal goes to
ANB1 and CMPB_IN0 and OPAMPB_IN0.1
OPAMPB_IN0)
GPIOB2
27
20
Input/
Output
GPIO Port B2 — After reset, the default state is
GPIOB2.
(ANB2
Input
ANB2 — ADCB input channel 2.
&
VREFHB — ADCB analog reference high.
CMPC_IN3 — Analog comparator C input 3.
VREFHB
&
When used as an analog input, the signal goes to
ANB2 (or VREFHB) and CMPC_IN3.1
CMPC_IN3)
NOTE: ADC input can be configured as either ANB2
or VREFHB in the ADC Calibration Register.
GPIOB3
28
21
—
Input
Input/
Output
GPIO Port B3 — After reset, the default state is
GPIOB3.
(ANB3
Input
ANB3 — ADCB input channel 3.
&
VREFLB — ADCB analog reference low.
CMPC_IN0 _ Analog comparator C input 0.
VREFLB
&
When used as an analog input, the signal goes to
ANB3 (or VREFHB) and CMPC_IN0.1
CMPC_IN0)
NOTE: ADC input can be configured as either ANB3
or VREFLB in the ADC Calibration Register.
Table continues on the next page...
MC56F81xxx, Rev. 1.1, 12/2020
18
NXP Semiconductors
MC56F81xxx signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
64
LQFP LQFP LQFP/ During
QFN Reset
48
32
State
Type
Signal Description
GPIOB4
21
20
19
14
—
—
—
Input
Input/
Output
GPIO Port B4 — After reset, the default state is
GPIOB4.
(ANB4
&
Input
ANB4 — ADCB input channel 4.
CMPC_IN1 — Analog comparator C input 1.
CMPC_IN1)
When used as an analog input, the signal goes to
ANB4 and CMPC_IN1.1
GPIOB5
—
—
Input
Input
Input/
Output
GPIO Port B5 — After reset, the default state is
GPIOB5.
(ANB5
&
Input
ANB5 — ADCB input channel 5.
CMPC_IN2 — Analog comparator C input 2.
CMPC_IN2)
When used as an analog input, the signal goes to
ANB5 and CMPC_IN2.1
GPIOB6
Input/
Output
GPIO Port B6 — After reset, the default state is
GPIOB6.
(ANB6
Input
ANB6 — ADCB input channel 6.
&
CMPB_IN1 — Analog comparator B input 1.
OPAMPB_IN1 — Operational amplifier B input 1.
CMPB_IN1
&
When used as an analog input, the signal goes to
ANB6 and CMPB_IN1 and OPAMPB_IN1. 1
OPAMPB_IN1)
GPIOB7
17
—
—
Input
Input/
Output
GPIO Port B7 — After reset, the default state is
GPIOB7.
(ANB7
Input
ANB7 — ADCB input channel 7.
&
CMPB_IN2 — Analog comparator B input 2.
OPAMPB_IN2 — Operational amplifier B input 2.
CMPB_IN2
&
When used as an analog input, the signal goes to
ANB7 and CMPB_IN2 and OPAMPB_IN2.1
OPAMPB_IN2)
GPIOC0
3
3
—
Input
Input/
Output
GPIO Port C0 — After reset, the default state is
GPIOC0.
(EXTAL)
(CLKIN0)
Input
External crystal oscillator input (EXTAL) connects the
internal crystal oscillator input to an external crystal or
ceramic resonator.
Input
External clock input 0 to OCCS.
NOTE: If this pin is selected as the device’s external
clock input, then both SIM_GPSCL[C0] bit in
SIM and OSCTL1[EXT_SEL] bit in OCCS
must be set. The crystal oscillator should be
powered down.
GPIOC1
4
4
—
Input
Input/
Output
GPIO Port C1 — After reset, the default state is
GPIOC1.
(XTAL)
Output
External crystal oscillator output (XTAL) connects the
internal crystal oscillator output to an external crystal or
ceramic resonator.
Table continues on the next page...
MC56F81xxx, Rev. 1.1, 12/2020
NXP Semiconductors
19
MC56F81xxx signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
64
LQFP LQFP LQFP/ During
QFN Reset
48
32
State
Type
Signal Description
GPIOC2
5
5
3
Input
Input/
Output
GPIO Port C2 — After reset, the default state is
GPIOC2.
(TXD0)
Output
SCI0 transmit data output or transmit/receive in single
wire operation.
(XB_OUT11)
(XB_IN2)
Output
Input
Crossbar module output 11.
Crossbar module input 2.
Buffered clock output 0.
(CLKO0)
Output
NOTE: The clock source is selected by
SIM_CLKOUT[CLKOSEL0] bits in SIM.
GPIOC3
7
6
4
Input
Input/
Output
GPIO Port C3 — After reset, the default state is
GPIOC3.
(TA0)
Input/
Quad timer channel 0 input/output.
Output
(CMPA_O)
(RXD0)
Output
Input
Analog comparator A output.
SCI0 receive data input.
(CLKIN1)
Input
External clock input 1 to OCCS.
NOTE: If this pin is selected as device's external clock
input, then both SIM_GPSCL[C3] bits in SIM
and OSCTL1[EXT_SEL] bit in OCCS must be
set.
GPIOC4
8
7
5
Input
Input/
Output
GPIO Port C4 — After reset, the default state is
GPIOC4.
(TA1)
Input/
Quad timer channel 1 input/output.
Output
(CMPB_O)
(XB_IN8)
Output
Input
Analog comparator B output.
Crossbar module input 8.
(OPAMPA_OUT)
GPIOC5
Output
Operational amplifier A output.
18
31
13
23
—
Input
Input
Input/
Output
GPIO Port C5 — After reset, the default state is
GPIOC5.
(DACA_O)
(XB_IN7)
GPIOC6
Output
Input
12-bit digital-to-analog output.
Crossbar module input 7.
15
Input/
Output
GPIO Port C6 — After reset, the default state is
GPIOC6.
(TA2)
Input/
Quad timer channel 2 input/output.
Output
(XB_IN3)
(CMP_REF)
(SS0_B)
Input
Input
Crossbar module input 3.
Input 5 of analog comparator A and B and C and D.
SPI0 slave select.
Input/
Output
GPIOC7
32
24
—
Input
Input/
Output
GPIO Port C7 — After reset, the default state is
GPIOC7.
Table continues on the next page...
MC56F81xxx, Rev. 1.1, 12/2020
20
NXP Semiconductors
MC56F81xxx signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
64
LQFP LQFP LQFP/ During
QFN Reset
48
32
State
Type
Signal Description
(SS0_B)
Input/
SPI0 slave select.
Output
(TXD0)
Output
SCI0 transmit data output or transmit/receive in single
wire operation.
(XB_IN8)
(XB_OUT6)
GPIOC8
Input
Crossbar module input 8.
Crossbar module output 6.
Output
33
34
25
26
16
Input
Input/
Output
GPIO Port C8 — After reset, the default state is
GPIOC8.
(MISO0)
Input/
Output
SPI0 master in/slave out.
(RXD0)
Input
Input
SCI0 receive data input.
Crossbar module input 9.
(XB_IN9)
GPIOC9
17
18
—
Input
Input
Input
Input/
Output
GPIO Port C9 — After reset, the default state is
GPIOC9.
(SCLK0)
Input/
Output
SPI0 serial clock.
(XB_IN4)
(TXD0)
Input
Crossbar module input 4.
Output
SCI0 transmit data output or transmit/receive in single
wire operation.
(XB_OUT8)
Output
Crossbar module output 8.
GPIOC10
35
27
Input/
Output
GPIO Port C10 — After reset, the default state is
GPIOC10.
(MOSI0)
Input/
Output
SPI0 master out/slave.
(XB_IN5)
(MISO0)
Input
Crossbar module input 5.
SPI0 master in/slave out.
Input/
Output
(XB_OUT9)
Output
Crossbar module output 9.
GPIOC11
37
29
Input/
Output
GPIO Port C11 — After reset, the default state is
GPIOC11.
(LP_SCLS0)
(LP_SCL1)
Output
I2C0 secondary serial clock line.
NOTE: In 4-wire mode, this is the I2C slave SCL
output for voltage level shift.
I2C1 serial clock line.
Input/
Open-
drain
NOTE: In 4-wire mode, this is the I2C slave SCL input.
Output
(TXD1)
Output
SCI1 transmit data output or transmit/receive in single
wire operation.
(PWMA_0X)
Output
PWM submodule 0, output X or input capture X.
GPIOC12
38
30
—
Input
Input/
Output
GPIO Port C12 — After reset, the default state is
GPIOC12.
(LP_SDAS0)
Output
I2C0 secondary serial data line.
Table continues on the next page...
MC56F81xxx, Rev. 1.1, 12/2020
NXP Semiconductors
21
MC56F81xxx signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
64
LQFP LQFP LQFP/ During
QFN Reset
48
32
State
Type
Signal Description
NOTE: In 4-wire mode, this is the I2C slave SDA
output for voltage level shift.
(LP_SDA1)
Input/
I2C1 serial data line
Open-
drain
Output
NOTE: In 4-wire mode, this is the I2C slave SDA
input.
(RXD1)
Input
SCI1 receive data input
(PWMA_1X)
GPIOC13
Output
PWM submodule 1, output X or input capture X.
49
55
37
41
—
Input
Input/
Output
GPIO Port C13 — After reset, the default state is
GPIOC13.
(TA3)
Input/
Output
Quad timer channel 3 input/output.
(XB_IN6)
Input
Crossbar module input 6.
(EWM_OUT_B)
GPIOC14
Output
External Watchdog Module output.
—
Input
Input/
Output
GPIO Port C14 — After reset, the default state is
GPIOC14.
(LP_SDA0)
Input/
Open-
drain
I2C0 serial data line
NOTE: In 4-wire mode, this is the I2C slave SDA
input.
Output
(XB_OUT4)
Output
Input
Crossbar module output 4.
(PWMA_FAULT4)
GPIOC15
PWM Fault input 4 for disabling selected PWM outputs.
56
42
—
Input
Input/
Output
GPIO Port C15: After reset, the default state is
GPIOC15.
(LP_SCL0)
Input/
Open-
drain
I2C0 serial clock line
NOTE: In 4-wire mode, this is the I2C slave SCL input.
Output
(XB_OUT5)
(PWMA_FAULT5)
GPIOE0
Output
Input
Crossbar module output 5.
PWM Fault input 5 for disabling selected PWM outputs.
45
46
47
33
34
35
21
22
23
Input
Input
Input
Input/
Output
GPIO Port E0 — After reset, the default state is
GPIOE0.
(PWMA_0B)
Input/
Output
PWM submodule 0, high resolution output B or input
capture B.
XB_OUT4
Output
Crossbar module output 4.
GPIOE1
Input/
Output
GPIO Port E1 — After reset, the default state is
GPIOE1.
(PWMA_0A)
Input/
Output
PWM submodule 0, high resolution output A or input
capture A.
(XB_OUT5)
Output
Crossbar module output 5.
GPIOE2
Input/
Output
GPIO Port E2 — After reset, the default state is
GPIOE2.
(PWMA_1B)
Input/
Output
PWM submodule 1, high resolution output B or input
capture B.
Table continues on the next page...
MC56F81xxx, Rev. 1.1, 12/2020
22
NXP Semiconductors
MC56F81xxx signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
64
LQFP LQFP LQFP/ During
QFN Reset
48
32
State
Type
Signal Description
XB_OUT6
Output
Crossbar module output 6.
GPIOE3
48
36
24
Input
Input/
Output
GPIO Port E3 — After reset, the default state is
GPIOE3.
(PWMA_1A)
Input/
Output
PWM submodule 1, high resolution output A or input
capture A.
(XB_OUT7)
Output
Crossbar module output 7.
GPIOE4
51
39
25
Input
Input/
Output
GPIO Port E4 — After reset, the default state is
GPIOE4.
(PWMA_2B)
Input/
Output
PWM submodule 2, high resolution output B or input
capture B.
(XB_IN2)
Input
Crossbar module input 2
(LP_SCL1)
Input/
Open-
drain
I2C1 serial clock line
NOTE: In 4-wire mode, this is the I2C slave SCL input.
Output
(XB_OUT8)
Output
Crossbar module output 8.
GPIOE5
52
40
26
Input
Input/
Output
GPIO Port E5 — After reset, the default state is
GPIOE5.
(PWMA_2A)
Input/
Output
PWM submodule 2, high resolution output A or input
capture A
(XB_IN3)
Input
Crossbar module input 3.
I2C1 serial data line
(LP_SDA1)
Input/
Open-
drain
NOTE: In 4-wire mode, this is the I2C slave SDA
input.
Output
(XB_OUT9)
Output
Crossbar module output 9.
GPIOE6
53
54
36
—
—
28
—
—
—
Input
Input
Input
Input/
Output
GPIO Port E6 — After reset, the default state is
GPIOE6.
(PWMA_3B)
Input/
Output
PWM submodule 3, high resolution output B or input
capture B.
(XB_IN4)
Input
Crossbar module input 4
(XB_OUT10)
GPIOE7
Output
Crossbar module output 10.
Input/
Output
GPIO Port E7 — After reset, the default state is
GPIOE7.
(PWMA_3A)
Input/
Output
PWM ,submodule 3, high resolution output A or input
capture A.
(XB_IN5)
(XB_OUT11)
GPIOF0
Input
Crossbar module input 5.
Output
Crossbar module output 11.
Input/
Output
GPIO Port F0 — After reset, the default state is
GPIOF0.
(XB_IN6)
Input
Crossbar module input 6
(OPAMPB_OUT)
Output
Operational amplifier B output.
Table continues on the next page...
MC56F81xxx, Rev. 1.1, 12/2020
NXP Semiconductors
23
MC56F81xxx signal and pin descriptions
Table 2. Signal descriptions (continued)
Signal Name
64
LQFP LQFP LQFP/ During
QFN Reset
48
32
State
Type
Signal Description
GPIOF1
50
38
—
Input
Input/
Output
GPIO Port F1 — After reset, the default state is
GPIOF1.
(CLKO1)
Output
Buffered clock output 1.
NOTE: The clock source is selected by
SIM_CLKOUT[CLKOSEL1] bits in SIM.
(XB_IN7)
(CMPD_O)
GPIOF2
Input
Crossbar module input 7.
Output
Analog comparator D output.
39
—
19
Input
Input/
Output
GPIO Port F2 — After reset, the default state is
GPIOF2.
(LP_SCL1)
Input/
Open-
drain
I2C1 serial clock line
NOTE: In 4-wire mode, this is the I2C slave SCL input.
Output
(XB_OUT6)
(LP_SDA0)
Output
Crossbar module output 6
I2C0 serial data line.
Input/
Open-
drain
NOTE: In 4-wire mode, this is the I2C slave SDA
input.
Output
GPIOF3
40
—
20
Input
Input/
Output
GPIO Port F3 — After reset, the default state is
GPIOF3.
(LP_SDA1)
Input/
Open-
drain
I2C1 serial data line.
NOTE: In 4-wire mode, this is the I2C slave SDA
input.
Output
(XB_OUT7)
(LP_SCL0)
Output
Crossbar module output 7
I2C0 serial clock line
Input/
Output
NOTE: In 4-wire mode, this is the I2C slave SCL input.
GPIOF4
41
—
—
Input
Input/
Output
GPIO Port F4 — After reset, the default state is
GPIOF4.
(TXD1)
Output
SCI1 transmit data output or transmit/receive in single
wire operation
(XB_OUT8)
(PWMA_0X)
Output
Crossbar module output 8
Input/
PWM submodule 0, output X or input capture X.
Output
(PWMA_FAULT6)
Input
PWM Fault input 6 for disabling selected PWM outputs.
GPIOF5
42
—
—
Input
Input/
Output
GPIO Port F5 — After reset, the default state is
GPIOF5.
(RXD1)
Input
SCI1 receive data input.
(XB_OUT9)
(PWMA_1X)
Output
Crossbar module output 9.
Input/
PWM submodule 1, output X or input capture X.
Output
(PWMA_FAULT7)
Input
PWM Fault input 7 for disabling selected PWM outputs.
Table continues on the next page...
MC56F81xxx, Rev. 1.1, 12/2020
24
NXP Semiconductors
Signal groups
Table 2. Signal descriptions (continued)
Signal Name
64
LQFP LQFP LQFP/ During
QFN Reset
48
32
State
Type
Signal Description
GPIOF6
58
—
—
Input
Input/
Output
GPIO Port F6 — After reset, the default state is
GPIOF6.
(PWMA_3X)
LP_SCLS1
Input/
Output
PWM submodule 3, output X or input capture X.
Output
Input
I2C1 secondary serial clock line.
NOTE: In 4-wire mode, this is the I2C slave SCL
output for voltage level shift.
(XB_IN2)
Crossbar module input 2.
GPIOF7
59
—
—
Input
Input/
Output
GPIO Port F7 — After reset, the default state is
GPIOF7.
(CMPC_O)
LP_SDAS1
Output
Output
Analog comparator C output.
I2C1 secondary serial data line.
NOTE: In 4-wire mode, this is the I2C slave SDA
output for voltage level shift.
(XB_IN3)
Input
Crossbar module input 3.
GPIOF8
6
—
—
Input
Input/
Output
GPIO Port F8 — After reset, the default state is
GPIOF8.
(RXD0)
Input
SCI0 receive data input.
(XB_OUT10)
(CMPD_O)
(PWMA_2X)
Output
Output
Output
Crossbar module output 10.
Analog comparator D output.
PWM submodule 2, output X or input capture X.
1. The glitch on this pin during ADC sampling may interfere with other analog inputs shared on this pin.
3 Signal groups
The input and output signals of the MC56F81xxx are organized into functional groups, as
detailed in the following table.
Table 3. Functional Group Pin Allocations
Functional Group
Number of Pins
32LQFP
48LQFP
64LQFP
Power Inputs (VDD, VDDA), Power output( VCAP
)
3
3
1
6
0
4
4
5
4
1
6
2
5
7
6
4
Ground (VSS, VSSA
Reset
)
1
eFlexPWM outputs high resolution PWM
8
eFlexPWM outputs without high resolution PWM
Queued Serial Peripheral Interface (QSPI0) ports
Queued Serial Communications Interface (QSCI0 and QSCI11) ports
6
5
10
Table continues on the next page...
MC56F81xxx, Rev. 1.1, 12/2020
NXP Semiconductors
25
Pinout
Table 3. Functional Group Pin Allocations
(continued)
Functional Group
Number of Pins
32LQFP
48LQFP
64LQFP
Inter-Integrated Circuit Interface (LPI2C0 and LPI2C1 ) ports
12-bit Analog-to-Digital Converter (ADC) inputs
Analog Comparator inputs/outputs
42
63
10
16
6
10
7/3
5/1
0
11/4
6/2
1
17/6
8/2
1
Analog Operational Amplifier inputs/outputs
12-bit Digital-to-Analog output
Quad Timer Module (TMR) ports
3
4
4
Inter-Module Crossbar inputs/outputs
Clock inputs/outputs
8/11
1/1
4
13/12
2/2
4
17/19
2/2
4
JTAG / Enhanced On-Chip Emulation (EOnCE)
1. Not available in 32-pin package.
2. 4-wire mode does not support.
3. Only LPI2C0 supports 4-wire mode.
4 Pinout
4.1 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
64
48
32
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
LQFP LQFP LQFP
1
2
1
2
1
2
TCK
TCK
GPIOD2
GPIOD4
EXTAL
XTAL
RESET_B
GPIOC0
GPIOC1
GPIOC2
GPIOF8
GPIOC3
GPIOC4
GPIOA7
GPIOA6
GPIOA5
GPIOA4
GPIOA0
RESET_B
GPIOC0
GPIOC1
GPIOC2
GPIOF8
GPIOC3
GPIOC4
GPIOA7
GPIOA6
GPIOA5
GPIOA4
GPIOA0
3
3
—
—
3
CLKIN0
4
4
5
5
TXD0
RXD0
TA0
XB_OUT11
XB_OUT10
CMPA_O
XB_IN2
CMPD_O
RXD0
CLKO0
6
—
6
—
4
PWMA_2X
CLKIN1
7
8
7
5
TA1
CMPB_O
XB_IN8
OPAMPA_OUT
9
—
—
—
8
—
—
—
—
6
ANA7+CMPD_IN3
ANA6+CMPD_IN2
ANA5+CMPD_IN1
ANA4+CMPD_IN0
10
11
12
13
9
ANA0+CMPA_
CMPC_O
IN3+OPAMPA_IN3
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Pinout
64
48
32
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
LQFP LQFP LQFP
14
15
16
17
10
11
12
—
7
8
GPIOA1
GPIOA2
GPIOA3
GPIOB7
GPIOA1
GPIOA2
GPIOA3
GPIOB7
ANA1+CMPA_
IN0+OPAMPA_IN0
ANA2+VREFHA+CMPA_
IN1+OPAMPA_IN1
—
—
ANA3+VREFLA+CMPA_
IN2+OPAMPA_IN2
ANB7+CMPB_
IN2+OPAMPB_IN2
18
19
13
—
—
—
GPIOC5
GPIOB6
GPIOC5
GPIOB6
DACA_O
XB_IN7
ANB6+CMPB_
IN1+OPAMPB_IN1
20
21
22
23
24
—
14
15
16
17
—
—
9
GPIOB5
GPIOB4
VDDA
GPIOB5
GPIOB4
VDDA
ANB5+CMPC_IN2
ANB4+CMPC_IN1
10
11
VSSA
VSSA
GPIOB0
GPIOB0
ANB0+CMPB_
IN3+OPAMPB_IN3
25
18
12
GPIOB1
GPIOB1
ANB1+CMPB_
IN0+OPAMPB_IN0
26
27
19
20
—
VCAP
VCAP
13
GPIOB2
GPIOB2
ANB2+VREFHB+CMPC_
IN3
28
21
—
GPIOB3
GPIOB3
ANB3+VREFLB+CMPC_
IN0
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
—
22
23
24
25
26
27
28
29
30
—
—
—
—
31
32
33
34
35
36
—
14
15
—
16
17
18
—
—
—
19
20
—
—
—
—
21
22
23
24
VDD
VDD
VSS
VSS
GPIOC6
GPIOC7
GPIOC8
GPIOC9
GPIOC6
GPIOC7
GPIOC8
GPIOC9
GPIOC10
GPIOF0
GPIOC11
GPIOC12
GPIOF2
GPIOF3
GPIOF4
GPIOF5
VSS
TA2
XB_IN3
TXD0
CMP_REF
XB_IN8
XB_IN9
TXD0
SS0_B
SS0_B
XB_OUT6
MISO0
RXD0
SCLK0
MOSI0
XB_IN4
XB_IN5
XB_OUT8
XB_OUT9
GPIOC10
GPIOF0
GPIOC11
GPIOC12
GPIOF2
GPIOF3
GPIOF4
GPIOF5
VSS
MISO0
XB_IN6
LP_SCLS0
LP_SDAS0
LP_SCL1
LP_SDA1
TXD1
OPAMPB_OUT
PWMA_0X
LP_SCL1
LP_SDA1
XB_OUT6
XB_OUT7
XB_OUT8
XB_OUT9
TXD1
RXD1
PWMA_1X
LP_SDA0
LP_SCL0
PWMA_0X
PWMA_1X
PWMA_FAULT6
PWMA_FAULT7
RXD1
VDD
VDD
GPIOE0
GPIOE1
GPIOE2
GPIOE3
GPIOE0
GPIOE1
GPIOE2
GPIOE3
PWMA_0B
PWMA_0A
PWMA_1B
PWMA_1A
XB_OUT4
XB_OUT5
XB_OUT6
XB_OUT7
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NXP Semiconductors
27
Pinout
64
48
32
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
LQFP LQFP LQFP
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
37
38
39
40
—
—
41
42
43
—
—
44
45
46
47
48
—
—
25
26
—
—
—
—
27
—
—
28
29
30
31
32
GPIOC13
GPIOC13
GPIOF1
GPIOE4
GPIOE5
GPIOE6
GPIOE7
GPIOC14
GPIOC15
VCAP
TA3
XB_IN6
XB_IN7
XB_IN2
XB_IN3
XB_IN4
XB_IN5
XB_OUT4
XB_OUT5
EWM_OUT_B
GPIOF1
GPIOE4
GPIOE5
GPIOE6
GPIOE7
GPIOC14
GPIOC15
VCAP
CLKO1
CMPD_O
LP_SCL1
LP_SDA1
PWMA_2B
PWMA_2A
PWMA_3B
PWMA_3A
LP_SDA0
LP_SCL0
XB_OUT8
XB_OUT9
XB_OUT10
XB_OUT11
PWMA_FAULT4
PWMA_FAULT5
GPIOF6
GPIOF7
VDD
GPIOF6
GPIOF7
VDD
PWMA_3X
CMPC_O
LP_SCLS1
LP_SDAS1
XB_IN2
XB_IN3
VSS
VSS
TDO
TDO
GPIOD1
GPIOD3
GPIOD0
TMS
TMS
TDI
TDI
4.2 Pinout diagrams
The following diagrams show pinouts for the packages. For each pin, the diagrams show
the default function. However, many signals may be multiplexed onto a single pin.
MC56F81xxx, Rev. 1.1, 12/2020
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NXP Semiconductors
Pinout
TCK
RESET_B
GPIOC0
GPIOC1
GPIOC2
GPIOF8
GPIOC3
GPIOC4
GPIOA7
GPIOA6
GPIOA5
GPIOA4
GPIOA0
GPIOA1
GPIOA2
GPIOA3
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GPIOE3
GPIOE2
GPIOE1
GPIOE0
VDD
2
3
4
5
6
VSS
7
GPIOF5
GPIOF4
GPIOF3
GPIOF2
GPIOC12
GPIOC11
GPIOF0
GPIOC10
GPIOC9
GPIOC8
8
9
10
11
12
13
14
15
16
Figure 2. 64-pin LQFP
MC56F81xxx, Rev. 1.1, 12/2020
NXP Semiconductors
29
Pinout
GPIOE3
GPIOE2
GPIOE1
GPIOE0
VDD
36
35
34
33
32
31
30
29
28
27
26
25
TCK
RESET_B
GPIOC0
GPIOC1
GPIOC2
GPIOC3
GPIOC4
GPIOA4
GPIOA0
GPIOA1
GPIOA2
GPIOA3
1
2
3
4
5
VSS
6
GPIOC12
GPIOC11
GPIOF0
GPIOC10
GPIOC9
GPIOC8
7
8
9
10
11
12
Figure 3. 48-pin LQFP
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NXP Semiconductors
Ordering parts
GPIOE3
GPIOE2
GPIOE1
GPIOE0
GPIOF3
GPIOF2
GPIOC10
GPIOC9
TCK
RESET_B
GPIOC2
GPIOC3
GPIOC4
GPIOA0
GPIOA1
GPIOA2
24
23
22
21
20
19
1
2
3
4
5
6
7
8
18
17
Figure 4. 32-pin LQFP
5 Ordering parts
5.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to nxp.com and perform a part number search for the
following device numbers: MC56F81
5.2 Part number list
The following table shows a part number list for this device.
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31
Part identification
Table 4. Part numbers
Part Number
Flash Size
Operating Temperature
Package
MC56F81768VLH
MC56F81748VLH
MC56F81766VLF
MC56F81746VLF
MC56F81763VLC
MC56F81743VLC
MC56F81763VFM
MC56F81743VFM
MC56F81668VLH
MC56F81648VLH
MC56F81666VLF
MC56F81646VLF
MC56F81663VLC
MC56F81643VLC
MC56F81768MLH
MC56F81748MLH
MC56F81766MLF
MC56F81746MLF
128 KB
64 KB
-40 to 105℃
-40 to 105℃
-40 to 105℃
-40 to 105℃
-40 to 105℃
-40 to 105℃
-40 to 105℃
-40 to 105℃
-40 to 105℃
-40 to 105℃
-40 to 105℃
-40 to 105℃
-40 to 105℃
-40 to 105℃
-40 to 125℃
-40 to 125℃
-40 to 125℃
-40 to 125℃
64 LQFP
64 LQFP
48 LQFP
48 LQFP
32 LQFP
32 LQFP
32 QFN
128 KB
64 KB
128 KB
64 KB
128 KB
64 KB
32 QFN
128 KB
64 KB
64 LQFP
64 LQFP
48 LQFP
48 LQFP
32 LQFP
32 LQFP
64 LQFP
64 LQFP
48 LQFP
48 LQFP
128 KB
64 KB
128 KB
64 KB
128 KB
64 KB
128 KB
64 KB
6 Part identification
6.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
6.2 Format
Part numbers for this device have the following format: Q 56F8 1 C F P T PP N
6.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
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NXP Semiconductors
Package marking information
Values
Field
Description
Q
Qualification status
• MC = Fully qualified, general market flow
• PC = Prequalification
56F8
DSC family with flash memory and DSP56800/
DSP56800E/DSP56800EX core
• 56F8
1
DSC subfamily
• 1
C
Maximum CPU frequency (MHz)
• 6 = 100 MHz
• 7 = 100 MHz
F
P
Primary program flash memory size
Pin count
• 4 = 64 KB
• 6 = 128 KB
• 3 = 32
• 6 = 48
• 8 = 64
T
Temperature range (°C)
Package identifier
• V = –40 to 105
• M = –40 to 125
PP
• LC = 32LQFP
• FM = 32QFN
• LF = 48LQFP
• LH = 64LQFP
N
Packaging type
• R = Tape and reel
• (Blank) = Trays
6.4 Example
This is an example part number: MC56F81768VLH
7 Package marking information
The MC56F81xxx 64LQFP package has the following top-side marking:
• First line: aaaaaaaaaaaaa
• Second line: mmmmm
• Third line: xxxyywwx
The MC56F81xxx 48LQFP package has the following top-side marking:
• First line: aaaaaaaaaaa
• Second line: mmmmm
• Third line: xxywx
The detailed code format for these identifiers is show in the table below.
Identifier
Description
Table continues on the next page...
MC56F81xxx, Rev. 1.1, 12/2020
NXP Semiconductors
33
Terminology and guidelines
a
Part number code, refer to the "Part identification" section.
For example, in 48LQFP package, the last digit 'V' stands for
VLF.
m
y
Mask set
Work year
w
x
Work week
NXP internal use
8 Terminology and guidelines
8.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
8.1.1 Example
This is an example of an operating requirement:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
0.9
1.1
V
8.2 Definition: Operating behavior
Unless otherwise specified, an operating behavior is a specified value or range of values
for a technical characteristic that are guaranteed during operation if you meet the
operating requirements and any other specified conditions.
8.2.1 Example
This is an example of an operating behavior:
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34
NXP Semiconductors
Terminology and guidelines
Symbol
Description
Min.
Max.
Unit
IWP
Digital I/O weak pullup/ 10
pulldown current
130
µA
8.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.
8.3.1 Example
This is an example of an attribute:
Symbol
Description
Min.
Max.
Unit
CIN_D
Input capacitance:
digital pins
—
7
pF
8.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
8.4.1 Example
This is an example of an operating rating:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
–0.3
1.2
V
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35
Terminology and guidelines
8.5 Result of exceeding a rating
40
30
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
20
10
0
Operating rating
Measured characteristic
8.6 Relationship between ratings and operating requirements
Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- No permanent failure
- Correct operation
- No permanent failure
Expected permanent failure
- Possible decreased life
- Possible incorrect operation
- Possible decreased life
- Possible incorrect operation
–∞
∞
Operating (power on)
Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
–∞
∞
Handling (power off)
8.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
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NXP Semiconductors
Terminology and guidelines
8.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
8.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol
Description
Min.
Typ.
Max.
Unit
IWP
Digital I/O weak
pullup/pulldown
current
10
70
130
µA
8.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
5000
4500
4000
TJ
3500
150 °C
3000
105 °C
2500
25 °C
2000
–40 °C
1500
1000
500
0
0.90
0.95
1.00
1.05
1.10
VDD (V)
MC56F81xxx, Rev. 1.1, 12/2020
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37
Ratings
8.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Ambient temperature
3.3 V supply voltage
Value
Unit
TA
25
°C
V
VDD
3.3
9 Ratings
9.1 Thermal handling ratings
Symbol
TSTG
Description
Min.
–55
—
Max.
150
Unit
°C
Notes
Storage temperature
Solder temperature, lead-free
1
2
TSDR
260
°C
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
9.2 Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
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NXP Semiconductors
General
9.3 ESD handling ratings
Although damage from electrostatic discharge (ESD) is much less common on these
devices than on early CMOS circuits, use normal handling precautions to avoid exposure
to static discharge. Qualification tests are performed to ensure that these devices can
withstand exposure to reasonable levels of static without suffering any permanent
damage.
A device is defined as a failure if after exposure to ESD pulses, the device no longer
meets the device specification. Complete DC parametric and functional testing is
performed as per the applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.
Table 5. ESD/Latch-up Protection
Characteristic1
Min
–2000
–500
–100
Max
+2000
+500
+100
Unit
V
Notes
ESD for Human Body Model (VHBM
)
2
3
4
ESD for Charge Device Model (VCDM
)
V
Latch-up current at TA= 85°C (ILAT) (V part)
mA
1. Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions
unless otherwise noted.
2. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
3. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
4. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
9.4 Voltage and current operating ratings
Table 6. Voltage and current operating ratings
Symbol
VDD
IDD
Description
Min.
–0.3
—
Max.
3.8
Unit
V
Digital supply voltage
Digital supply current
IO pin input voltage
120
mA
V
VIO
–0.3
–25
VDD + 0.3
25
ID
Instantaneous maximum current single pin limit (applies to all
port pins)
mA
VDDA
Analog supply voltage
VDD – 0.3
VDD + 0.3
V
10 General
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39
General
10.1 General characteristics
Absolute maximum ratings in the table of "Voltage and current operating ratings" section
are stress ratings only, and functional operation at the maximum is not guaranteed. Stress
beyond these ratings may affect device reliability or cause permanent damage to the
device.
Unless otherwise stated, all specifications within this chapter apply to the temperature
range specified in the table of "Voltage and current operating ratings" section over the
following supply ranges: VSS = VSSA = 0 V, VDD = VDDA = 3.0 V to 3.6 V, CL ≤ 50 pF,
fOP = 50 MHz.
CAUTION
This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields. However,
normal precautions are advised to avoid application of any
voltages higher than maximum-rated voltages to this high-
impedance circuit. Reliability of operation is enhanced if
unused inputs are tied to an appropriate voltage level.
10.2 AC electrical characteristics
Tests are conducted using the input levels specified in the section "Voltage and current
operating behaviors". Unless otherwise specified, propagation delays are measured from
the 50% to the 50% point, and rise and fall times are measured between the 20% and 80%
points, as shown in Figure 5.
High
Low
VIH
80%
50%
20%
Input Signal
Midpoint1
VIL
Fall Time
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 5. Input signal measurement references
All digital I/O switching characteristics, unless otherwise specified, assume that the
output pins have the following characteristics.
• CL=30 pF loads
• Slew rate disabled
• Normal drive strength
MC56F81xxx, Rev. 1.1, 12/2020
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NXP Semiconductors
General
Figure 6 shows the definitions of the following signal states:
• Active state, when a bus or signal is driven, and enters a low impedance state
• Tri-stated, when a bus or signal is placed in a high impedance state
• Data Valid state, when a signal level has reached VOL or VOH
• Data Invalid state, when a signal level is in transition between VOL and VOH
Data1 Valid
Data1
Data2 Valid
Data2
Data3 Valid
Data3
Data
Data Invalid State
Tri-stated
Data Active
Data Active
Figure 6. Signal states
10.3 Nonswitching electrical specifications
10.3.1 Voltage and current operating requirements
This section includes information about recommended operating conditions.
Table 7. Voltage and current operating requirements
Symbol Description
Min.
2.7
Typ.
3.3
Max.
3.6
Unit
V
Notes
—
VDD
Supply voltage
VDDA
Analog supply voltage
VDD-to-VDDA differential voltage
2.7
3.3
3.6
V
—
VDD
–
–0.1
0.1
V
—
VDDA
VSS – VSSA VSS-to-VSSA differential voltage
–0.1
0.1
—
V
V
—
—
VIH
Input high voltage
• 2.7 V ≤ VDD ≤ 3.6 V
0.7 × VDD
VIL
Input low voltage
—
• 2.7 V ≤ VDD ≤ 3.6 V
—
0.35 × VDD
V
VHYS
Input hysteresis
0.06 × VDD
2.0
—
V
V
—
—
VIHOSC
Oscillator Input Voltage High
XTAL driven by an external clock source
Oscillator Input Voltage Low
IO pin negative DC injection current—single pin
• VIN < VSS–0.3V
VDD + 0.3
VILOSC
IICIO
-0.3
–3
0.8
—
V
—
1
mA
IICcont
Contiguous pin DC injection current —regional
limit, includes sum of negative injection currents
of 16 contiguous pins
—
MC56F81xxx, Rev. 1.1, 12/2020
NXP Semiconductors
41
General
Table 7. Voltage and current operating requirements
Symbol Description
• Negative current injection
Min.
Typ.
Max.
Unit
Notes
–25
—
mA
1. All I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN
greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If this
limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is
calculated as R = (VIO_MIN - VIN)/|IICIO|.
10.3.2 LVD and POR operating requirements
Table 8. PMC Low-Voltage Detection (LVD) and Power-On Reset (POR) Parameters
Characteristic
Symbol
POR
Min
Typ
2.0
Max
Unit
V
POR Assert Voltage1
POR Release Voltage2
Low-Voltage Warning Interrupt
Low-Voltage Alarm Interrupt
POR
2.7
V
LVI_2p7
LVI_2p2
2.73
2.23
V
V
1. During 3.3-volt VDD power supply ramp down
2. During 3.3-volt VDD power supply ramp up (gated by LVI_2p7)
10.3.3 Voltage and current operating behaviors
Table 9. Voltage and current operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
VOH
Output high voltage — Normal drive pad (except
RESET)
1
VDD – 0.5
—
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –5 mA
VOH
Output high voltage — High drive pad (except RESET)
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –20 mA
2, 1
VDD – 0.5
—
—
V
IOHT
VOL
Output high current total for all ports
100
mA
—
1
Output low voltage — Normal drive pad (except
RESET)
—
0.5
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA
VOL
Output low voltage — High drive pad (except RESET)
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 20 mA
2, 1
—
—
—
0.5
100
1
V
IOLT
IIN
Output low current total for all ports
mA
μA
—
3
Input leakage current (per pin) for full temperature
range
IIN
Input leakage current (per pin) at 25 °C
—
0.025
μA
3
Table continues on the next page...
MC56F81xxx, Rev. 1.1, 12/2020
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General
Table 9. Voltage and current operating behaviors (continued)
Symbol
Description
Min.
Max.
Unit
Notes
IIN
Input leakage current (total all pins) for full temperature
range
—
41
μA
3
IOZ
RPU
RPD
Hi-Z (off-state) leakage current (per pin)
Internal pullup resistors
—
20
20
1
μA
kΩ
kΩ
—
4
50
50
Internal pulldown resistors
5
1. The reset pin only contains an active pull down device when configured as the RESET signal or as a GPIO. When
configured as a GPIO output, it acts as a pseudo open drain output.
2. GPIOC2, GPIOC7~12, GPIOF2~3 and GPIOC14~15 support high drive strength mode.
3. Measured at VDD = 3.6 V
4. Measured at VDD supply voltage = VDD min and Vinput = VSS
5. Measured at VDD supply voltage = VDD min and Vinput = VDD
10.3.4 Power mode transition operating behaviors
Parameters listed are guaranteed by design.
NOTE
All address and data buses described here are internal.
Table 10. Reset, stop, wait, and interrupt timing
Characteristic
Symbol
Typical Min
Typical
Max
Unit
See
Figure
Minimum RESET Assertion Duration
tRA
tRDA
tIF
16 1
865 × TOSC + 8 × T
361.3
—
ns
ns
ns
—
—
—
RESET deassertion to First Address Fetch
Delay from Interrupt Assertion to Fetch of first
instruction (exiting Stop)
570.9
1. If the RESET pin filter is enabled by setting the RST_FLT bit in the SIM_CTRL register to 1, the minimum pulse assertion
must be greater than 21 ns. Recommended a capacitor of up to 0.1 µF on RESET.
NOTE
In Table 10, T = system clock cycle and TOSC = oscillator clock
cycle. For an operating frequency of 50MHz, T=20 ns. At 4
MHz (used coming out of reset and stop modes), T=250 ns.
Table 11. Power mode transition behavior
Symbol
Description
Typical
Max
Unit Notes1
TPOR
After a POR event, the amount of delay from when VDD reaches
2.7 V to when the first instruction executes (over the operating
temperature range).
250
288
µs
STOP mode to RUN mode
7.10
8.17
µs
2
Table continues on the next page...
MC56F81xxx, Rev. 1.1, 12/2020
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43
General
Symbol
Table 11. Power mode transition behavior (continued)
Description
Typical
285
Max
328
Unit Notes1
LPS mode to LPRUN mode
VLPS mode to VLPRUN mode
WAIT mode to RUN mode
µs
µs
µs
µs
µs
3
4
5
3
4
878
1010
0.454
328
0.395
285
LPWAIT mode to LPRUN mode
VLPWAIT mode to VLPRUN mode
868
998
1. Wakeup times are measured from GPIO toggle for wakeup till GPIO toggle at the wakeup interrupt subroutine from
respective stop/wait mode.
2. Clock configuration: CPU clock=4 MHz. System clock source is 8 MHz IRC in normal mode.
3. CPU clock = 200 kHz and 8 MHz IRC on standby. Exit by an interrupt on PORTA GPIO.
4. Using 64 kHz external clock; CPU Clock = 32 kHz. Exit by an interrupt on PORTA GPIO.
5. Clock configuration: CPU and system clocks= 100 MHz. Bus Clock = 50MHz. Exit by interrupt on PORTA GPIO
10.3.5 Power consumption operating behaviors
Table 12. Current Consumption (Unit: mA)
Mode
Maximum
Frequency
Conditions
Typical at Maximum Maximum
3.3 V,
25°C
at 3.6 V,
105°C
at 3.6V,
125°C
1
1
1
IDD IDDA IDD IDDA IDD IDDA
RUN1
100 MHz
• 100 MHz Core
24.9 8.6 46.0 13.2 46.9 13.2
• 50 MHz Peripheral clock
• Regulators are in full regulation
• Relaxation Oscillator on
• PLL powered on
• Continuous MAC instructions with fetches from
Program Flash
• All peripheral modules enabled. TMRs and SCIs
using 1X peripheral clock
• NanoEdge within eFlexPWM using 2X peripheral
clock
• ADC/DAC (only one 12-bit DAC and all 8-bit DACs)
powered on and clocked
• Comparator powered on
RUN2
50 MHz
• 50 MHz Core and Peripheral clock
• Regulators are in full regulation
• Relaxation Oscillator on
20.3 8.7 43.0 12.2 43.4 12.3
• PLL powered on
• Continuous MAC instructions with fetches from
Program Flash
• All peripheral modules enabled. TMRs and SCIs
using 1X peripheral clock
• NanoEdge within eFlexPWM using 2X peripheral
clock
• ADC/DAC (only one 12-bit DAC and all 8-bit DACs)
powered on and clocked
• Comparator powered on
WAIT
50 MHz
• 50 MHz Core and Peripheral clock
17.3
—
35.0
—
35.7
—
Table continues on the next page...
MC56F81xxx, Rev. 1.1, 12/2020
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NXP Semiconductors
General
Table 12. Current Consumption (Unit: mA) (continued)
Mode
Maximum
Frequency
Conditions
Typical at Maximum Maximum
3.3 V,
25°C
at 3.6 V,
105°C
at 3.6V,
125°C
1
1
1
IDD IDDA IDD IDDA IDD IDDA
• Regulators are in full regulation
• Relaxation Oscillator on
• PLL powered on
• Processor Core in WAIT state
• All Peripheral modules enabled.
• TMRs and SCIs using 1X Clock
• NanoEdge within PWMA using 2X clock
• ADC/DAC (single 12-bit DAC, all 8-bit DACs),
Comparator powered off
STOP
4 MHz
2 MHz
• 4 MHz Device Clock
• Regulators are in full regulation
• Relaxation Oscillator on
4.4
—
12.5
—
13.1
—
• PLL powered off
• Processor Core in STOP state
• All peripheral module and core clocks are off
• ADC/DAC/Comparator powered off
LPRUN
(LsRUN)
• 200 kHz Device Clock from Relaxation Oscillator's
(ROSC) low speed clock
1.1 2.4 11.1 4.0 12.8 4.0
• ROSC in standby mode
• Regulators are in standby
• PLL disabled
• Repeat NOP instructions
• All peripheral modules enabled, except NanoEdge
and cyclic ADCs. One 12-bit DAC and all 8-bit
DACs enabled.
• Simple loop with running from platform instruction
buffer
LPWAIT
(LsWAIT)
2 MHz
• 200 kHz Device Clock from Relaxation Oscillator's
(ROSC) low speed clock
1.0 2.4 11.1 4.0 12.8 4.0
• ROSC in standby mode
• Regulators are in standby
• PLL disabled
• All peripheral modules enabled, except NanoEdge
and cyclic ADCs. One 12-bit DAC and all 8-bit
DACs enabled.2
• Processor core in wait mode
LPSTOP
(LsSTOP)
2 MHz
• 200 kHz Device Clock from Relaxation Oscillator's
(ROSC) low speed clock
• ROSC in standby mode
• Regulators are in standby
• PLL disabled
• Only PITs and COP enabled; other peripheral
modules disabled and clocks gated off2
• Processor core in stop mode
1.0
0.4
—
—
9.1
7.5
—
—
10.5
—
—
VLPRUN
200 kHz
• 32 kHz Device Clock
9.0
• Clocked by a 64 kHz external clock source
• Oscillator in power down
• All ROSCs disabled
• Large regulator is in standby
• Small regulator is disabled
Table continues on the next page...
MC56F81xxx, Rev. 1.1, 12/2020
NXP Semiconductors
45
General
Mode
Table 12. Current Consumption (Unit: mA) (continued)
Maximum
Conditions
Typical at Maximum Maximum
Frequency
3.3 V,
25°C
at 3.6 V,
105°C
at 3.6V,
125°C
1
1
1
IDD IDDA IDD IDDA IDD IDDA
• PLL disabled
• Repeat NOP instructions
• All peripheral modules, except COP and EWM,
disabled and clocks gated off
• Simple loop running from platform instruction buffer
VLPWAIT
200 kHz
• 32 kHz Device Clock
0.4
—
7.5
—
9.0
—
• Clocked by a 64 kHz external clock source
• Oscillator in power down
• All ROSCs disabled
• Large regulator is in standby
• Small regulator is disabled
• PLL disabled
• All peripheral modules, except COP, disabled and
clocks gated off
• Processor core in wait mode
VLPSTOP
200 kHz
• 32 kHz Device Clock
0.4
—
7.5
—
9.0
—
• Clocked by a 64 kHz external clock source
• Oscillator in power down
• All ROSCs disabled
• Large regulator is in standby.
• Small regulator is disabled.
• PLL disabled
• All peripheral modules, except COP, disabled and
clocks gated off
• Processor core in stop mode
1. No output switching, all ports configured as inputs, all inputs low, no DC loads.
2. In all chip LP modes and flash memory VLP modes, the maximum frequency for flash memory operation is 500 kHz due to
the fixed frequency ratio of 1:2 between the CPU clock and the flash clock when running with 2 MHz external clock input
and CPU running at 1 MHz.
10.3.6 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.nxp.com.
2. Perform a keyword search for “EMC design.”
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NXP Semiconductors
General
10.3.7 Capacitance attributes
Table 13. Capacitance attributes
Description
Symbol
CIN
Min.
—
Typ.
10
Max.
—
Unit
Input capacitance
Output capacitance
pF
pF
COUT
—
10
—
10.4 Switching specifications
10.4.1 Device clock specifications
Table 14. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Notes
Normal run mode
fSYSCLK
Device (system and core) clock frequency
• using relaxation oscillator
0.001
0
100
100
50
MHz
MHz
• using external clock source
fBUS
Bus clock
—
10.4.2 General switching specifications
These general-purpose specifications apply to all signals configured for GPIO signals.
Table 15. General switching specifications
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter disabled) —
Synchronous path
1.5
—
Bus clock
cycles
1
External RESET and NMI pin interrupt pulse width —
Asynchronous path
100
—
ns
2
GPIO pin interrupt pulse width — Asynchronous path
Port rise and fall time
16
—
—
ns
ns
2
3
36
1. The synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. 75 pF load
10.5 Thermal specifications
MC56F81xxx, Rev. 1.1, 12/2020
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47
General
10.5.1 Thermal operating requirements
Table 16. Thermal operating requirements
Symbol
Description
Grade
Min
–40
–40
–40
–40
Max
125
135
105
125
Unit
°C
TJ
Die junction temperature
V
M
V
°C
TA
Ambient temperature
°C
M
°C
10.5.2 Thermal attributes
This section provides information about operating temperature range, power dissipation,
and package thermal resistance. Power dissipation on I/O pins is usually small compared
to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-
determined rather than being controlled by the MCU design. To account for PI/O in power
calculations, determine the difference between actual pin voltage and VSS or VDD and
multiply by the pin current for each I/O pin. Except in cases of unusually high pin current
(heavy loads), the difference between pin voltage and VSS or VDD is very small.
See Thermal design considerations for more detail on thermal design considerations.
Board type 1
Symbol
Description
48 LQFP
64 LQFP
Unit
Notes
Four-layer
(2s2p)
RθJA
Thermal
resistance,
junction to
55
52
°C/W
2
ambient (natural
convection)
Single-layer
(1s)
RθJC
Thermal
resistance,
junction to case
23
3
20
3
°C/W
°C/W
3
2
—
ΨJT
Thermal
characterization
parameter,
junction to
package top
outside center
(natural
convection)
1. Thermal test board meets JEDEC specification for this package (JESD51-7, 2s2p and JESD51-3, 1s).
2. Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this report is
solely for a thermal performance comparison of one package to another in a standardized specified environment. It is not
meant to predict the performance of a package in an application-specific environment.
3. Junction-to-Case (Top) thermal resistance is determined using an isothermal cold plate attached to the package top. Case
(Top) temperature refers to the mold surface temperature at the center.
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NXP Semiconductors
Peripheral operating requirements and behaviors
11 Peripheral operating requirements and behaviors
11.1 Core modules
11.1.1 JTAG timing
Table 17. JTAG timing
Characteristic
Symbol
Min
Max
Unit
See
Figure
TCK frequency of operation
TCK clock pulse width
fOP
tPW
tDS
tDH
tDV
tTS
DC
50
5
SYS_CLK/ 8
MHz
ns
Figure 7
Figure 7
Figure 8
Figure 8
Figure 8
Figure 8
—
—
—
30
30
TMS, TDI data set-up time
TMS, TDI data hold time
TCK low to TDO data valid
TCK low to TDO tri-state
ns
5
ns
—
—
ns
ns
1/f
OP
t
t
PW
PW
V
IH
V
V
V
M
M
TCK
(Input)
IL
V
= V + (V – V )/2
IL IH IL
M
Figure 7. Test clock input timing diagram
TCK
(Input)
t
t
DH
DS
TDI
TMS
Input Data Valid
(Input)
t
DV
TDO
(Output)
Output Data Valid
t
TS
TDO
(Output)
Figure 8. Test access port timing diagram
MC56F81xxx, Rev. 1.1, 12/2020
NXP Semiconductors
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System modules
11.2 System modules
11.2.1 Voltage regulator specifications
The voltage regulator supplies approximately 1.2 V to the device's core logic. For proper
operations, the voltage regulator requires a minimum external 2.2 µF capacitor on each
VCAP pin with total capacitors on all VCAP pins at a minimum of 4.4 µF. Ceramic and
tantalum capacitors tend to provide better performance tolerances. The output voltage can
be measured directly on the VCAP pin. The specifications for this regulator are shown in
Table 18.
Table 18. Regulator 1.2 V parameters
Characteristic
Output Voltage 1
Short Circuit Current 2
Symbol
VCAP
ISS
Min
—
Typ
1.23
600
—
Max
—
Unit
V
—
—
mA
Short Circuit Tolerance (VCAP shorted to ground)
TRSC
—
1
minute
1. Value is after trim
2. Guaranteed by design
Table 19. Bandgap electrical specifications
Characteristic
Reference Voltage (after trim)
Symbol
Min
Typ
Max
Unit
VREF
—
1.241
—
V
1. Typical value is trimmed at 25℃. There could be 50 mV variation due to temperature change.
11.3 Clock modules
11.3.1 External clock operation timing
Parameters listed are guaranteed by design.
Table 20. External clock operation timing requirements
Characteristic
Symbol
fosc
Min
—
8
Typ
Max
Unit
MHz
ns
Frequency of operation (external clock driver)1
Clock pulse width2
—
50
tPW
External clock input rise time3
External clock input fall time4
trise
—
—
—
—
1
1
ns
tfall
ns
Table continues on the next page...
MC56F81xxx, Rev. 1.1, 12/2020
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NXP Semiconductors
System modules
Table 20. External clock operation timing requirements (continued)
Characteristic
Symbol
Vih
Min
0.85×VDD
—
Typ
—
Max
—
Unit
V
Input high voltage overdrive by an external clock
Input low voltage overdrive by an external clock
Vil
—
0.3×VDD
V
1. See the "External clock timing" figure for details on using the recommended connection of an external clock driver.
2. The chip may not function if the high or low pulse width is smaller than 6.25 ns.
3. External clock input rise time is measured from 10% to 90%.
4. External clock input fall time is measured from 90% to 10%.
V
IH
External
Clock
90%
50%
10%
90%
50%
10%
t
V
IL
t
fall
rise
t
t
PW
PW
Note: The midpoint is V + (V – V )/2.
IL
IH
IL
Figure 9. External clock timing
11.3.2 Phase-Locked Loop timing
Table 21. Phase-Locked Loop timing
Characteristic
PLL input reference frequency1
PLL output frequency2
Symbol
fref
Min
8
Typ
8
Max
Unit
MHz
MHz
µs
16
550
100
60
fop
200
—
—
—
50
PLL lock time3
tplls
Allowed Duty Cycle of input reference
tdc
40
%
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly.
The PLL is optimized for 8 MHz input.
2. The frequency of the core system clock cannot exceed 100 MHz. If the NanoEdge PWM is available, the PLL output must
be set to 400 MHz.
3. This is the time required after the PLL is enabled to ensure reliable operation.
11.3.3 External crystal or resonator requirement
Table 22. Crystal or resonator requirement
Characteristic
Symbol
Min
Typ
Max
Unit
Frequency of operation
fXOSC
4
8
16
MHz
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NXP Semiconductors
51
System modules
11.3.4 RC Oscillator Timing
Table 23. RC Oscillator Electrical Specifications
Characteristic
Symbol
Min
Typ
Max
Unit
8 MHz Output Frequency1
Run Mode
0°C to 105°C
7.84
7.76
7.76
1.9
8
8
8.16
8.24
8.24
2.1
MHz
MHz
MHz
MHz
MHz
-40°C to 105°C
-40°C to 125°C
8
2M Mode (IRC trimmed @ -40°C to 105°C
8 MHz)
2.0
2.0
-40°C to 125°C
1.9
2.1
8 MHz Frequency Variation over 25°C
RUN Mode
0°C to 105°C
1.5
1.5
1.5
2
3
%
%
%
-40°C to 105°C
-40°C to 125°C
-3 to +3
200 kHz Output Frequency2
RUN Mode
-40°C to 105°C
-40°C to 125°C
194
192
200
200
206
208
kHz
kHz
200 kHz Output Frequency Variation over 25°C
RUN Mode
0°C to 85°C
1.5
1.5
1.5
-
2
3
%
%
%
µs
µs
%
-40°C to 105°C
-40°C to 125°C
8 MHz output3
200 kHz output3
4
Stabilization Time
Output Duty Cycle
tstab
1
15
375
55
-
125
50
45
1. Frequency after factory trim
2. Frequency after factory trim
3. Power down to run mode transition
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NXP Semiconductors
System modules
Figure 10. RC Oscillator Temperature Variation (Typical) After Trim (Preliminary)
11.4 Memories and memory interfaces
11.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
11.4.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 24. NVM program/erase timing specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
thvpgm4
Longword Program high-voltage time
—
7.5
18
μs
—
Table continues on the next page...
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53
System modules
Table 24. NVM program/erase timing specifications (continued)
Symbol Description
Min.
—
Typ.
13
Max.
113
Unit
ms
Notes
thversscr Sector Erase high-voltage time
1
1
thversall
Erase All high-voltage time
—
52
452
ms
1. Maximum time based on expectations at cycling end-of-life.
11.4.1.2 Flash timing specifications — commands
Table 25. Flash command timing specifications
Symbol Description
Min.
—
—
—
—
—
—
—
—
—
—
—
Typ.
—
Max.
60
Unit
μs
Notes
trd1sec1k Read 1s Section execution time (flash sector)
1
1
tpgmchk
trdrsrc
tpgm4
Program Check execution time
Read Resource execution time
Program Longword execution time
Erase Flash Sector execution time
Read 1s All Blocks execution time
Read Once execution time
—
45
μs
—
30
μs
1
65
14
—
145
114
1.8
25
μs
—
2
tersscr
trd1all
ms
ms
μs
1
trdonce
—
1
tpgmonce Program Once execution time
65
88
—
—
μs
—
2
tersall
tvfykey
tersallu
Erase All Blocks execution time
650
30
ms
μs
Verify Backdoor Access Key execution time
Erase All Blocks Unsecure execution time
1
88
650
ms
2
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
11.4.1.3 Flash high voltage current behaviors
Table 26. Flash high voltage current behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
IDD_PGM
Average current adder during high voltage
flash programming operation
—
2.5
6.0
mA
IDD_ERS
Average current adder during high voltage
flash erase operation
—
1.5
4.0
mA
11.4.1.4 Reliability specifications
Table 27. NVM reliability specifications
Symbol Description
Min.
Program Flash
Typ.1
Max.
Unit
Notes
tnvmretp10k Data retention after up to 10 K cycles
tnvmretp1k Data retention after up to 1 K cycles
5
50
—
—
years
years
—
—
20
100
Table continues on the next page...
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System modules
Table 27. NVM reliability specifications (continued)
Symbol Description
Min.
10 K
1 K
Typ.1
50 K
—
Max.
—
Unit
Notes
nnvmcycp Cycling endurance
nnvmcycp Cycling endurance
cycles
cycles
2
3
—
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant
25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering
Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.
3. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 135 °C. If the product application is
exposed to Tj > 125 °C, the reduced W/E spec applies independent of the number of W/E cycles in the high Tj band.
11.5 Analog
11.5.1 12-bit Cyclic Analog-to-Digital Converter (ADC) Parameters
Table 28. 12-bit ADC Electrical Specifications
Characteristic
Symbol
Min
Typ
Max
Unit
Recommended Operating Conditions
Supply Voltage1
VDDA
Vrefhx
fADCCLK
RAD
3
3.3
3.6
VDDA
12.5
V
V
VREFH (in external reference mode)
ADC Conversion Clock2
Conversion Range3
VDDA-0.6
0.1
MHz
V
VREFH – VREFL
VREFH
Fully Differential
– (VREFH – VREFL
VREFL
)
Single Ended/Unipolar
Input Voltage Range (per input)4
External Reference
VADIN
V
VREFL
0
VREFH
VDDA
Internal Reference
Timing and Power
Conversion Time5
tADC
8
ADC Clock
Cycles
ADC Power-Up Time (from adc_pdn)
ADC RUN Current (per ADC block)
tADPU
13
ADC Clock
Cycles
IADRUN
2.5
0.1
mA
µA
ADC Powerdown Current (adc_pdn
enabled)
IADPWRDWN
VREFH Current (in external mode)
Accuracy (DC or Absolute)
Integral non-Linearity6
Differential non-Linearity6
Monotonicity
IVREFH
190
225
µA
INL
+/- 1.5
+/- 0.5
+/- 2.2
+/- 0.8
LSB7
LSB7
DNL
GUARANTEED
Offset8
VOFFSET
mV
Table continues on the next page...
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System modules
Table 28. 12-bit ADC Electrical Specifications (continued)
Characteristic
Symbol
Min
Typ
Max
Unit
Fully Differential
+/- 8
Single Ended/Unipolar
Gain Error
+/- 12
EGAIN
0.996 to
1.004
0.990 to 1.010
AC Specifications9
Signal to Noise Ratio
SNR
THD
66
75
dB
dB
dB
dB
bits
Total Harmonic Distortion
Spurious Free Dynamic Range
Signal to Noise plus Distortion
Effective Number of Bits
Gain = 1x (Fully Differential/Unipolar)
Gain = 2x (Fully Differential/Unipolar)
Gain = 4x (Fully Differential/Unipolar)
Gain = 1x (Single Ended)
Gain = 2x (Single Ended)
Gain = 4x (Single Ended)
Variation across channels10
ADC Inputs
SFDR
SINAD
ENOB
77
66
—
10.6
—
10.3
10.6
10.4
10.2
0.1
Input Leakage Current
IIN
1
nA
mV/°C
V
Temperature sensor slope
Temperature sensor voltage at 25 °C
Disturbance
TSLOPE
VTEMP25
1.3
0.82
Input Injection Current 11
Channel to Channel Crosstalk12
Memory Crosstalk13
IINJ
+/-3
mA
dB
dB
pF
ISOXTLK
MEMXTLK
CADI
-82
-71
Input Capacitance
4.8
Sampling Capacitor
1. The ADC functions up to VDDA = 2.7 V. When VDDA is below 3.0 V, ADC specifications are not guaranteed
2. ADC clock duty cycle is 45% ~ 55%
3. Conversion range is defined for x1 gain setting. For x2 and x4 the range is 1/2 and 1/4, respectively.
4. In unipolar mode, positive input must be ensured to be always greater than negative input.
5. First conversion takes 10 clock cycles.
6. INL/DNL is measured from VIN = VREFL to VIN = VREFH using Histogram method at x1 gain setting
7. Least Significant Bit = 0.806 mV at 3.3 V VDDA, x1 gain Setting
8. Offset measured at 2048 code
9. Measured converting a 1 kHz input full scale sine wave
10. When code runs from internal RAM
11. The current that can be injected into or sourced from an unselected ADC input without affecting the performance of the
ADC
12. Any off-channel with 50 kHz full-scale input to the channel being sampled with DC input (isolation crosstalk)
13. From a previously sampled channel with 50 kHz full-scale input to the channel being sampled with DC input (memory
crosstalk).
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11.5.1.1 Equivalent circuit for ADC inputs
The following figure shows the ADC input circuit during sample and hold. S1 and S2 are
always opened/closed at non-overlapping phases, and both S1 and S2 are dependent on
the ADC clock frequency. The following equation gives equivalent input impedance
when the input is selected.
1
+
ohm
+Resistor
50
(ADC ClockRate) x CADI
NOTE
Resistor=1200 ohm@gain1×, or 730 ohm@gain2×, or 500
ohm@gain4×
C1
Channel Mux
equivalent resistance
S1
50 ESD
Resistor
Analog Input
C1
C1
Resistor(value see the note)
S1
S1
S/H
1
2
S1
S2
S2
(VREFHx - VREFLx ) / 2
C1
1. Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling =
1.8pF
2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal
routing = 2.04pF
3. S1 and S2 switch phases are non-overlapping and depend on the ADC clock
frequency
S1
S2
Figure 11. Equivalent circuit for A/D loading
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11.5.2 12-bit Digital-to-Analog Converter (DAC) parameters
NOTE
RLD = 3 kΩ and CLD = 400 pF, unless otherwise specified.
Table 29. DAC parameters
Parameter
Conditions/Comments
Symbol
Min
Typ
Max
Unit
DC Specifications
Resolution
Settling time1
12
—
12
12
bits
µs
At output load
RLD = 3 kΩ
1 (high-
speed
mode)
CLD = 400 pF
2 (low-
speed
mode)
Range of input digital words: 410 to
3891
Power-up time
Time from release of PWRDWN
signal until DACOUT signal is valid
tDAPU
—
—
11
µs
Accuracy
Integral non-linearity
Range of input digital words:
410 to 3891 ($19A - $F33)
INL
—
—
+/- 3
+/- 4
+/- 1
LSB
LSB
Differential non-linearity
Range of input digital words:
410 to 3891 ($19A - $F33)
DNL
+/- 0.5
Monotonicity
Offset error
> 6 sigma monotonicity,
< 3.4 ppm non-monotonicity
Range of input digital words:
410 to 3891 ($19A - $F33)
guaranteed
+/- 25
—
VOFFSET
—
—
+ /- 43
+/- 1.5
mV
Gain error
Range of input digital words: 410 to
3891 ($19A - $F33)
EGAIN
+/- 0.5
—
%
V
DAC Output
Output voltage range Within 40 mV of either VSSA or VDDA
VOUT
VSSA
0.04 V
+
VDDA - 0.04
V
AC Specifications
SNR
Signal-to-noise ratio
—
—
80
—
—
dB
dB
Spurious free dynamic
range
SFDR
-72
Effective number of bits
IDD from VDDA
ENOB
—
—
10
—
—
bits
mA
average IDD of VDDA (IDD varies with
DAC input word)
IDDA
3.2
1. When DAC output is fed to other internal peripherals, the settling time is much shorter.
11.5.3 OPAMP electrical specifications
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Table 30. OPAMP electrical specifications
Symbol
VCC
Description
Power supply
Supply current
Min.
3.0
—
Typ.
—
Max.
3.6
—
Unit
V
ICC
500
100
μA
• high-speed mode
• low-power mode
—
—
VOS
Input offset voltage
• high-speed mode
• low-power mode
—
—
1.5
2
5
mV
6.5
VIN
VOUT
CMRR
PSRR
SR
Common input voltage
VSSA
0.15
60
—
—
80
80
8
VDDA - 1.2
V
V
Output voltage range
VDDA - 0.15
Input common mode rejection ratio
Power supply rejection ratio
Slew rate 1
—
—
—
—
dB
dB
V/μs
60
4
• high-speed mode
• low-power mode
—
1
GBW
Unity gain bandwidth 1
• high-speed mode
• low-power mode
—
8
—
MHz
1.5
1. RL = 5 ~ 10 kΩ, CL = 30 ~ 50 pf
11.5.4 CMP and 8-bit DAC electrical specifications
Table 31. Comparator and 8-bit DAC electrical specifications
Symbol
VDD
Description
Min.
3.0
—
Typ.
—
Max.
3.6
—
Unit
V
Supply voltage
IDDHS
IDDLS
VAIN
Supply current, high-speed mode (EN=1, PMODE=1)
Supply current, low-speed mode (EN=1, PMODE=0)
Analog input voltage
Analog input offset voltage 1
Analog comparator hysteresis
• CR0[HYSTCTR] = 002
300
36
μA
μA
V
—
—
VSS
—
—
VDD
20
VAIO
—
mV
VH
—
—
—
—
5
13
48
mV
mV
mV
mV
• CR0[HYSTCTR] = 011
25
55
80
• CR0[HYSTCTR] = 101
105
148
• CR0[HYSTCTR] = 111
VCMPOh
VCMPOl
tDHS
Output high
Output low
VDD – 0.5
—
—
25
—
0.5
70
V
V
—
—
Propagation delay, high-speed mode (EN=1,
PMODE=1)3
ns
tDLS
Propagation delay, low-speed mode (EN=1,
PMODE=0)3
Analog comparator initialization delay4
—
—
60
40
200
—
ns
μs
Table continues on the next page...
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Table 31. Comparator and 8-bit DAC electrical specifications (continued)
Symbol
Description
Min.
—
Typ.
7
Max.
—
Unit
μA
V
IDAC8b
8-bit DAC current adder (enabled)
Vreference 8-bit DAC reference inputs, Vin1 and Vin2
—
VDD
—
There are two reference input options selectable (via
VRSEL control bit). The reference options must fall
within this range.
INL
8-bit DAC integral non-linearity
8-bit DAC differential non-linearity
–1
–1
—
—
1
1
LSB5
LSB
DNL
1. Measured with input voltage range limited to 0.7≤Vin≤VDD-0.8
2. Measured with input voltage range limited to 0 to VDD
3. Input voltage range: 0.1VDD≤Vin≤0.9VDD, step = 100mV, across all temperature. Does not include PCB and PAD delay.
4. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN,
VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.
5. 1 LSB = Vreference/256
250.00E-03
hystCR
200.00E-03
0
150.00E-03
1
100.00E-03
2
50.00E-03
3
000.00E+00
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
Vin Level (V)
2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2
Figure 12. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
400.00E-03
350.00E-03
300.00E-03
250.00E-03
200.00E-03
150.00E-03
100.00E-03
50.00E-03
hystCR
0
1
2
3
000.00E+00
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
Vin Level (V)
2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2
Figure 13. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
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PWMs and timers
11.6 PWMs and timers
11.6.1 Enhanced NanoEdge PWM characteristics
Table 32. NanoEdge PWM timing parameters
Characteristic
Symbol
pwmp
tpu
Min
Typ
100
312
Max
Unit
MHz
ps
PWM clock frequency
NanoEdge Placement (NEP) Step Size1, 2
Delay for fault input activating to PWM output deactivated
Power-up Time3
1
33
ns
25
µs
Resolution of Deadtime
312
ps
1. Reference IPbus clock of 100 MHz in NanoEdge Placement mode.
2. Temperature and voltage variations do not affect NanoEdge Placement step size.
3. Powerdown to NanoEdge mode transition.
11.6.2 Quad Timer timing
Parameters listed are guaranteed by design.
Table 33. Timer timing
Characteristic
Timer input period
Symbol
PIN
Min1
2T + 6
1T + 3
20
Max
—
Unit
ns
See Figure
Figure 14
Figure 14
Figure 14
Figure 14
Timer input high/low period
Timer output period
PINHL
POUT
—
ns
—
ns
Timer output high/low period
POUTHL
10
—
ns
1. T = clock cycle. For 100 MHz operation, T = 10 ns.
Timer Inputs
P
P
INHL
INHL
P
IN
Timer Outputs
P
P
OUTHL
OUTHL
P
OUT
Figure 14. Timer timing
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PWMs and timers
11.6.3 QDC Timing Specifications
Parameters listed are guaranteed by design.
Table 34. Quadrature Decoder Timing
Characteristic
Symbol
PIN
Min1
4T + 12
2T + 6
1T + 3
Max
—
Unit
ns
Quadrature input period
Quadrature input high/low period
Quadrature phase period
PHL
—
ns
PPH
—
ns
1. In the formulas listed, T equals the system clock cycle. For 50 MHz operation, T = 20 ns. For 100 MHz operation,
T = 10 ns.
PPH
PPH
PPH
PPH
Phase A
Input
PIN
PHL
PHL
Phase B
Input
PIN
PHL
PHL
PIN Input period
PPH Phase period
PHL Input high/low period
Figure 15. Quadrature Decoder Timing
11.7 Communication interfaces
11.7.1 Queued Serial Peripheral Interface (SPI) timing
Parameters listed are guaranteed by design.
Table 35. SPI timing
Characteristic
Symbol
Min
Max
Unit
See Figure
Cycle time
tC
Figure 16
60
—
ns
Table continues on the next page...
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PWMs and timers
Table 35. SPI timing (continued)
Characteristic
Symbol
Min
Max
Unit
See Figure
Master
60
—
ns
Figure 17
Figure 18
Slave
Figure 19
Figure 19
Enable lead time
Master
tELD
tELG
tCH
—
—
—
ns
ns
20
Slave
Enable lag time
Master
Figure 19
—
—
—
ns
ns
20
Slave
Clock (SCK) high time
Master
Figure 16
Figure 17
Figure 18
Figure 19
Figure 19
—
—
ns
ns
Slave
Clock (SCK) low time
tCL
28
28
—
—
ns
ns
Master
Slave
Data set-up time required for inputs
tDS
Figure 16
Figure 17
Figure 18
Figure 19
Figure 16
Figure 17
Figure 18
Figure 19
Figure 19
20
1
—
—
ns
ns
Master
Slave
Data hold time required for inputs
tDH
1
3
—
—
ns
ns
Master
Slave
Access time (time to data active
from high-impedance state)
tA
5
5
—
—
ns
ns
Slave
Disable time (hold time to high-
impedance state)
tD
Figure 19
Slave
Data valid for outputs
Master
tDV
Figure 16
Figure 17
Figure 18
Figure 19
Figure 16
Figure 17
Figure 18
Figure 19
Figure 16
—
—
ns
ns
Slave (after enable edge)
Data invalid
Master
tDI
0
0
—
—
ns
ns
Slave
Rise time
tR
Table continues on the next page...
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PWMs and timers
Table 35. SPI timing (continued)
Characteristic
Symbol
Min
Max
Unit
See Figure
Master
Slave
—
1
ns
Figure 17
—
1
ns
Figure 18
Figure 19
Figure 16
Fall time
Master
Slave
tF
—
—
1
1
ns
ns
Figure 17
Figure 18
Figure 19
SS
(Input)
SS is held high on master
t
C
t
R
t
F
t
CL
SCLK (CPOL = 0)
(Output)
t
CH
t
F
t
R
t
CL
SCLK (CPOL = 1)
(Output)
t
t
DH
CH
t
DS
MISO
(Input)
MSB in
t
Bits 14–1
LSB in
t (ref)
DI
t
DI
DV
MOSI
(Output)
Master MSB out
Bits 14–1
Master LSB out
t
t
R
F
Figure 16. SPI master timing (CPHA = 0)
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PWMs and timers
SS
(Input)
SS is held High on master
t
C
t
F
t
R
t
CL
SCLK (CPOL = 0)
(Output)
t
CH
t
F
t
CL
SCLK (CPOL = 1)
(Output)
t
CH
t
DS
t
R
t
DH
MISO
(Input)
MSB in
t
Bits 14–1
LSB in
t
(ref)
DI
t
DV
t (ref)
DV
DI
MOSI
(Output)
Master MSB out
Bits 14– 1
Master LSB out
t
t
R
F
Figure 17. SPI master timing (CPHA = 1)
SS
(Input)
t
C
t
F
t
ELG
t
CL
t
R
SCLK (CPOL = 0)
(Input)
t
CH
t
ELD
t
CL
SCLK (CPOL = 1)
(Input)
t
CH
t
F
t
t
A
R
t
D
MISO
(Output)
Slave MSB out
Bits 14–1
Slave LSB out
t
t
DS
DV
t
t
DI
DI
t
DH
MOSI
(Input)
MSB in
Bits 14–1
LSB in
Figure 18. SPI slave timing (CPHA = 0)
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PWMs and timers
SS
(Input)
t
F
t
C
t
R
t
CL
SCLK (CPOL = 0)
(Input)
t
CH
t
ELG
t
ELD
t
CL
SCLK (CPOL = 1)
(Input)
t
t
DV
CH
t
R
t
t
D
t
A
F
MISO
(Output)
Slave MSB out
Bits 14–1
Slave LSB out
t
t
DV
DS
t
DI
t
DH
MOSI
(Input)
MSB in
Bits 14–1
LSB in
Figure 19. SPI slave timing (CPHA = 1)
11.7.2 Queued Serial Communication Interface (SCI) timing
Parameters listed are guaranteed by design.
Table 36. SCI timing
Characteristic
Baud rate1
Symbol
BR
Min
—
Max
Unit
Mbit/s
μs
See Figure
—
(fMAX/16)
1.04/BR
1.04/BR
RXD pulse width
TXD pulse width
RXDPW
TXDPW
0.965/BR
0.965/BR
Figure 20
Figure 21
μs
LIN Slave Mode
Deviation of slave node clock from nominal FTOL_UNSYNCH
clock rate before synchronization
-14
14
2
%
%
—
—
Deviation of slave node clock relative to
the master node clock after
synchronization
FTOL_SYNCH
-2
Minimum break character length
TBREAK
13
11
—
—
Master
node bit
periods
—
—
Slave node
bit periods
1. fMAX is the frequency of operation of the SCI clock in MHz, which can be selected as the bus clock (max.50 MHz
depending on part number) or 2x bus clock (max. 100 MHz) for the devices.
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Design Considerations
RXD
SCI receive
data pin
RXD
PW
(Input)
Figure 20. RXD pulse width
TXD
SCI transmit
data pin
TXD
PW
(output)
Figure 21. TXD pulse width
11.7.3 LPI2C
Table 37. LPI2C specifications
Symbol Description
Min.
Max.
100
Unit
Notes
fSCL
SCL clock frequency
Standard mode (Sm)
Fast mode (Fm)
0
0
0
0
0
kHz
1, 2, 3
400
Fast mode Plus (Fm+)
Ultra Fast mode (UFm)
High speed mode (Hs-mode)
1000
5000
3400
1. Hs-mode is only supported in slave mode.
2. The maximum SCL clock frequency in Fast mode with maximum bus loading (400pF) can only be achieved with
appropriate pull-up devices on the bus when using the high or normal drive pins across the full voltage range . The
maximum SCL clock frequency in Fast mode Plus can support maximum bus loading (400pF) with appropriate pull-up
devices when using the high drive pins. The maximum SCL clock frequency in Ultra Fast mode can support maximum bus
loading (400pF) when using the high drive pins. The maximum SCL clock frequency for slave in High speed mode can
support maximum bus loading (400pF) with appropriate pull-up devices when using the high drive pins. For more
information on the required pull-up devices, see I2C Bus Specification.
3. See the section "General switching specifications".
12 Design Considerations
12.1 Thermal design considerations
An estimate of the chip junction temperature (TJ) can be obtained from the equation:
TJ = TA + (RΘJA × PD)
where
TA = Ambient temperature for the package (°C)
RΘJA = Junction-to-ambient thermal resistance (°C/W)
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67
Design Considerations
PD = Power dissipation in the package (W).
The junction-to-ambient thermal resistance is an industry-standard value that provides a
quick and easy estimation of thermal performance. Unfortunately, there are two values in
common usage: the value determined on a single-layer board and the value obtained on a
board with two planes. For packages such as the PBGA, these values can be different by
a factor of two. Which TJ value is closer to the application depends on the power
dissipated by other components on the board.
• The TJ value obtained on a single layer board is appropriate for a tightly packed
printed circuit board.
• The TJ value obtained on a board with the internal planes is usually appropriate if the
board has low-power dissipation and if the components are well separated.
When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-
case thermal resistance and a case-to-ambient thermal resistance:
RΘJA = RΘJC + RΘCA
where
RΘJA = Package junction-to-ambient thermal resistance (°C/W)
RΘJC = Package junction-to-case thermal resistance (°C/W)
RΘCA = Package case-to-ambient thermal resistance (°C/W).
RΘJC is device related and cannot be adjusted. You control the thermal environment to
change the case to ambient thermal resistance, RΘCA. For instance, you can change the
size of the heat sink, the air flow around the device, the interface material, the mounting
arrangement on printed circuit board, or change the thermal dissipation on the printed
circuit board surrounding the device.
To determine the junction temperature of the device in the application when heat
sinks are not used, the thermal characterization parameter (ΨJT) can be used to
determine the junction temperature with a measurement of the temperature at the top
center of the package case using the following equation:
TJ = TT + (ΨJT × PD)
where
TT = Thermocouple temperature on top of package (°C/W)
ΨJT = hermal characterization parameter (°C/W)
PD = Power dissipation in package (W).
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Design Considerations
The thermal characterization parameter is measured per JESD51–2 specification using a
40-gauge type T thermocouple epoxied to the top center of the package case. The
thermocouple should be positioned so that the thermocouple junction rests on the
package. A small amount of epoxy is placed over the thermocouple junction and over
about 1 mm of wire extending from the junction. The thermocouple wire is placed flat
against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
To determine the junction temperature of the device in the application when heat
sinks are used, the junction temperature is determined from a thermocouple inserted at
the interface between the case of the package and the interface material. A clearance slot
or hole is normally required in the heat sink. Minimizing the size of the clearance is
important to minimize the change in thermal performance caused by removing part of the
thermal interface to the heat sink. Because of the experimental difficulties with this
technique, many engineers measure the heat sink temperature and then back-calculate the
case temperature using a separate measurement of the thermal resistance of the interface.
From this case temperature, the junction temperature is determined from the junction-to-
case thermal resistance.
12.2 Electrical design considerations
CAUTION
This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields. However,
take normal precautions to avoid application of any voltages
higher than maximum-rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if unused inputs are
tied to an appropriate voltage level.
Use the following list of considerations to assure correct operation of the device:
• Provide a low-impedance path from the board power supply to each VDD pin on the
device and from the board ground to each VSS (GND) pin.
• The minimum bypass requirement is to place 0.01–0.1 µF capacitors positioned as
near as possible to the package supply pins. The recommended bypass configuration
is to place one bypass capacitor on each of the VDD/VSS pairs, including VDDA/VSSA
Ceramic and tantalum capacitors tend to provide better tolerances.
• Ensure that capacitor leads and associated printed circuit traces that connect to the
chip VDD and VSS (GND) pins are as short as possible.
.
• Bypass the VDD and VSS with approximately 100 µF, plus the number of 0.1 µF
ceramic capacitors.
• PCB trace lengths should be minimal for high-frequency signals.
MC56F81xxx, Rev. 1.1, 12/2020
NXP Semiconductors
69
Design Considerations
• Consider all device loads as well as parasitic capacitance due to PCB traces when
calculating capacitance. This is especially critical in systems with higher capacitive
loads that could create higher transient currents in the VDD and VSS circuits.
• Take special care to minimize noise levels on the VREF, VDDA, and VSSA pins.
• Using separate power planes for VDD and VDDA and separate ground planes for VSS
and VSSA are recommended. Connect the separate analog and digital power and
ground planes as near as possible to power supply outputs. If an analog circuit and
digital circuit are powered by the same power supply, then connect a small inductor
or ferrite bead in serial with VDDA. Traces of VSS and VSSA should be shorted
together.
• Physically separate analog components from noisy digital components by ground
planes. Do not place an analog trace in parallel with digital traces. Place an analog
ground trace around an analog signal trace to isolate it from digital traces.
• Because the flash memory is programmed through the JTAG/EOnCE port, SPI, SCI,
or I2C, the designer should provide an interface to this port if in-circuit flash
programming is desired.
• If desired, connect an external RC circuit to the RESET pin. The resistor value
should be in the range of 4.7 kΩ–10 kΩ; the capacitor value should be in the range of
0.1 µF–4.7 µF.
• Configuring the RESET pin to GPIO output in normal operation in a high-noise
environment may help to improve the performance of noise transient immunity.
• Add a 2.2 kΩ external pullup on the TMS pin of the JTAG port to keep EOnCE in a
reset state during normal operation if JTAG converter is not present. Furthermore,
configure TMS, TDI, TDO and TCK to GPIO if operation environment is very noisy.
• During reset and after reset but before I/O initialization, all the GPIO pins are at tri-
state.
• To eliminate PCB trace impedance effect, each ADC input should have a no less than
33 pF 10Ω RC filter.
12.3 Power-on Reset design considerations
12.3.1 Improper power-up sequence between VDD/VSS and VDDA/
VSSA:
It is recommended that VDD be kept within 100 mV of VDDA at all times, including
power ramp-up and ramp-down. Failure to keep VDD within 100 mV of VDDA may
cause a leakage current through the substrate, between the VDD and VDDA pad cells.
This leakage current could prevent operation of the device after it powers up. The voltage
MC56F81xxx, Rev. 1.1, 12/2020
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NXP Semiconductors
Obtaining package dimensions
difference between VDD and VDDA must be limited to below 0.3 V at all times, to avoid
permanent damage to the part (See the table in "Voltage and current operating ratings"
section). Also see the table in "Voltage and current operating requirements" section.
12.3.2 Heavy capacitive load on power supply output:
In some applications, the low cost DC/DC converter may not regulate the output voltage
well before it reaches the regulation point, which is roughly around 2.5V to 2.7V.
However, the device might exit power-on reset at around 2.3V. If the initialization code
enables the PLL to run the DSC at full speed right after reset, then the high current will
be pulled by DSC from the supply, which can cause the supply voltage to drop below the
operation voltage; see the captured graph (Figure 22). This can cause the DSC fail to start
up.
Figure 22. Supply Voltage Drop
A recommended initialization sequence during power-up is:
1. After POR is released, run a few hundred NOP instructions from the internal
relaxation oscillator; this gives time for the supply voltage to stabilize.
2. Configure the peripherals (except the ADC) to the desired settings; the ADC should
stay in low power mode.
3. Power up the PLL.
4. After the PLL locks, switch the clock from PLL prescale to postscale.
5. Configure the ADC.
13 Obtaining package dimensions
Package dimensions are provided in package drawings.
MC56F81xxx, Rev. 1.1, 12/2020
NXP Semiconductors
71
Product documentation
To find a package drawing, go to nxp.com and perform a keyword search for the
drawing's document number:
Drawing for package
32LQFP
Document number to be used
98ASH70029A
32QFN
98ASA00473D
48-pin LQFP
64-pin LQFP
98ASH00962A
98ASS23234W
14 Product documentation
The documents listed in Table 38 are required for a complete description and to
successfully design using the device. Documentation is available from local NXP
distributors, NXP sales offices, or online at www.nxp.com.
Table 38. Device documentation
Topic
Description
Document Number
DSP56800E/DSP56800EX
Reference Manual
Detailed description of the 56800EX family architecture, 32-bit
digital signal controller core processor, and the instruction set
DSP56800ERM
MC56F81xxx Reference Manual Detailed functional description and programming model
MC56F81XXXRM
MC56F81XXX
MC56F81xxx Data Sheet
Electrical and timing specifications, pin descriptions, and
package information (this document)
MC56F81xxx Errata
Details any chip issues that might be present
MC56F81XXX_0N91Z
15 Revision history
The following table provides a revision history for this document.
Table 39. Revision history
Rev.
1
Date
Substantial Changes
08/2020 Initial public release
1.1
12/2020 Added M-part devices (temperature range as –40 to 125℃), and updated related specifications: e.g.
the "Current Consumption" table, the "NVM reliability specifications" table.
MC56F81xxx, Rev. 1.1, 12/2020
72
NXP Semiconductors
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© 2019-2021 NXP B.V.
Document Number MC56F81XXX
Revision 1.1, 12/2020
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