MC34984CHFK [NXP]
High-Side Switch, 12V, Dual 4mOhm, PQFN 16, Tray;
| 型号： | MC34984CHFK |
| 厂家： | 
NXP |
| 描述： | High-Side Switch, 12V, Dual 4mOhm, PQFN 16, Tray |
| 文件： | 总36页 (文件大小：680K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MC34984
Rev. 1.0, 9/2014
ale Semiconductor
ce Information
Dual Intelligent High-current
Self-protected Silicon High-side
Switch (4.0 mOhm
34984
The 34984 is a dual self-protected 4.0 mOhm switch used to replace
electromechanical relays, fuses, and discrete devices in power management
applications. The 34984 is designed for harsh environments, and it includes
self-recovery features. The device is suitable for loads with high inrush current,
as well as motors and all types of resistive and inductive loads.
HIGH-SIDE SWITCH
Programming, control and diagnostics are implemented via the serial peripheral
interface (SPI). A dedicated parallel input is available for alternate and pulse-
width modulation (PWM) control of each output. SPI-programmable fault trip
thresholds allow the device to be adjusted for optimal performance in the
application.
The 34984 is packaged in a power-enhanced 12 x 12 mm nonleaded PQFN
package with exposed tabs and powered by SMARTMOS technology.
BOTTOM VIEW
FK SUFFIX
98ARL10521D
16-PIN PQFN
Features
• Dual 4.0 m max. high-side switch with parallel input or SPI control
• 6.0 V to 27 V operating voltage with standby currents < 5.0 A
• Output current monitoring with two SPI-selectable current ratios
• SPI control of overcurrent limit, overcurrent fault blanking time, output OFF
open load detection, output ON/OFF control, watchdog timeout, slew-rates,
and fault status reporting
• SPI status reporting of overcurrent, open and shorted loads,
overtemperature, undervoltage and overvoltage shutdown, fail-safe pin
status, and program status
Applications
• Low-voltage factory automation
• DC motor or solenoid
• Resistive and inductive loads
• Low-voltage industrial lighting
• Enhanced -16 V reverse polarity VPWR protection
VDD
VDD
VDD
VPWR
34984
VDD
FS
VPWR
GND
I/O
I/O
WAKE
SI
HS1
HS0
SO
SCLK
CS
SCLK
CS
MCU
SO
SI
LOAD
RST
INO
IN1
I/O
I/O
I/O
LOAD
CSNS
FSI
A/D
GND
Figure 1. 34984 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2014. All rights reserved.
BLE PARTS
ORDERABLE PARTS
Table 1. Orderable Part Variations
Temperature Range (T )
Package
Part Number
A
MC34984CHFK(1)
-40 °C to 125 °C
16 PQFN
Notes
1. To order parts in Tape & Reel, add the R2 suffix to the part number.
34984
Analog Integrated Circuit Device Data
2
Freescale Semiconductor
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VPWR
VDD
V
IC
Internal
Overvoltage
Protection
I
UP
Regulator
CS
SO
Programmable
Switch Delay
0–525 ms
Selectable Slew
Rate Gate Drive
SPI
3.0 MHz
HS0
Selectable Overcurrent
SI
SCLK
FS
High Detection
100A or 75A
IN[0:1]
RST
WAKE
Selectable Overcurrent
Selectable Overcurrent
Low Detection
7.5 –25 A
Low Detection
Blanking Time
0.15–155 ms
Logic
Open Load
Detection
Overtemperature
Detection
HS0
HS1
I
R
DWN
DWN
HS1
Programmable
Watchdog
V
IC
310–2500 ms
I
Selectable
UP
Output Current
Recopy
1/20500 or 1/41000
FSI
CSNS
GND
Figure 2. 34984 Simplified Internal Block Diagram
34984
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
ECTIONS
PIN CONNECTIONS
12 11 10
9
8
7
6
5
4
3
2
1
13
GND
TRANSPARENT
TOP VIEW
14
VPWR
16
HS0
15
HS1
Figure 3. 34984 Pin Connections (Transparent Top View)
Functional descriptions of many of these pins can be found in the Functional Pin Description section beginning on page 16.
Table 2. Pin Definitions
Pin
Pin
Pin Name
Formal Name
Definition
Function
1
2
CSNS
WAKE
Output
Output Current Monitoring This pin is used to output a current proportional to the designated HS0-1 output.
This pin is used to input a Logic [1] signal so as to enable the watchdog timer
Input
Wake
function.
This input pin is used to initialize the device configuration and fault registers, as
Reset (Active Low)
3
4
5
RST
IN0
FS
Input
Input
well as place the device in a low current Sleep mode.
Direct Input 0
This input pin is used to directly control the output HS0.
This is an open drain configured output requiring an external pull-up resistor to
VDD for fault reporting.
Output
Fault Status (Active Low)
The value of the resistance connected between this pin and ground determines
the state of the outputs after a watchdog timeout occurs.
6
7
FSI
CS
Input
Input
Input
Input
Input
Output
Fail-safe Input
Chip Select (Active Low)
Serial Clock
This input pin is connected to a chip select output of a master microcontroller
(MCU).
This input pin is connected to the MCU providing the required bit shift clock for
SPI communication.
8
SCLK
SI
This is a command data input pin connected to the SPI Serial Data Output of the
MCU or to the SO pin of the previous device of a daisy chain of devices.
9
Serial Input
Digital Drain Voltage
(Power)
10
11
VDD
SO
This is an external voltage input pin used to supply power to the SPI circuit.
This output pin is connected to the SPI serial data input pin of the MCU or to the
SI pin of the next device of a daisy chain of devices.
Serial Output
12
13
IN1
Input
Direct Input 1
Ground
This input pin is used to directly control the output HS1.
GND
Ground
This pin is the ground for the logic and analog circuitry of the device.
This pin connects to the positive power supply and is the source input of
operational power for the device.
14
VPWR
Input
Positive Power Supply
34984
Analog Integrated Circuit Device Data
4
Freescale Semiconductor
PIN CONNECTIONS
Table 2. Pin Definitions (continued)
Pin
Pin
Pin Name
Formal Name
Definition
Function
15
16
HS1
HS0
Output
High-side Output 1
High-side Output 0
Protected 4.0 m high-side power output to the load.
Protected 4.0 m high-side power output to the load.
Output
34984
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
CAL CHARACTERISTICS
RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings
All voltages are with respect to ground unless otherwise noted.
Symbol
Rating
Value
Unit
Notes
ELECTRICAL RATINGS
Operating Voltage Range
VPWR
-16 to 41
V
V
Steady-state
VDD
VDD Supply Voltage
-0.3 to 5.5
VIN[0:1], RST, FSI,
CSNS, SI, SCLK, Input/Output Voltage
CS, FS
(2)
(2)
-0.3 to 7.0
V
VSO
SO Output Voltage
-0.3 to VDD+0.3
V
ICL(WAKE)
ICL(CSNS)
WAKE Input Clamp Current
CSNS Input Clamp Current
2.5
10
mA
mA
Output Voltage
Positive
VHS
41
-15
V
A
J
Negative
(3)
(4)
IHS[0:1]
Output Current
30
Output Clamp Energy
34984B
ECL[0:1]
0.75
0.5
34984C
ESD Voltage
VESD1
VESD3
Human Body Model (HBM)
Charge Device Model (CDM)
Corner Pins (1, 12, 15, 16)
All Other Pins (2, 11, 13, 14)
±2000
(5)
V
±750
±500
Notes
2. Exceeding this voltage limit may cause permanent damage to the device.
3. Continuous high-side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output current using
package thermal resistance is required.
4. Active clamp energy using single-pulse method (L = 16 mH, RL = 0,VPWR = 12 V, TJ = 150 °C).
5. ESD1 testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 ESD3 testing is performed in
accordance with the Charge Device Model (CDM), Robotic (CZAP = 4.0 pF).
34984
Analog Integrated Circuit Device Data
6
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings (continued)
All voltages are with respect to ground unless otherwise noted.
Symbol
Rating
Value
Unit
Notes
THERMAL RATINGS
Operating Temperature
Ambient
TA
TJ
-40 to 125
-40 to 150
C
C
Junction
TSTG
Storage Temperature
-55 to 150
Thermal Resistance
Junction-to-Case
(7)
R
R
<1.0
30
C/W
JC
Junction-to-Ambient
JA
(8), (9)
°C
TPPRT
Peak Package Reflow Temperature During Reflow
Note 9
Notes
6. To achieve high reliability over 10 years of continuous operation, the device's continuous operating junction temperature should not exceed 125 C
7. Device mounted on a 2s2p test board according to JEDEC JESD51-2.
8. Pin soldering temperature limit is for 40 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause
malfunction or permanent damage to the device.
9. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020. For Peak Package Reflow Temperature and
Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view
all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
34984
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
CAL CHARACTERISTICS
LECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics
Characteristics noted under conditions 4.5 V VDD 5.5 V, 6.0 V VPWR 27 V, -40 C TA 125 C, unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit
Notes
POWER INPUT
Power Supply Voltage Range
VPWR
6.0
–
–
–
27
20
V
Full Operational
VPWR Operating Supply Current
Output ON, IHS0 and IHS1 = 0 A
IPWR(ON)
mA
VPWR Supply Current
Output OFF, Open Load Detection Disabled, WAKE > 0.7 x VDD,
RST = VLOGIC HIGH
IPWR(SBY)
–
–
5.0
mA
Sleep State Supply Current (VPWR < 14 V, RST < 0.5 V, WAKE <
0.5 V)
IPWR(SLEEP)
A
TJ = 25 C
TJ = 85 C
–
–
–
–
10
50
VDD(ON)
VDD Supply Voltage
4.5
5.0
5.5
V
VDD Supply Current
IDD(ON)
No SPI Communication
3.0 MHz SPI Communication
–
–
–
–
1.0
5.0
mA
IDD(SLEEP)
VPWR(OV)
VPWR(OVHYS)
VPWR(UV)
VDD Sleep State Current
–
28
0.2
5.0
–
–
32
5.0
36
1.5
6.0
–
A
V
Overvoltage Shutdown Threshold
Overvoltage Shutdown Hysteresis
Undervoltage Output Shutdown Threshold
Undervoltage Hysteresis
0.8
5.5
0.25
–
V
(10)
(11)
V
VPWR(UVHYS)
VPWR(UVPOR)
POWER OUTPUT
V
Undervoltage Power-ON Reset
–
5.0
V
Output Drain-to-Source ON Resistance (IHS[0:1] = 15 A, TJ = 25 C)
VPWR = 6.0 V
–
–
–
–
–
–
6.0
4.0
4.0
m
m
RDS(on)
VPWR = 10 V
VPWR = 13 V
Output Drain-to-Source ON Resistance (IHS[0:1] = 15 A, TJ = 150 C)
VPWR = 6.0 V
–
–
–
–
–
–
10.2
7.2
6.8
RDS(on)
VPWR = 10 V
VPWR = 13 V
Output Source-to-Drain ON Resistance IHS[0:1] = 15 A, TJ = 25 C
(12)
RDS(on)
m
VPWR = -12 V
–
–
8.0
Output Overcurrent High Detection Levels (9.0 V < VPWR < 16 V)
IOCH0
IOCH1
SOCH = 0
SOCH = 1
80
60
100
75
120
90
A
Notes
10. This applies to all internal device logic supplied by VPWR and assumes the external VDD supply is within specification.
11. This applies when the undervoltage fault is not latched (IN[0:1] = 0).
12. Source-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VPWR
.
34984
Analog Integrated Circuit Device Data
8
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 4.5 V VDD 5.5 V, 6.0 V VPWR 27 V, -40 C TA 125 C, unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit
Notes
POWER OUTPUT (CONTINUED)
Overcurrent Low Detection Levels (SOCL[2:0])
IOCL0
IOCL1
IOCL2
IOCL3
IOCL4
IOCL5
IOCL6
IOCL7
000
001
010
011
100
101
110
111
21
18
16
14
12
10
8.0
6.0
25
22.5
20
17.5
15
12.5
10
7.5
29
27
24
21
18
15
12
9.0
A
Current Sense Ratio (9.0 V < VPWR < 16 V, CSNS < 4.5 V)
CSR0
CSR1
DICR D2 = 0
DICR D2 = 1
–
–
1/20500
1/41000
–
–
–
Current Sense Ratio (CSR0) Accuracy
Output Current
5.0 A
-20
-14
-13
-12
-13
-13
–
–
–
–
–
–
20
14
13
12
13
13
10 A
12.5 A
15 A
20 A
25 A
CSR0_ACC
%
Current Sense Ratio (CSR1) Accuracy
Output Current
5.0 A
-25
-19
-18
-17
-18
-18
–
–
–
–
–
–
25
19
18
17
18
18
10 A
12.5 A
15 A
20 A
25 A
CSR1_ACC
%
Current Sense Clamp Voltage
CSNS Open; IHS[0:1] = 29 A
VCL(CSNS)
IOLDC
4.5
30
6.0
–
7.0
100
4.0
V
A
V
(13)
Open Load Detection Current
Output Fault Detection Threshold
Output Programmed OFF
VOLD(THRES)
2.0
3.0
Output Negative Clamp Voltage
VCL
-20
–
-15
V
0.5 A < IHS[0:1] < 2.0 A, Output OFF
(14)
(14)
TSD
Overtemperature Shutdown
160
5.0
175
–
190
20
C
C
TSD(HYS)
Overtemperature Shutdown Hysteresis
Notes
13. Output OFF open load detection current is the current required to flow through the load for the purpose of detecting the existence of an open load
condition when the specific output is commanded OFF.
14. Guaranteed by process monitoring. Not production tested.
34984
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
CAL CHARACTERISTICS
LECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 4.5 V VDD 5.5 V, 6.0 V VPWR 27 V, -40 C TA 125 C, unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit
Notes
Control Interface
(15)
(15)
(16)
VIH
VIL
Input Logic High-voltage
Input Logic Low-voltage
0.7 x VDD
–
–
–
0.2 x VDD
1200
20
V
V
–
100
5.0
4.5
–
VIN[0:1](HYS)
IDWN
Input Logic Voltage Hysteresis
Input Logic Pull-down Current (SCLK, IN, SI)
RST Input Voltage Range
600
–
mV
A
V
VRST
5.0
–
5.5
(17)
CSO
SO, FS Tri-state Capacitance
20
pF
k
pF
RDWN
CIN
Input Logic Pull-down Resistor (RST) and WAKE
Input Capacitance
100
–
200
4.0
400
(17)
(18)
12
WAKE Input Clamp Voltage
ICL(WAKE) < 2.5 mA
VCL(WAKE)
VF(WAKE)
VSOH
7.0
-2.0
–
–
14
-0.3
–
V
V
WAKE Input Forward Voltage
ICL(WAKE) = -2.5 mA
SO High-state Output Voltage
IOH = 1.0 mA
0.8x VDD
–
V
FS, SO Low-state Output Voltage
IOL = -1.6 mA
VSOL
–
0.2
0.0
–
0.4
5.0
20
V
SO Tri-state Leakage Current
CS > 0.7VDD
ISO(LEAK)
-5.0
A
A
Input Logic Pull-up Current
CS, VIN[0:1] > 0.7 x VDD
(19)
IUP
5.0
RFS
RFSDIS
RFSOFFOFF
RFSONOFF
RFSONON
FSI Input Pin External Pull-down Resistance
FSI Disabled, HS[0:1] Indeterminate
FSI Enabled, HS[0:1] OFF
–
0.0
6.5
17
1.0
7.0
19
–
6.0
15
40
k
FSI Enabled, HS0 ON, HS1 OFF
FSI Enabled, HS[0:1] ON
Infinite
Notes
15. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IN[0:1], and WAKE input signals. The WAKE and RST signals may
be supplied by a derived voltage reference to VPWR
.
16. No hysteresis on FSI and WAKE pins. Parameter is guaranteed by processing monitoring but is not production tested.
17. Input capacitance of SI, CS, SCLK, RST, and WAKE. This parameter is guaranteed by process monitoring but is not production tested.
18. The current must be limited by a series resistance when using voltages > 7.0 V.
19. Pull-up current is with CS Open. CS has an active internal pull-up to VDD
.
34984
Analog Integrated Circuit Device Data
10
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions 4.5 V VDD 5.5 V, 6.0 V VPWR 27 V, -40 C TA 125 C, unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit
Notes
POWER OUTPUT TIMING
Output Rising Slow Slew Rate A (DICR D3 = 0)
9.0 V < VPWR < 16 V
(20)
(21)
(20)
(21)
(20)
(21)
(20)
SRRA_SLOW
SRRB_SLOW
SRRA_FAST
0.15
0.06
0.3
0.5
0.2
0.8
0.2
0.5
0.2
1.6
1.0
0.6
3.2
2.4
1.0
0.6
3.2
V/s
V/s
V/s
V/s
V/s
V/s
V/s
Output Rising Slow Slew Rate B (DICR D3 = 0)
9.0 V < VPWR < 16 V
Output Rising Fast Slew Rate A (DICR D3 = 1)
9.0 V < VPWR < 16 V
Output Rising Fast Slew Rate B (DICR D3 = 1)
9.0 V < VPWR < 16 V
SRRB_FAST
SRFA_SLOW
0.06
0.15
0.06
0.6
Output Falling Slow Slew Rate A (DICR D3 = 0)
9.0 V < VPWR < 16 V
Output Falling Slow Slew Rate B (DICR D3 = 0)
9.0 V < VPWR < 16 V
SRFB_SLOW
SRFA_FAST
SRFB_FAST
Output Falling Fast Slew Rate A (DICR D3 = 1)
9.0 V < VPWR < 16 V
Output Falling Fast Slew Rate B (DICR D3 = 1)
9.0 V < VPWR < 16 V
(21)
(22)
(23)
(23)
0.2
0.5
10
0.7
18
2.4
100
250
V/s
s
Output Turn-ON Delay Time in Fast/Slow Slew Rate
DICR = 0, DICR = 1
tDLY(ON)
Output Turn-OFF Delay Time in Slow Slew Rate Mode
DICR = 0
tDLY_SLOW(OFF)
115
s
Output Turn-OFF Delay Time in Fast Slew Rate Mode
DICR = 1
tDLY_FAST(OFF)
fPWM
1.0
–
30
100
–
s
Direct Input Switching Frequency (DICR D3 = 0)
300
Hz
Overcurrent Detection Blanking Time (OCLT[1:0])
tOCL0
tOCL1
tOCL2
tOCL3
00
01
10
11
108
7.0
0.8
155
10
1.2
202
13
1.6
ms
0.08
0.15
0.25
tOCH
Overcurrent High Detection Blanking Time
CS to CSNS Valid Time
1.0
–
10
–
20
10
s
s
(24)
tCNSVAL
Notes
20. Rise and Fall Slew Rates A measured across a 5.0 resistive load at high-side output = 0.5 V to VPWR- 3.5 V. These parameters are guaranteed
by process monitoring.
21. Rise and Fall Slew Rates B measured across a 5.0 resistive load at high-side output = VPWR-3.5 V to VPWR-0.5 V. These parameters are
guaranteed by process monitoring.
22. Turn-ON delay time measured from rising edge of IN[0:1] signal that would turn the output ON to VHS[0:1] = 0.5 V with RL = 5.0 resistive load.
23. Turn-OFF delay time measured from falling edge that would turn the output OFF to VHS[0:1] = VPWR-0.5 V with RL = 5.0 resistive load.
24. Time necessary for the CSNS to be within ±5% of the targeted value.
34984
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
CAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 4.5 V VDD 5.5 V, 6.0 V VPWR 27 V, -40 C TA 125 C, unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit
Notes
POWER OUTPUT TIMING (CONTINUED)
HS1 Switching Delay Time (OSD[2:0])
tOSD0
tOSD1
tOSD2
tOSD3
tOSD4
tOSD5
tOSD6
tOSD7
000
001
010
011
100
101
110
111
–
55
0
75
–
95
110
165
220
275
330
385
150
225
300
375
450
525
190
285
380
475
570
665
ms
HS0 Switching Delay Time (OSD[2:0])
tOSD0
tOSD1
tOSD2
tOSD3
tOSD4
tOSD5
tOSD6
tOSD7
000
001
010
011
100
101
110
111
–
–
0
0
–
–
110
110
220
220
330
330
150
150
300
300
450
450
190
190
380
380
570
570
ms
ms
Watchdog Timeout (WD[1:0])
tWDTO0
tWDTO1
tWDTO2
tWDTO3
00
01
10
11
434
207
1750
875
620
310
2500
1250
806
403
3250
1625
(25)
SPI INTERFACE CHARACTERISTICS
fSPI
tWRST
tCS
Recommended Frequency of SPI Operation
–
–
–
–
–
–
–
–
–
–
–
50
–
3.0
350
300
5.0
167
167
167
167
83
MHz
ns
ns
s
ns
ns
ns
ns
ns
ns
(26)
(27)
(27)
(27)
(27)
(27)
(27)
(28)
(28)
Required Low State Duration for RST
Rising Edge of CS to Falling Edge of CS (Required Setup Time)
Rising Edge of RST to Falling Edge of CS (Required Setup Time)
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)
Required High State Duration of SCLK (Required Setup Time)
Required Low State Duration of SCLK (Required Setup Time)
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)
SI to Falling Edge of SCLK (Required Setup Time)
tENBL
–
tLEAD
50
–
tWSCLKh
tWSCLKl
tLAG
–
50
25
25
tSI(SU)
tSI(HOLD)
Falling Edge of SCLK to SI (Required Setup Time)
83
SO Rise Time
CL = 200 pF
tRSO
tFSO
ns
ns
–
25
50
SO Fall Time
CL = 200 pF
–
–
–
25
–
50
50
50
(28)
(28)
tRSI
tRSI
SI, CS, SCLK, Incoming Signal Rise Time
SI, CS, SCLK, Incoming Signal Fall Time
ns
ns
–
Notes
25. Watchdog timeout delay measured from the rising edge of WAKE to RST from a sleep-state condition to output turn-ON with the output driven OFF
and FSI floating. The values shown are for WDR setting of [00]. The accuracy of tWDTO is consistent for all configured watchdog timeouts.
26. RST low duration measured with outputs enabled and going to OFF or disabled condition.
27. Maximum setup time required for the 34984 is the minimum guaranteed time needed from the microcontroller.
28. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
34984
Analog Integrated Circuit Device Data
12
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
Table 5. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 4.5 V VDD 5.5 V, 6.0 V VPWR 27 V, -40 C TA 125 C, unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Symbol
Characteristic
Min
Typ
Max
Unit
Notes
SPI INTERFACE CHARACTERISTICS (CONTINUED)
Time from Falling Edge of CS to SO Low-impedance
(29)
(30)
tSO(EN)
tSO(DIS)
–
–
–
145
145
ns
ns
Time from Rising Edge of CS to SO High-impedance
65
Time from Rising Edge of SCLK to SO Data Valid
(31)
tVALID
ns
0.2 x VDD SO 0.8 x VDD, CL = 200 pF
–
65
105
Notes
29. Time required for output status data to be available for use at SO. 1.0 kon pull-up on CS.
30. Time required for output status data to be terminated at SO. 1.0 kon pull-up on CS.
31. Time required to obtain valid data out from SO following the rise of SCLK.
TIMING DIAGRAMS
CS
VPWR
VPWR -0.5 V
S
SRRB_SLOW & SRRB_FAST
SRFB_SLOW & SRFB_FAST
VPWR-3.5V
SRRA_SLOW & SRRA_FAST
SRFA_SLOW & SRFA_FAST
0.5 V
HS
tDLY_SLOW(OFF) & tDLY_FAST(OFF)
t
DLY(ON)
Figure 4. Output Slew Rate and Time Delays
IOCHx
Load
Current
IOCLx
tOCH
Time
tOCLx
Figure 5. Overcurrent Shutdown
34984
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
CAL CHARACTERISTICS
AGRAMS
I
I
I
OCH0
OCH1
OCL0
IOCL1
I
OCL2
Load
Current
I
OCL3
I
I
I
I
OCL4
OCL5
OCL6
OCL7
Time
t
t
t
t
t
OCL0
OCHx
OCL3
OCL2
OCL1
Figure 6. Overcurrent Low and High Detection
Figure 6 illustrates the overcurrent detection level (Ioclx, Iochx) the device can reach for each overcurrent detection blanking time (tochx,
toclx):
• During tochx, the device can reach up to Ioch0 overcurrent level.
• During tocl3 or tocl2 or tocl1 or tocl0, the device can be programmed to detect up to Iocl0.
VIH
RST
0.2 x VDD
0.2 VDD
VIL
tENBL
t CS
tWRST
VIH
0.7 x V
DD
C
0.2xVDD
VIL
tRSI
t
WSCLKh
TrSI
t
LEAD
tLAG
VIH
0.7 x VDD
SCLK
0.2 x VDD
VIL
t
SI(SU)
t
WSCLKl
tFSI
t
SI(HOLD)
VIH
0.7xV
DD
Don’t Care
Don’t Care
Don’t Care
Valid
Valid
SI
0.2xVDD
V
IH
Figure 7. Input Timing Switching Characteristics
34984
Analog Integrated Circuit Device Data
14
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
tRSI
tFSI
VOH
3.5 V
50%
SCLK
1.0 V
VOL
tSO(EN)
VOH
0.7 x V
DD
SO
0.2xVDD
VOL
Low to High
tRSO
tVALID
tFSO
SO
VOH
0.7 x V
DD
High to Low
0.2 x VDD
VOL
tSO(DIS)
Figure 8. SCLK Waveform and Valid SO Data Delay Time
34984
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
NAL DESCRIPTION
NAL PIN DESCRIPTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 34984 is a dual self-protected 4.0 m silicon switch used to replace electromechanical relays, fuses, and discrete devices in power
management applications. The 34984 is designed for harsh environments, and it includes self-recovery features. The device is suitable
for loads with high inrush current, as well as motors and all types of resistive and inductive loads.
Programming, control, and diagnostics are implemented via the serial peripheral interface (SPI). A dedicated parallel input is available for
alternate and pulse width modulation (PWM) control of each output. SPI-programmable fault trip thresholds allow the device to be adjusted
for optimal performance in the application.
The 34984 is packaged in a power-enhanced 12 x 12 nonleaded PQFN package with exposed tabs.
FUNCTIONAL PIN DESCRIPTION
OUTPUT CURRENT MONITORING (CSNS)
This pin is used to output a current proportional to the designated HS0-1 output. That current is fed into a ground-referenced resistor and
its voltage is monitored by an MCU's A/D. The channel to be monitored is selected via the SPI. This pin can be tri-stated through the SPI.
WAKE (WAKE)
This pin is used to input a Logic [1] signal so as to enable the watchdog timer function. An internal clamp protects this pin from high
damaging voltages when the output is current limited with an external resistor. This input has a passive internal pull-down.
RESET (RST)
This input pin is used to initialize the device configuration and fault registers, as well as place the device in a low-current Sleep mode. The
pin also starts the watchdog timer when transitioning from Logic Low to Logic High. This pin should not be allowed to be Logic High until
VDD is in regulation. This pin has a passive internal pull-down.
DIRECT IN 0 & 1 (INx)
This input pin is used to directly control the output HS0 and 1. This input has an active internal pull-down current source and requires
CMOS logic levels. This input may be configured via the SPI.
FAULT STATUS (FS)
This is an open drain configured output requiring an external pull-up resistor to VDD for fault reporting. When a device fault condition is
detected, this pin is active Low. Specific device diagnostic faults are reported via the SPI SO pin.
FAIL-SAFE INPUT (FSI)
The value of the resistance connected between this pin and ground determines the state of the outputs after a watchdog timeout occurs.
Depending on the resistance value, either all outputs are OFF, ON, or the output HS0 only is ON. When the FSI pin is connected to GND,
the watchdog circuit and Fail-safe operation are disabled. This pin incorporates an active internal pull-up current source.
CHIP SELECT (CS)
This input pin is connected to a chip select output of a master microcontroller (MCU). The MCU determines which device is addressed
(selected) to receive data by pulling the CS pin of the selected device Logic Low, enabling SPI communication with the device. Other
unselected devices on the serial link having their CS pins pulled-up Logic High disregard the SPI communication data sent. This pin
incorporates an active internal pull-up current source.
SERIAL CLOCK (SCLK)
This input pin is connected to the MCU providing the required bit shift clock for SPI communication. It transitions one time per bit transferred
at an operating frequency, fSPI, defined by the communication interface. The 50 percent duty cycle CMOS-level serial clock signal is idle
between command transfers. The signal is used to shift data into and out of the device. This input has an active internal pull-down current
source.
SERIAL INPUT (SI)
This is a command data input pin connected to the SPI Serial Data Output of the MCU or to the SO pin of the previous device of a daisy
chain of devices. The input requires CMOS logic-level signals and incorporates an active internal pull-down current source. Device control
is facilitated by the input's receiving the MSB first of a serial 8-bit control command. The MCU ensures data is available upon the falling
edge of SCLK. The logic state of SI present upon the rising edge of SCLK loads that bit command into the internal command shift register.
34984
Analog Integrated Circuit Device Data
16
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
DIGITAL DRAIN VOLTAGE (VDD)
This is an external voltage input pin used to supply power to the SPI circuit. In the event VDD is lost, an internal supply provides
power to a portion of the logic, ensuring limited functionality of the device. All device configuration registers are reset.
SERIAL OUTPUT (SO)
This output pin is connected to the SPI Serial Data Input pin of the MCU or to the SI pin of the next device of a daisy chain of
devices. This output will remain tri-stated (high-impedance OFF condition) so long as the CS pin of the device is Logic High. SO
is only active when the CS pin of the device is asserted Logic Low. The generated SO output signals are CMOS logic levels. SO
output data is available on the falling edge of SCLK and transitions immediately on the rising edge of SCLK.
POSITIVE POWER SUPPLY (VPWR)
This pin connects to the positive power supply and is the source input of operational power for the device. The VPWR pin is a
backside surface mount tab of the package.
HIGH-SIDE OUTPUT 0 & 1 (HSx)
This pin protects 4.0 m high-side power output to the load.
34984
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
NAL DESCRIPTION
NAL INTERNAL BLOCK DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
POWER SUPPLY
SELF-PROTECTED
High-side Switch
MCU INTERFACE AND
OUTPUT CONTROL
HS [0:1]
SPI INTERFACE
MCU
INTERFACE
PARALLEL CONTROL
INPUTS
POWER SUPPLY
The 34984 is designed to operate from 4.0 V to 28 V on the VPWR pin. Characteristics are provided from 6.0 V to 20 V for the device. The
VPWR pin supplies power to internal regulator, analog, and logic circuit blocks. The VDD supply is used for serial peripheral interface (SPI)
communication in order to configure and diagnose the device. This IC architecture provides a low quiescent current sleep mode. Applying
VPWR and VDD to the device will place the device in the Normal mode. The device will transit to Fail-safe mode in case of failures on the
SPI (watchdog timeout).
HIGH-SIDE SWITCH: HS[0:1]
Those pins are the high-side outputs controlling multiple loads with high inrush current, as well as motors and all types of resistive and
inductive loads. This N-channel MOSFET with 4.0 m RDS(on), is self-protected and each N-channel presents extended diagnostics in
order to detect load disconnections and short-circuit fault conditions. The HS[0:1] outputs are actively clamped during a turn-off of inductive
loads.
MCU INTERFACE AND OUTPUT CONTROL
In Normal mode, the loads are controlled directly from the MCU through the SPI. With a dedicated SPI command, it is possible to
independently turn on and off several loads that are PWMed at the same frequency, and duty cycles with only one PWM signal. An analog
feedback output provides a current proportional to each load current. The SPI is used to configure and to read the diagnostic status (faults)
of the high-side output. The reported fault conditions are: open load, short-circuit to ground (OCLO-resistive and OCHI-severe short-
circuit), thermal shutdown, and under/overvoltage.
In Fail-safe mode, the loads are controlled with dedicated parallel input pins. The device is configured in default mode.
34984
Analog Integrated Circuit Device Data
18
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
The 34984 has four operating modes: Sleep, Normal, Fault, and Fail-safe. Table 6 summarizes details contained in succeeding
paragraphs.
Table 6. Fail-safe Operation and Transitions to Other 34984 Modes
WAK
E
WDT
O
Mode
FS
RST
Comments
Sleep
x
1
0
0
1
1
1
0
x
1
x
0
1
1
0
1
x
1
1
1
0
x
Device is in Sleep mode. All outputs are OFF.
Normal mode. Watchdog is active if enabled.
Normal
No
Fault
No
The device is currently in Fault mode. The faulted output(s) is (are) OFF.
Watchdog has timed out and the device is in Fail-safe mode. The outputs are as configured with the RFS
resistor connected to FSI. RST and WAKE must be transitioned to Logic [0] simultaneously to bring the device
out of the Fail-safe mode or momentarily tied the FSI pin to ground.
Fail-
safe
Yes
x = Don’t care.
SLEEP MODE
The default mode of the 34984 is the Sleep mode. This is the state of the device after first applying power voltage (VPWR), prior to any I/
O transitions. This is also the state of the device when the WAKE and RST are both Logic [0]. In the Sleep mode, the output and all unused
internal circuitry, such as the internal 5.0 V regulator, are off to minimize current draw. In addition, all SPI-configurable features of the
device are as if set to Logic [0]. The device will transition to the Normal or Fail-safe operating modes based on the WAKE and RST inputs
as defined in Table 6.
NORMAL MODE
The 34984 is in Normal mode when:
• VPWR is within the normal voltage range.
•
RST pin is Logic [1].
• No fault has occurred.
FAIL-SAFE AND WATCHDOG
If the FSI input is not grounded, the watchdog timeout detection is active when either the WAKE or RST input pin transitions from Logic [0]
to Logic [1]. The WAKE input is capable of being pulled up to VPWR with a series of limiting resistance that limits the internal clamp current
according to the specification.
The watchdog timeout is a multiple of an internal oscillator and is specified in Table 15. As long as the WD bit (D7) of an incoming SPI
message is toggled within the minimum watchdog timeout period (WDTO), based on the programmed value of the WDR the device will
operate normally. If an internal watchdog timeout occurs before the WD bit, the device will revert to a Fail-safe mode until the device is
reinitialized.
During the Fail-safe mode, the outputs will be ON or OFF depending upon the resistor RFS connected to the FSI pin, regardless of the
state of the various direct inputs and modes (Table 7). In this mode, the SPI register content is retained except for overcurrent high and
low detection levels and timing, which are reset to their default value (SOCL, SOCH, and OCLT). Then the watchdog, overvoltage,
overtemperature, and overcurrent circuitry (with default value) are fully operational.
Table 7. Output State During Fail-safe Mode
RFS (k)
High-side State
Fail-safe mode Disabled
Both HS0 and HS1 OFF
HS0 ON, HS1 OFF
0
6.0
15
30
Both HS0 and HS1 ON
34984
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
NAL DEVICE OPERATION
ION AND DIAGNOSIS FEATURES
The Fail-safe mode can be detected by monitoring the WDTO bit D2 of the WD register. This bit is Logic [1] when the device is in Fail-safe
mode. The device can be brought out of the Fail-safe mode by transitioning the WAKE and RST pins from Logic [1] to Logic [0] or forcing
the FSI pin to Logic [0]. Table 6 summarizes the various methods for resetting the device from the latched Fail-safe mode.
If the FSI pin is tied to GND, the watchdog Fail-safe operation is disabled.
LOSS OF VDD
If the external 5.0 V supply is not within specification, or even disconnected, all register content is reset. The two outputs can still be driven
by the direct inputs IN1:IN0. The 34984 uses the supply input to power the output MOSFET related current sense circuitry and any other
internal logic providing Fail-safe device operation with no VDD supplied. In this state, the watchdog, overvoltage, overtemperature, and
overcurrent circuitry are fully operational with default values.
FAULT MODE
The 34984 indicates the following faults as they occur by driving the FS pin to Logic [0]:
• Overtemperature fault
• Open load fault
• Overcurrent fault (high and low)
• Overvoltage and undervoltage fault
The FS pin will automatically return to Logic [1] when the fault condition is removed, except for overcurrent and in some cases
undervoltage.
Fault information is retained in the fault register and is available (and reset) via the SO pin during the first valid SPI communication (refer
to Table 17).
PROTECTION AND DIAGNOSIS FEATURES
OVERTEMPERATURE FAULT (NON-LATCHING)
The 34984 incorporates overtemperature detection and shutdown circuitry in each output structure. Overtemperature detection is enabled
when an output is in the ON state.
For the output, an overtemperature fault (OTF) condition results in the faulted output turning OFF until the temperature falls below the
TSD(HYS). This cycle will continue indefinitely until action is taken by the MCU to shut OFF the output, or until the offending load is removed.
When experiencing this fault, the OTF fault bit will be set in the status register and cleared after either a valid SPI read or a power reset
of the device.
OVERVOLTAGE FAULT (NON-LATCHING)
The 34984 shuts down the output during an overvoltage fault (OVF) condition on the VPWR pin. The output remains in the OFF state until
the overvoltage condition is removed. When experiencing this fault, the OVF fault bit is set in the bit OD1 and cleared after either a valid
SPI read or a power reset of the device.
The overvoltage protection and diagnostic can be disabled trough the SPI (bit OV_dis).
UNDERVOLTAGE SHUTDOWN (LATCHING OR NON-LATCHING)
The output(s) will latch off at some supply voltage below 6.0 V. As long as the VDD level stays within the normal specified range, the internal
logic states within the device will be sustained.
In the case where supply voltage drops below the undervoltage threshold (VPWRUV) output will turn off, FS will go to Logic [0], and the
fault register UVF bit will be set to 1.
Two cases need to be considered when the supply level recovers:
• If output(s) command is (are) low, FS will go to Logic [1] but the UVF bit will remain set to 1 until the next read operation.
• If the output command is ON, then FS will remain at Logic [0]. The output must be turned OFF and ON again to re-enable the state
of output and release FS. The UVF bit will remain set to 1 until the next read operation.
The undervoltage protection can be disabled through the SPI (bit UV_dis = 1). In this case, the FS and UVF bits do not report any
undervoltage fault condition and the output state will not be changed as long as supply voltage does not drop any lower than 2.5 V.
OPEN LOAD FAULT (NON-LATCHING)
The 34984 incorporates open load detection circuitry on each output. Output open load fault (OLF) is detected and reported as a fault
condition when that output is disabled (OFF). The open load fault is detected and latched into the status register after the internal gate
voltage is pulled low enough to turn OFF the output. The OLF fault bit is set in the status register. If the open load fault is removed, the
status register will be cleared after reading the register.
The open load protection can be disabled trough SPI (bit OL_dis). It is recommended to disable the open load detection circuitry (OL_dis
bit sets to logic [1]) in case of permanent open load fault condition.
34984
Analog Integrated Circuit Device Data
20
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSIS FEATURES
OVERCURRENT FAULT (LATCHING)
The device has eight programmable overcurrent low detection levels (IOCL) and two programmable overcurrent high detection levels
(IOCH) for maximum device protection. The two selectable, simultaneously active overcurrent detection levels, defined by IOCH and IOCL
are illustrated in Figure 6. The eight different overcurrent low detect levels (IOCL0:IOCL7) are likewise illustrated in Figure 6.
,
If the load current level ever reaches the selected overcurrent low detect level and the overcurrent condition exceeds the programmed
overcurrent time period (tOCx), the device will latch the effected output OFF.
If at any time the current reaches the selected IOCH level, then the device will immediately latch the fault and turn OFF the output,
regardless of the selected tOCL driver. For both cases, the device output will stay off indefinitely until the device is commanded OFF and
then ON again.
REVERSE VOLTAGE
The output survives the application of reverse voltage as low as -16 V. Under these conditions, the output’s gates are enhanced to keep
the junction temperature less than 150 °C. The ON resistance of the output is fairly similar to that in the Normal mode. No additional
passive components are required. If one or more of the outputs is driving a DC motor with an external freewheeling diode in parallel to the
load, a direct current passes through this diode and the internal high-side switch, in cases of reverse voltage.
As Figure 9 shows, it is essential to protect this power line. The proposed solution is an external N-channel low-side with its gate tied to
supply voltage through a resistor.
34984
Figure 9. Reverse Voltage Protection
GROUND DISCONNECT PROTECTION
In the event the 34984 ground is disconnected from load ground, the device protects itself and safely turns OFF the output regardless the
state of the output at the time of disconnection. A 10 k resistor needs to be added between the wake pin and the rest of the circuitry in
order to ensure that the device turns off in case of ground disconnect, and to prevent this pin from exceeding its maximum ratings
Table 8. Device Behavior in Case of Undervoltage
High-side
Switch
(VPWR
UV Disable
IN = 0
(Falling or
Rising VPWR)
UV Disable
IN = 1
(Falling or
UV Enable
IN = 0
UV Enable
IN = 0
UV Enable
IN = 1
UV Enable
IN = 1
State
(Falling VPWR) (Rising VPWR) (Falling VPWR) (Rising VPWR)
Voltage)
Rising VPWR)
Output State
FS State
OFF
1
OFF
1
ON
1
OFF
0
OFF
1
ON
1
VPWR >
VPWRUV
SPI Fault
0
1 until next read
0
1
0
0
Register UVF Bit
Output State
FS State
OFF
0
OFF
0
OFF
0
OFF
0
OFF
1
ON
1
VPWRUV >
VPWR >
UVPOR
SPI Fault
Register UVF Bit
1
1
1
1
0
0
34984
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
NAL DEVICE OPERATION
MMANDS AND REGISTERS
Table 8. Device Behavior in Case of Undervoltage
High-side
UV Enable
Switch
UV Disable
IN = 0
(Falling or
Rising VPWR)
UV Disable
IN = 1
(Falling or
UV Enable
IN = 0
UV Enable
IN = 1
UV Enable
IN = 1
State
IN = 0
(VPWR
(Falling VPWR) (Rising VPWR) (Falling VPWR) (Rising VPWR)
Voltage)
Rising VPWR)
Output State
FS State
OFF
1
OFF
1
OFF
1
OFF
1
OFF
1
ON
1
UVPOR >
VPWR > 2.5 V
SPI Fault
1 until next read
1
1 until next read 1 until next read
0
0
Register UVF Bit
Output State
OFF
1
OFF
1
OFF
1
OFF
1
OFF
1
OFF
1
2.5 V > VPWR > FS State
0 V
SPI Fault
1 until next read 1 until next read 1 until next read 1 until next read
0
0
Register UVF Bit
UV fault is
not latched
UV fault is
not latched
UV fault
is latched
Comments
Typical value; not guaranteed
While VDD remains within specified range.
= IN is equivalent to IN direct input or IN_spi SPI input.
LOGIC COMMANDS AND REGISTERS
SPI PROTOCOL DESCRIPTION
The SPI interface has a full duplex, three-wire synchronous data transfer with four I/O lines associated with it: Serial Clock (SCLK), Serial
Input (SI), Serial Output (SO), and Chip Select (CS).
The SI/SO pins of the 34984 follow a first-in first-out (D7/D0) protocol with both input and output words transferring the most significant
bit (MSB) first. All inputs are compatible with 5.0 V CMOS logic levels.
The SPI lines perform the following functions:
SERIAL CLOCK (SCLK)
Serial clocks (SCLK) the internal shift registers of the 34984 device. The serial input (SI) pin accepts data into the input shift register on
the falling edge of the SCLK signal while the serial output (SO) pin shifts data information out of the SO line driver on the rising edge of
the SCLK signal. It is important that the SCLK pin be in a logic low state whenever CS makes any transition. For this reason, it is
recommended that the SCLK pin be in a Logic [0] state whenever the device is not accessed (CS Logic [1] state). SCLK has an active
internal pull-down, IDWN. When CS is Logic [1], signals at the SCLK and SI pins are ignored and SO is tri-stated (high-impedance). See
Figure 10 and Figure 11.
SERIAL INPUT (SI)
This is a serial interface (SI) command data input pin. SI instruction is read on the falling edge of SCLK. An 8-bit stream of serial data is
required on the SI pin, starting with D7 to D0. The internal registers of the 34984 are configured and controlled using a 4-bit addressing
scheme, as shown in Table 9. Register addressing and configuration are described in Table 10. The SI input has an active internal pull-
down, IDWN
.
SERIAL OUTPUT (SO)
The SO data pin is a tri-stateable output from the shift register. The SO pin remains in a high-impedance state until the CS pin is put into
a Logic [0] state. The SO data is capable of reporting the status of the output, the device configuration, and the state of the key inputs. The
SO pin changes states on the rising edge of SCLK and reads out on the falling edge of SCLK. Fault and Input Status descriptions are
provided in Table 6.
CHIP SELECT (CS)
The CS pin enables communication with the master microcontroller (MCU). When this pin is in a Logic [0] state, the device is capable of
transferring information to, and receiving information from, the MCU. The 34984 device latches in data from the Input shift registers to the
addressed registers on the rising edge of CS. The device transfers status information from the power output to the shift register on the
falling edge of CS. The SO output driver is enabled when CS is Logic [0]. CS should transition from a Logic [1] to a Logic [0] state only
when SCLK is a Logic [0]. CS has an active internal pull-up, IUP
.
34984
Analog Integrated Circuit Device Data
22
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
CS
SCLK
SI
D7
D6
D5
D4
D3
D2
D1
D0
SO
OD7
OD6
OD5
OD4
OD3
OD2
OD1 OD0
Notes 1. RST is a Logic [1] state during the above operation.
2. D7:D0 relate to the most recent ordered entry of data into the device.
3. OD7:OD0 relate to the first 8 bits of ordered fault and status data out of the device.
Figure 10. Single 8-Bit Word SPI Communication
CS
SCLK
SI
D
7
D
6
D
5
D
2
D
1
D
0
D
7
*
D
6
*
D
5
*
D
2
*
D
1
*
D
0
*
SO
O
D
7
O
D
6
O
D
5
O
D
2
O
D
1
O
D
0
D
7
D
6
D
5
D
2
D
1
D
0
Notes
1. RST is a Logic [1] state during the above operation.
2. D7:D0relate to the most recentorderedentry of data into the device.
3. D7*:D0* relateto the previous8 bits (lastcommandword)of data thatwas previously shifted into the device.
4. OD7:OD0 relate to thefirst8bits ofordered fault and statusdata out ofthedevice.
Figure 11. Multiple 8-Bit Word SPI Communication
SERIAL INPUT COMMUNICATION
SPI communication is accomplished using 8-bit messages. A message is transmitted by the MCU starting with the MSB, D7, and ending
with the LSB, D0 (Table 9). Each incoming command message on the SI pin can be interpreted using the following bit assignments: the
MSB (D7) is the watchdog bit and in some cases a register address bit common to both outputs or specific to an output; the next three
bits, D6:D4, are used to select the command register; and the remaining four bits, D3:D0, are used to configure and control the outputs
and their protection features.
Multiple messages can be transmitted in succession to accommodate those applications where daisy chaining is desirable, or to confirm
transmitted data, as long as the messages are all multiples of eight bits. Any attempt made to latch in a message that is not eight bits will
be ignored.
The 34984 has defined registers, which are used to configure the device and to control the state of the output. Table 10, summarizes the
SI registers. The registers are addressed via D6:D4 of the incoming SPI word (Table 9).
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NAL DEVICE OPERATION
MMANDS AND REGISTERS
Table 9. SI Message Bit Assignment
Bit Sig
SI Msg Bit
D7
Message Bit Description
Register address bit for output selection. Also used for watchdog:
toggled to satisfy watchdog requirements.
MSB
D6:D4
D3:D1
Register address bits.
Used to configure the inputs, outputs, and the device protection
features and SO status content.
Used to configure the inputs, outputs, and the device protection
features and SO status content.
LSB
D0
Table 10. Serial Input Address and Configuration Bit Map
Serial Input Data
SI Register
D7 D6 D5 D4
D3
D2
D1
D0
SOA0
IN0_SPI
SOCL0s
OCLT0s
A/Os
STATR
OCR
s
x
s
s
s
0
1
0
1
x
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
0
1
1
1
0
1
0
1
0
1
1
0
0
1
0
SOA2
SOA1
CSNS1 EN
SOCHs
OL_DIS s
IN1_SPI
SOCL2s
CD_DIS s
CSNS0 EN
SOCL1s
OCLT1s
SOCHLR
CDTOLR
DICR
FAST SR s CSNS high s IN DIS s
OSDR
WDR
0
0
0
0
OSD2
OSD1
WD1
0
OSD0
WD0
0
0
0
NAR
0
UOVR
TEST
UV_dis
OV_dis
Freescale Internal Use (Test)
x = Don’t care.
s (SOA3 bit) = Selection of output: Logic [0] = HS0, Logic [1] = HS1.
DEVICE REGISTER ADDRESSING
The following section describes the possible register addresses and their impact on device operation.
Address x000—Status Register (STATR)
The STATR register is used to read the device status and the various configuration register contents without disrupting the device
operation or the register contents. The register bits D2:D0, determine the content of the first eight bits of SO data. When register content
is specific to one of the two outputs, bit D7 is used to select the desired output (SOA3). In addition to the device status, this feature provides
the ability to read the content of the OCR, SOCHLR, CDTOLR, DICR, OSDR, WDR, NAR, and UOVR registers. (Refer to the section
entitled Serial Output Communication (Device Status Return Data).)
Address x001—Output Control Register (OCR)
The OCR register allows the MCU to control the outputs through the SPI. Incoming message bit D0 reflects the desired states of the high-
side output HS0 (IN0_SPI): a Logic [1] enables the output switch and a Logic [0] turns it OFF. A Logic [1] on message bit D1 enables the
Current Sense (CSNS) pin. Similarly, incoming message bit D2 reflects the desired states of the high-side output HS1 (IN1_SPI): Logic [1]
enables the output switch and a Logic [0] turns it OFF. A Logic [1] on message bit D3 enables the CSNS pin. In the event that the current
sense is enabled for both outputs, the current will be summed. Bit D7 is used to feed the watchdog if enabled.
Address x010— Select Overcurrent High and Low Register (SOCHLR)
The SOCHLR register allows the MCU to configure the output overcurrent low and high detection levels, respectively. Each output is
independently selected for configuration based on the state of the D7 bit; a write to this register when D7 is Logic [0] will configure the
current detection levels for the HS0. Similarly, if D7 is Logic [1] when this register is written, HS1 is configured. Each output can be
configured to different levels. In addition to protecting the device, this slow blow fuse emulation feature can be used to optimize the load
requirements matching system characteristics. Bits D2:D0 set the overcurrent low detection level to one of eight possible levels, as shown
in Table 11. Bit D3 sets the overcurrent high detection level to one of two levels, which is described inTable 12.
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Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 11. Overcurrent Low Detection Levels
SOCL2 (D2) SOCL1 (D1) SOCL0 (D0) Overcurrent Low Detection (Amperes)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
25
22.5
20
17.5
15
12.5
10
7.5
Table 12. Overcurrent High Detection Levels
SOCH (D3)
Overcurrent High Detection (Amperes)
0
1
100
75
Address x011—Current Detection Time and Open Load Register (CDTOLR)
The CDTOLR register is used by the MCU to determine the amount of time the device will allow an overcurrent low condition before output
latches OFF occurs. Each output is independently selected for configuration based on the state of the D7 bit. A write to this register when
bit 7 is Logic [0] will configure the timeout for the HS0. Similarly, if D7 is Logic [1] when this register is written, then HS1 is configured. Bits
D1:D0 allow the MCU to select one of four fault blanking times defined in Table 13. Note that these timeouts apply only to the overcurrent
low detection levels. If the selected overcurrent high level is reached, the device will latch off within 20 s.
Table 13. Overcurrent Low Detection Blanking Time
OCLT[1:0]
Timing
155 ms
10 ms
00
01
10
11
1.2 ms
150 s
A Logic [1] on bit D2 disables the overcurrent low (CD_dis) detection timeout feature. A Logic [1] on bit D3 disables the open load (OL)
detection feature.
Address x100—Direct Input Control Register (DICR)
The DICR register is used by the MCU to enable, disable, or configure the direct IN pin control of each output. Each output is independently
selected for configuration based on the state of bit D7. A write to this register when bit D7 is Logic [0] will configure the direct input control
for the HS0. Similarly, if D7 is Logic [1] when this register is written, then HS1 is configured.
A Logic [0] on bit D1 will enable the output for direct control by the IN pin. A Logic [1] on bit D1 will disable the output from direct control.
While addressing this register, if the input was enabled for direct control, a Logic [1] for the D0 bit will result in a Boolean AND of the IN
pin with its corresponding D0 message bit when addressing the OCR register. Similarly, a Logic [0] on the D0 pin results in a Boolean OR
of the IN pin with the corresponding message bits when addressing the OCR register.
The DICR register is useful if there is a need to independently turn on and off several loads that are PWM’d at the same frequency and
duty cycle with only one PWM signal. This type of operation can be accomplished by connecting the pertinent direct IN pins of several
devices to a PWM output port from the MCU and configuring each of the outputs to be controlled via their respective direct IN pin. The
DICR is then used to Boolean AND the direct IN(s) of each of the outputs with the dedicated SPI bit that also controls the output. Each
configured SPI bit can now be used to enable and disable the common PWM signal from controlling its assigned output.
A Logic [1] on bit D2 is used to select the high ratio (CSR1, 1/41000) on the CSNS pin for the selected output. The default value [0] is used
to select the low ratio (CSR0, 1/20500). A Logic [1] on bit D3 is used to select the high speed slew rate for the selected output. The default
value [0] corresponds to the low speed slew rate.
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NAL DEVICE OPERATION
MMANDS AND REGISTERS
Address 0101—Output Switching Delay Register (OSDR)
The OSDR register configures the device with a programmable time delay that is active during Output ON transitions initiated via the SPI
(not via direct input).
A write to this register configures both outputs for different delay. Whenever the input is commanded to transition from Logic [0] to Logic [1],
both outputs will be held OFF for the time delay configured in the OSDR. The programming of the contents of this register have no effect
on device Fail-safe mode operation. The default value of the OSDR register is 000, equating to no delay. This feature allows the user a
way to minimize inrush currents, or surges, thereby allowing loads to be switched ON with a single command. There are eight selectable
output switching delay times that range from 0 ms to 525 ms. Refer to Table 14.
Table 14. Switching Delay
OSD[2:0] (D2:D0)
Turn ON Delay (ms) HS0
Turn ON Delay (ms) HS1
000
001
010
011
100
101
110
111
0
0
0
75
150
150
300
300
450
450
150
225
300
375
450
525
Address 1101—Watchdog Register (WDR)
The WDR register is used by the MCU to configure the watchdog timeout. Watchdog timeout is configured using bits D1:D0. When D1:D0
bits are programmed for the desired watchdog timeout period, the WD bit (D7) should be toggled as well, ensuring the new timeout period
is programmed at the beginning of a new count sequence. Refer to Table 15.
Table 15. Watchdog Timeout
WD[1:0] (D1:D0)
Timing (ms)
620
00
01
10
11
310
2500
1250
Address 0110—No Action Register (NAR)
The NAR register can be used to no-operation fill SPI data packets in a daisy chain SPI configuration. This allows devices to not be affected
by commands being clocked over a daisy-chained SPI configuration, and by toggling the WD bit (D7), the watchdog circuitry will continue
to be reset while no programming or data readback functions are being requested from the device.
Address 1110—Undervoltage/Overvoltage Register (UOVR)
The UOVR register can be used to disable or enable overvoltage and/or undervoltage protection. By default (Logic [0]), both protections
are active. When disabled, an undervoltage or overvoltage condition fault will not be reported in the output fault register.
Address x111—TEST
The TEST register is reserved for test and is not accessible with SPI during normal operation.
SERIAL OUTPUT COMMUNICATION (DEVICE STATUS RETURN DATA)
When the CS pin is pulled low, the output status register is loaded. Meanwhile, the data is clocked out MSB- (OD7-) first as the new
message data is clocked into the SI pin. The first eight bits of data clocking out of the SO, and following a CS transition, are dependant
upon the previously written SPI word.
Any bits clocked out of the SO pin after the first eight will be representative of the initial message bits clocked into the SI pin since the CS
pin first transitioned to a Logic [0]. This feature is useful for daisy chaining devices as well as message verification.
A valid message length is determined following a CS transition of Logic [0] to Logic [1]. If there is a valid message length, the data is latched
into the appropriate registers. A valid message length is a multiple of eight bits. At this time, the SO pin is tri-stated and the fault status
register is now able to accept new fault status information.
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FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
The output status register correctly reflects the status of the STATR-selected register data at the time that the CS is pulled to a Logic [0]
during SPI communication and/or for the period of time since the last valid SPI communication, with the following exceptions:
• The previous SPI communication was determined to be invalid. In this case, the status will be reported as though the invalid SPI
communication never occurred.
• Supply transients below 6.0 V resulting in an undervoltage shutdown of the outputs may result in incorrect data loaded into the status
register. The SO data transmitted to the MCU during the first SPI communication following an undervoltage VPWR condition should
be ignored.
• The RST pin transition from a Logic [0] to Logic [1] while the WAKE pin is at Logic [0] may result in incorrect data loaded into the
status register. The SO data transmitted to the MCU during the first SPI communication following this condition should be ignored.
SERIAL OUTPUT BIT ASSIGNMENT
The 8 bits of serial output data depend on the previous serial input message, as explained in the following paragraphs. Table 16
summarizes the SO register content.
Bit OD7 reflects the state of the watchdog bit (D7) addressed during the prior communication. The value of the previous D7 will determine
which output the status information applies to for the Fault (FLTR), SOCHLR, CDTOLR, and DICR registers. SO data will represent
information ranging from fault status to register contents, user selected by writing to the STATR bits D2:D0. Note that the SO data will
continue to reflect the information for each output (depending on the previous D7 state) that was selected during the most recent STATR
write until changed with an updated STATR write.
Previous Address SOA[2:0]=000
If the previous three MSBs are 000, bits OD6:OD0 will reflect the current state of the Fault register (FLTR) corresponding to the output
previously selected with the bit OD7 (Table 17).
Previous Address SOA[2:0]=001
Data in bits OD1:OD0 contain CSNS0 EN and IN0_SPI programmed bits, respectively. Data in bits OD3:OD2 contain CSNS0 EN and
IN0_SPI programmed bits, respectively.
Previous Address SOA[2:0]=010
The data in bit OD3 contain the programmed overcurrent high detection level (refer to Table 12), and the data in bits OD2:OD0 contain
the programmed overcurrent low detection levels (refer to Table 13).
Table 16. Serial Output Bit Map Description
Previous STATR
Serial Output Returned Data
D7, D2, D1, D0
SOA3 SOA2 SOA1 SOA0
OD7
OD6
OD5
OD4
OD3
OLFs
OD2
UVF
OD1
OVF
OD0
FAULT
IN0_SPI
SOCL0s
OCLT0s
A/Os
s
x
s
s
s
0
1
0
1
x
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
0
1
1
1
0
1
0
1
0
1
1
0
0
1
s
x
s
s
s
0
1
0
1
–
OTFs
OCHFs
OCLFs
0
0
0
1
1
1
1
1
–
0
1
1
0
0
0
1
1
–
1
0
1
0
1
1
0
0
–
CSNS1 EN
SOCHs
OL_DIS s
IN1_SPI
SOCL2s
CD_DIS s
CSNS0 EN
SOCL1s
OCLT1s
IN DIS s
OSD1
FAST SR s CSNS high s
FSM_HS0
FSM_HS1
IN1 Pin
OSD2
WDTO
IN0 Pin
–
OSD0
WD1
WD0
FSI Pin
UV_dis
–
WAKE Pin
OV_dis
–
–
See Table 2
–
s = Selection of output: Logic [0] = HS0, Logic [1] = HS1.
x = Don’t care.
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NAL DEVICE OPERATION
MMANDS AND REGISTERS
Table 17. Fault Register
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
s
OTF
OCHFs
OCLFs
OLFs
UVF
OVF
FAULT
OD7 (s) = Selection of output: Logic [0] = HS0, Logic [1] = HS1.
OD6 (OTF) = Overtemperature Flag.
OD5 (OCHFs) = Overcurrent High Flag. (This fault is latched.)
OD4 (OCLFs) = Overcurrent Low Flag. (This fault is latched.)
OD3 (OLFs) = Open load Flag.
OD2 (UVF) = Undervoltage Flag. (This fault is latched or not latched.)
OD1 (OVF) = Overvoltage Flag.
OD0 (FAULT) = This flag reports a fault and is reset by a read operation.
FAULT report of any fault on HS0 or HS1
Note The FS pin reports a fault. For latched faults, this pin is reset by a new Switch ON
command (via SPI or direct input IN).
Previous Address SOA[2:0]=011
Data returned in bits OD1 and OD0 are current values for the overcurrent fault blanking time, illustrated in Table 13. Bit OD2 reports if the
overcurrent detection timeout feature is active. OD3 reports if the open load circuitry is active.
Previous Address SOA[2:0]=100
The returned data contain the programmed values in the DICR.
Previous Address SOA[2:0]=101
• SOA3 = 0. The returned data contain the programmed values in the OSDR. Bit OD3 (FSM_HS0) reflects the state of the output HS0
in the Fail-safe mode after a watchdog timeout occurs.
• SOA3 = 1. The returned data contain the programmed values in the WDR. Bit OD2 (WDTO) reflects the status of the watchdog
circuitry. If WDTO bit is Logic [1], the watchdog has timed out and the device is in Fail-safe mode. If WDTO is Logic [0], the device
is in Normal mode (assuming the device is powered and not in Sleep mode), with the watchdog either enabled or disabled. Bit OD3
(FSM_HS1) reflects the state of the output HS1 in the Fail-safe mode after a watchdog timeout occurs.
Previous Address SOA[2:0] =110
• SOA3 = 0. OD3:OD0 return the state of the IN1, IN0, FSI, and WAKE pins, respectively (Table 18).
Table 18. Pin Register
OD3
OD2
OD1
OD0
IN1 Pin
IN0 Pin
FSI Pin
WAKE Pin
• SOA3 = 1. The returned data contain the programmed values in the UOVR. Bit OD1 reflects the state of the undervoltage protection
and bit OD0 reflects the state of the overvoltage protection. Refer to Table 16).
Previous Address SOA[2:0]=111
Null Data. No previous register Read Back command received, so bits OD2:OD0 are null, or 000.
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TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
VPWR
VDD
Voltage
Regulator
VDD
VDD NC VPWR
VDD
VPWR
2.2 k
10 k
10
MCU
14
VDD
VPWR
HS1
100 nF
10 µF
2.5 µF
10 nF
2
4
WAKE
IN0
10 k
15
16
I/O
I/O
10 k
12
8
IN1
10 k
10 k
34984
SCLK
CS
SCLK
CS
7
10 k
3
I/O
RST
SO
SI
HS0
11
9
SI
SO
I/O
10 k
5
FS
LOAD
LOAD
1
13
CSNS
FSI
A/D
GND
6
1 k
RFSI
Figure 12. Typical Applications
The loads must be chosen in order to guarantee the device normal operating conditions for junction temperatures from -40 °C to 150 °C.
In case of permanent short-circuit conditions, the duration and number of activation cycles must be limited with a dedicated MCU fault
management, using the fault reporting through the SPI. When driving DC motor or solenoid loads demanding multiple switching, an
external recirculation device must be used to maintain the device in its safe operating area. In this case, an additional protection will be
necessary to sustain reverse supply (Figure 9).
Two application notes are available:
• AN3274, which proposes safe configurations of the eXtreme switch devices in case of application faults, and to protect all circuitry with
minimum external components.
• AN2469, which provides guidelines for printed circuit board (PCB) design and assembly.
Development effort will be required by the end users to optimize the board design and PCB layout, in order to reach electromagnetic
compatibility standards (emission and immunity).
OUTPUT CURRENT MONITORING
This section relates to the output current monitoring for 34984, dual 4.0 m high-side switch. This device is a self-protected silicon switch
used to replace electromechanical relays, fuses, and discrete circuits in power management applications. The MC34984 features a
current recopy which is proportional to the load current. It can be configured between 2 ratios via the SPI (CSR0 and CSR1).
This section presents the current recopy tolerance of the device and the improvement of this feature with the calibration practice.
CURRENT RECOPY TOLERANCE
The current sense ratio accuracies described in Current Sense Ratio (CSR0) Accuracy (CSR0_ACC and CSR1_ACC) take into account:
• part to part deviation due to manufacturing,
• ambient temperature derating (from -40 °C to 125 °C),
• battery voltage range (from 9 V to 16 V).
With statistical data analysis performed on 3 production lots (initial testing only), the effect of each contributor has been demonstrated.
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APPLICATIONS
CURRENT MONITORING
Figure 13 shows the CSR0 tolerance in function to 3 previous listed contributors in comparison to the minimum and maximum specified
values.
Current Recopy at Vbat=9V/16V from -40°C to
125°C
24000
Spec_max
23000
Max(Data_9V) at 6 sigmas
22000
Max(Data_16V) at 6 sigmas
10%
21000
Average (Data)
20000
Min(Data_16V) at 6 sigmas
Min(Data_9V) at 6 sigmas
19000
18000
Spec_min
17000
16000
10
15
20
25
Output current (A)
Figure 13. CSR0 Ratio Deviation in Function All Contributors
Lower VPWR Voltage causes more error. 9.0 V corresponding to the worst case. Figure 14 shows the CSR0 tolerance without battery
variation effect.
Current Recopy at Vbat=9V from -40°C to 125°C
24000
23000
22000
21000
20000
19000
18000
17000
16000
10
15
20
25
Output current (A)
Figure 14. CSR0 Ratio Deviation in Function Manufacturing and Temperature
The main contributor is the manufacturing deviation, as described in Figure 15. At 15 A of output current, the tolerance will be about 8.5%
versus 10% when all contributors are considered.
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TYPICAL APPLICATIONS
OUTPUT CURRENT MONITORING
Current Recopy at Vbat=9V at 25°C
24000
23000
22000
21000
20000
19000
18000
17000
16000
Spec_max
Max(Data) at 6 sigmas
8.5%
Average (Data)
Min(Data) at 6 sigmas
Spec_min
10
15
20
25
Output current (A)
Figure 15. CSR0 Ratio Deviation in Function Manufacturing
PART CALIBRATION
With a calibration strategy, the part to part contribution can be removed.
An experiment was done on low output current values (below 5.0 A). The relative CSR0 deviation based on only one calibration point per
output (5.0 A, VPWR = 16 V at 25 °C) has been performed on three production lots. Those parts have tested at initial and after high
temperature operating life, to take into account the ageing of devices.
Table 19 summaries test results covering 99.74% of parts.
Table 19. CSR0 Precision for Several Output Current Values with One Calibration Point at 5.0 A
CSR0 ratio
0.5 A
Min
Max
25%
12%
8.0%
5.0%
-25%
-12%
-8.0%
-5.0%
1.0 A
2.5 A
5.0 A
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NG
NG INFORMATION
PACKAGING
SOLDERING INFORMATION
SOLDERING INFORMATION
The 34984 is packaged in a surface mount power package (PQFN), intended to be soldered directly on the printed circuit board.
The AN2467 provides guidelines for Printed Circuit Board design and assembly.
PACKAGE DIMENSIONS
For the most current revision of the package, visit www.freescale.com and perform a keyword search on 98ARL10521D. Dimensions
shown are provided for reference ONLY.
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PACKAGING
PACKAGE DIMENSIONS
34984
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33
NG
DIMENSIONS
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REVISION HISTORY
REVISION HISTORY
REVISION
DATE
DESCRIPTION OF CHANGES
• Initial release
1.0
9/2014
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35
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© 2014 Freescale Semiconductor, Inc.
Document Number: MC34984
Rev. 1.0
9/2014
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