MC10XS3412 [NXP]
Quad high-side switch (dual 10 mOhm, dual 12 mOhm);
| 型号： | MC10XS3412 |
| 厂家： | 
NXP |
| 描述： | Quad high-side switch (dual 10 mOhm, dual 12 mOhm) |
| 文件： | 总60页 (文件大小：2026K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MC10XS3412
Rev. 13.0, 8/2018
NXP Semiconductors
Technical Data
Quad high-side switch
(dual 10 mOhm, dual 12 mOhm)
10XS3412
The 10XS3412 is one in a family of devices designed for low-voltage automotive
lighting applications. Its four low RDS(on) MOSFETs (dual 10 mOhm/dual
12 mOhm) can control four separate 55/28 W bulbs, and/or Xenon modules,
and/or LEDs.
HIGH-SIDE SWITCH
Programming, control and diagnostics are accomplished using a 16-bit SPI
interface. Its output with selectable slew rate improves electromagnetic
compatibility (EMC) behavior. Additionally, each output has its own parallel input
or SPI control for pulse-width modulation (PWM) control. The 10XS3412 allows
the user to program via the SPI the fault current trip levels and duration of
acceptable lamp inrush. The device has Fail-safe mode to provide functionality
of the outputs in case of MCU damage.
Features
• Four protected 10 mΩ and 12 mΩ high-side switches (at 25 °C)
FK SUFFIX (PB-FREE)
FK SUFFIX (PB-FREE)
98ASA00426D
• Operating voltage range of 6.0 to 20 V with sleep current < 5.0 μA,
98ARL10596D
24-PIN PQFN
extended mode from 4.0 to 28 V
24-PIN PQFN
• 8.0 MHz 16-bit 3.3 V and 5.0 V SPI control and status reporting with daisy
chain capability
• PWM module using external clock or calibratable internal oscillator with
programmable outputs delay management
• Smart overcurrent shutdown, severe short-circuit, overtemperature
protection with time limited autoretry, and Fail-safe mode in case of MCU
damage
• Output OFF or ON openload detection compliant to bulbs or LEDs and
short to battery detection
• Analog current feedback with selectable ratio and board temperature
feedback
V
VDD
VPWR VDD
VPWR
DD
10XS3412
VDD
VPWR
HS0
WAKE
FS
LOAD
LOAD
LOAD
LOAD
I/O
SCLK
CS
SCLK
CS
SO
RST
SI
IN0
IN1
IN2
IN3
CSNS
FSI
HS1
HS2
HS3
SI
I/O
SO
I/O
I/O
I/O
MCU
I/O
A/D
GND
GND
Figure 1. 10XS3412 simplified application diagram
© NXP B.V. 2018.
Table of Contents
1
2
3
4
5
Orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Device variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5.2 Static electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.3 Dynamic electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.4 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.2 Functional pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.3 Functional internal block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Functional device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.1 SPI protocol description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.2 Operational modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.3 Protection and diagnostic features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.4 Logic commands and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.1 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.2 Package mechanical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6
7
8
9
10 Additional documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
10.1Thermal addendum (Rev 2.0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10XS3412
2
NXP Semiconductors
1
Orderable parts
Table 1. Orderable part variations
Part number (1)
Temperature (TA)
Package
MC10XS3412CHFK
MC10XS3412JHFK
-40 to 125 °C
24-pin PQFN
Notes
1. To order parts in tape and reel, add the R2 suffix to the part number.
2
Device variations
Table 2. Device variations
Characteristic
Wake input clamp voltage, I < 2.5 mA
Symbol
Min
Typ
Max
Unit
CL(WAKE)
• 10XS3412CHFK
• 10XS3412JHFK
V
19
20
25
27
32
35
V
CL(WAKE)
Fault detection blanking time
• 10XS3412CHFK
tFAULT
-
-
5.0
5.0
20
10
μs
μs
°C
• 10XS3412JHFK
Output shutdown delay time
• 10XS3412CHFK
tDETECT
-
-
7.0
7.0
30
20
• 10XS3412JHFK
Peak Package Reflow Temperature During Reflow, (2) (3)
• 10XS3412CHFK
,
Note 3
TPPRT
• 10XS3412JHFK
Notes
2. Pin soldering temperature limit is for 40 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause
malfunction or permanent damage to the device.
3. NXP’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and
Moisture Sensitivity Levels (MSL), go to www.nxp.com, search by part number (remove prefixes/suffixes) and enter the core ID to view all
orderable parts, and review parametrics.
10XS3412
NXP Semiconductors
3
3
Internal block diagram
VDD
VPWR
VPWR
Voltage Clamp
Internal
Regulator
Over/Undervoltage
Protections
VDD Failure
Detection
Charge
Pump
POR
I
UP
VREG
CS
SCLK
Selectable Slew Rate
Gate Driver
I
DWN
Selectable Overcurrent
Detection
HS0
SO
SI
RST
WAKE
FS
Severe Short-circuit
Detection
Logic
Short to VPWR
Detection
IN0
Overtemperature
Detection
IN1
IN2
IN3
Open-load
Detections
HS0
R
R
I
DWN
DWN
DWN
HS1
HS1
HS2
HS3
PWM
Module
Calibratable
Oscillator
HS2
HS3
VREG
Programmable
Watchdog
FSI
Temperature
Feedback
Selectable Output
Current Recopy
Overtemperature
Prewarning
Analog MUX
VDD
GND
CSNS
Figure 2. 10XS3412 simplified internal block diagram
10XS3412
4
NXP Semiconductors
4
Pin connections
Transparent Top View of Package
13 12 11 10
9
8
7
6
5
4
3
2
1
SO
16
17
24
FSI
GND
23
GND
14
GND
HS3
18
22
HS2
15
VPWR
19
20
21
HS0
HS1
NC
Figure 3. 10XS3412 pin connections
Table 3. 10XS3412 pin definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 24.
Pin
number
Pin name Pin function
Formal name
Definition
This pin reports an analog value proportional to the designated HS[0:3] output
current or the temperature of the GND flag (pin 14). It is used externally to generate
a ground-referenced voltage for the microcontroller (MCU) . Current recopy and
temperature feedback is SPI programmable.
Output current
monitoring
1
CSNS
Output
Input
Each direct input controls the device mode. The IN[0:3] high-side input pins are used
to directly control HS0:HS3 high-side output pins.
The PWM frequency can be generated from IN0 pin to PWM module in case of
external clock is set.
2
3
5
6
IN0
IN1
IN2
IN3
Direct inputs
Fault status
(active low)
This pin is an open drain configured output requiring an external pull-up resistor to
7
8
9
FS
Output
Input
V
DD for fault reporting.
WAKE
RST
Wake
Reset
This input pin controls the device mode.
This input pin is used to initialize the device configuration and fault registers, as well
as place the device in a low-current Sleep mode.
Input
Chip select
(active low)
10
11
CS
SCLK
SI
Input
Input
This input pin is connected to a chip select output of a master microcontroller (MCU).
This input pin is connected to the MCU providing the required bit shift clock for SPI
communication.
Serial clock
Serial input
This pin is a command data input pin connected to the SPI serial data output of the
MCU or to the SO pin of the previous device of a daisy-chain of devices.
12
Input
This pin is an external voltage input pin used to supply power interfaces to the SPI
bus.
13
VDD
GND
Power
Ground
Digital drain voltage
Ground
These pins, internally shorted, are the ground for the logic and analog circuitry of the
device. These ground pins must be also shorted in the board.
14, 17, 23
10XS3412
NXP Semiconductors
5
Table 3. 10XS3412 pin definitions (continued)
A functional description of each pin can be found in the Functional Pin Description section beginning on page 24.
Pin
number
Pin name Pin function
Formal name
Definition
This pin connects to the positive power supply and is the source of operational power
for the device.
15
VPWR
SO
Power
Output
Positive power supply
Serial output
This output pin is connected to the SPI serial data input pin of the MCU or to the SI
pin of the next device of a daisy-chain of devices.
16
18
19
21
22
HS3
HS1
HS0
HS2
Protected 10 mΩ (HS0 and HS1) 12 mΩ (HS2 and HS3) high-side power output pins
to the load.
Output
High-side outputs
4, 20
24
NC
FSI
N/A
No connect
These pins may not be connected.
Input
Fail-safe input
This input enables the watchdog timeout feature.
10XS3412
6
NXP Semiconductors
5
Electrical characteristics
5.1
Maximum ratings
Table 4. Maximum ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage
to the device.
Ratings
Symbol
Value
Unit
ELECTRICAL RATINGS
supply voltage range
V
PWR
• Load dump at 25 °C (400 ms)
• Maximum operating voltage
41
28
V
V
PWR(SS)
• Reverse battery at 25 °C (2.0 min.)
-18
VDD supply voltage range
Input/output voltage
VDD
-0.3 to 5.5
V
V
(7)
-0.3 to V +0.3
DD
WAKE input clamp current
CSNS input clamp current
I
2.5
2.5
mA
mA
CL(WAKE)
I
CL(CSNS)
HS [0:3] voltage
• Positive
V
I
41
-16
V
HS[0:3]
• Negative
Output current(4)
6
A
HS[0:3]
Output clamp energy using Single-pulse method(5)
E
100
mJ
CL[0:3]
ESD Voltage(6)
• Human Body Model (HBM) for HS[0:3], VPWR and GND
• Human Body Model (HBM) for other pins
• Charge Device Model (CDM)
V
V
±8000
±2000
ESD1
ESD2
V
Corner pins (1, 13, 19, 21)
V
V
±750
±500
ESD3
ESD4
All other pins (2-12, 14-18, 20, 22-24)
THERMAL RATINGS
Operating temperature
• Ambient
TA
TJ
-40 to 125
-40 to 150
°C
°C
• Junction
Storage temperature
TSTG
-55 to 150
Notes
4. Continuous high-side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output current
using package thermal resistance is required.
5. Active clamp energy using single-pulse method (L = 2.0 mH, R = 0 Ω, V
= 14 V, T = 150°C initial).
J
L
PWR
6. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), the Machine Model (MM) (CZAP
200 pF, RZAP = 0 Ω), and the Charge Device Model (CDM), Robotic (CZAP = 4.0 pF).
=
7. Input / Output pins are: IN[0:3], RSTB, FSI, CSNS, SI, SCLK, CSB, SO, FSB
10XS3412
NXP Semiconductors
7
Table 4. Maximum ratings (continued)
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage
to the device.
Ratings
Symbol
Value
Unit
THERMAL RESISTANCE
Thermal Resistance(8)
• Junction to Case
R
R
<1.0
30
°C/W
θJC
θJA
• Junction to Ambient
(10)
Peak Package Reflow Temperature During Reflow(9)
• 10XS3412CHFK
,
°C
TPPRT
Note 9
• 10XS3412JHFK
Notes
8. Device mounted on a 2s2p test board per JEDEC JESD51-2. 15 °C/W of RθJA can be reached in a real application case (4 layers board).
9. Pin soldering temperature limit is for 40 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause
malfunction or permanent damage to the device.
10. NXP’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and
Moisture Sensitivity Levels (MSL), go to www.nxp.com, search by part number (remove prefixes/suffixes) and enter the core ID to view all
orderable parts, and review parametrics.
10XS3412
8
NXP Semiconductors
5.2
Static electrical characteristics
Table 5. Static electrical characteristics
Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 20 V, 3.0 V ≤ VDD ≤ 5.5 V, -40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise
noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER INPUTS
Battery supply voltage range
• Fully operational
V
6.0
4.0
–
–
20
28
V
PWR
• Extended mode(11)
Battery clamp voltage(12)
V
41
47
53
V
PWR(CLAMP)
V
operating supply current
• Outputs commanded ON, HS[0:3] open, IN[0:3] > V
PWR
I
mA
PWR(ON)
–
6.5
20
IH
V
PWR supply current
I
mA
• Outputs commanded OFF, OFF openload detection disabled, HS[0:3] shorted
to the ground with VDD= 5.5 V WAKE > VIH or RST > VIH and IN[0:3] < VIL
PWR(SBY)
–
6.5
8.0
Sleep state supply current
VPWR = 12 V, RST = WAKE = IN[0:3] < VIL, HS[0:3] shorted to the ground
• TA = 25 °C
• TA = 85 °C
I
μA
PWR(SLEEP)
–
–
1.0
–
5.0
30
V
V
supply voltage
V
3.0
–
5.5
V
DD
DD(ON)
supply current at V = 5.5 V
DD
DD
• No SPI communication
• 8.0 MHz SPI communication(13)
I
–
–
1.6
5.0
2.2
–
mA
DD(ON)
V
sleep state current at V = 5.5 V
I
DD(SLEEP)
–
–
5.0
36
μA
V
DD
DD
Overvoltage shutdown threshold
Overvoltage shutdown hysteresis
Undervoltage shutdown threshold(14)
V
28
32
0.8
3.9
-
PWR(OV)
V
0.2
3.3
0.5
3.4
2.2
1.5
4.3
0.9
4.5
2.8
V
PWR(OVHYS)
V
V
PWR(UV)
V
and VDD power-on reset threshold
V
V
PWR
SUPPLY(POR)
PWR(UV)
V
Recovery undervoltage threshold
supply failure threshold (for VPWR > VPWR(UV)
Vpwr(UV)_UP
4.1
2.5
V
)
V
V
DD
DD(FAIL)
Notes
11. In extended mode, the functionality is guaranteed but not the electrical parameters. From 4.0 V to 6.0 V voltage range, the device is only protected
with the thermal shutdown detection.
12. Measured with the outputs open.
13. Typical value guaranteed per design.
14. Output will automatically recover with time limited autoretry to instructed state when VPWR voltage is restored to normal as long as the VPWR
degradation level did not go below the undervoltage power-on reset threshold. This applies to all internal device logic that is supplied by VPWR
and assumes that the external VDD supply is within specification.
10XS3412
NXP Semiconductors
9
Table 5. Static electrical characteristics (continued)
Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 20 V, 3.0 V ≤ VDD ≤ 5.5 V, -40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise
noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
OUTPUTS HS0 TO HS3
HS[0,1] output Drain-to-Source ON resistance (I = 5.0 A, T = 25 °C)
HS
A
• V
• V
• V
• V
= 4.5 V
= 6.0 V
= 10 V
= 13 V
–
–
–
–
–
–
–
–
36
16
10
10
PWR
PWR
PWR
PWR
R
mΩ
DS_01(ON)
HS[0,1] output Drain-to-Source ON resistance (I = 5.0 A, T = 150 °C)
HS
A
• V
• V
• V
• V
= 4.5 V
= 6.0 V
= 10 V
= 13 V
–
–
–
–
–
–
–
–
62
27
17
17
PWR
PWR
PWR
PWR
R
R
R
mΩ
mΩ
mΩ
DS_01(ON)
SD_01(ON)
DS_23(ON)
HS[0,1] output Source-to-Drain ON resistance (I = -5.0 A, V
HS
= 18 V)(15)
PWR
• T = 25 °C
–
–
–
–
15
20
A
• T = 150 °C
A
HS[2,3] output Drain-to-Source ON resistance (I = 5.0 A, T = 25 °C)
HS
A
• V
• V
• V
• V
= 4.5 V
= 6.0 V
= 10 V
= 13 V
–
–
–
–
–
–
–
–
44
19
12
12
PWR
PWR
PWR
PWR
HS[2,3] output Drain-to-Source ON resistance (I = 5.0 A, T = 150 °C)
HS
A
• V
• V
• V
• V
= 4.5 V
= 6.0 V
= 10 V
= 13 V
–
–
–
–
–
–
–
–
75
33
21
21
PWR
PWR
PWR
PWR
R
R
mΩ
DS_23(ON)
SD_23(ON)
HS[2,3] output Source-to-Drain ON resistance
(I = -5.0 A, V
= -18 V)(15)
HS
PWR
–
–
–
–
18
24
mΩ
mΩ
• T = 25 °C
A
• T = 150 °C
A
Maximum severe short-circuit impedance detection(16)
R
28
64
100
SHORT
Notes
15. Source-Drain ON resistance (reverse Drain-to-Source ON resistance) with negative polarity V
16. Short-circuit impedance calculated from HS[0:3] to GND pins. Value guaranteed per design.
.
PWR
10XS3412
10
NXP Semiconductors
Table 5. Static electrical characteristics (continued)
Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 20 V, 3.0 V ≤ VDD ≤ 5.5 V, -40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise
noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
OUTPUTS HS0 TO HS3 (continued)
Symbol
Min
Typ
Max
Unit
Output overcurrent detection levels (6.0 V < V
28 W bit = 0
< 20 V)
A
HS[0:3]
78
94.0
60.0
52.5
45.0
37.5
30.0
22.5
15.0
12.0
8.0
110
70
OCHI1_0
OCHI2_0
OC1_0
50
44.1
37.8
31.5
25.2
18.9
12.6
10.0
6.4
60.9
52.2
43.5
34.8
26.1
17.4
14.0
9.6
OC2_0
OC3_0
OC4_0
OCLO4_0
OCLO3_0
OCLO2_0
OCLO1_0
39
25
47.0
30.0
26.2
22.5
18.7
15.0
11.2
7.5
55
35
OCHI1_1
OCHI2_1
OC1_1
28 W bit = 1
22.0
18.9
15.7
12.6
9.4
30.5
26.1
21.8
17.4
13.1
9.0
OC2_1
OC3_1
OC4_1
OCLO4_1
OCLO3_1
OCLO2_1
OCLO1_1
6.0
4.5
6.0
7.5
3.0
4.0
5.0
Current sense ratio (6.0 V <
• 28 W bit = 0
< 20 V, CSNS < 5.0 V)(17)
HS[0:3]
• CSNS_ratio bit = 0
• CSNS_ratio bit = 1
C
C
–
–
1/8700
1/53000
–
–
SR0_0
SR1_0
–
• 28 W bit = 1
• CSNS_ratio bit = 0
• CSNS_ratio bit = 1
C
C
–
–
1/4350
1/26500
–
–
SR0_1
SR1_1
Current sense ratio (C
with 28 W bit=0
) accuracy (6.0 V < V
< 20 V)
HS[0:3]
SR0
• Output current
-12
-13
-16
-20
–
–
–
–
12
13
16
20
12.5 A
5.0 A
3.0 A
1.5 A
C
%
SR0_0_ACC
Notes
17. Current sense ratio = ICSNS / IHS[0:3]
10XS3412
NXP Semiconductors
11
Table 5. Static electrical characteristics (continued)
Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 20 V, 3.0 V ≤ VDD ≤ 5.5 V, -40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise
noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
OUTPUTS HS0 TO HS3 (continued)
Symbol
Min
Typ
Max
Unit
Current sense ratio (C
with 28 W bit=1
) accuracy (6.0 V < V < 20 V)
HS
SR0
• Output current
3.0 A
C
%
SR0_1_ACC
-16
-20
–
–
16
20
1.5 A
C
C
current recopy accuracy with one calibration point (6.0 V < V
• Output current
< 20 V)(18)
HS[0:3]
SR0
C
SR0_0_ACC(C
AL)
-5.0
–
5.0
%
5.0 A
current recopy temperature drift (6.0 V < V
< 20 V)
HS[0:3]
SR0
with 28 W bit=0(19)
• Output current
Δ(C
)/
SR0_0
%/°C
Δ(T)
0.04
5.0 A
Current sense ratio (C
with 28 W bit=0
) accuracy (6.0 V < V
< 20 V)
HS[0:3]
SR1
• Output current
12.5 A
C
%
V
SR1_0_ACC
-17
-12
–
–
+17
+12
75 A
Current sense clamp voltage
• CSNS Open; I = 5.0 A with C
V
CL(CSNS)
ratio
SR0
VDD+0.25
30
VDD+1.0
100
HS[0:3]
OFF openload detection source current(20)
I
–
μA
V
OLD(OFF)
OFF openload fault detection voltage threshold
ON openload fault detection current threshold
V
2.0
3.0
300
4.0
OLD(THRES)
I
100
600
mA
OLD(ON)
ON openload fault detection current threshold with LED
I
mA
V
OLD(ON_LED)
V
= V
- 0.75 V
2.5
5.0
10
HS[0:3]
PWR
Output short to V
detection voltage threshold
PWR
V
OSD(THRES)
VCL
Output programmed OFF
V
-1.2
V
-0.8
V
-0.4
PWR
PWR
PWR
Output negative clamp voltage
V
• 0.5 A < I
< 5.0 A, output programmed OFF
-22
155
–
-16
HS[0:3]
Output overtemperature shutdown for 4.5 V < VPWR < 28 V
T
175
195
°C
SD
Notes
18. Based on statistical analysis. It is not production tested.
19. Based on statistical data: delta(C
tested.
)/delta(T)={(measured ICSNS at T1 - measured ICSNS at T2) / measured ICSNS at room} / {T1-T2}. No production
SR0
20. Output OFF openload detection current is the current required to flow through the load for the purpose of detecting the existence of an openload
condition when the specific output is commanded OFF. Pull-up current is measured for VHS=VOLD(THRES)
10XS3412
12
NXP Semiconductors
Table 5. Static electrical characteristics (continued)
Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 20 V, 3.0 V ≤ VDD ≤ 5.5 V, -40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise
noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
CONTROL INTERFACE
Input logic high voltage(21)
Input logic low voltage(21)
V
2.0
-0.3
5.0
5.0
–
–
–
VDD+0.3
0.8
V
IH
V
IL
V
Input logic pull-down current (SCLK, SI)(24)
Input logic pull-up current (CS)(25)
SO, FS tri-state capacitance(22)
I
–
20
μA
μA
pF
kΩ
pF
DWN
I
–
20
UP
C
–
20
SO
Input logic pull-down resistor (RST, WAKE and IN[0:3])
Input capacitance(22)
R
125
–
250
4.0
500
12
DWN
C
IN
Wake input clamp voltage(23), I
• 10XS3412CHFK
< 2.5 mA
CL(WAKE)
V
19
20
25
27
32
35
V
CL(WAKE)
• 10XS3412JHFK
Wake input forward voltage
V
V
V
F(WAKE)
• I
= -2.5 mA
-2.0
–
–
–
0
-0.3
–
CL(WAKE)
SO high state output voltage
• I = 1.0 mA
V
SOH
V
-0.4
DD
OH
SO and FS low state output voltage
• I = -1.0 mA
V
V
SOL
–
0.4
2.0
OL
SO, CSNS and FS tri-state leakage current
I
μA
SO(LEAK)
RFS
• CS = VIH and 0 V < VSO < VDD, or FS = 5.5 V, or CSNS=0.0 V
-2.0
FSI external pull-down resistance(26)
• Watchdog disabled
–
10
0
1.0
–
kΩ
• Watchdog enabled
Infinite
Notes
21. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IN[0:3] and WAKE input signals. The WAKE and RST signals may
be supplied by a derived voltage referenced to V
.
PWR
22. Input capacitance of SI, CS, SCLK, RST, IN[0:3] and WAKE. This parameter is guaranteed by process monitoring but is not production tested.
23. The current must be limited by a series resistance when using voltages > 7.0 V.
24. Pull-down current is with VSI > 1.0 V and VSCLK > 1.0 V.
25. Pull-up current is with VCS < 2.0 V. CS has an active internal pull-up to V
.
DD
26. In Fail-safe HS[0:3] depends respectively on ON[0:3]. FSI has an active internal pull-up to V
~ 3.0 V.
REG
10XS3412
NXP Semiconductors
13
5.3
Dynamic electrical characteristics
Table 6. Dynamic electrical characteristics
Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 20 V, 3.0 V ≤ VDD ≤ 5.5 V, -40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise
noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
POWER OUTPUT TIMING HS0 TO HS3
Output rising medium slew rate (medium speed slew rate / SR[1:0]=00)(27)
Symbol
Min
Typ
Max
Unit
SR
V/μs
V/μs
V/μs
V/μs
V/μs
V/μs
μs
R_00
• V = 14 V
0.15
0.07
0.3
0.3
0.15
0.6
0.6
0.3
1.2
0.6
0.3
PWR
Output rising slow slew rate (low speed slew rate / SR[1:0]=01)(27)
• V = 14 V
SR
R_01
PWR
Output falling fast slew rate (high speed slew rate / SR[1:0]=10)(27)
• V = 14 V
SR
R_10
PWR
Output falling medium slew rate (medium speed slew rate / SR[1:0]=00)(27)
• V = 14 V
SR
F_00
0.15
0.07
0.3
PWR
Output falling slow slew rate (low speed slew rate / SR[1:0]=01)(27)
• V = 14 V
SR
F_01
0.15
PWR
Output rising fast slew rate (high speed slew rate / SR[1:0]=10)(27)
• V = 14 V
SR
F_10
0.3
45
0.6
70
1.2
95
PWR
HS[0,1] output turn-on and turn-off delay time(28)
• V = 14 V
t
DLY_01
PWR
HS[2,3] output turn-on and turn-off delay time(28)
• V = 14 V
tDLY_23
40
0.8
-25
65
1.0
-5.0
90
1.2
15
μs
PWR
Driver output matching slew rate (SR /SR )
R
F
ΔSR
V
= 14 V @ 25 °C and for medium speed slew rate (SR[1:0]=00)
PWR
Driver output matching time (tDLY(ON) - tDLY(OFF)
)
ΔtRF
μs
V
= 14 V, f = 240 Hz, PWM duty cycle = 50%, @ 25 °C for medium
PWR
PWM
speed slew rate (SR[1:0]=00)
Notes
27. Rise and fall slew rates measured across a 5.0 Ω resistive load at high-side output = 30% to 70% (see Figure 4, page 21).
28. Turn-on delay time measured from rising edge of any signal (IN[0:3] and CS) that would turn the output ON to V = V
/ 2 with R = 5.0 Ω
HS[0:3]
PWR
L
resistive load. Turn-OFF delay time measured from falling edge of any signal (IN[0:3] and CS) that would turn the output OFF to V
=V
PWR
HS[0:3]
/ 2 with R = 5.0 Ω resistive load.
L
10XS3412
14
NXP Semiconductors
Table 6. Dynamic electrical characteristics (continued)
Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 20 V, 3.0 V ≤ VDD ≤ 5.5 V, -40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise
noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING HS0 TO HS3 (continued)
Fault detection blanking time(29)
• 10XS3412CHFK
tFAULT
-
-
5.0
5.0
20
10
μs
μs
• 10XS3412JHFK
Output shutdown delay time(30)
• 10XS3412CHFK
tDETECT
-
-
7.0
7.0
30
20
• 10XS3412JHFK
CSNS valid time(31)
Watchdog timeout(32)
tCNSVAL
tWDTO
–
70
100
400
μs
217
310
ms
ON openload fault cyclic detection period with LED
• Internal clock (PWM_en bit = 1 & CLOCK_Set = 1)
• External clock (PWM_en bit = 1 & CLOCK_Set = 0)
TOLLED
6.4
-
8.3
PWM period
12
-
ms
Notes
29. Time necessary to report the fault to FS pin.
30. Time necessary to switch off the output in case of OT or OC or SC or UV fault detection (from negative edge of FS pin to HS voltage = 50% of VPWR
31. Time necessary for CSNS to be within ±5% of the targeted value (from HS voltage = 50% of VPWR to ±5% of the targeted CSNS value).
32. For FSI open, the Watchdog timeout delay measured from the rising edge of RST, to HS[0,2] output state depend on the corresponding input
command.
10XS3412
NXP Semiconductors
15
Table 6. Dynamic electrical characteristics (continued)
Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 20 V, 3.0 V ≤ VDD ≤ 5.5 V, -40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise
noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Output overcurrent time step for 28 W bit = 0
OC[1:0]=00 (slow by default)
Symbol
Min
Typ
Max
Unit
ms
tOC1_00
tOC2_00
tOC3_00
tOC4_00
tOC5_00
tOC6_00
tOC7_00
4.40
1.62
2.10
2.88
4.58
10.16
73.2
6.30
2.32
8.02
3.00
3.00
3.90
4.12
5.36
6.56
8.54
14.52
104.6
18.88
134.0
OC[1:0]=01 (fast)
tOC1_01
tOC2_01
tOC3_01
tOC4_01
tOC5_01
tOC6_01
tOC7_01
1.10
0.40
0.52
0.72
1.14
2.54
18.2
1.57
0.58
0.75
1.03
1.64
3.63
26.1
2.00
0.75
0.98
1.34
2.13
4.72
34.0
OC[1:0]=10 (medium)
tOC1_10
tOC2_10
tOC3_10
tOC4_10
tOC5_10
tOC6_10
tOC7_10
2.20
0.81
1.05
1.44
2.29
5.08
36.6
3.15
1.16
1.50
2.06
3.28
7.26
52.3
4.01
1.50
1.95
2.68
4.27
9.44
68.0
OC[1:0]=11 (very slow)
tOC1_11
tOC2_11
tOC3_11
tOC4_11
tOC5_11
tOC6_11
tOC7_11
8.8
3.2
12.6
4.6
16.4
21.4
7.8
4.2
6.0
5.7
8.2
10.7
17.0
37.7
272.0
9.1
13.1
29.0
209.2
20.3
146.4
10XS3412
16
NXP Semiconductors
Table 6. Dynamic electrical characteristics (continued)
Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 20 V, 3.0 V ≤ VDD ≤ 5.5 V, -40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise
noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Output overcurrent time step for 28 W bit = 1
OC[1:0]=00 (slow by default)
Symbol
Min
Typ
Max
Unit
ms
tOC1_00
tOC2_00
tOC3_00
tOC4_00
tOC5_00
tOC6_00
tOC7_00
3.4
1.1
1.4
2.0
3.4
8.5
62.4
4.9
1.6
6.4
2.1
2.1
2.8
2.9
3.8
4.9
6.4
12.2
89.2
15.9
116.0
OC[1:0]=01 (fast)
tOC1_01
tOC2_01
tOC3_01
tOC4_01
tOC5_01
tOC6_01
tOC7_01
0.86
0.28
0.36
0.51
0.78
2.14
20.2
1.24
0.40
0.52
0.74
1.12
3.06
22.2
1.61
0.52
0.68
0.96
1.46
3.98
28.9
OC[1:0]=10 (medium)
tOC1_10
tOC2_10
tOC3_10
tOC4_10
tOC5_10
tOC6_10
tOC7_10
1.7
0.5
0.7
1.0
1.7
4.2
31.2
2.5
0.8
1.0
1.5
2.5
6.1
44.6
3.3
1.0
1.3
2.0
3.3
6.0
58.0
OC[1:0]=11 (very slow)
tOC1_11
tOC2_11
tOC3_11
tOC4_11
tOC5_11
tOC6_11
tOC7_11
6.8
2.2
9.8
3.2
12.8
16.7
5.5
2.9
4.2
4.0
5.8
7.6
6.8
9.8
12.8
31.8
232.0
17.0
124.8
24.4
178.4
10XS3412
NXP Semiconductors
17
Table 6. Dynamic electrical characteristics (continued)
Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 20 V, 3.0 V ≤ VDD ≤ 5.5 V, -40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise
noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Bulb cooling time step for 28 W bit = 0
Symbol
Min
Typ
Max
Unit
ms
CB[1:0]=00 or 11 (medium)
tBC1_00
tBC2_00
tBC3_00
tBC4_00
tBC5_00
tBC6_00
242
126
140
158
181
211
347
181
200
226
259
302
452
236
260
294
337
393
CB[1:0]=01 (fast)
tBC1_01
tBC2_01
tBC3_01
tBC4_01
tBC5_01
tBC6_01
121
63
173
90
226
118
130
147
169
197
70
100
113
129
151
79
90
105
CB[1:0]=10 (slow)
tBC1_10
tBC2_10
tBC3_10
tBC4_10
tBC5_10
tBC6_10
484
252
280
316
362
422
694
362
400
452
518
604
1904
472
520
588
674
786
for 28 W bit = 1
CB[1:0]=00 or 11 (medium)
tBC1_00
tBC2_00
tBC3_00
tBC4_00
tBC5_00
291
156
178
208
251
314
417
224
255
298
359
449
542
292
332
388
467
584
tB
C6_00
CB[1:0]=01 (fast)
tBC1_01
tB
146
78
209
112
127
145
180
324
272
146
166
189
234
422
C2_01
tBC3_01
tBC4_01
tB
88
101
126
226
C5_01
tBC6_01
CB[1:0]=10 (slow)
tBC1_10
tBC2_10
tBC3_10
tBC4_10
tBC5_10
tBC6_10
583
312
357
417
501
628
834
448
510
596
717
898
1085
582
665
775
933
1170
10XS3412
18
NXP Semiconductors
Table 6. Dynamic electrical characteristics (continued)
Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 20 V, 3.0 V ≤ VDD ≤ 5.5 V, -40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise
noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
PWM MODULE TIMING
Input PWM clock range on IN0
fIN0
7.68
1.0
100
–
–
2.0
200
–
51.2
4.0
400
1.0
+10
156
26
kHz
kHz
kHz
kHz
%
Input PWM clock low frequency detection range on IN0(33)
Input PWM clock high frequency detection range on IN0(33)
Output PWM frequency range
fIN0(LOW)
fIN0(HIGH)
fPWM
Output PWM frequency accuracy using calibrated oscillator
Default output PWM frequency using internal oscillator
CS calibration low minimum time detection range
CS calibration low maximum time detection range
Output PWM duty-cycle range for fpwm = 1.0 kHz for high speed slew rate(34)
Output PWM duty-cycle range for fpwm = 400 Hz(34)
Output PWM duty-cycle range for fpwm = 200 Hz (34)
INPUT TIMING
AFPWM(CAL)
fPWM(0)
-10
84
–
120
20
200
–
Hz
μs
tCSB(MIN)
tCSB(MAX)
RPWM_1k
RPWM_400
RPWM_200
14
140
6.0
10
260
94
μs
%
–
98
%
5.0
–
98
%
Direct input toggle timeout
tIN
175
105
250
150
325
195
ms
ms
AUTORETRY TIMING
Autoretry period
tAUTO
TEMPERATURE ON THE GND FLAG
Thermal prewarning detection(35)
TOTWAR
110
1.15
-3.5
125
1.20
-3.7
140
1.25
-3.9
°C
V
Analog temperature feedback at TA = 25 °C with RCSNS=2.5 kΩ
Analog temperature feedback derating with RCSNS=2.5 kΩ(36)
Notes
TFEED
DTFEED
mV/°C
33. Clock fail detector available for PWM_en bit is set to logic [1] and CLOCK_sel is set to logic [0].
34. The PWM ratio is measured at VHS = 50% of VPWR and for the default SR value. It is possible to put the device fully-on (PWM duty-cycle 100%)
and fully-off (duty-cycle 0%). For values outside this range, a calibration is needed between the PWM duty-cycle programming and the PWM on
the output with R = 5.0 Ω resistive load.
L
35. Typical value guaranteed per design.
36. Value guaranteed per statistical analysis.
10XS3412
NXP Semiconductors
19
Table 6. Dynamic electrical characteristics (continued)
Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 20 V, 3.0 V ≤ VDD ≤ 5.5 V, -40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise
noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
SPI INTERFACE CHARACTERISTICS(37)
Maximum frequency of SPI operation
Symbol
Min
Typ
Max
Unit
fSPI
tWRST
tCS
–
10
–
–
–
–
–
–
–
–
–
–
–
8.0
–
MHz
μs
μs
μs
ns
(38)
Required low state duration for RST
Rising edge of CS to falling edge of CS (required setup time)(39)
Rising edge of RST to falling edge of CS (required setup time)(39)
Falling edge of CS to rising edge of SCLK (required setup time)(39)
Required high state duration of SCLK (required setup time)(39)
Required low state duration of SCLK (required setup time)(39)
Falling edge of SCLK to rising edge of CS (required setup time)(39)
SI to falling edge of SCLK (required setup time)(40)
Falling edge of SCLK to SI (required setup time)(40)
SO rise time
1.0
5.0
500
50
50
60
37
49
tENBL
–
tLEAD
–
tWSCLKh
tWSCLKl
tLAG
–
ns
–
ns
–
ns
tSI(SU)
tSI(HOLD)
–
ns
–
ns
tRSO
tFSO
ns
ns
• C = 80 pF
–
–
13
L
SO fall time
• C = 80 pF
L
–
–
–
–
–
–
–
–
–
–
13
13
13
60
60
SI, CS, SCLK, incoming signal rise time(40)
tRSI
tFSI
tSO(EN)
tSO(DIS)
ns
ns
ns
ns
SI, CS, SCLK, incoming signal fall time(40)
Time from rising edge of SCLK to SO low-impedance(41)
Time from rising edge of SCLK to SO high-impedance(42)
Notes
37. Parameters guaranteed by design.
38. RST low duration measured with outputs enabled and going to OFF or disabled condition.
39. Maximum setup time required for the 10XS3412 is the minimum guaranteed time needed from the microcontroller.
40. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
41. Time required for output status data to be available for use at SO. 1.0 kΩ on pull-up on CS.
42. Time required for output status data to be terminated at SO. 1.0 kΩ on pull-up on CS.
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20
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5.4
Timing diagrams
IN[0:3]
high logic level
low logic level
Time
Time
Time
or
CS
high logic level
low logic level
VHS[0:3]
V
PWR
R
PWM
50%V
PWR
tDLY(OFF)
tDLY(ON)
VHS[0:3]
70% V
PWR
SRF
SRR
30% V
PWR
Time
Figure 4. Output slew rate and time delays
I
OCH1
I
I
OCH2
OC1
OC2
Load
Current
I
I
I
OC3
OC4
I
I
I
OCLO4
OCLO3
OCLO2
I
OCLO1
Time
t
t
t
t
OC3
OC1
t
OC5
t
OC6
OC7
t
OC4
OC2
Figure 5. Overcurrent shutdown protection
10XS3412
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21
I
OCH1
OCH2
I
I
OC1
OC2
I
I
I
I
I
OC3
OC4
OCLO4
OCLO3
I
OCLO2
I
OCLO1
Previous OFF duration
(tOFF
)
t
t
t
B
C5
B
C3
B
C1
t
B
C6
t
B
C4
t
B
C2
Figure 6. Bulb cooling management
V
IH
RST
10% VDD
0.2 VDD
VIL
tCS
t
ENBL
t
WRST
90% V
DD
V
IH
C
10%V
DD
V
IL
t
RSI
t
WSCLKh
t
LEAD
t
LAG
VIH
90% VDD
V
IH
SCLK
10% VDD
V
IL
t
SI(SU)
t
TwSCLKl
WSCLKl
t
FSI
t
SI(HOLD)
V
IH
90%V
DD
Don’t Care
Don’t Care
Don’t Care
Valid
Valid
SI
10% VDD
V
IH
Figure 7. Input timing switching characteristics
10XS3412
22
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t
t
FSI
RSI
VOH
90% V
DD
50%
SCLK
10% VDD
VOL
tSO(EN)
10%VDD
VOH
90% V
DD
SO
VOL
Low to High
tRSO
tVALID
tFSO
SO
VOH
90% V
DD
High to Low
10% VDD
VOL
tSO(DIS)
Figure 8. SCLK waveform and valid SO data delay time
10XS3412
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23
6
Functional description
6.1
Introduction
The 10XS3412 is one in a family of devices designed for low-voltage automotive lighting applications. Its four low RDS(on) MOSFETs (dual
10 mΩ, dual 12 mΩ) can control four separate 55 W / 28 W bulbs and/or Xenon modules.
Programming, control and diagnostics are accomplished using a 16-bit SPI interface. Its output with selectable slew-rate improves
electromagnetic compatibility (EMC) behavior. Additionally, each output has its own parallel input or SPI control for pulse-width modulation
(PWM) control if desired. The 10XS3412 allows the user to program via the SPI the fault current trip levels and duration of acceptable
lamp inrush. The device has Fail-safe mode to provide functionality of the outputs in case of MCU damage.
6.2
Functional pin description
6.2.1 Output current monitoring (CSNS)
The Current Sense pin provides a current proportional to the designated HS0:HS3 output or a voltage proportional to the temperature on
the GND flag. That current is fed into a ground-referenced resistor (4.7 kΩ typical) and its voltage is monitored by an MCU's A/D. The
output type is selected via the SPI. This pin can be tri-stated through the SPI.
6.2.2 Direct inputs (IN0, IN1, IN2, IN3)
Each IN input wakes the device. The IN0:IN3 high-side input pins are also used to directly control HS0:HS3 high-side output pins. In case
of the outputs are controlled by PWM module, the external PWM clock is applied to IN0 pin. These pins are to be driven with CMOS levels,
and they have a passive internal pull-down, RDWN
.
6.2.3 Fault status (FS)
This pin is an open drain configured output requiring an external pull-up resistor to VDD for fault reporting. If a device fault condition is
detected, this pin is active LOW. Specific device diagnostics and faults are reported via the SPI SO pin.
6.2.4 Wake
The wake input wakes the device. An internal clamp protects this pin from high damaging voltages with a series resistor (10 kΩ typ). This
input has a passive internal pull-down, RDWN
.
6.2.5 Reset (RST)
The reset input wakes the device. This is used to initialize the device configuration and fault registers, as well as place the device in a low-
current Sleep mode. The pin also starts the watchdog timer when transitioning from logic [0] to logic [1]. This pin has a passive internal
pull-down, RDWN
.
6.2.6 Chip select (CS)
The CS pin enables communication with the master microcontroller (MCU). When this pin is in a logic [0] state, the device is capable of
transferring information to, and receiving information from, the MCU. The 10XS3412 latches in data from the Input Shift registers to the
addressed registers on the rising edge of CS. The device transfers status information from the power output to the Shift register on the
falling edge of CS. The SO output driver is enabled when CS is logic [0]. CS should transition from a logic [1] to a logic [0] state only when
SCLK is a logic [0]. CS has an active internal pull-up from VDD, IUP
.
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24
NXP Semiconductors
6.2.7 Serial clock (SCLK)
The SCLK pin clocks the internal shift registers of the 10XS3412 device. The serial input (SI) pin accepts data into the input shift register
on the falling edge of the SCLK signal while the serial output (SO) pin shifts data information out of the SO line driver on the rising edge
of the SCLK signal. It is important the SCLK pin be in a logic low state whenever CS makes any transition. For this reason, it is
recommended the SCLK pin be in a logic [0] whenever the device is not accessed (CS logic [1] state). SCLK has an active internal pull-
down. When CS is logic [1], signals at the SCLK and SI pins are ignored and SO is tri-stated (high-impedance) (see Figure 10, page 27).
SCLK input has an active internal pull-down, IDWN
.
6.2.8 Serial input (SI)
This is a serial interface (SI) command data input pin. Each SI bit is read on the falling edge of SCLK. A 16-bit stream of serial data is
required on the SI pin, starting with D15 (MSB) to D0 (LSB). The internal registers of the 10XS3412 are configured and controlled using
a 5-bit addressing scheme described in Table 11. Register addressing and configuration are described in Table 12. The SI input has an
active internal pull-down, IDWN
.
6.2.9 Digital drain voltage (VDD)
This pin is an external voltage input pin used to supply power to the SPI circuit. In the event VDD is lost (VDD Failure), the device goes to
Fail-safe mode.
6.2.10 Ground (GND)
These pins are the ground for the device.
6.2.11 Positive power supply (VPWR)
This pin connects to the positive power supply and is the source of operational power for the device. The VPWR contact is the backside
surface mount tab of the package.
6.2.12 Serial output (SO)
The SO data pin is a tri-stateable output from the shift register. The SO pin remains in a high-impedance state until the CS pin is put into
a logic [0] state. The SO data is capable of reporting the status of the output, the device configuration, the state of the key inputs, etc. The
SO pin changes state on the rising edge of SCLK and reads out on the falling edge of SCLK. SO reporting descriptions are provided in
Table 24.
6.2.13 High-side outputs (HS3, HS1, HS0, HS2)
Protected 10 mΩ and 12 mΩ high-side power outputs to the load.
6.2.14 Fail-safe input (FSI)
This pin incorporates an active internal pull-up current source from internal supply (VREG). This enables the watchdog timeout feature.
When the FSI pin is opened, the watchdog circuit is enabled. After a Watchdog timeout occurs, the output states depends on IN[0:3].
When the FSI pin is connected to GND, the watchdog circuit is disabled. The output states depends on IN[0:3] in case of VDD Failure
condition, in case VDD failure detection is activated (VDD_FAIL_en bit sets to logic [1]).
10XS3412
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25
6.3
Functional internal block description
MC10XS3412 - Functional Block Diagram
Self-protected
High Side Switches
Power Supply
MCU Interface and Output Control
HS0 - HS3
Parallel Control Inputs
SPI Interface
PWM Controller
Self-protected High Side Switches
Power Supply
MCU Interface and Output Control
Figure 9. Functional block diagram
6.3.1 Power supply
The 10XS3412 is designed to operate from 4.0 V to 28 V on the VPWR pin. Characteristics are provided from 6.0 V to 20 V for the device.
The VPWR pin supplies power to internal regulator, analog, and logic circuit blocks. The VDD supply is used for Serial Peripheral Interface
(SPI) communication in order to configure and diagnose the device. This IC architecture provides a low quiescent current Sleep mode.
Applying VPWR and VDD to the device will place the device in the Normal mode. The device will transit to Fail-safe mode in case of failures
on the SPI or/and on VDD voltage.
6.3.2 High-side switches: HS0 – HS3
These pins are the high-side outputs controlling automotive lamps located for the front of vehicle, such as 65 W/55 W bulbs and Xenon-
HID modules. Those N-channel MOSFETs with 10 mΩ & 12 mΩ RDS(ON) are self-protected and present extended diagnostics in order to
detect bulb outage and short-circuit fault condition. The HS output is actively clamped during turn off of inductive loads and inductive
battery line. When driving DC motor or Solenoid loads demanding multiple switching, an external recirculation device must be used to
maintain the device in its Safe Operating Area.
6.3.3 MCU interface and output control
In Normal mode, each bulb is controlled directly from the MCU through SPI. A pulse width modulation control module allows improvement
of lamp lifetime with bulb power regulation (PWM frequency range from 100 to 400 Hz) and addressing the dimming application (day
running light). An analog feedback output provides a current proportional to the load current or the temperature of the board. The SPI is
used to configure and to read the diagnostic status (faults) of high-side outputs. The reported fault conditions are: open load, short circuit
to battery, short circuit to ground (overcurrent and severe short-circuit), thermal shutdown, and under/overvoltage. Thanks to accurate
and configurable overcurrent detection circuitry and wire-harness optimization, the vehicle is lighter.
In Fail-safe mode, each lamp is controlled with dedicated parallel input pins. The device is configured in default mode.
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26
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7
Functional device operation
7.1
SPI protocol description
The SPI interface has a full duplex, three-wire synchronous data transfer with four I/O lines associated with it: Serial Input (SI), Serial
Output (SO), Serial Clock (SCLK), and Chip Select (CS).
The SI/SO pins of the 10XS3412 follow a first-in first-out (D15 to D0) protocol, with both input and output words transferring the most
significant bit (MSB) first. All inputs are compatible with 5.0 or 3.3 V CMOS logic levels.
CS
SCLK
SI
D15
D14
D13
D12 D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SO
OD15 OD14 OD13 OD12 OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0
Notes 1. RST is a logic [1] state during the above operation.
2. D15 D0 relate to the most recent ordered entry of data into the device.
:
3. OD15:OD0 relate to the first 16 bits of ordered fault and status data out of the device.
Figure 10. Single 16-bit word SPI communication
7.2
Operational modes
The 10XS3412 has four operating modes: Sleep, Normal, Fail-safe and Fault. Table 7 and Figure 12 summarize details contained in
succeeding paragraphs.
The Figure 11 describes an internal signal called IN_ON[x] depending on IN[x] input.
tIN
IN[x]
IN_ON[x]
Figure 11. IN_ON[x] internal signal
The 10XS3412 transits to operating modes according to the following signals:
• wake-up = RST or WAKE or IN_ON[0] or IN_ON[1] or IN_ON[2] or IN_ON[3],
• fail = (VDD Failure and VDD_FAIL_en) or (Watchdog timeout and FSI input not shorted to ground),
• fault = OC[0:3] or OT[0:3] or SC[0:3] or UV or (OV and OV_dis).
10XS3412
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27
Table 7. 10XS3412 operating modes
Mode
wake-up
fail
fault
Comments
Sleep
0
1
x
x
Device is in Sleep mode. All outputs are OFF.
Normal
0
0
Device is currently in Normal mode. Watchdog is active if enabled.
Device is currently in Fail-safe mode due to watchdog timeout or VDD
Failure conditions. The output states depend on the corresponding
input in case the FSI is open.
Fail-safe
1
1
1
0
1
Device is currently in Fault mode. The faulted output(s) is (are) OFF.
The safe autoretry circuitry is active to turn-on again the output(s).
Fault
X
x = Don’t care.
(fail=0) and (wake-up=1) and (fault=0)
Sleep
(wake-up=0)
(wake-up=1) and
(fail=1)
and (fault=0)
(wake-up=0)
(wake-up=1)
and (fault=1)
(wake-up=0)
(fail=1) and
(wake-up=1)
and (fault=1)
(fail=0) and
(wake-up=1)
and (fault=1)
Fault
Normal
(fail=0) and
(wake-up=1)
and (fault=0)
(fail=1) and
(wake-up=1)
and (fault=0)
Fail-safe
(fail=0) and (wake-up=1) and (fault=0)
(fail=1) and (wake-up=1) and (fault=0)
Figure 12. Operating modes
7.2.1 Sleep mode
The 10XS3412 is in Sleep mode when:
• VPWR and VDD are within the normal voltage range,
• wake-up = 0,
• fail = X,
• fault = X.
This is the Default mode of the device after first applying battery voltage (VPWR) prior to any I/O transitions. This is also the state of the
device when the WAKE and RST and IN_ON[0:3] are logic [0]. In the Sleep mode, the output and all unused internal circuitry, such as the
internal regulator, are off to minimize draw current. In addition, all SPI-configurable features of the device are as if set to logic [0].
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28
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7.2.2 Normal mode
The 10XS3412 is in Normal mode when:
• VPWR and VDD are within the normal voltage range,
• wake-up = 1,
• fail = 0,
• fault = 0.
In this mode, the NM bit is set to lfault_contrologic [1] and the outputs HS[0:3] are under control, as defined by hson signal:
hson[x] = ( ( (IN[x] and DIR_dis[x]) or On bit[x] ) and PWM_en ) or (On bit [x] and Duty_cycle[x] and PWM_en).
In this mode and also in Fail-safe, the fault condition reset depends on fault_control signal, as defined below:
fault_control[x] = ( (IN_ON[x] and DIR_dis[x]) and PWM_en ) or (On bit [x]).
7.2.2.1
Programmable PWM module
The outputs HS[0:3] are controlled by the programmable PWM module if PWM_en and On bits are set to logic [1].
The clock frequency from IN0 input pin or from internal clock is the factor 27 (128) of the output PWM frequency (CLOCK_sel bit). The
outputs HS[0:3] can be controlled in the range of 5% to 98% with a resolution of 7 bits of duty cycle (Table 8). The state of other IN pin is
ignored.
Table 8. Output PWM resolution
On bit
Duty cycle
X
Output state
OFF
0
1
1
1
1
1
0000000
0000001
0000010
n
PWM (1/128 duty cycle)
PWM (2/128 duty cycle)
PWM (3/128 duty cycle)
PWM ((n+1)/128 duty cycle)
fully ON
1111111
The timing includes seven programmable PWM switching delay (number of PWM clock rising edges) to improve overall EMC behavior of
the light module (Table 9).
Table 9. Output PWM switching delay
Delay bits
Output delay
000
001
010
011
100
101
110
111
no delay
16 PWM clock periods
32 PWM clock periods
48 PWM clock periods
64 PWM clock periods
80 PWM clock periods
96 PWM clock periods
112 PWM clock periods
The clock frequency from IN0 is permanently monitored in order to report a clock failure in case of the frequency is out a specified
frequency range (from fIN0(LOW) to fIN0(HIGH)). In case of clock failure, no PWM feature is provided, the On bit defines the outputs state and
the CLOCK_fail bit reports [1].
10XS3412
NXP Semiconductors
29
7.2.2.2
Calibratable internal clock
The internal clock can vary as much as +/-30 percent corresponding to typical fPWM(0) output switching period.
Using the existing SPI inputs and the precision timing reference already available to the MCU, the 10XS3412 allows clock period setting
within +/-10 percent of accuracy. Calibrating the internal clock is initiated by defined word to CALR register. The calibration pulse is
provided by the MCU. The pulse is sent on the CS pin after the SPI word is launched. At the moment, the CS pin transitions from logic [1]
to [0] until from logic [0] to [1] determine the period of internal clock with a multiplicative factor of 128.
CS
SI
SI command
ignored
CALR
Internal
clock duration
Figure 13. Internal clock calibration diagram
In case of negative CS pulse is outside a predefined time range (from tCSB(MIN) to tCSB(MAX)), the calibration event will be ignored and the
internal clock will be unaltered or reset to default value (fPWM(0)) if this was not calibrated before.
The calibratable clock is used, instead of the clock from IN0 input, when CLOCK_sel is set to [1].
7.2.3 Fail-safe mode
The 10XS3412 is in Fail-safe mode when:
• VPWR is within the normal voltage range,
• wake-up = 1,
• fail = 1,
• fault = 0.
7.2.3.1
Watchdog
If the FSI input is not grounded, the watchdog timeout detection is active when either the WAKE or IN_ON[0:3] or RST input pin transitions
from logic [0] to logic [1]. The WAKE input is capable of being pulled up to VPWR with a series of limiting resistance limiting the internal
clamp current according to the specification.
The watchdog timeout is a multiple of an internal oscillator. As long as the WD bit (D15) of an incoming SPI message is toggled within the
minimum watchdog timeout period (WDTO), the device will operate normally.
7.2.3.2
Fail-safe conditions
If an internal watchdog timeout occurs before the WD bit for FSI open (Table 10) or in case of VDD failure condition (VDD< VDD(FAIL))) for
VDD_FAIL_en bit is set to logic [1], the device will revert to a Fail-safe mode until the WD bit is written to logic [1] (see Fail-safe to Normal
mode transition paragraph) and VDD is within the normal voltage range.
Table 10. SPI watchdog activation
Typical RFSI (Ω)
Watchdog
0 (shorted to ground)
(open)
Disabled
Enabled
During the Fail-safe mode, the outputs will depend on the corresponding input. The SPI register content is reset to their default value
(except POR bit) and fault protections are fully operational.
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30
NXP Semiconductors
The Fail-safe mode can be detected by monitoring the NM bit is set to [0].
7.2.4 Normal and Fail-safe mode transitions
7.2.4.1
Transition Fail-safe to Normal mode
To leave the Fail-safe mode, VDD must be in nominal voltage and the microcontroller has to send a SPI command with WDIN bit set to
logic [1] ; the other bits are not considered. The previous latched faults are reset by the transition into Normal mode (autoretry included).
Moreover, the device can be brought out of the Fail-safe mode due to watchdog timeout issue by forcing the FSI pin to logic [0].
7.2.4.2
Transition Normal to Fail-safe mode
To leave the Normal mode, a Fail-safe condition must occurred (fail=1). The previous latched faults are reset by the transition into Fail-
safe mode (autoretry included).
7.2.5 Fault mode
The 10XS3412 is in Fault mode when:
• VPWR and VDD are within the normal voltage range
• wake-up = 1
• fail = X
• fault=1
This device indicates the faults below as they occur by driving the FS pin to logic [0] for RST input is pulled up:
• Overtemperature fault
• Overcurrent fault
• Severe short-circuit fault
• Output(s) shorted to VPWR fault in OFF state
• Openload fault in OFF state
• Overvoltage fault (enabled by default)
• Undervoltage fault
The FS pin will automatically return to logic [1] when the fault condition is removed, except for overcurrent, severe short-circuit,
overtemperature and undervoltage which will be reset by a new turn-on command (each fault_control signal to be toggled).
Fault information is retained in the SPI fault register and is available (and reset) via the SO pin during the first valid SPI communication.
The Open load fault in ON state is only reported through SPI register without effect on the corresponding output state (HS[x]) and the FS
pin.
7.2.6 Start-up sequence
The 10XS3412 enters in Normal mode after start-up if following sequence is provided:
• VPWR and VDD power supplies must be above their undervoltage thresholds,
• generate wake-up event (wake-up=1) from 0 to 1 on RST. The device switches to Normal mode with SPI register content is reset
(as defined in Table 12 and Table 24). All features of the 10XS3412 will be available after 50 μs typical and all SPI registers are set
to default values (set to logic [0]). The UV fault is reported in the SPI status registers.
And, in case of the PWM module is used (PWM_en bit is set to logic [1]) with an external reference clock:
• apply PWM clock on IN0 input pin after maximum 200 μs (min. 50 μs).
If the correct start-up sequence is not provided, the PWM function is not guaranteed.
10XS3412
NXP Semiconductors
31
7.3
Protection and diagnostic features
7.3.1 Protections
7.3.1.1
Overtemperature fault
The 10XS3412 incorporates overtemperature detection and shutdown circuitry for each output structure.
Two cases need to be considered when the output temperature is higher than TSD
:
• If the output command is ON: the corresponding output is latched OFF. FS will be also latched to logic [0]. To delatch the fault and
be able to turn ON again the outputs, the failure condition must disappear and the autoretry circuitry must be active or the
corresponding output must be commanded OFF and then ON (toggling fault_control signal of corresponding output) or VSUPPLY(POR)
condition if VDD = 0.
• If the output command is OFF: FS will go to logic [0] till the corresponding output temperature will be below TSD
.
For both cases, the fault register OT[0:3] bit into the status register will be set to [1]. The fault bits will be cleared in the status register after
a SPI read command.
7.3.1.2
Overcurrent fault
The 10XS3412 incorporates output shutdown in order to protect each output structure against resistive short-circuit condition. This
protection is composed by eight predefined current levels (time dependent) to fit Xenon-HID manners by default or, 55 W or 28 W bulb
profiles, selectable separately by Xenon bit and 28 W bits (as illustrated Figure 17, page 39).
In the first turn-on, the lamp filament is cold and the current will be huge. fault_control signal transition from logic [0] to [1] or an autoretry
define this event. In this case, the overcurrent protection will be fitted to inrush current, as shown in Figure 5. This overcurrent protection
is programmable: OC[1:0] bits select overcurrent slope speed and OCHI1 current step can be removed in case of OCHI bit is set to [1].
Over-current thresholds
fault_control
hson
Figure 14. Overcurrent detection profile
In steady state, the wire harness will be protected by OCLO2 current level by default. Three other DC overcurrent levels are available:
OCLO1 or OCLO3 or OCLO4 based on the state of the OCLO[1,0] bits.
If the load current level ever reaches the overcurrent detection level, the corresponding output will latch the output OFF and FS will be
also latched to logic [0]. To delatch the fault and be able to turn ON again the corresponding output, the failure condition must disappear
and the autoretry circuitry must be active or the corresponding output must be commanded OFF and then ON (toggling fault_control signal
of corresponding output) or VSUPPLY(POR) condition if VDD = 0.
The SPI fault report (OC[0:3] bits) is removed after a read operation.
In Normal mode using internal PWM module, the 10XS3412 incorporates also a cooling bulb filament management if OC_mode and
Xenon are set to logic [1]. In this case, the 1st step of multi-step overcurrent protection will depend to the previous OFF duration, as
illustrated in Figure 6. The following figure illustrates the current level will be used in function to the duration of previous OFF state (toff).
The slope of cooling bulb emulator is configurable with OCOFFCB[1:0] bits.
10XS3412
32
NXP Semiconductors
Depending on toff
Over-current thresholds
Cooling
toff
fault_control
hson
Figure 15. Bulb cooling principle
7.3.1.3
Severe short-circuit fault
The 10XS3412 provides output shutdown in order to protect each output in case of severe short-circuit during of the output switching.
If the short-circuit impedance is below R , the device will latch the output OFF, FS will go to logic [0] and the fault register SC[0:3] bit
SHORT
will be set to [1]. To delatch the fault and be able to turn ON again the outputs, the failure condition must disappear and the corresponding
output must be commanded OFF and then ON (toggling fault_control signal of corresponding output) or VSUPPLY(POR) condition if VDD = 0.
The SPI fault report (SC[0:3] bits) is removed after a read operation.
7.3.1.4
Overvoltage fault (enabled by default)
By default, the overvoltage protection is enabled. The 10XS3412 shuts down all outputs and FS will go to logic [0] during an overvoltage
fault condition on the VPWR pin (VPWR > VPWR(OV)). The outputs remain in the OFF state until the overvoltage condition is removed (VPWR
< VPWR(OV) - VPWR(OVHYS)). When experiencing this fault, the OVF fault bit is set to logic [1] and cleared after either a valid SPI read.
The overvoltage protection can be disabled through SPI (OV_dis bit is disabled set to logic [1]). The fault register reflects any overvoltage
condition (VPWR > VPWR(OV)). This overvoltage diagnosis, as a warning, is removed after a read operation, if the fault condition disappears.
The HS[0:3] outputs are not commanded in RDS(ON) above the OV threshold.
In Fail-safe mode, the overvoltage activation depends on the RST logic state: enable for RST = 1 and disable for RST = 0. The device is
still protected with overtemperature protection in case the overvoltage feature is disabled.
7.3.1.5
Undervoltage fault
The output(s) will latch off at some battery voltage below VPWR(UV). As long as the VDD level stays within the normal specified range, the
internal logic states within the device will remain (configuration and reporting).
In the case where battery voltage drops below the undervoltage threshold (VPWR < VPWR(UV)), the outputs will turn off, FS will go to logic
[0], and the fault register UV bit will be set to [1].
Two cases need to be considered when the battery level recovers (VPWR > VPWR(UV)_UP):
• If outputs command are low, FS will go to logic [1] but the UV bit will remain set to 1 until the next read operation (warning report).
• If the output command is ON, FS will remain at logic [0]. To delatch the fault and be able to turn ON again the outputs, the failure
condition must disappear and the autoretry circuitry must be active or the corresponding output must be commanded OFF and then
ON (toggling fault_control signal of corresponding output) or VSUPPLY(POR) condition if VDD = 0.
In extended mode, the output is protected by overtemperature shutdown circuitry. All previous latched faults, occurred when VPWR was
within the normal voltage range, are guaranteed if VDD is within the operational voltage range or until VSUPPLY(POR) if VDD = 0. Any new
OT fault is detected (VDD failure included) and reported through SPI above VPWR(UV). The output state is not changed as long as the
VPWR voltage does not drop any lower than 3.5 V typical.
All latched faults (overtemperature, overcurrent, severe short-circuit, over and undervoltage) are reset if:
• VDD < VDD(FAIL) with VPWR in nominal voltage range,
• VDD and VPWR supplies is below VSUPPLY(POR) voltage value.
10XS3412
NXP Semiconductors
33
(fault_control=0)
(open-loadOFF=1
or ShortVpwr=1
or OV=1)
(Open-load OFF=1
or ShortVpwr=1
or OV=1)
(fault_control=1 and OV=0)
(fault_control=0 or OV=1)
(fault_control=0)
(Open-load ON=1)
OFF
if hson=0
(SC=1)
ON
if hson=1
Latched
OFF
(count=16)
(Retry=1)
(SC=1)
(Open-load ON=1)
(after Retry Period and OV=0)
(OV=1)
Auto-retry
OFF
Auto-retry
ON
if hson=1
(Retry=1)
=> count=count+1
(Open-load OFF=1
or ShortVpwr=1
or OV=1)
(fault_control=0)
Figure 16. Autoretry state machine
7.3.2 Autoretry
The autoretry circuitry is used to reactivate the output(s) automatically in case of overcurrent or overtemperature or undervoltage failure
conditions to provide a high availability of the load.
Autoretry feature is available in Fault mode. It is activated in case of internal retry signal is set to logic [1]:
retry[x] = OC[x] or OT[x] or UV.
The feature retries to switch-on the output(s) after one autoretry period (tAUTO) with a limitation in term of number of occurrence (16 for
each output). The counter of retry occurrences is reset in cases of mode transitions (see Normal and Fail-safe mode transitions) and
Retry_dis bit toggling. At each autoretry, the overcurrent detection will be set to default values in order to sustain the inrush current.
The Figure 16 describes the autoretry state machine.
7.3.3 Diagnostic
7.3.3.1
Output shorted to VPWR fault
The 10XS3412 incorporates output shorted to VPWR detection circuitry in OFF state. Output shorted to VPWR fault is detected if output
voltage is higher than V and reported as a fault condition when the output is disabled (OFF). The output shorted to VPWR fault
OSD(THRES)
is latched into the status register after the internal gate voltage is pulled low enough to turn OFF the output. The OS[0:3] and OL_OFF[0:3]
fault bits are set in the status register and FS pin reports in real time the fault. If the output shorted to VPWR fault is removed, the status
register will be cleared after reading the register.
The open output shorted to VPWR protection can be disabled through SPI (OS_DIS[0:3] bit).
7.3.3.2
Openload faults
The 10XS3412 incorporates three dedicated openload detection circuitries on the output to detect in OFF and in ON state.
10XS3412
34
NXP Semiconductors
7.3.3.3
Openload detection in OFF state
The OFF output openload fault is detected when the output voltage is higher than V
pulled up with internal current source
OLD(THRES)
(IOLD(OFF)) and reported as a fault condition when the output is disabled (OFF). The OFF Output openload fault is latched into the status
register or when the internal gate voltage is pulled low enough to turn OFF the output. The OL_OFF[0:3] fault bit is set in the status register.
If the open load fault is removed (FS output pin goes to high), the status register will be cleared after reading the register.
The OFF output openload protection can be disabled through SPI (OLOFF_DIS[0:3] bit).
7.3.3.4
Openload detection in ON state
The ON output openload current thresholds can be chosen by SPI to detect a standard bulbs or LEDs (OLLED[0:3] bit set to logic [1]). In
the cases where load current drops below the defined current threshold, the OLON bit is set to logic [1], and the output stays ON and FS
will not be disturbed.
7.3.3.5
Openload detection in ON state for LED
Open load for LEDs only (OLLED[0:3] set to logic [1]) is detected periodically each tOLLED (fully-on, D[7:0]=FF). To detect OLLED in the
fully-on state, the output must be ON at least tOLLED and PWM module must be enabled (PWM_en = 1 in GCR register).
To delatch the diagnosis, the condition should be removed and SPI read operation is needed (OL_ON[0:3] bit). The ON output openload
protection can be disabled through SPI (OLON_DIS[0:3] bit).
7.3.4 Analog current recopy and temperature feedback
The CSNS pin is an analog output reporting a current proportional to the designed output current or a voltage proportional to the
temperature of the GND flag (pin #14). The routing is SPI programmable (TEMP_en, CSNS_en, CSNS_s[1,0] and CSNS_ratio_s bits).
In case the current recopy is active, the CSNS output delivers current only during ON time of the output switch without overshoot. The
maximum current is 2.0 mA typical. The typical value of external CSNS resistor connected to the ground is 4.7 kΩ.
The current recopy is not active in Fail-safe mode.
7.3.4.1
Temperature prewarning detection
In Normal mode, the 10XS3412 provides a temperature prewarning reported via SPI in case of the temperature of the GND flag is higher
than TOTWAR. This diagnosis (OTW bit set to [1]) is latched in the SPI DIAGR0 register. To delatch, a read SPI command is needed.
7.3.5 Active clamp on VPWR
The device provides an active gate clamp circuit in order to limit the maximum transient VPWR voltage at VPWR(CLAMP). In case of an
overload on an output, the corresponding output is turned off, which leads to a high-voltage at VPWR with an inductive VPWR line. When
VPWR voltage exceeds VPWR(CLAMP) threshold, the turn-off on the corresponding output is deactivated and all HS[0:3] outputs are
switched ON automatically to demagnetize the inductive Battery line.
For a long battery line between the battery and the device (> 20 meters), the smart high-side switch output may exceed the energy
capability in case of a short-circuit. It is recommended to implement a voltage transient suppressor to drain the battery line energy.
7.3.6 Reverse battery on VPWR
The output survives the application of reverse voltage as low as -18 V. Under these conditions, the ON resistance of the output is 2 times
higher than typical ohmic value in forward mode. No additional passive components are required except on VDD current path.
7.3.7 Ground disconnect protection
In the event the 10XS3412 ground is disconnected from load ground, the device protects itself and safely turns OFF the output regardless
of the state of the output at the time of disconnection (maximum VPWR=16 V). A 10 kΩ resistor needs to be added between the MCU and
each digital input pin in order to ensure that the device turns off in case of ground disconnect and to prevent this pin from exceeding
maximum ratings.
10XS3412
NXP Semiconductors
35
7.3.8 Loss of supply lines
7.3.8.1
Loss of VDD
If the external VDD supply is disconnected (or not within specification: VDD<VDD(FAIL)) with VDD_FAIL_en bit is set to logic [1]), all SPI
register content is reset.
The outputs can still be driven by the direct inputs IN[0:3] if VPWR is within specified voltage range. The 10XS3412 uses the battery input
to power the output MOSFET-related current sense circuitry and any other internal logic providing Fail-safe device operation with no VDD
supplied. In this state, the overtemperature, overcurrent, severe short-circuit, short to VPWR and OFF openload circuitry are fully
operational with default values corresponding to all SPI bits are set to logic [0]. No current is conducted from VPWR to VDD
.
7.3.8.2
Loss of VPWR
If the external VPWR supply is disconnected (or not within specification), the SPI configuration, reporting, and daisy chain features are
provided for RST is set to logic [1] under VDD in nominal conditions. The SPI pull-up and pull-down current sources are not operational.
This fault condition can be diagnosed with UV fault in the SPI STATR_s registers. The previous device configuration is maintained. No
current is conducted from VDD to VPWR.
7.3.8.3
Loss of VPWR and VDD
If the external VPWR and VDD supplies are disconnected (or not within specification: (VDD and VPWR) < VSUPPLY(POR)), all SPI register
contents are reset with default values corresponding to all SPI bits are set to logic [0] and all latched faults are also reset.
7.3.9 EMC performances
All following tests are performed on NXP evaluation board in accordance with the typical application schematic.
The device is protected in case of positive and negative transients on the VPWR line (per ISO 7637-2).
The 10XS3412 successfully meets Class 5 of the CISPR25 emission standard, and 200 V/m or BCI 200 mA injection level for immunity
tests.
7.4
Logic commands and registers
7.4.1 Serial input communication
SPI communication is accomplished using 16-bit messages. A message is transmitted by the MCU starting with the MSB D15 and ending
with the LSB, D0 (Table 11). Each incoming command message on the SI pin can be interpreted using the following bit assignments: the
MSB, D15, is the watchdog bit (WDIN). In some cases, output selection is done with bits D14:D13. The next three bits, D12:D10, are
used to select the command register. The remaining nine bits, D8:D0, are used to configure and control the outputs and their protection
features.
Multiple messages can be transmitted in succession to accommodate those applications where daisy-chaining is desirable, or to confirm
transmitted data, as long as the messages are all multiples of 16 bits. Any attempt made to latch in a message that is not 16 bits will be
ignored.
The 10XS3412 has defined registers, which are used to configure the device and to control the state of the outputs. Table 12 summarizes
the SI registers.
Table 11. SI message bit assignment
Bit sig
SI msg bit
Message bit description
Watchdog in: toggled to satisfy watchdog requirements.
MSB
D15
D14:D13
D12:D10
D9
Register address bits used in some cases for output selection (Table 12).
Register address bits.
Not used (set to logic [0]).
LSB
D8:D0
Used to configure the inputs, outputs, and the device protection features and SO status content.
10XS3412
36
NXP Semiconductors
Table 12. Serial input address and configuration bit map
SI Data
D5
SI Register
D1
4
D1 D1 D1
D15
D13
D9
D8
D7
D6
D4
D3
D2
D1
D0
2
1
0
WDI
N
STATR_s
PWMR_s
CONFR0_s
CONFR1_s
OCR_s
X
X
0
0
0
0
0
0
0
0
0
0
0
0
ON_s
0
0
PWM6_s
0
0
SOA4
PWM4_s
SR1_s
SOA3
PWM3_s
SR0_s
SOA2
SOA1
SOA0
WDI
N
A
A
A
A
A
A
A
A
0
0
0
1
1
1
0
1
1
0
0
1
1
0
1
0
1
1
28W_s
PWM5_s
DIR_dis_s
PWM2_s
DELAY2_s
PWM1_s
PWM0_s
1
1
1
1
0
0
0
0
WDI
N
0
0
DELAY1_s DELAY0_s
Retry_
WDI
N
OLOFF_dis_ OLLED_en CSNS_ratio
0
Retry_dis_s OS_dis_s OLON_dis_s
s
_s
_s
unlimited_s
WDI
N
Xenon_
s
BC1_s
BC0_s
OC1_s
OC0_s
CSNS_en
1
OCHI_s
CSNS1
1
OCLO1_s
OCLO0_s OC_mode_s
WDI
N
VDD_F
AIL_en
GCR
0
0
PWM_en CLOCK_sel TEMP_en
CSNS0
0
X
1
OV_dis
1
WDI
N
CALR
0
0
1
0
1
0
Register
state after
RST=0 or
0
0
0
X
X
X
0
0
0
0
0
0
0
0
0
0
V
or
DD(FAIL)
V
SUPPLY(POR)
condition
x=Don’t care.
s=Output selection with the bits A1A0 as defined in Table 13.
7.4.2 Device register addressing
The following section describes the possible register addresses (D[14:10]) and their impact on device operation.
7.4.2.1
Address XX000—Status register (STATR_S)
The STATR register is used to read the device status and the various configuration register contents without disrupting the device
operation or the register contents. The register bits D[4:0] determine the content of the first sixteen bits of SO data. In addition to the device
status, this feature provides the ability to read the content of the PWMR_s, CONFR0_s, CONFR1_s, OCR_s, GCR and CALR registers
(see Serial output communication (device status return data).
7.4.2.2
Address A A 001—Output PWM control register (PWMR_S)
1 0
The PWMR_s register allows the MCU to control the state of corresponding output through the SPI. Each output “s” is independently
selected for configuration based on the state of the D14:D13 bits (Table 13).
Table 13. Output selection
A1 (D14)
A0 (D13)
HS selection
0
0
1
1
0
1
0
1
HS0 (default)
HS1
HS2
HS3
A logic [1] on bit D8 (28W_s) selects the 28 W overcurrent protection profile: the overcurrent thresholds are divided by 2 and, the inrush
and cooling responses are dedicated to 28 W lamp.
Bit D7 sets the output state. A logic [1] enables the corresponding output switch and a logic [0] turns it OFF (if IN input is also pulled down).
Bits D6:D0 set the output PWM duty-cycle to one of 128 levels for PWM_en is set to logic [1], as shown Table 8.
10XS3412
NXP Semiconductors
37
7.4.2.3
Address A A 010—Output configuration register (CONFR0_S)
1 0
The CONFR0_s register allows the MCU to configure corresponding output switching through the SPI. Each output “s” is
independently selected for configuration based on the state of the D14:D13 bits (Table 13).
For the selected output, a logic [0] on bit D5 (DIR_DIS_s) will enable the output for direct control. A logic [1] on bit D5 will disable
the output from direct control (in this case, the output is only controlled by On bit).
D4:D3 bits (SR1_s and SR0_s) are used to select the high or medium or low speed slew rate for the selected output, the default
value [00] corresponds to the medium speed slew rate (Table 14).
Table 14. Slew rate speed selection
SR1_s (D4)
SR0_s (D3)
Slew rate speed
0
0
1
1
0
1
0
1
medium (default)
low
high
Not used
Incoming message bits D2:D0 reflect the desired output that will be delayed of predefined PWM clock rising edges number, as
shown Table 9, (only available for PWM_en bit is set to logic [1]).
7.4.2.4
Address A A 011—Output configuration register (CONFR1_S)
1 0
The CONFR1_s register allows the MCU to configure corresponding output fault management through the SPI. Each output “s”
is independently selected for configuration based on the state of the D14:D13 bits (Table 13).
A logic [1] on bit D6 (RETRY_unlimited_s) disables the autoretry counter for the selected output, the default value [0]
corresponds to enable autoretry feature without time limitation.
A logic [1] on bit D5 (RETRY_dis_s) disables the autoretry for the selected output, the default value [0] corresponds to enable
this feature.
A logic [1] on bit D4 (OS_dis_s) disables the output hard shorted to VPWR protection for the selected output, the default value
[0] corresponds to enable this feature.
A logic [1] on bit D3 (OLON_dis_s) disables the ON output openload detection for the selected output, the default value [0]
corresponds to enable this feature (Table 15).
A logic [1] on bit D2 (OLOFF_dis_s) disables the OFF output openload detection for the selected output, the default value [0]
corresponds to enable this feature.
A logic [1] on bit D1 (OLLED_en_s) enables the ON output openload detection for LEDs for the selected output, the default value
[0] corresponds to ON output openload detection is set for bulbs (Table 15).
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38
NXP Semiconductors
Table 15. ON openload selection
OLON_dis_s (D3)
OLLED_en_s (D1)
ON openload detection
0
0
1
0
1
X
enable with bulb threshold (default)
enable with LED threshold
disable
A logic [1] on bit D0 (CSNS_ratio_s) selects the high ratio on the CSNS pin for the corresponding output. The default value [0] is
the low ratio (Table 16).
Table 16. Current sense ratio selection
CSNS_high_s (D0)
Current sense ratio
0
1
CRS0 (default)
CRS1
7.4.2.5
Address A A 100—Output overcurrent register (OCR)
1 0
The OCR_s register allows the MCU to configure corresponding output overcurrent protection through the SPI. Each output “s”
is independently selected for configuration based on the state of the D14:D13 bits (Table 13).
A logic [1] on bit D8 (Xenon_s) enables the bulb overcurrent profile, as described Figure 17.
Xenon bit set to logic [0]:
I
OCH1
I
OCH2
I
OC1
I
OC2
I
I
I
I
OCLO4
OCLO3
OCLO2
OCLO1
Time
t
t
t
t
OC7
t
OC3
OC1
t
t
OC5
OC6
OC4
OC2
Xenon bit set to logic [1]:
I
I
OCH1
OCH2
I
I
I
I
OC1
OC2
OC3
OC4
I
I
I
I
OCLO4
OCLO3
OCLO2
OCLO1
Time
t
t
t
t
OC7
t
OC3
OC1
t
t
OC5
OC6
OC4
OC2
Figure 17. Overcurrent profile depending on Xenon bit
D[7:6] bits allow to MCU to programmable bulb cooling curve and D[5:4] bits inrush curve for selected output, as shown Table 17
and Table 18.
10XS3412
NXP Semiconductors
39
Table 17. Cooling curve selection
BC1_s (D7)
BC0_s (D6)
Profile curves speed
0
0
1
1
0
1
0
1
medium (default)
slow
fast
medium
Table 18. Inrush curve selection
OC1_s (D5)
OC0_s (D4)
Profile curves speed
slow (default)
fast
0
0
1
1
0
1
0
1
medium
very slow
A logic [1] on bit D3 (OCHI_s bit) the OCHI1 level is replaced by OCHI2 during tOC1, as shown Figure 18.
I
OCH1
I
OCH2
I
OC1
OC2
OC3
OC4
OCLO4
OCLO3
OCLO2
OCLO1
I
I
I
I
I
I
I
Time
t
t
t
t
OC7
t
OC3
OC1
t
OC5
OC6
OC4
t
OC2
Figure 18. Overcurrent profile with OCHI bit set to ‘1’
The wire harness is protected by one of four possible current levels in steady state, as defined in Table 19.
Table 19. Output steady state selection
OCLO1 (D2)
OCLO0 (D1)
Steady state current
0
0
1
1
0
1
0
1
OCLO2 (default)
OCLO3
OCLO4
OCLO1
Bit D0 (OC_mode_sel) allows to select the overcurrent mode, as described Table 20.
Table 20. Overcurrent mode selection
OC_mode_s (D0)
Overcurrent mode
0
1
only inrush current management (default)
inrush current and bulb cooling management
7.4.2.6
Address 00101—Global configuration register (GCR)
The GCR register allows the MCU to configure the device through the SPI.
Bit D8 allows the MCU to enable or disable the VDD failure detector. A logic [1] on VDD_FAIL_en bit allows transitioning to Fail-safe mode
for VDD < VDD(FAIL).
10XS3412
40
NXP Semiconductors
Bit D7 allows the MCU to enable or disable the PWM module. A logic [1] on PWM_en bit allows control of the outputs HS[0:3] with PWMR
register (the direct input states are ignored).
Bit D6 (CLOCK_sel) allows to select the clock used as reference by PWM module, as described in the following Table 21.
Table 21. PWM module selection
PWM_en (D7)
CLOCK_sel (D6)
PWM module
0
X
PWM module disabled (default)
PWM module enabled with external clock from
IN0
1
1
0
1
PWM module enabled with internal calibrated
clock
Bits D5:D4 allow the MCU to select one of two analog feedbacks on the CSNS output pin, as shown in Table 22.
Table 22. CSNS reporting selection
TEMP_en (D5) CSNS_en (D4)
CSNS reporting
0
X
1
0
1
0
CSNS tri-stated (default)
current recopy of selected output (D3:2] bits)
temperature on GND flag
Table 23. Output current recopy selection
CSNS1 (D3)
CSNS0 (D2)
CSNS reporting
0
0
1
1
0
1
0
1
HS0 (default)
HS1
HS2
HS3
The GCR register disables the overvoltage protection (D0). When this bits is [0], the overvoltage is enabled (default value).
7.4.2.7
Address 00111—Calibration register (CALR)
The CALR register allows the MCU to calibrate internal clock, as explained in Figure 16.
7.4.3 Serial output communication (device status return data)
When the CS pin is pulled low, the output register is loaded. Meanwhile, the data is clocked out MSB- (OD15-) first as the new message
data is clocked into the SI pin. The first sixteen bits of data clocking out of the SO, and following a CS transition, is dependent upon the
previously written SPI word.
Any bits clocked out of the Serial Output (SO) pin after the first 16 bits will be representative of the initial message bits clocked into the SI
pin since the CS pin first transitioned to a logic [0]. This feature is useful for daisy-chaining devices as well as message verification.
A valid message length is determined following a CS transition of [0] to [1]. If there is a valid message length, the data is latched into the
appropriate registers. A valid message length is a multiple of 16 bits. At this time, the SO pin is tri-stated and the fault status register is
now able to accept new fault status information.
SO data will represent information ranging from fault status to register contents, user selected by writing to the STATR bits OD4, OD3,
OD2, OD1, and OD0. The value of the previous bits SOA4 and SOA3 will determine which output the SO information applies to for the
registers which are output specific; viz., Fault, PWMR, CONFR0, CONFR1, and OCR registers.
Note that the SO data will continue to reflect the information for each output (depending on the previous SOA4, SOA3 state) that was
selected during the most recent STATR write until changed with an updated STATR write.
The output status register correctly reflects the status of the STATR-selected register data at the time that the CS is pulled to a logic [0]
during SPI communication, and/or for the period of time since the last valid SPI communication, with the following exception:
• The previous SPI communication was determined to be invalid. In this case, the status will be reported as though the invalid SPI
communication never occurred.
• The VPWR voltage is below 4.0 V, the status must be ignored by the MCU.
10XS3412
NXP Semiconductors
41
7.4.4 Serial output bit assignment
The 16 bits of serial output data depend on the previous serial input message, as explained in the following paragraphs. Table 24,
summarizes SO returned data for bits OD15:OD0.
• Bit OD15 is the MSB; it reflects the state of the Watchdog bit from the previously clocked-in message.
• Bits OD14:OD10 reflect the state of the bits SOA4:SOA0 from the previously clocked in message.
• Bit OD9 is set to logic [1] in Normal mode (NM).
• The contents of bits OD8:OD0 depend on bits D4:D0 from the most recent STATR command SOA4:SOA0 as explained in the
paragraphs following Table 24.
Table 24. Serial output bit map description
Previous STATR
SO Returned Data
SO SO SO SO SO OD
A4 A3 A2 A1 A0 15
OD
14
OD
13
OD
12
OD
11
OD
10
OD9 OD8
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
STATR_s
PWMR_s
A
A
A
A
0
0
0
0
0
1
WDIN SOA4 SOA3 SOA2 SOA1 SOA0 NM POR
WDIN SOA4 SOA3 SOA2 SOA1 SOA0 NM 28W_s
UV
OV
OLON_s OLOFF_s
OS_s
PWM3_s
SR0_s
OT_s
SC_s
OC_s
1
1
0
0
ON_s PWM6_s PWM5_s PWM4_s
DIR_dis_
PWM2_s
DELAY2_s
PWM1_s
DELAY1_s
PWM0_s
DELAY0_s
CONFR0_s
CONFR1_s
A
A
A
A
0
0
1
1
0
1
WDIN SOA4 SOA3 SOA2 SOA1 SOA0 NM
WDIN SOA4 SOA3 SOA2 SOA1 SOA0 NM
X
X
X
X
SR1_s
1
1
0
0
s
Retry_
Retry_dis
_s
CSNS_ratio_
s
X
OS_dis_s OLON_dis_s
OLOFF_dis_s OLLED_en_s
unlimited
_s
Xenon
_s
OCR_s
GCR
A
A
1
1
0
0
0
1
WDIN SOA4 SOA3 SOA2 SOA1 SOA0 NM
WDIN SOA4 SOA3 SOA2 SOA1 SOA0 NM
BC1_s
BC0_s
OC1_s
OC0_s
OCHI_s
CSNS1
OCLO1_s
CSNS0
OCLO0_s OC_mode_s
1
0
VDD_F PWM_ CLOCK_
AIL_en
CSNS_e
n
0
0
TEMP_en
X
OV_dis
OTW
WD_en
0
en
sel
DIAGR0
DIAGR1
DIAGR2
0
0
1
0
1
0
1
1
1
1
1
1
1
1
1
WDIN SOA4 SOA3 SOA2 SOA1 SOA0 NM
WDIN SOA4 SOA3 SOA2 SOA1 SOA0 NM
WDIN SOA4 SOA3 SOA2 SOA1 SOA0 NM
X
X
X
X
X
X
0
X
IN3
X
CAL_fail
X
IN2
X
CLOCK_fail
X
X
X
X
X
0
X
X
0
IN0
0
IN1
0
Register state
afterRST=0or
N/A N/A N/A N/A N/A
0
0
0
0
0
0
0
0
0
0
V
or
0
0
DD(FAIL)
V
SUPPLY(POR)
condition
s=Output selection with the bits A1A0 as defined in Table 13
7.4.4.1
Previous address SOA4:SOA0=A A 000 (STATR_S)
1 0
The returned data OD8 reports logic [1] in case of previous Power ON Reset condition (VSUPPLY(POR)). This bit is only reset by a read
operation.
Bits OD7:OD0 reflect the current state of the Fault register (FLTR) corresponding to the output previously selected with the bits
SOA4:SOA3 = A1A0 (Table 24).
• OC_s: overcurrent fault detection for a selected output,
• SC_s: severe short-circuit fault detection for a selected output,
• OS_s: output shorted to VPWR fault detection for a selected output,
• OLOFF_s: openload in OFF state fault detection for a selected output,
• OLON_s: openload in ON state fault detection (depending on current level threshold: bulb or LED) for a selected output,
• OV: overvoltage fault detection,
• UV: undervoltage fault detection
• POR: power on reset detection.
The FS pin reports all faults. For latched faults, this pin is reset by a new Switch OFF command (toggling fault_control signal).
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7.4.4.2
Previous address SOA4:SOA0=A A 001 (PWMR_S)
1 0
The returned data contains the programmed values in the PWMR register for the output selected with A1A0.
7.4.4.3
Previous address SOA4:SOA0=A A 010 (CONFR0_S)
1 0
The returned data contains the programmed values in the CONFR0 register for the output selected with A1A0.
7.4.4.4
Previous address SOA4:SOA0=A A 011 (CONFR1_S)
1 0
The returned data contains the programmed values in the CONFR1 register for the output selected with A1A0.
7.4.4.5
Previous address SOA4:SOA0=A A 100 (OCR_S)
1 0
The returned data contains the programmed values in the OCR register for the output selected with A1A0.
7.4.4.6
Previous address SOA4:SOA0=00101 (GCR)
The returned data contains the programmed values in the GCR register.
7.4.4.7
Previous address SOA4:SOA0=00111 (DIAGR0)
The returned data OD2 reports logic [1] in case of PWM clock on IN0 pin is out of specified frequency range.
The returned data OD1 reports logic [1] in case of calibration failure.
The returned data OD0 reports logic [1] in case of an overtemperature prewarning (temperature of the GND flag is above TOTWAR).
7.4.4.8
Previous address SOA4:SOA0=01111 (DIAGR1)
The returned data OD4: OD1 report in real time the state of the direct input IN[3:0].
The OD0 indicates if the watchdog is enabled (set to logic [1]) or not (set to logic [0]). OD4:OD1 report the output state in case of Fail-safe
state due to watchdog timeout as explained in the following Table 25.
Table 25. Watchdog activation report
WD_en (OD0)
SPI watchdog
0
1
disabled
enabled
7.4.4.9
Previous Address SOA4:SOA0=10111 (DIAGR2)
The returned data is the product ID. Bits OD2:OD0 are set to 000 for protected dual 10 mΩ and 12 mΩ high-side switches.
7.4.5 Default device configuration
The default device configuration is explained below:
• HS output is commanded by corresponding IN input or On bit through SPI. The medium slew rate is used,
• HS output is fully protected by the Xenon overcurrent profile by default, the severe short-circuit protection, the undervoltage and the
overtemperature protection. The autoretry feature is enabled,
• Openload in ON and OFF state and HS shorted to VPWR detections are available,
• No current recopy and no analog temperature feedback active,
• Overvoltage protection is enabled,
• SO reporting fault status from HS0,
• VDD failure detection is disabled.
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43
8
Typical applications
The following figure shows a typical automotive lighting application (only one vehicle corner) using an external PWM clock from the
main MCU. A redundancy circuitry has been implemented to substitute light control (from MCU to watchdog) in case of a Fail-safe
condition.
It is recommended to locate a 22 nF decoupling capacitor to the module connector.
VPWR
VDD
Voltage regulator
10µF
100nF
10µF
100nF
VPWR
VDD
VDD
VPWR
ignition
switch
VDD
VPWR
VDD
100nF
100nF
10k
10k
100nF
VDD
WAKE
HS0
HS1
HS2
22nF
I/O
FS
LOAD 0
IN0
IN1
IN2
IN3
MCU
22nF
22nF
22nF
10XS3412
10k
LOAD 1
LOAD 2
LOAD 3
SCLK
10k
SCLK
CS
RST
CS
10k
10k
I/O
SO
SI
SI
SO
HS3
A/D
CSNS
FSI
10k
GND
22nF
4.7k
10k
10k
10k
10k
VPWR
Watchdog
direct light commands (pedal, comodo,...)
Figure 19. Typical application schematic
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9
Packaging
9.1
Soldering information
The 10XS3412 is packaged in a surface mount power package intended to be soldered directly on the printed circuit board.
The AN2467 provides guidelines for printed circuit board design and assembly.
9.2
Package mechanical dimensions
Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.nxp.com and
perform a keyword search for the drawing’s document number.
Package
Suffix
Package outline drawing number
CHFK
JHFK
98ARL10596D
98ASA00426D
24-pin PQFN
10XS3412
NXP Semiconductors
45
FK SUFFIX
24-PIN PQFN
98ARL10596D
ISSUE D
10XS3412
46
NXP Semiconductors
FK SUFFIX
24-PIN PQFN
98ARL10596D
ISSUE D
10XS3412
NXP Semiconductors
47
FK SUFFIX
24-PIN PQFN
98ARL10596D
ISSUE D
10XS3412
48
NXP Semiconductors
FK SUFFIX
24-PIN PQFN
98ARL10596D
ISSUE D
10XS3412
NXP Semiconductors
49
FK SUFFIX
24-PIN PQFN
98ASA00426D
ISSUE X0
10XS3412
50
NXP Semiconductors
FK SUFFIX
24-PIN PQFN
98ASA00426D
ISSUE X0
10XS3412
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51
FK SUFFIX
24-PIN PQFN
98ASA00426D
ISSUE X0
10XS3412
52
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FK SUFFIX
24-PIN PQFN
98ASA00426D
ISSUE X0
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53
10 Additional documentation
10XS3412
10.1 Thermal addendum (Rev 2.0)
10.1.1 Introduction
24-PIN
PQFN
This thermal addendum is provided as a supplement to the 10XS3412 technical data
sheet. The addendum provides thermal performance information that may be critical in
the design and development of system applications. All electrical, application and
packaging information is provided in the data sheet.
10.1.2 Package and thermal considerations
This 10XS3412 is a dual die package. There are two heat sources in the package
independently heating with P1 and P2. This results in two junction temperatures, TJ1
and TJ2, and a thermal resistance matrix with RθJAmn
.
98ARL10596D
24-PIN PQFN (12 x 12)
For m, n = 1, RθJA11 is the thermal resistance from Junction 1 to the reference
temperature while only heat source 1 is heating with P1.
Note For package dimensions, refer to
98ARL10596D.
For m = 1, n = 2, RθJA12 is the thermal resistance from Junction 1 to the reference
temperature while heat source 2 is heating with P2. This applies to RθJ21 and RθJ22
,
respectively.
RθJA11 RθJA12
RθJA21 RθJA22
TJ1
TJ2
P1
P2
.
=
The stated values are solely for a thermal performance comparison of one package to another in a standardized environment. This
methodology is not meant to and will not predict the performance of a package in an application-specific environment. Stated values were
obtained by measurement and simulation according to the standards listed below.
10.1.3 Standards
Table 26. Thermal performance comparison
1 = Power Chip, 2 = Logic Chip [°C/W]
Thermal
m = 1,
n = 1
m = 1, n = 2
m = 2, n = 1
m = 2,
n = 2
Resistance
(1)(2)
26.04
13.21
46.42
0.67
18.18
6.40
35.49
23.94
53.82
0.00
RθJAmn
RθJBmn
RθJAmn
RθJCmn
(2)(3)
(1)(4)
(5)
37.03
0.95
Notes:
1. Per JEDEC JESD51-2 at natural convection, still air condition.
2. 2s2p thermal test board per JEDEC JESD51-7and
JESD51-5.
3. Per JEDEC JESD51-8, with the board temperature on the center trace near the power outputs.
4. Single layer thermal test board per JEDEC JESD51-3 and JESD51-5.
5. Thermal resistance between the die junction and the exposed pad, “infinite” heat sink attached to exposed pad.
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0.2mm
0.2mm
0.5mm dia.
Figure 20. Detail of copper traces under device with thermal vias
76.2mm
Figure 21. 1s JEDEC thermal test board layout
10XS3412
NXP Semiconductors
55
76.2mm
Figure 22. 2s2p JDEC thermal test board
(Red - top layer, Yellow - two buried layers)
Transparent Top View
13 12 11 10
9
8
7
6
5
4
3
2
1
16
17
24
SO
FSI
23
GND
GND
14
GND
HS3
18
22
HS2
15
VPWR
MC10XS3412 Pin Connections
24-PIN PQFN (12 x 12)
0.9 mm Pitch
12.0mm 12.0mm Body
19
20
21
HS0
HS1
NC
Figure 23. Thermal test board
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10.1.4 Device on thermal test board
Material:
Single layer printed circuit board
FR4, 1.6 mm thickness
Cu traces, 0.07 mm thickness
Cu buried traces thickness 0.035 mm
Outline:
76.2 mm x 114.3 mm board area, including edge connector for thermal testing,
74 mm x 74 mm buried layers area
Area A:
Cu heat-spreading areas on board surface
Natural convection, still air
Ambient Conditions:
Table 27. Thermal resistance performance
1 = Power Chip, 2 = Logic Chip (°C/W)
Area A
Thermal resistance
(mm2)
m = 1,
n = 1
m = 1, n = 2
m = 2, n = 1
m = 2,
n = 2
0
46.42
41.60
40.02
38.86
38.04
37.03
32.90
31.63
30.68
29.99
53.82
51.27
55.05
49.47
48.63
150
300
RθJAmn
450
600
RθJA is the thermal resistance between die junction and ambient air.
This device is a dual die package. Index m indicates the die that is heated. Index n refers to the number of the die where the junction
temperature is sensed.
65.00
60.00
55.00
50.00
45.00
40.00
35.00
30.00
25.00
0
100
200
300
400
500
600
Heat spreading area [sqmm]
RJA11
RJA12=RJA21
RJA22
Figure 24. Steady state thermal resistance in dependence on heat spreading area;
1s JEDEC thermal test board with spreading areas
10XS3412
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57
100
10
1
0.1
0.000001
0.0001
0.01
1
100
10000
Time[s]
RJA11
RJA12
RJA22
Figure 25. Transient thermal 1W step response; device on
1s JEDEC standard thermal test board with heat spreading areas 600 sq. mm
100
10
1
0.1
0.000001
0.0001
0.01
1
100
10000
Time [s]
RJA11
RJA12
RJA22
Figure 26. Transient thermal 1W step response;
device on 2s2p JEDEC standard thermal test board
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11 Revision history
Revision
Date
Description of changes
•
Initial release
7.0
10/2008
•
•
Revised wording of VPWR Supply Voltage Range in Maximum Rating Table on page 5.
Changed Maximum rating for Output Source-to-Drain ON Resistance in Static Electrical Characteristics
Table on page 8.
8.0
9.0
10/2008
7/2009
•
Added MC10XS3412DPNA part number. The “D” version has different soldering limits.
•
•
Corrected minor formatting
Separated definitions for the 10XS3412C and 10XS3412D in the Static and Dynamic Tables and created
a Device Variation Table on page 2.
10.0
10/2009
•
•
•
•
Added MC10XS3412CHFK and removed MC10XS3412CPNA from the ordering information
Added MC10XS3412DHFK and removed MC10XS3412DPNA from the ordering information
Updated the pin soldering temperature limit from 10 seconds to 40 seconds (Note (2) and (9)).
Updated Freescale form and style
11.0
12.0
5/2012
2/2013
•
•
•
•
Removed MC10XS3412DPNA from the ordering information
Added MC10XS3412JHFK
Added a new Max Solder Reflow temp of the JHFK package.
Added the package drawing for 98ASA00426D
•
Updated as per CIN 201808007I
• Corrected TOLLED values in Table 6, Dynamic electrical characteristics
• Updated Openload detection in ON state for LED (added clarification for the usage of openload LED
function and changed D[6:0]=7F to D[7:0]=FF)
13.0
8/2018
10XS3412
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59
Information in this document is provided solely to enable system and software implementers to use NXP products.
There are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits
based on the information in this document. NXP reserves the right to make changes without further notice to any
products herein.
How to Reach Us:
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NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular
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specifically disclaims any and all liability, including without limitation, consequential or incidental damages. "Typical"
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and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each
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service names are the property of their respective owners. All rights reserved.
© NXP B.V. 2018.
Document Number: MC10XS3412
Rev. 13.0
8/2018
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