LPC2136FBD64/01 [NXP]

IC 32-BIT, FLASH, 60 MHz, RISC MICROCONTROLLER, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, PLASTIC, MS-026, SOT314-2, LQFP-64, Microcontroller;


型号：	LPC2136FBD64/01
厂家：	NXP
描述：	IC 32-BIT, FLASH, 60 MHz, RISC MICROCONTROLLER, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, PLASTIC, MS-026, SOT314-2, LQFP-64, Microcontroller 时钟微控制器外围集成电路
文件：	总11页 (文件大小：135K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ES_LPC2136/01

Errata sheet LPC2136/01

Rev. 2.1 — 1 May 2012

Errata sheet

Document information

Info

Content

Keywords

Abstract

LPC2136FBD64/01, LPC2136/01 errata

This errata sheet describes both the known functional problems and any

deviations from the electrical specifications known at the release date of

this document.

Each deviation is assigned a number and its history is tracked in a table.

ES_LPC2136/01

NXP Semiconductors

Errata sheet LPC2136/01

Revision history

Rev

2.1

Date

Description

20120501

20110301

• Added Rev F.

• The format of this errata sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

• Added ADC.1

1.3

1.2

20090209

20080607

• Added Rev E.

• Added WDT.1.

• Added table for errata notes.

• Added Errata Note 2.

1.1

20070608

20060830

• Added MAM.1.

• Added ESD.1.

• Initial version.

Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

ES_LPC2136_01

All information provided in this document is subject to legal disclaimers.

Errata sheet

Rev. 2.1 — 1 May 2012

2 of 11

ES_LPC2136/01

NXP Semiconductors

Errata sheet LPC2136/01

1. Product identification

The LPC2136/01 devices typically have the following top-side marking:

LPC2136xxx

/01

xxxxxxx

xxYYWW R

The last letter in the last line (field ‘R’) will identify the device revision. This Errata Sheet

covers the following revisions of the LPC2136/01:

Table 1.

Revision overview table

Revision identifier

Revision description

First device revision

Second device revision

Third device revision

‘D’

‘E’

‘F’

Field ‘YY’ states the year the device was manufactured. Field ‘WW’ states the week the

device was manufactured during that year.

2. Errata overview

Table 2.

Functional problems table

Short description

Functional

problems

Revision identifier

Detailed description

Core.1

Incorrect update of the Abort link register

‘D’, ‘E’, ‘F’

‘D’

Section 3.1

Section 3.2

Timer.1

Timer Counter reset occurs on incorrect edge in

counter mode

SSP.1

MAM.1

WDT.1

Initial data bits/clocks corrupted in SSP transmission

Code execution failure can occur with MAM Mode 2

‘D’, ‘E’, ‘F’

‘D’

Section 3.3

Section 3.4

Section 3.5

Accessing non-Watchdog APB registers in the middle ‘D’

of the feed sequence causes a reset

ADC.1

External sync inputs not operational

‘D’, ‘E’, ‘F’

Section 3.6

Table 3.

AC/DC deviations table

AC/DC

Short description

Revision identifier

Detailed description

deviations

ESD.1

ESD weakness on RTCX1 pin

‘D’

Section 4.1

Table 4.

Errata notes table

Errata notes

Note 1

Short description

Revision identifier

Detailed description

Section 5.1

Port pin P0.31 must not be driven low during reset.

‘D’, ‘E’, ‘F’

Note 2

When the input voltage is Vi  Vdd I/O + 0.5 v on port ‘D’, ‘E’, ‘F’

pin P0.25 (configured as general purpose input pin),

current must be limited to less than 4 mA by using a

series limiting resistor.

Section 5.2

ES_LPC2136_01

All information provided in this document is subject to legal disclaimers.

Errata sheet

Rev. 2.1 — 1 May 2012

3 of 11

ES_LPC2136/01

NXP Semiconductors

Errata sheet LPC2136/01

3. Functional problems detail

3.1 Core.1: Incorrect update of the Abort Link register in Thumb state

Introduction:

If the processor is in Thumb state and executing the code sequence STR, STMIA or

PUSH followed by a PC relative load, and the STR, STMIA or PUSH is aborted, the PC is

saved to the abort link register.

Problem:

In this situation the PC is saved to the abort link register in word resolution, instead of

half-word resolution.

Conditions:

The processor must be in Thumb state, and the following sequence must occur:

<STR, STMIA, PUSH> <---- data abort on this instruction

LDR rn, [pc,#offset]

In this case the PC is saved to the link register R14_abt in only word resolution, not

half-word resolution. The effect is that the link register holds an address that could be #2

less than it should be, so any abort handler could return to one instruction earlier than

intended.

Work-around:

In a system that does not use Thumb state, there will be no problem.

In a system that uses Thumb state but does not use data aborts, or does not try to use

data aborts in a recoverable manner, there will be no problem.

Otherwise the workaround is to ensure that a STR, STMIA or PUSH cannot precede a

PC-relative load. One method for this is to add a NOP before any PC-relative load

instruction. However this would have to be done manually.

ES_LPC2136_01

All information provided in this document is subject to legal disclaimers.

Errata sheet

Rev. 2.1 — 1 May 2012

4 of 11

ES_LPC2136/01

NXP Semiconductors

Errata sheet LPC2136/01

3.2 Timer.1: In counter mode, the Timer Counter reset does not occur on

the correct incoming edge

Introduction:

Timer0 and Timer1 can be used in a counter mode. In this mode, the Timer Counter

CAP input pin.

This counter mode can be combined with the match functionality to provide additional

features. One of the features would be to reset the Timer Counter register on a match.

The same would also apply for Timer1.

Problem:

The Timer Counter reset does not trigger on the same incoming edge when the match

takes place between the corresponding Match register and the Timer Counter register.

The Timer Counter register will be reset only on the next incoming edge.

Workaround:

There are two possible workarounds:

1. Combine the Timer Counter reset feature with the “interrupt on match” feature. The

interrupt on match occurs on the correct incoming edge. In the ISR, the Timer Counter

the duration of the ISR.

2. In this solution, the “interrupt on match” feature is not used. Instead, the following

specific initialization can achieve the counting operation:

a. Initialize the Timer Counter register to 0xFFFFFFFF.

b. If “n” edges have to be counted then initialize the corresponding Match register

with value n-1. For instance, if 2 edges need to be counted then load the Match

More details on the above example:

1. Edge 1 - Timer overflows and Timer Counter (TC) is set to 0.

2. Edge 2 - TC = 1. Match takes place.

3. Edge 3 - TC = 0.

4. Edge 4 - TC = 1. Match takes place.

5. Edge 5 - TC = 0.

ES_LPC2136_01

All information provided in this document is subject to legal disclaimers.

Errata sheet

Rev. 2.1 — 1 May 2012

5 of 11

ES_LPC2136/01

NXP Semiconductors

Errata sheet LPC2136/01

3.3 SSP.1: Initial data bits/clocks of the SSP transmission are shorter

than subsequent pulses at higher frequencies

Introduction:

The SSP is a Synchronous Serial Port (SSP) controller capable of operation on a SPI,

4-wire SSI or a Microwire bus. The SSP can operate at a maximum speed of 30 MHz and

is referred to as SPI1 in the device documentation.

Problem:

At high SSP frequencies, it is found that the first four pulses are shorter than the

subsequent pulses.

At 30 MHz, the first pulse can be expected to be approximately 10 ns shorter and the

second pulse around 5 ns shorter. The remaining two pulses are around 2 ns shorter than

subsequent pulses.

At 25 MHz, the length of the first pulse would be around 7 ns shorter. The subsequent

three pulses are around 2 ns shorter.

At 20 MHz only the first pulse is affected and it is around 2 ns shorter. All subsequent

pulses are fine.

The deviation of the initial data bits/clocks will decrease as the SSP frequency decreases.

Work-around:

None.

3.4 MAM.1: Under certain conditions in MAM Mode 2 code execution out

of internal Flash can fail

Introduction:

The MAM block maximizes the performance of the ARM processor when it is running

code in Flash memory. It includes three 128-bit buffers called the Prefetch Buffer, the

Branch Trail Buffer and the data buffer. It can operate in 3 modes; Mode 0 (MAM off),

Mode 1 (MAM partially enabled) and Mode 2 (MAM fully enabled).

Problem:

Under certain conditions when the MAM is fully enabled (Mode 2) code execution from

internal Flash can fail. The conditions under which the problem can occur is dependent on

the code itself along with its positioning within the Flash memory.

Work-around:

If the above problem is encountered then Mode 2 should not be used. Instead, partially

enable the MAM using Mode 1.

ES_LPC2136_01

All information provided in this document is subject to legal disclaimers.

Errata sheet

Rev. 2.1 — 1 May 2012

6 of 11

ES_LPC2136/01

NXP Semiconductors

Errata sheet LPC2136/01

3.5 WDT.1: Accessing non-Watchdog APB registers during the feed

sequence causes a reset

Introduction:

The Watchdog timer can reset the microcontroller within a reasonable amount of time if it

enters an erroneous state.

Problem:

After writing 0xAA to WDFEED, any APB register access other than writing 0x55 to

WDFEED may cause an immediate reset.

Work-around:

Avoid APB accesses in the middle of the feed sequence. This implies that interrupts and

the GPDMA should be disabled while feeding the Watchdog.

ES_LPC2136_01

All information provided in this document is subject to legal disclaimers.

Errata sheet

Rev. 2.1 — 1 May 2012

7 of 11

ES_LPC2136/01

NXP Semiconductors

Errata sheet LPC2136/01

3.6 ADC.1: External sync inputs not operational

Introduction:

In software-controlled mode (BURST bit is 0), the 10-bit ADCs can start conversion by

using the following options in the A/D Control Register:

Fig 1. A/D control register options

Problem:

The external start conversion feature, ADxCR:START = 0x2 or 0x3, may not work reliably

and ADC external trigger edges on P0.16 or P0.22 may be missed. The occurrence of this

problem is peripheral clock (pclk) dependent. The probability of error (missing an ADC

trigger from GPIO) is estimated as follows:

• For PCLK_ADC = 60 MHz, probability error = 12 %

• For PCLK_ADC = 50 MHz, probability error = 6 %

• For PCLK_ADC = 12 MHz, probability error = 1.5 %

The probability of error is not affected by the frequency of ADC start conversion edges.

Work-around:

In software-controlled mode (BURST bit is 0), the START conversion options (bits 26:24

set to 0x1 or 0x4 or 0x5 or 0x6 or 0x7) can be used. The user can also start a conversion

by connecting an external trigger signal to a capture input pin (CAPx) from a Timer

peripheral to generate an interrupt. The timer interrupt routine can then start the ADC

conversion by setting the START bits (26:24) to 0x1. The trigger can also be generated

from a timer match register.

ES_LPC2136_01

All information provided in this document is subject to legal disclaimers.

Errata sheet

Rev. 2.1 — 1 May 2012

8 of 11

ES_LPC2136/01

NXP Semiconductors

Errata sheet LPC2136/01

4. AC/DC deviations detail

4.1 ESD.1: The device does not meet the 2 kV ESD requirements on the

RTCX1 pin

Introduction:

The LPC2136/01 is rated for 2 kV ESD. The RTCX1 pin is the input pin for the RTC

oscillator circuit.

Problem:

The LPC2136/01 does not meet the required 2 kV ESD specified.

Work-around:

Observe proper ESD handling precautions for the RTCX1 pin.

5. Errata notes detail

5.1 Note.1

Port pin P0.31 must not be driven low during reset. If low on reset the device behavior is

undetermined.

5.2 Note.2

On port pin P0.25 (when configured as general purpose input pin), leakage current

increases when the input voltage is Vi  Vdd I/O + 0.5 V. Care must be taken to limit the

current to less than 4 mA by using a series limiting resistor.

ES_LPC2136_01

All information provided in this document is subject to legal disclaimers.

Errata sheet

Rev. 2.1 — 1 May 2012

9 of 11

ES_LPC2136/01

NXP Semiconductors

Errata sheet LPC2136/01

6. Legal information

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

6.1

Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

6.2

Disclaimers

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

6.3

Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

ES_LPC2136_01

All information provided in this document is subject to legal disclaimers.

Errata sheet

Rev. 2.1 — 1 May 2012

10 of 11

ES_LPC2136/01

NXP Semiconductors

Errata sheet LPC2136/01

7. Contents

Product identification . . . . . . . . . . . . . . . . . . . . 3

Errata overview . . . . . . . . . . . . . . . . . . . . . . . . . 3

3.1

Functional problems detail . . . . . . . . . . . . . . . . 4

Core.1: Incorrect update of the Abort Link register

in Thumb state . . . . . . . . . . . . . . . . . . . . . . . . . 4

Timer.1: In counter mode, the Timer Counter reset

does not occur on the correct incoming edge. . 5

SSP.1: Initial data bits/clocks of the SSP

3.2

3.3

transmission are shorter than subsequent pulses

at higher frequencies . . . . . . . . . . . . . . . . . . . . 6

MAM.1: Under certain conditions in MAM Mode 2

code execution out of internal Flash can fail . . 6

WDT.1: Accessing non-Watchdog APB registers

during the feed sequence causes a reset. . . . . 7

ADC.1: External sync inputs not operational . . 8

3.4

3.5

3.6

4.1

AC/DC deviations detail . . . . . . . . . . . . . . . . . . 9

ESD.1: The device does not meet the 2 kV ESD

requirements on the RTCX1 pin . . . . . . . . . . . . 9

5.1

5.2

Errata notes detail . . . . . . . . . . . . . . . . . . . . . . . 9

Note.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Note.2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Legal information. . . . . . . . . . . . . . . . . . . . . . . 10

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 10

6.1

6.2

6.3

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 1 May 2012

Document identifier: ES_LPC2136_01

LPC2136FBD64/01 [NXP]

相关型号：

LPC2136FBD64/01,15

LPC2136FBD64/01EL

LPC2138

LPC2138-01

LPC2138/01

LPC2138FBD64

LPC2138FBD64,151

LPC2138FBD64/01

LPC2138FBD64/01EL

LPC2138FHN64

LPC2138FHN64,557

LPC2138FHN64/01