LD6935L/1828P [NXP]
IC VREG FIXED POSITIVE LDO REGULATOR, Fixed Positive Multiple Output LDO Regulator;
| 型号： | LD6935L/1828P |
| 厂家： | 
NXP |
| 描述： | IC VREG FIXED POSITIVE LDO REGULATOR, Fixed Positive Multiple Output LDO Regulator 输出元件 调节器 |
| 文件： | 总24页 (文件大小：736K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LD6935 series
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Dual low-dropout regulators, high PSRR, 300 mA
Rev. 1 — 29 May 2013
Preliminary data sheet
1. Product profile
1.1 General description
The LD6935 series consists of small-size dual Low DropOut regulators (LDO). Each
device delivers two times 300 mA with a typical voltage drop of 240 mV at 300 mA for
each LDO. Each device offers two individual fixed nominal output voltages (VO(nom)) from
1.2 V to 3.6 V.
The LDO has an integrated Soft start to control the inrush current during start-up. The
output states when disabled can be high-ohmic 3-state or auto discharge. Optionally a
delayed output circuit is available for the second output. The devices are available in
DFN1612-8 (SOT1225) plastic package with a height of 0.4 mm.
1.2 Features and benefits
Extremely low standby current in shutdown mode ( 0.1 A)
Low quiescent current
Low output noise
Fast turn-on time
High Power Supply Rejection Ratio (PSRR)
Auto discharge or high-ohmic mode for output states when disabled
Delayed output circuit for second LDO (optional)
DFN1612-8 (SOT1225) leadless package 1.6 1.2 0.4 mm
Pb-free, Restriction of Hazardous Substances (RoHS) compliant, free of halogen and
antimony (Dark Green compliant)
1.3 Applications
Smartphones
Tablet PCs
Mobile handsets
Digital still cameras
Mobile internet devices
Portable media players
1.4 Quick reference data
IO = 300 mA for each LDO
PSRR = 80 dB at 1 kHz
VI = 1.75 V to 5.5 V
VO = 1.2 V to 3.6 V (fixed value)
RMS noise Vn(o)RMS = 60 V
Dropout voltage Vdo = 240 mV
at 10 Hz to 100 kHz
at IO = 300 mA for each LDO
tstartup(reg) = 150 s
Quiescent current Iq = 2 35 A at
IO = 0 mA
LD6935 series
NXP Semiconductors
Dual low-dropout regulators, high PSRR, 300 mA
2. Pinning information
2.1 Pinning
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Fig 1. Pin configuration for DFN1612-8 (SOT1225)
2.2 Pin description
Table 1.
Pin description for DFN1612-8 (SOT1225)
Symbol
GND
OUT1
OUT2
GND
EN2
Pin
1
Description
supply ground
2
regulator 1 output voltage
regulator 2 output voltage
supply ground
3
4
5
regulator 2 enable input
regulator 2 supply voltage input
regulator 1 supply voltage input
regulator 1 enable input
internal connected [1]
IN2
6
IN1
7
EN1
8
i.c.
TAB
[1] The TAB is GND level (it is placed on the reverse side of the IC).
It is recommended to connect the TAB to GND. Leaving it unconnected is also allowed but it may result in
lower thermal performance.
3. Ordering information
Table 2.
Ordering information
Type number
Package
Name
Description
Version
LD6935L
DFN1612-8 plastic extremely thin small outline package; no leads; SOT1225
8 terminals; body 1.6 1.2 0.4 mm
LD6935_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Preliminary data sheet
Rev. 1 — 29 May 2013
2 of 24
LD6935 series
NXP Semiconductors
Dual low-dropout regulators, high PSRR, 300 mA
3.1 Ordering options
Further output voltage information available on request; see Section 19 “Contact
information”.
Table 3.
Type number and nominal output voltage of high-ohmic output
Type number
Nominal output voltage VO(nom)
OUT1
2.8 V
3.3 V
OUT2
2.8 V
1.8 V
LD6935L/2828H
LD6935L/3318H
Table 4.
Type number and nominal output voltage of pull-down output
Type number
Nominal output voltage VO(nom)
OUT1
1.8 V
2.8 V
3.3 V
3.3 V
3.3 V
OUT2
2.8 V
2.8 V
1.8 V
2.8 V
3.3 V
LD6935L/1828P
LD6935L/2828P
LD6935L/3318P
LD6935L/3328P
LD6935L/3333P
Table 5.
Type number and nominal output voltage of pull-down output with delay circuit
Type number
Nominal output voltage VO(nom)
OUT1
OUT2
LD6935L/3118PD
3.1 V
1.8 V
LD6935_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Preliminary data sheet
Rev. 1 — 29 May 2013
3 of 24
LD6935 series
NXP Semiconductors
Dual low-dropout regulators, high PSRR, 300 mA
4. Block diagram
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Fig 2. Block diagram dual LDO with auto discharge function (-P and -PD versions)
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Fig 3. Block diagram dual LDO with high-ohmic output (-H version)
LD6935_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Preliminary data sheet
Rev. 1 — 29 May 2013
4 of 24
LD6935 series
NXP Semiconductors
Dual low-dropout regulators, high PSRR, 300 mA
5. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Max
Unit
Pin IN1, IN2, EN1 and EN2
VI
input voltage
4 ms transient
4 ms transient
0.5
0.5
+6.0
+6.0
V
V
VEN
voltage on pin EN
Pin OUT1 and OUT2
VO
output voltage
4 ms transient
0.5
-
+6.0
740
V
[1]
Ptot
Tstg
Tj
total power dissipation
storage temperature
junction temperature
ambient temperature
mW
C
C
C
kV
V
55
40
40
-
+150
+125
+85
Tamb
VESD
[2]
[3]
electrostatic discharge
voltage
human body model
machine model
2
-
200
[1] The (absolute) maximum power dissipation depends on the junction temperature Tj. Higher power
dissipation is allowed with lower ambient temperatures. The conditions to determine the specified values
are Tamb = 25 C and the use of a two-layer Printed-Circuit Board (PCB).
[2] According to JESD22-A114F.
[3] According to JESD22-A115C.
6. Recommended operating conditions
Table 7.
Operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol
Tamb
Tj
Parameter
Conditions
Min
40
-
Max
+85
Unit
°C
ambient temperature
junction temperature
+125
°C
Pin IN1 and IN2
VI
input voltage
external capacitance on pin IN
1.75
1.0
5.5
-
V
[1]
Cext(IN)
F
Pin EN1 and EN2
VEN
voltage on pin EN
0
VI
V
Pin OUT1 and OUT2
VO
output voltage
external load capacitance
0
VI + 0.3
-
V
CL(ext)
1.0
F
[1] See Section 10.1 “Input and output capacitor values”.
LD6935_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Preliminary data sheet
Rev. 1 — 29 May 2013
5 of 24
LD6935 series
NXP Semiconductors
Dual low-dropout regulators, high PSRR, 300 mA
7. Thermal characteristics
Table 8.
Thermal characteristics
Symbol Parameter
Conditions
Typ
Unit
[1][2]
Rth(j-a)
thermal resistance from junction to ambient
135
K/W
[1] The overall Rth(j-a) can vary depending on the board layout. To minimize the effective Rth(j-a), all pins must
have a solid connection to larger Cu layer areas for example to the power and ground layer. In multilayer
PCB applications, use the second layer to create a large heat spreader area directly below the LDO. If this
layer is either ground or power, connect it with several vias to the top layer connecting to the device ground
or supply. Avoid using solder-stop varnish under the chip.
[2] Use the measurement data given for a rough estimation of the Rth(j-a) in your application. The actual Rth(j-a)
value can vary in applications using different layer stacks and layouts.
8. Characteristics
Table 9.
Electrical characteristics
At recommended input voltages and Tamb = 40 C to +85 C; voltages are referenced to GND (ground = 0 V);
unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max Unit
Output voltage per LDO
[2]
[2]
Vdo
dropout voltage
output voltage variation
IO = 300 mA; VI VO(nom)
VO 1.8 V; IO = 1 mA
Tamb = +25 C
-
240
-
mV
VO
-2
-3
-
-
+2
+3
%
%
30 C Tamb +85 C
VO < 1.8 V; IO = 1 mA
Tamb = +25 C
3
4
-
-
+3
+4
%
%
[2]
[2]
30 C Tamb +85 C
Line regulation error per LDO
VO/(VOxVI) relative output voltage
VI = (VO(nom) + 1 V) to 5 V;
IO = 1 mA
0.1
-
+0.1 %/V
variation with input voltage
Load regulation error per LDO
[2]
VO/(VOxIO) relative output voltage
1 mA IOUT 300 mA;
-0.01 0.0025 0.01 %/mA
variation with output current
VI = (VO(nom) + 1 V)
Output current per LDO
[2]
[2]
[2]
IO
output current
300
-
-
-
-
mA
mA
mA
Iact(fold)
Isc
foldback activation current
short-circuit current
-
-
750
100
VO = 0 V
Regulator input current per LDO
[2]
[2]
Iinrush(lim)
Iq
inrush current limit
quiescent current
CL(ext) = 1 F at OUT1 and OUT2
-
-
-
400
50
mA
(VEN1 or VEN2) > 1.1 V; IO = 0 mA at
OUT1 and OUT2;
VI = (VO(nom) + 1 V)
35
A
(VEN1 or VEN2) > 1.1 V;
1 mA IO 300 mA at OUT1 and
OUT2; VI = (VO(nom) + 1 V)
-
-
400
0.1
-
A
A
(VEN1 or VEN2) 0.4 V
1.0
LD6935_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Preliminary data sheet
Rev. 1 — 29 May 2013
6 of 24
LD6935 series
NXP Semiconductors
Dual low-dropout regulators, high PSRR, 300 mA
Table 9.
Electrical characteristics …continued
At recommended input voltages and Tamb = 40 C to +85 C; voltages are referenced to GND (ground = 0 V);
unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max Unit
Ripple rejection and output noise per LDO
[2]
[2]
PSRR
power supply rejection ratio
RMS output noise voltage
VI = VO(nom) + 1 V; IO = 30 mA;
-
-
80
60
-
-
dB
f
ripple = 1 kHz
Vn(o)(RMS)
bandwidth = 10 Hz to 100 kHz;
V
CL(ext) = 1 F; VO = 1.8 V
Enable input and timing (pin EN1, pin EN2) per LDO
VIL
LOW-level input voltage
HIGH-level input voltage
enable current
0
-
0.4
5.5
-
V
VIH
1.1
-
V
Ien
-
-
400
150
nA
s
[2]
[2]
tstartup(reg)
regulator start-up time
for each LDO; VI = 5.5 V;
VO = 0.95 VO(nom); IO = 300 mA;
-
CL(ext) = 1 F
td
delay time
for LDO2; -PD version
-
100
-
s
Automatic discharge function (LD6935L/xxxxP or LD6935L/xxxxPD) per LDO
[2]
[2]
Rpd
pull-down resistance
-
-
100
300
-
-
tsd(reg)
regulator shutdown time
VI = 5.5 V; CL(ext) = 1 F; IO = 0 A;
VO = 0.1 VO(nom)
s
Thermal protection
[2]
Tsd
shutdown temperature
-
-
160
20
-
-
C
K
[1][2]
Tsd(hys)
shutdown temperature
hysteresis
[1] The junction temperature must decrease by Tsd(hys) to enable the device after Tsd was reached and the device was disabled.
[2] The parameter was verified and is guaranteed by design.
LD6935_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Preliminary data sheet
Rev. 1 — 29 May 2013
7 of 24
LD6935 series
NXP Semiconductors
Dual low-dropout regulators, high PSRR, 300 mA
9. Dynamic behavior
All results described in Section 9 are based on measurements of types LD6935L/xxxxH
from the LD6935 product series.
9.1 Dropout
The dropout voltage is defined as the smallest input-to-output voltage difference at a
specified load current when the regulator operates within its linear region with the pass
transistor functioning simply as a resistor. This means that the input voltage is below the
nominal output voltage value.
A small dropout voltage guarantees lower power consumption and maximizes efficiency.
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VI = 3.2 V; VO(nom) = 3.3 V; CL(ext) = 1 F; Cext(IN) = 1 F
Fig 4. Dropout voltage as a function of output
current for LD6935L/3318x
Fig 5. Dropout voltage as a function of output
current for LD6935L/3318x
LD6935_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Preliminary data sheet
Rev. 1 — 29 May 2013
8 of 24
LD6935 series
NXP Semiconductors
Dual low-dropout regulators, high PSRR, 300 mA
9.2 Working voltage tolerance
The guaranteed output voltages are specified in Table 9.
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VI = 4.5 V; VO(nom) = 1.8 V; CL(ext) = 1 F; Cext(IN) = 1 F
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Fig 6. Working voltage tolerance for LD6935L/3318x
Fig 7. Working voltage tolerance for LD6935L/3318x
9.3 Noise
Output noise voltage of an LDO circuit is given as noise density or RMS output noise
voltage over a defined range of frequencies (10 Hz to 100 kHz). Permanent conditions are
a constant output current and a ripple-free input voltage. The output noise voltage is
generated by the LDO regulator.
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VI = 4.5 V; VO(nom) = 1.8 V; CL(ext) = 1 F; Cext(IN) = 1 F
VI = 4.5 V; VO(nom) = 3.3 V; CL(ext) = 1 F; Cext(IN) = 1 F
Fig 8. Noise density for LD6935L/3318x
Fig 9. Noise density for LD6935L/3318x
LD6935_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Preliminary data sheet
Rev. 1 — 29 May 2013
9 of 24
LD6935 series
NXP Semiconductors
Dual low-dropout regulators, high PSRR, 300 mA
9.4 Quiescent current
Quiescent or ground current is the difference between the input and the output current of
the regulator.
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VI = 4.5 V; VO(nom) = 1.8 V; CL(ext) = 1 F; Cext(IN) = 1 F
VI = 4.5 V; VO(nom) = 3.3 V; CL(ext) = 1 F; Cext(IN) = 1 F
Fig 10. Quiescent current for LD6935L/3318x
Fig 11. Quiescent current for LD6935L/3318x
LD6935_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Preliminary data sheet
Rev. 1 — 29 May 2013
10 of 24
LD6935 series
NXP Semiconductors
Dual low-dropout regulators, high PSRR, 300 mA
9.5 Line regulation
Line regulation response is the capability of the circuit to maintain the nominal output
voltage while varying the input voltage.
VO
---------- --------
100
VI VO
Line regulation % V =
(1)
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VO(nom) = 1.8 V; IO = 300 mA; tr = tf = 2 s;
L(ext) = 1 F; Cext(IN) = 1 F
VO(nom) = 3.3 V; IO = 300 mA; tr = tf = 2 s;
L(ext) = 1 F; Cext(IN) = 1 F
C
C
Fig 12. Line regulation for LD6935L/3318x
Fig 13. Line regulation for LD6935L/3318x
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VO(nom) = 1.8 V; IO = 1 mA; tr = tf = 2 s; CL(ext) = 1 F;
Cext(IN) = 1 F
V
O(nom) = 3.3 V; IO = 1 mA; tr = tf = 2 s; CL(ext) = 1 F;
Cext(IN) = 1 F
Fig 14. Line regulation for LD6935L/3318x
Fig 15. Line regulation for LD6935L/3318x
LD6935_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Preliminary data sheet
Rev. 1 — 29 May 2013
11 of 24
LD6935 series
NXP Semiconductors
Dual low-dropout regulators, high PSRR, 300 mA
9.6 Load regulation
Load regulation is the capability of the circuit to maintain the nominal output voltage while
varying the output load current.
VO
------------------
100
VOnom
----------------------------------
Load regulation % mA =
IO
(2)
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VO(nom) = 1.8 V; IO = 50 mA to 100 mA; tr = tf = 2 s;
L(ext) = 1 F; Cext(IN) = 1 F
VO(nom) = 3.3 V; IO = 50 mA to 100 mA; tr = tf = 2 s;
CL(ext) = 1 F; Cext(IN) = 1 F
C
Fig 16. Load regulation for LD6935L/3318x
Fig 17. Load regulation for LD6935L/3318x
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VO(nom) = 1.8 V; IO = 0 mA to 300 mA; tr = tf = 2 s;
CL(ext) = 1 F; Cext(IN) = 1 F
V
O(nom) = 3.3 V; IO = 50 mA to 300 mA; tr = tf = 2 s;
CL(ext) = 1 F; Cext(IN) = 1 F
Fig 18. Load regulation for LD6935L/3318x
Fig 19. Load regulation for LD6935L/3318x
LD6935_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Preliminary data sheet
Rev. 1 — 29 May 2013
12 of 24
LD6935 series
NXP Semiconductors
Dual low-dropout regulators, high PSRR, 300 mA
9.7 Start-up, inrush current
Start-up time defines the time needed for the LDO to achieve 95 % of its typical output
voltage level after activation via the enable pin.
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Fig 20. Start-up and inrush current for LD6935L/3318x
9.8 Power Supply Rejection Ratio (PSRR)
PSRR stands for the capability of the regulator to suppress unwanted signals on the input
voltage like noise or ripples.
VOripple
VIripple
PSRR dB = –20log
for all frequencies.
-----------------------
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VO(nom) = 1.8 V; CL(ext) = 1 F; Cext(IN) = 1 F
VO(nom) = 3.3 V; CL(ext) = 1 F; Cext(IN) = 1 F
Fig 21. PSRR for LD6935L/3318x
Fig 22. PSRR for LD6935L/3318x
LD6935_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Preliminary data sheet
Rev. 1 — 29 May 2013
13 of 24
LD6935 series
NXP Semiconductors
Dual low-dropout regulators, high PSRR, 300 mA
10. Application information
10.1 Input and output capacitor values
The devices require external capacitors at the output to guarantee a stable regulator
behavior. Also an input capacitor is recommended to keep the input voltage stable. These
capacitors should not under-run the specified minimum Equivalent Series
Resistance (ESR).
The absolute value of the total capacitance attached to the output pins OUT1 and OUT2
influences the shutdown time (tsd(reg)) of the devices.
Table 10. External load capacitor
Symbol Parameter
Conditions
Min
0.7
0.7
5
Typ
1.0
1.0
-
Max Unit
Cext(IN)
CL(ext)
ESR
external capacitance on pin IN
pin IN1 and IN2
-
F
[1]
external load capacitance
equivalent series resistance
-
F
500
m
[1] The minimum value of capacitance for stability and correct operation is 0.7 F. The capacitor tolerance
should be 30 % or better over the temperature range. The full range of operating conditions for the
capacitor in the application should be considered during device selection to ensure that this minimum
capacitance specification is met. The recommended capacitor type is X7R to meet the full device
temperature specification of 40 C to +125 C.
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Fig 23. Application diagram
10.2 Optional delay circuit
The two enable input pins EN1 and EN2 allow a control of both LDOs. In case the
availability of General-Purpose Input/Output (GPIO) pins is limited, the optional delay
circuit of -D version can be used to control both LDOs at once without the drawback of
doubled inrush current. When both enable signals EN1 and EN2 are activated
simultaneously, the delay circuit delays the activation of LDO2 and postpones the
associated inrush current. The LDO2 is only active when LDO1 is set to HIGH.
LD6935_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Preliminary data sheet
Rev. 1 — 29 May 2013
14 of 24
LD6935 series
NXP Semiconductors
Dual low-dropout regulators, high PSRR, 300 mA
Table 11. Truth table output mode with delay circuit
EN1
EN2
LDO1 output
LDO2 output
OFF
LOW
HIGH
LOW
HIGH
LOW
LOW
HIGH
HIGH
OFF
ON
OFF
OFF
ON
OFF
ON
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Fig 26. Timing diagram for delay circuit of -PD version
LD6935_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Preliminary data sheet
Rev. 1 — 29 May 2013
15 of 24
LD6935 series
NXP Semiconductors
Dual low-dropout regulators, high PSRR, 300 mA
11. Test information
11.1 Quality information
This product has been qualified in accordance with NX1-00023 NXP Semiconductors
Quality and Reliability Specification and is suitable for use in consumer applications.
12. Marking
INDICATOR
(READING EXAMPLE: -oo)
(“o” = blank)
MARKING CODE
(EXAMPLE)
YEAR CODE
MONTHLY
DATE CODE
PIN 1 INDICATION
VENDOR CODE
aaa-007572
Fig 27. Marking DFN1612-8 (SOT1225)
Table 12. Marking code and indicator of high-ohmic output
Type number
VO(nom)
Marking code
Indicator
oo-
LD6935L/2828H
LD6935L/3318H
2.8 V / 2.8 V
3.3 V / 1.8 V
AK
AE
oo-
Table 13. Marking code and indicator of pull-down output
Type number
VO(nom)
Marking code
Indicator
-oo
LD6935L/1818P
LD6935L/2828P
LD6935L/3318P
LD6935L/3328P
LD6935L/3333P
1.8 V / 1.8 V
2.8 V / 2.8 V
3.3 V / 1.8 V
3.3 V / 2.8 V
3.3 V / 3.3 V
AR
AK
AE
AC
AA
-oo
-oo
-oo
-oo
Table 14. Marking code and indicator of pull-down output with delay circuit
Type number
VO(nom)
Marking code
Indicator
LD6935L/3118PD
3.1 V / 1.8 V
AU
o-o
LD6935_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Preliminary data sheet
Rev. 1 — 29 May 2013
16 of 24
LD6935 series
NXP Semiconductors
Dual low-dropout regulators, high PSRR, 300 mA
13. Package outline
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Fig 28. Package outline DFN1612-8 (SOT1225)
LD6935_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Preliminary data sheet
Rev. 1 — 29 May 2013
17 of 24
LD6935 series
NXP Semiconductors
Dual low-dropout regulators, high PSRR, 300 mA
14. Packing information
14.1 Packing methods
Table 15. Packing methods
Type
number
Package Description
Orientation 12NC
Packing
quantity
[1]
ending
LD6935L
SOT1225 4 mm pitch,
5.4 mm tape and reel
Q1
115
<tbd>
[1] For further information about orientation, see Section 14.2.
14.2 Carrier tape information
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Fig 29. Carrier tape
Table 16. Orientations
Orientation
Meaning
Pin 1 location
upper left
Q1
Q2
Q3
Q4
quadrant 1
quadrant 2
quadrant 3
quadrant 4
upper right
lower left
lower right
LD6935_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Preliminary data sheet
Rev. 1 — 29 May 2013
18 of 24
LD6935 series
NXP Semiconductors
Dual low-dropout regulators, high PSRR, 300 mA
15. Soldering
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Fig 30. Soldering footprint DFN1612-8 (SOT1225)
LD6935_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Preliminary data sheet
Rev. 1 — 29 May 2013
19 of 24
LD6935 series
NXP Semiconductors
Dual low-dropout regulators, high PSRR, 300 mA
16. PCB assembly guidelines for Pb-free soldering
Table 17. Assembly recommendations
Parameter
Value or specification
Solder screen thickness
Solder paste: Pb-free
Solder to flux ratio
Solder reflow profile
100 m (0.004 inch)
SnAg (3 % to 4 %); Cu (0.5 % to 0.9 %)
50 : 50
see Figure 31
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
The device can withstand at least three reflows at this profile.
Fig 31. Pb-free solder reflow profile
Table 18. Characteristics
Symbol
Parameter
Conditions
Min Typ Max Unit
Treflow(peak)
peak reflow temperature
230
60
-
-
-
-
-
-
-
-
-
260 C
t1
time 1
time 2
time 3
time 4
time 5
soak time
180
30
s
t2
time during T 250 C
time during T 230 C
time during T > 217 C
s
t3
10
30
-
50
s
t4
150
540
6
s
t5
s
dT/dt
rate of change of
temperature
cooling rate
preheat
-
C/s
C/s
2.5
4.0
LD6935_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Preliminary data sheet
Rev. 1 — 29 May 2013
20 of 24
LD6935 series
NXP Semiconductors
Dual low-dropout regulators, high PSRR, 300 mA
17. Revision history
Table 19. Revision history
Document ID
Release date
20130529
Data sheet status
Change notice
Supersedes
LD6935_SER v.1
Preliminary data sheet
-
-
LD6935_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Preliminary data sheet
Rev. 1 — 29 May 2013
21 of 24
LD6935 series
NXP Semiconductors
Dual low-dropout regulators, high PSRR, 300 mA
18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
18.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
18.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
LD6935_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Preliminary data sheet
Rev. 1 — 29 May 2013
22 of 24
LD6935 series
NXP Semiconductors
Dual low-dropout regulators, high PSRR, 300 mA
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
LD6935_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Preliminary data sheet
Rev. 1 — 29 May 2013
23 of 24
LD6935 series
NXP Semiconductors
Dual low-dropout regulators, high PSRR, 300 mA
20. Contents
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
20
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.1
1.2
1.3
1.4
General description . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits. . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . 1
2
2.1
2.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2
3
3.1
4
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 5
Thermal characteristics . . . . . . . . . . . . . . . . . . 6
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 6
5
6
7
8
9
Dynamic behavior . . . . . . . . . . . . . . . . . . . . . . . 8
Dropout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Working voltage tolerance . . . . . . . . . . . . . . . . 9
Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Quiescent current . . . . . . . . . . . . . . . . . . . . . . 10
Line regulation . . . . . . . . . . . . . . . . . . . . . . . . 11
Load regulation. . . . . . . . . . . . . . . . . . . . . . . . 12
Start-up, inrush current . . . . . . . . . . . . . . . . . . 13
Power Supply Rejection Ratio (PSRR). . . . . . 13
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
10
10.1
10.2
Application information. . . . . . . . . . . . . . . . . . 14
Input and output capacitor values. . . . . . . . . . 14
Optional delay circuit . . . . . . . . . . . . . . . . . . . 14
11
11.1
12
Test information. . . . . . . . . . . . . . . . . . . . . . . . 16
Quality information . . . . . . . . . . . . . . . . . . . . . 16
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17
13
14
14.1
14.2
Packing information . . . . . . . . . . . . . . . . . . . . 18
Packing methods . . . . . . . . . . . . . . . . . . . . . . 18
Carrier tape information . . . . . . . . . . . . . . . . . 18
15
16
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PCB assembly guidelines for Pb-free
soldering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
17
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 21
18
Legal information. . . . . . . . . . . . . . . . . . . . . . . 22
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 23
18.1
18.2
18.3
18.4
19
Contact information. . . . . . . . . . . . . . . . . . . . . 23
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 29 May 2013
Document identifier: LD6935_SER
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