JN5189 [NXP]
IEEE 802.15.4 low power wireless MCU;
| 型号： | JN5189 |
| 厂家： | 
NXP |
| 描述： | IEEE 802.15.4 low power wireless MCU |
| 文件： | 总92页 (文件大小：2595K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
JN5189
IEEE 802.15.4 low power wireless MCU
JN5189
Rev. 1.2 — June 2020
product data sheet
1. General description
The JN5189 and JN5189T (called JN5189 throughout this document) are ultra-low power,
high performance Arm® Cortex®-M4 based wireless microcontrollers supporting
Zigbee 3.0 and Thread networking stacks to facilitate the development of Home
Automation, Smart Lighting and wireless sensor network applications.
The JN5189 includes a 2.4 GHz IEEE 802.15.4 compliant transceiver and a
comprehensive mix of analog and digital peripherals. Ultra-low current consumption in
both radio receive and transmit modes and also in the power down modes allow use of
coin cell batteries.
The product has 640 KB embedded Flash and 152 KB RAM memory. The embedded
flash can support Over The Air (OTA) code download to applications. The devices include
10-channel PWM, two timers, one RTC/alarm timer, a Windowed Watchdog Timer
(WWDT), two USARTs, two SPI interfaces, two I2C interfaces, a DMIC subsystem with
dual-channel PDM microphone interface with voice activity detector, one 12-bit ADC,
temperature sensor and comparator.
The JN5189T variant has an internal NFC tag and with connections to the external NFC
antenna.
The JN5188 variant has the same functionality as the JN5189 except for reduced memory
sizes of 320 KB embedded Flash, 88 KB RAM. The JN5188T variant has the functionality
of the JN5188 with the addition of an embedded NFC tag.
The Arm Cortex-M4 is a 32-bit core that offers system enhancements such as low power
consumption, enhanced debug features, and a high level support of the block integration.
The Arm Cortex-M4 CPU, operates at up to 48 MHz.
2. Features and benefits
2.1 Benefits
Very low current solution for long battery life
Single chip device to run stack and application
System BOM is low in component count and cost
Flexible sensor interfacing
Embedded NTAG on JN5189T and JN5188T devices
Package
6 6 mm HVQFN40, 0.5 mm pitch
Lead-free and RoHS compliant
Junction temperature range: 40 C to +125 C
NXP Semiconductors
IEEE 802.15.4 low power wireless MCU
JN5189(T)/JN5188(T)
2.2 Radio features
2.4 GHz IEEE 802.15.4 2011 compliant
Receiver current 4.3 mA
IEEE 802.15.4 Receiver sensitivity 100 dBm
Improved co-existence with WiFi
Configurable transmit power up to +11 dBm, with 46 dB range
Transmit power / current +10 dBm / 20.28 mA
Transmit power / current +3 dBm / 9.44 mA
Transmit power / current 0 dBm / 7.36 mA
1.9 V to 3.6 V supply voltage
Antenna Diversity control
32 MHz XTAL cell with internal capacitors, able with suitable external XTAL to meet
the required accuracy for radio operation over the operating conditions
Integrated RF balun
Integrated ultra Low-power sleep oscillator
Deep Power-down current 350 nA (with wake-up from IO)
128-bit, 192-bit or 256-bit AES security processor
MAC accelerator with packet formatting, CRCs, address check, auto-acks, timers
2.3 Microcontroller features
Application CPU, Arm Cortex-M4 CPU:
Arm Cortex-M4 processor, running at a frequency of up to 48 MHz.
Arm built-in Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit (MPU)
Non-maskable Interrupt (NMI) with a selection of sources
Serial Wire Debug (SWD) with 8 breakpoints and 4 watchpoints
System tick timer
Includes Serial Wire Output for enhanced debug capabilities.
On-Chip memory
640 KB flash (320 KB for JN5188)
152 KB SRAM (88 KB for JN5188)
12 MHz to 48 MHz system clock speed for low-power
2 x I2C-bus interface, operate as either master or slave
10 x PWM
2 x Low-power timers
2 x USART, one with flow control
2 x SPI-bus, master or slave
1 x PDM digital audio interface with a hardware based voice activity detector to reduce
power consumption in voice applications. Support for dual-channel microphone
interface, flexible decimators, 16 entry FIFOs and optional DC blocking.
19-channel DMA engine for efficient data transfer between peripherals and SRAM, or
SRAM to SRAM. DMA can operate with fixed or incrementing addresses. Operations
can be chained together to provide complex functionality with low CPU overhead.
JN5189
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 1.2 — June 2020
2 of 92
NXP Semiconductors
IEEE 802.15.4 low power wireless MCU
JN5189(T)/JN5188(T)
Up to four GPIOs can be selected as pin interrupts (PINT), triggered by rising, falling or
both input edges.
Two GPIO grouped interrupts (GINT) enable an interrupt based on a logical (AND/OR)
combination of input states.
32-bit Real Time clock (RTC) with 1 s resolution. A timer in the RTC can be used to
wake from Sleep, Deep-sleep and Power-down, with 1 ms resolution
Voltage Brown Out with 8 programmable thresholds
8-input 12-bit ADC, 190 kS/sec. HW support for continuous operation or single
conversions, single or multiple inputs can be sampled within a sequence. DMA
operation can be linked to achieve low overhead operation.
1 x analog comparator
Battery and temperature sensors
Watchdog timer and POR
Standby power controller
Up to 22 Digital IOs (DIO)
1 x Quad SPIFI for accessing an external flash device
Integrated NTAG I2C plus device, NFC Forum Type 2, on JN5189T and JN5188T only
Random Number Generator engine
AES engine AES-128 to 256
Hash hardware accelerator supporting SHA-1 and SHA-256
EFuse:
128-bit random AES key
Configuration modes
Trimming
ISO7816 smart card digital interface which with a suitable external analogue device
can operate as a smart card reader
2.4 Low power features
Sleep mode supported, the CPU in low power state waiting for interrupt
Deep-sleep mode supported, the CPU in low power state waiting for interrupt, but
extra functionality disabled or in low power state compared to sleep mode
Power Down mode, main functionality powered down, wakeup possible from IOs,
wakeup possible from some peripherals (I2C, USART, SPI) in a limited function mode
and low power timers
Deep -power down, very low power state with option of wake-up triggered by IOs, 350
nA
41-bit and 28-bit Low power timers can run in power down mode, clocked by 32 kHz
FRO or 32 kHz XTAL. Timers can run for over one year or 2 days
3. Applications
Zigbee 3.0, Thread networks
Robust and secure Low-power wireless applications
Smart lighting, thermostats and home automation
Home security and access
Wireless sensor networks
JN5189
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 1.2 — June 2020
3 of 92
NXP Semiconductors
IEEE 802.15.4 low power wireless MCU
JN5189(T)/JN5188(T)
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
JN5189HN
JN5189THN
JN5188HN
JN5188THN
HVQFN40
Plastic thermal enhanced very thin quad
flat package; no leads; 40 terminals; body
6 6 0.85 mm
SOT618-1
Table 2.
Ordering information details
Type number Flash size
SRAM size
NTAG
no
JN5189HN
JN5189THN
JN5188HN
JN5188THN
640 KB
152 KB
yes
no
320 KB
88 KB
yes
5. Marking
Table 3.
Marking codes
Type number
Marking code
JN5189
JN5189T
JN5188
JN5189HN
JN5189THN
JN5188HN
JN5188THN
JN5188T
JN5189
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 1.2 — June 2020
4 of 92
NXP Semiconductors
IEEE 802.15.4 low power wireless MCU
JN5189(T)/JN5188(T)
6. Block diagram
Core
System
Memories
Digital peripherals
Cortex-M4
48 MHz
Flash
640/320 KB
Watchdog timer
2
2 × I C
SRAM
Serial wire debug
POR
2 × SPI
2 × USART
10 × PWM
152/88 KB
Brown-out
detectors
RF transceiver
Analog peripherals
IEEE 802.15.4
2011
12-bit ADC
8 channels
DMA
Fast antenna
diversity
NFC Tag
JN5189T/JN5188T Only)
Power
management
controller
1 × DMIC
(
1 × Analog
comparator
1 × QSPI
Battery sensor
Clocks
DC/DC converter
Up to 22 × GPIO
1 × IR modulator
1 × ISO7816
Temperature
sensor
32 MHz XTAL
oscillator
Timers
Security
HASH
32.768 kHz XTAL
oscillator
2 × Counter/timer
Low frequency free
running oscillator
AES 128/256
Real time clock
High frequency free
running oscillator
Random number
generator
2 x Wakeup timers
Fig 1. High level hardware block diagram
JN5189
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 1.2 — June 2020
5 of 92
NXP Semiconductors
IEEE 802.15.4 low power wireless MCU
JN5189(T)/JN5188(T)
7. Pinning information
7.1 HVQFN40 - with NTAG
7.1.1 Pinning
terminal 1
index area
XTAL_P
XTAL_N
1
2
30
29
28
27
26
25
24
23
22
21
V
SS(DCDC)
LX
V
3
BAT
PIO0
PIO1
4
RSTN
PIO2
PIO3
5
TRST
JN5188THN; JN5189THN
6
PIO21/ACM
PIO20/ACP
PIO19/ADC5
PIO18/ADC4
PIO17/ADC3
PIO4
7
PIO5/ISP_ENTRY
PIO6
8
9
PIO7
10
aaa-023712
Transparent top view
(1) JN5188THN and JN5189THN HVQFN40 with NTAG
Fig 2. Pin configuration
7.1.2 Pin description
Table 4.
Symbol
XTAL_P
XTAL_N
PIO0
Pin descriptions
Pin
1
Type Default at reset Description
System crystal oscillator 32 MHz
System crystal oscillator 32 MHz
2
3
IO
GPIO0[1]
GPIO0 — General Purpose digital Input/Output 0
USART0_SCK — Universal Synchronous/Asynchronous
Receiver/Transmitter 0 - synchronous clock
USART1_TXD — Universal Synchronous/Asynchronous
Receiver/Transmitter 1 - transmit data output
PWM0 — Pulse Width Modulator output 0
SPI1_SCK — Serial Peripheral Interface-bus 1 clock input/output
PDM0_DATA — Pulse Density Modulation Data input from digital
microphone (channel 0)
JN5189
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© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 1.2 — June 2020
6 of 92
NXP Semiconductors
IEEE 802.15.4 low power wireless MCU
JN5189(T)/JN5188(T)
Table 4.
Symbol
PIO1
Pin descriptions
Pin
Type Default at reset Description
4
IO
GPIO1[1]
GPIO1 — General Purpose digital Input/Output 1
USART1_RXD — Universal Synchronous/Asynchronous
Receiver/Transmitter 1 - receive data input
PWM1 — Pulse Width Modulator output 1
SPI1_MISO — Serial Peripheral Interface-bus 1 master data input
PDM0_CLK — Pulse Density Modulation Clock output to digital
microphone (channel 0)
PIO2
5
IO
GPIO2[1]
GPIO2 — General Purpose digital Input/Output 2
SPI0_SCK — Serial Peripheral Interface-bus 0 clock input/output
PWM2 — Pulse Width Modulator output 2
SPI1_MOSI — Serial Peripheral Interface-bus 1 master output slave
input
USART0_RXD — Universal Synchronous/Asynchronous
Receiver/Transmitter 0 - receive data input
ISO7816_RST — RST signal, output, for ISO7816 interface
MCLK — External clock, can be provided to DMIC IP
GPIO3 — General Purpose digital Input/Output 3
PIO3
6
IO
GPIO3[1]
SPI0_MISO — Serial Peripheral Interface-bus 0 master input
PWM3 — Pulse Width Modulator output 3
SPI1_SSELN0 — Serial Peripheral Interface-bus 1 slave select not 0
USART0_TXD — Universal Synchronous/Asynchronous
Receiver/Transmitter 0 - transmit data output
ISO7816_CLK — Clock output for ISO7816 interface
GPIO4 — General Purpose digital Input/Output 4
PIO4
7
IO
GPIO4[1][2]
SPI0_MOSI — Serial Peripheral Interface-bus 0 master output slave
input
PWM4 — Pulse Width Modulator output 4
SPI1_SSELN1 — Serial Peripheral Interface-bus 1 slave select not 1
USART0_CTS — Universal Synchronous/Asynchronous
Receiver/Transmitter 0 - Clear To Send input
ISO7816_IO — IO of ISO7816 interface
RFTX — Radio Transmit Control Output
ISP_SEL — In-System Programming Mode Selection
PIO5/ISP_ENT 8
RY
IO
GPIO5/ISP_ENT GPIO5/ISP_ENTRY — General Purpose digital Input/Output 5;
RY[1][3]
In-System Programming Entry
SPI0_SSELN — Serial Peripheral Interface-bus 0 slave select not
SPI1_MISO — Serial Peripheral Interface-bus 1 master data input
SPI1_SSELN2 — Serial Peripheral Interface-bus 1 slave select not 2
USART0_RTS — Universal Synchronous/Asynchronous
Receiver/Transmitter 0 - Request To Send output
RFRX — Radio Receiver Control Output
JN5189
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© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 1.2 — June 2020
7 of 92
NXP Semiconductors
IEEE 802.15.4 low power wireless MCU
JN5189(T)/JN5188(T)
Table 4.
Symbol
PIO6
Pin descriptions
Pin
Type Default at reset Description
9
IO
IO
IO
GPIO6[1]
GPIO6 — General Purpose digital Input/Output 6
USART0_RTS — Universal Synchronous/Asynchronous
Receiver/Transmitter 0 - Request to Send output
CT32B1_MAT0 — 32-bit CT32B1 match output 0
PWM6 — Pulse Width Modulator output 6
I2C1_SCL — I2C-bus 1 master/slave SCL input/output
USART1_TXD — Universal Synchronous/Asynchronous
Receiver/Transmitter 1 - transmit data output
ADE — Antenna Diversity Even output
SPI0_SCK — Serial Peripheral Interface 0- synchronous clock
GPIO7 — General Purpose digital Input/Output 7
PIO7
10
GPIO7[1]
USART0_CTS — Universal Synchronous/Asynchronous
Receiver/Transmitter 0 - Clear to Send input
CT32B1_MAT1 — 32-bit CT32B1 match output 1
PWM7 — Pulse Width Modulator output 7
I2C1_SDA — I2C-bus 1 master/slave SDA input/output
USART1_RXD — Universal Synchronous/Asynchronous
Receiver/Transmitter 1 - receive data input
ADO — Antenna Diversity Odd Output
SPI0_MISO — Serial Peripheral Interface-bus 0 master input
GPIO8 — General Purpose digital Input/Output 8
PIO8/TXD0
11
GPIO8[1][4]
USART0_TXD — Universal Synchronous/Asynchronous
Receiver/Transmitter 0 - transmit data output
CT32B0_MAT0 — 32-bit CT32B0 match output 0
PWM8 — Pulse Width Modulator output 8
ANA_COMP_OUT — Analog Comparator digital output
PDM1_DATA — Pulse Density Modulation Data input from digital
microphone (channel 1)
SPI0_MOSI — Serial Peripheral Interface-bus 0 master output slave
input
RFTX — Radio Transmit Control Output
PIO9/RXD0
12
IO
GPIO9[1][5]
GPIO9 — General Purpose digital Input/Output 9
USART0_RXD — Universal Synchronous/Asynchronous
Receiver/Transmitter 0 - receive data input
CT32B1_CAP1 — 32-bit CT32B1 capture input 1
PWM9 — Pulse Width Modulator output 9
USART1_SCK — Universal Synchronous/Asynchronous
Receiver/Transmitter 1 - synchronous clock
PDM1_CLK — Pulse Density Modulation Clock output
to digital microphone (channel 1)
SPI0_SSELN — Serial Peripheral Interface-bus 0 slave select not
ADO — Antenna Diversity Odd Output
JN5189
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© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 1.2 — June 2020
8 of 92
NXP Semiconductors
IEEE 802.15.4 low power wireless MCU
JN5189(T)/JN5188(T)
Table 4.
Symbol
PIO10
Pin descriptions
Pin
Type Default at reset Description
13
IO
GPIO10[1]
GPIO10 — General Purpose digital Input/Output 10
CT32B0_CAP0 — 32-bit CT32B0 capture input 0
USART1_TXD — Universal Synchronous/Asynchronous
Receiver/Transmitter 1 - transmit data output
RFTX — Radio Transmit Control Output
I2C0_SCL — I2C-bus 0 master/slave SCL input/output (open drain)
SPI0_SCK — Serial Peripheral Interface-bus 0 clock input/output
PDM0_DATA — Pulse Density Modulation Data input from digital
microphone (channel 0)
PIO11
14
IO
GPIO11[1]
GPIO11 — General Purpose digital Input/Output 11
CT32B1_CAP0 — 32-bit CT32B1 capture input 0
USART1_RXD — Universal Synchronous/Asynchronous
Receiver/Transmitter 1 - receive data input
RFRX — Radio Receiver Control Output
I2C0_SDA — I2C-bus 0 master/slave SDA input/output (open drain)
SPI0_MISO — Serial Peripheral Interface-bus 0 master input slave
output
PDM0_CLK — Pulse Density Modulation Clock output to digital
microphone (channel 0)
PIO12/SWCLK 15
IO
SWCLK
GPIO12 — General Purpose digital Input/Output 12
SWCLK — Serial Wire Debug Clock
PWM0 — Pulse Width Modulator output 0
I2C1_SCL — I2C-bus 1 master/slave SCL input/output (open drain)
SPI0_MOSI — Serial Peripheral Interface-bus 0 master output slave
input
ANA_COMP_OUT — Analog Comparator digital output
IR_BLASTER — Infra-Red Modulator output
PIO13/SWDIO 16
IO
SWDIO
GPIO13 — General Purpose digital Input/Output 13
SPI1_SSELN2 — Serial Peripheral Interface-bus 1, slave select not
2
SWDIO — Serial Wire Debug Input/Output
PWM2 — Pulse Width Modulator output 2
I2C1_SDA — I2C-bus 1 master/slave SDA input/output (open drain)
SPI0_SSELN — Serial Peripheral Interface-bus 0, slave select not
JN5189
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 1.2 — June 2020
9 of 92
NXP Semiconductors
IEEE 802.15.4 low power wireless MCU
JN5189(T)/JN5188(T)
Table 4.
Pin descriptions
Symbol
Pin
Type Default at reset Description
PIO14/ADC0
17
IO
GPIO14[1]
ADC0 — ADC input 0
GPIO14 — General Purpose digital Input/Output 14
SPI1_SSELN1 — Serial Peripheral Interface-bus 1, slave select not
1
CT32B0_CAP1 — 32-bit CT32B0 capture input 1
PWM1 — Pulse Width Modulator output 1
SWO — Serial Wire Output
USART0_SCK — Universal Synchronous/Asynchronous
Receiver/Transmitter 0 - synchronous clock
MCLK — External clock, can be provided to DMIC IP
RFTX — Radio Transmit Control Output
PIO15/ADC1
18
IO
GPIO15[1]
ADC1 — ADC input 1
GPIO15 — General Purpose digital Input/Output 15
SPI1_SCK — Serial Peripheral Interface-bus 1, clock input/output
ANA_COMP_OUT — Analog Comparator digital output
PWM3 — Pulse Width Modulator output 3
PDM1_DATA — Pulse Density Modulation Data input from digital
microphone (channel 1)
I2C0_SCL — I2C-bus 0 master/slave SCL input/output (open drain)
RFRX — Radio Receiver Control Output
PIO16/ADC2
19
IO
GPIO16[1]
ADC2 — ADC input 2
GPIO16 — General Purpose digital Input/Output 16
SPI1_SSELN0 — Serial Peripheral Interface-bus 1, slave select not
0
PWM5 — Pulse Width Modulator output 5
PDM1_CLK — Pulse Density Modulation Clock output to digital
microphone (channel 1)
SPIFI_CSN — Quad-SPI Chip Select Not, output
ISO7816_RST — RST signal, output, for ISO7816 interface
I2C0_SDA — I2C-bus 0 master/slave SDA input/output (open drain)
VDDE — Supply voltage for IO
VDDE
20
21
P
PIO17/ADC3
IO
GPIO17[1]
ADC3 — ADC input 3
GPIO17 — General Purpose digital Input/Output 17
SPI1_MOSI — Serial Peripheral Interface-bus 1, master output slave
input
SWO — Serial Wire Output
PWM6 — Pulse Width Modulator output 6
SPIFI_IO3 — Quad-SPI Input/Output 3
ISO7816_CLK — Clock output for ISO7816 interface
CLK_OUT — Clock out
JN5189
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© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 1.2 — June 2020
10 of 92
NXP Semiconductors
IEEE 802.15.4 low power wireless MCU
JN5189(T)/JN5188(T)
Table 4.
Pin descriptions
Symbol
Pin
Type Default at reset Description
PIO18/ADC4
22
IO
GPIO18[1]
ADC4 — ADC input 4
GPIO18 — General Purpose digital Input/Output 18
SPI1_MISO — Serial Peripheral Interface-bus 1, master data input
CT32B0_MAT1 — 32-bit CT32B0 match output 1
PWM7 — Pulse Width Modulator output 7
SPIFI_CLK — Quad-SPI Clock output
ISO7816_IO — IO of ISO7816 interface
USART0_TXD — Universal Synchronous/Asynchronous
Receiver/Transmitter 0 - transmit data output
PIO19/ADC5
23
IO
GPIO19[1]
ADC5 — ADC input 5
GPIO19 — General Purpose digital Input/Output 19
ADO — Antenna Diversity Odd Output
PWM4 — Pulse Width Modulator output 4
SPIFI_IO0 — Quad-SPI Input/Output 0
USART1_RXD — Universal Synchronous/Asynchronous
Receiver/Transmitter 1 - receive data input
CLK_IN — External clock
USART0_RXD — Universal Synchronous/Asynchronous
Receiver/Transmitter 0 - receive data input
PIO20/ACP
24
IO
GPIO20[1]
ACP — Analog Comparator Positive input
GPIO20 — General Purpose digital Input/Output 20
IR_BLASTER — Infra-Red Modulator output
PWM8 — Pulse Width Modulator output 8
RFTX — Radio Transmit Control Output
SPIFI_IO2 — Quad-SPI Input/Output 2
USART1_TXD — Universal Synchronous/Asynchronous
Receiver/Transmitter 1 - transmit data output
PIO21/ACM
25
IO
GPIO21[1]
ACM — Analog Comparator Negative input
GPIO21 — General Purpose digital Input/Output 21
IR_BLASTER — Infra-Red Modulator output
PWM9 — Pulse Width Modulator output 9
RFRX — Radio Receiver Control Output
SWO — Serial Wire Output
SPIFI_IO1 — Quad-SPI Input/Output 1
USART1_SCK — Universal Synchronous/Asynchronous
Receiver/Transmitter 1 - synchronous clock
TRST
RSTN
VBAT
26
27
28
29
30
31
G
I
TRST — must be connected to GND
RSTN — Reset Not input
P
VBAT — Supply voltage DCDC input
LX — DCDC filter
LX
VSS(DCDC)
FB
G
VSS(DCDC) — ground for DCDC section
FB — DCDC Feedback input
JN5189
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© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 1.2 — June 2020
11 of 92
NXP Semiconductors
IEEE 802.15.4 low power wireless MCU
JN5189(T)/JN5188(T)
Table 4.
Symbol
VDD(PMU)
Pin descriptions
Pin
Type Default at reset Description
32
P
VDD(PMU) — supply voltage for PMU section
crystal oscillator 32.768 kHz
XTAL_32K_P 33
XTAL_32K_N 34
crystal oscillator 32.768 kHz
VDD(RADIO)
VSS(RF)
35
36
37
P
VDD(RADIO) — supply voltage for radio section
VSS(RF) — RF ground
G
IO
RF_IO
RF_IO — RF antenna, RF pin which can be considered as RF
Input/output. The radio transceiver is connected here.
VSS(RF)
LB
38
39
40
G
VSS(RF) — RF ground
NFC tag antenna input B
LA
NFC tag antenna input A
exposed die
pad
G
must be connected to RF ground plane
[1] I: input at reset.
[2] For standard operation (normal boot or ISP programming mode), this pin should be high during the release
of reset. If there is no external driver to this pin, then the internal pull-up will keep this pin high.
[3] ISP programming mode: leave pin floating high during reset to avoid entering UART programming mode or
hold it low to program.
[4] In ISP mode, it is configured to USART0_TXD.
[5] In ISP mode, it is configured to USART0_RXD.
JN5189
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 1.2 — June 2020
12 of 92
NXP Semiconductors
IEEE 802.15.4 low power wireless MCU
JN5189(T)/JN5188(T)
7.2 HVQFN40 - without NTAG
7.2.1 Pinning
terminal 1
index area
XTAL_P
XTAL_N
1
2
30
29
28
27
26
25
24
23
22
21
V
SS(DCDC)
LX
V
3
BAT
PIO0
PIO1
4
RSTN
PIO2
PIO3
5
TRST
JN5188HN; JN5189HN
6
PIO21/ACM
PIO20/ACP
PIO19/ADC5
PIO18/ADC4
PIO17/ADC3
PIO4
7
PIO5/ISP_ENTRY
PIO6
8
9
PIO7
10
aaa-023713
Transparent top view
(1) JN5188HN and JN5189HN HVQFN40 without NTAG
Fig 3. Pin configuration
7.2.2 Pin description
Table 5.
Symbol
XTAL_P
XTAL_N
PIO0
Pin descriptions
Pin
1
Type Default at reset Description
System crystal oscillator 32 MHz
System crystal oscillator 32 MHz
2
3
IO
GPIO0[1]
GPIO0 — General Purpose digital Input/Output 0
USART0_SCK — Universal Synchronous/Asynchronous
Receiver/Transmitter 0 - synchronous clock
USART1_TXD — Universal Synchronous/Asynchronous
Receiver/Transmitter 1 - transmit data output
PWM0 — Pulse Width Modulator output 0
SPI1_SCK — Serial Peripheral Interface-bus 1 clock input/output
PDM0_DATA — Pulse Density Modulation Data input from digital
microphone (channel 0)
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Table 5.
Symbol
PIO1
Pin descriptions
Pin
Type Default at reset Description
4
IO
GPIO1[1]
GPIO1 — General Purpose digital Input/Output 1
USART1_RXD — Universal Synchronous/Asynchronous
Receiver/Transmitter 1 - receive data input
PWM1 — Pulse Width Modulator output 1
SPI1_MISO — Serial Peripheral Interface-bus 1 master data input
PDM0_CLK — Pulse Density Modulation Clock output to digital
microphone (channel 0)
PIO2
5
IO
GPIO2[1]
GPIO2 — General Purpose digital Input/Output 2
SPI0_SCK — Serial Peripheral Interface-bus 0 clock input/output
PWM2 — Pulse Width Modulator output 2
SPI1_MOSI — Serial Peripheral Interface-bus 1 master output slave
input
USART0_RXD — Universal Synchronous/Asynchronous
Receiver/Transmitter 0 - receive data input
ISO7816_RST — RST signal, output, for ISO7816 interface
MCLK — External clock, can be provided to DMIC IP
GPIO3 — General Purpose digital Input/Output 3
PIO3
6
IO
GPIO3[1]
SPI0_MISO — Serial Peripheral Interface-bus 0 master input
PWM3 — Pulse Width Modulator output 3
SPI1_SSELN0 — Serial Peripheral Interface-bus 1 slave select not 0
USART0_TXD — Universal Synchronous/Asynchronous
Receiver/Transmitter 0 - transmit data output
ISO7816_CLK — Clock output for ISO7816 interface
GPIO4 — General Purpose digital Input/Output 4
PIO4
7
IO
GPIO4[1][2]
SPI0_MOSI — Serial Peripheral Interface-bus 0 master output slave
input
PWM4 — Pulse Width Modulator output 4
SPI1_SSELN1 — Serial Peripheral Interface-bus 1 slave select not 1
USART0_CTS — Universal Synchronous/Asynchronous
Receiver/Transmitter 0 - Clear To Send input
ISO7816_IO — IO of ISO7816 interface
RFTX — Radio Transmit Control Output
ISP_SEL — In-System Programming Mode Selection
PIO5/ISP_EN
TRY
8
IO
GPIO5/ISP_ENT GPIO5/ISP_ENTRY — General Purpose digital Input/Output 5;
RY[1][3]
In-System Programming Entry
SPI0_SSELN — Serial Peripheral Interface-bus 0 slave select not
SPI1_MISO — Serial Peripheral Interface-bus 1 master data input
SPI1_SSELN2 — Serial Peripheral Interface-bus 1 slave select not 2
USART0_RTS — Universal Synchronous/Asynchronous
Receiver/Transmitter 0 - Request To Send output
RFRX — Radio Receiver Control Output
JN5189
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Table 5.
Symbol
PIO6
Pin descriptions
Pin
Type Default at reset Description
9
IO
IO
IO
GPIO6[1]
GPIO6 — General Purpose digital Input/Output 6
USART0_RTS — Universal Synchronous/Asynchronous
Receiver/Transmitter 0 - Request to Send output
CT32B1_MAT0 — 32-bit CT32B1 match output 0
PWM6 — Pulse Width Modulator output 6
I2C1_SCL — I2C-bus 1 master/slave SCL input/output
USART1_TXD — Universal Synchronous/Asynchronous
Receiver/Transmitter 1 - transmit data output
ADE — Antenna Diversity Even output
SPI0_SCK — Serial Peripheral Interface 0- synchronous clock
GPIO7 — General Purpose digital Input/Output 7
PIO7
10
GPIO7[1]
USART0_CTS — Universal Synchronous/Asynchronous
Receiver/Transmitter 0 - Clear to Send input
CT32B1_MAT1 — 32-bit CT32B1 match output 1
PWM7 — Pulse Width Modulator output 7
I2C1_SDA — I2C-bus 1 master/slave SDA input/output
USART1_RXD — Universal Synchronous/Asynchronous
Receiver/Transmitter 1 - receive data input
ADO — Antenna Diversity Odd Output
SPI0_MISO — Serial Peripheral Interface-bus 0 master input
GPIO8 — General Purpose digital Input/Output 8
PIO8/TXD0
11
GPIO8[1][4]
USART0_TXD — Universal Synchronous/Asynchronous
Receiver/Transmitter 0 - transmit data output
CT32B0_MAT0 — 32-bit CT32B0 match output 0
PWM8 — Pulse Width Modulator output 8
ANA_COMP_OUT — Analog Comparator digital output
PDM1_DATA — Pulse Density Modulation Data input from digital
microphone (channel 1)
SPI0_MOSI — Serial Peripheral Interface-bus 0 master output slave
input
RFTX — Radio Transmit Control Output
PIO9/RXD0
12
IO
GPIO9[1][5]
GPIO9 — General Purpose digital Input/Output 9
USART0_RXD — Universal Synchronous/Asynchronous
Receiver/Transmitter 0 - receive data input
CT32B1_CAP1 — 32-bit CT32B1 capture input 1
PWM9 — Pulse Width Modulator output 9
USART1_SCK — Universal Synchronous/Asynchronous
Receiver/Transmitter 1 - synchronous clock
PDM1_CLK — Pulse Density Modulation Clock output
to digital microphone (channel 1)
SPI0_SSELN — Serial Peripheral Interface-bus 0 slave select not
ADO — Antenna Diversity Odd Output
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Table 5.
Symbol
PIO10
Pin descriptions
Pin
Type Default at reset Description
13
IO
GPIO10[1]
GPIO10 — General Purpose digital Input/Output 10
CT32B0_CAP0 — 32-bit CT32B0 capture input 0
USART1_TXD — Universal Synchronous/Asynchronous
Receiver/Transmitter 1 - transmit data output
RFTX — Radio Transmit Control Output
I2C0_SCL — I2C-bus 0 master/slave SCL input/output (open drain)
SPI0_SCK — Serial Peripheral Interface-bus 0 clock input/output
PDM0_DATA — Pulse Density Modulation Data input from digital
microphone (channel 0)
PIO11
14
IO
GPIO11[1]
GPIO11 — General Purpose digital Input/Output 11
CT32B1_CAP0 — 32-bit CT32B1 capture input 0
USART1_RXD — Universal Synchronous/Asynchronous
Receiver/Transmitter 1 - receive data input
RFRX — Radio Receiver Control Output
I2C0_SDA — I2C-bus 0 master/slave SDA input/output (open drain)
SPI0_MISO — Serial Peripheral Interface-bus 0 master input slave
output
PDM0_CLK — Pulse Density Modulation Clock output to digital
microphone (channel 0)
PIO12/SWCL 15
K
IO
SWCLK
GPIO12 — General Purpose digital Input/Output 12
SWCLK — Serial Wire Debug Clock
PWM0 — Pulse Width Modulator output 0
I2C1_SCL — I2C-bus 1 master/slave SCL input/output (open drain)
SPI0_MOSI — Serial Peripheral Interface-bus 0 master output slave
input
ANA_COMP_OUT — Analog Comparator digital output
IR_BLASTER — Infra-Red Modulator output
PIO13/SWDIO 16
IO
SWDIO
GPIO13 — General Purpose digital Input/Output 13
SPI1_SSELN2 — Serial Peripheral Interface-bus 1, slave select not
2
SWDIO — Serial Wire Debug Input/Output
PWM2 — Pulse Width Modulator output 2
I2C1_SDA — I2C-bus 1 master/slave SDA input/output (open drain)
SPI0_SSELN — Serial Peripheral Interface-bus 0, slave select not
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Table 5.
Symbol
Pin descriptions
Pin Type Default at reset Description
PIO14/ADC0 17
IO
GPIO14[1]
ADC0 — ADC input 0
GPIO14 — General Purpose digital Input/Output 14
SPI1_SSELN1 — Serial Peripheral Interface-bus 1, slave select not
1
CT32B0_CAP1 — 32-bit CT32B0 capture input 1
PWM1 — Pulse Width Modulator output 1
SWO — Serial Wire Output
USART0_SCK — Universal Synchronous/Asynchronous
Receiver/Transmitter 0 - synchronous clock
MCLK — External clock, can be provided to DMIC IP
RFTX — Radio Transmit Control Output
PIO15/ADC1 18
IO
GPIO15[1]
ADC1 — ADC input 1
GPIO15 — General Purpose digital Input/Output 15
SPI1_SCK — Serial Peripheral Interface-bus 1, clock input/output
ANA_COMP_OUT — Analog Comparator digital output
PWM3 — Pulse Width Modulator output 3
PDM1_DATA — Pulse Density Modulation Data input from digital
microphone (channel 1)
I2C0_SCL — I2C-bus 0 master/slave SCL input/output (open drain)
RFRX — Radio Receiver Control Output
PIO16/ADC2 19
IO
GPIO16[1]
ADC2 — ADC input 2
GPIO16 — General Purpose digital Input/Output 16
SPI1_SSELN0 — Serial Peripheral Interface-bus 1, slave select not
0
PWM5 — Pulse Width Modulator output 5
PDM1_CLK — Pulse Density Modulation Clock output to digital
microphone (channel 1)
SPIFI_CSN — Quad-SPI Chip Select Not, output
ISO7816_RST — RST signal, output, for ISO7816 interface
I2C0_SDA — I2C-bus 0 master/slave SDA input/output (open drain)
VDDE — Supply voltage for IO
VDDE
20
P
PIO17/ADC3 21
IO
GPIO17[1]
ADC3 — ADC input 3
GPIO17 — General Purpose digital Input/Output 17
SPI1_MOSI — Serial Peripheral Interface-bus 1, master output slave
input
SWO — Serial Wire Output
PWM6 — Pulse Width Modulator output 6
SPIFI_IO3 — Quad-SPI Input/Output 3
ISO7816_CLK — Clock output for ISO7816 interface
CLK_OUT — Clock out
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Table 5.
Symbol
Pin descriptions
Pin Type Default at reset Description
PIO18/ADC4 22
IO
GPIO18[1]
ADC4 — ADC input 4
GPIO18 — General Purpose digital Input/Output 18
SPI1_MISO — Serial Peripheral Interface-bus 1, master data input
CT32B0_MAT1 — 32-bit CT32B0 match output 1
PWM7 — Pulse Width Modulator output 7
SPIFI_CLK — Quad-SPI Clock output
ISO7816_IO — IO of ISO7816 interface
USART0_TXD — Universal Synchronous/Asynchronous
Receiver/Transmitter 0 - transmit data output
PIO19/ADC5 23
IO
GPIO19[1]
ADC5 — ADC input 5
GPIO19 — General Purpose digital Input/Output 19
ADO — Antenna Diversity Odd Output
PWM4 — Pulse Width Modulator output 4
SPIFI_IO0 — Quad-SPI Input/Output 0
USART1_RXD — Universal Synchronous/Asynchronous
Receiver/Transmitter 1 - receive data input
CLK_IN — External clock
USART0_RXD — Universal Synchronous/Asynchronous
Receiver/Transmitter 0 - receive data input
PIO20/ACP
24
IO
GPIO20[1]
ACP — Analog Comparator Positive input
GPIO20 — General Purpose digital Input/Output 20
IR_BLASTER — Infra-Red Modulator output
PWM8 — Pulse Width Modulator output 8
RFTX — Radio Transmit Control Output
SPIFI_IO2 — Quad-SPI Input/Output 2
USART1_TXD — Universal Synchronous/Asynchronous
Receiver/Transmitter 1 - transmit data output
PIO21/ACM
25
IO
GPIO21[1]
ACM — Analog Comparator Negative input
GPIO21 — General Purpose digital Input/Output 21
IR_BLASTER — Infra-Red Modulator output
PWM9 — Pulse Width Modulator output 9
RFRX — Radio Receiver Control Output
SWO — Serial Wire Output
SPIFI_IO1 — Quad-SPI Input/Output 1
USART1_SCK — Universal Synchronous/Asynchronous
Receiver/Transmitter 1 - synchronous clock
TRST
RSTN
VBAT
26
27
28
29
30
31
G
I
TRST — must be connected to GND
RSTN — Reset Not input
P
VBAT — Supply voltage DCDC input
LX — DCDC filter
LX
VSS(DCDC)
FB
G
VSS(DCDC) — ground for DCDC section
FB — DCDC Feedback input
JN5189
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Table 5.
Symbol
VDD(PMU)
Pin descriptions
Pin
Type Default at reset Description
32
P
VDD(PMU) — supply voltage for PMU section
crystal oscillator 32.768 kHz
XTAL_32K_P 33
XTAL_32K_N 34
crystal oscillator 32.768 kHz
VDD(RADIO)
VSS(RF)
35
36
37
P
VDD(RADIO) — supply voltage for radio section
VSS(RF) — RF ground
G
IO
RF_IO
RF_IO — RF antenna, RF pin which can be considered as RF
Input/output. The radio transceiver is connected here.
VSS(RF)
n.c.
38
39
40
G
VSS(RF) — RF ground
not connected
n.c.
not connected
exposed die
pad
G
must be connected to RF ground plane
[1] I: input at reset.
[2] For standard operation (normal boot or ISP programming mode), this pin should be high during the release
of reset. If there is no external driver to this pin, then the internal pull-up will keep this pin high.
[3] ISP programming mode: leave pin floating high during reset to avoid entering UART programming mode or
hold it low to program.
[4] In ISP mode, it is configured to USART0_TXD.
[5] In ISP mode, it is configured to USART0_RXD.
7.3 Pin properties
Table 6.
Pin properties
1
2
3
4
5
6
7
8
9
XTAL_P
XTAL_N
PIO0
H
L
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
Y
N
N
N
N
N
N
N
PU
PD
PD
PU
PU
PU
PD
SS
SS
SS
SS
SS
SS
SS
PIO1
Y
Y
PIO2
L
Y
Y
PIO3
H
H
H
L
Y
Y
PIO4
Y
Y
PIO5/ISP_ENTRY
PIO6
Y
Y
Y
Y
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Table 6.
Pin properties
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
PIO7
L
H
Y
Y
PD
PU
PU
EPU[1]
EPU[1]
PU
PU
PU
PU
PU
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
N
N
N
N
N
N
Y
Y
N
N
PIO8/TXD0
PIO9/RXD0
PIO10
H
Y
N
N
N
Y
N
Hi-Z
Hi-Z
H
N[1]
N[1]
Y
N
N
Y
Y
N
PIO11
N
N
Y
Y
N
PIO12/SWCLK
PIO13/SWDIO
PIO14/ADC0
PIO15/ADC1
PIO16/ADC2
VDDE
N
N
N
Y
N
H
Y
N
N
N
Y
N
H
Y
N
N
N
Y
N
H
Y
N
N
N
Y
N
H
Y
N
N
N
Y
N
L
Y
N
N
N
Y
Y
PIO17/ADC3
PIO18/ADC4
PIO19/ADC5
PIO20/ACP
PIO21/ACM
TRST[2]
PD
PD
PD
PD
PU
SS
SS
SS
SS
SS
L
Y
N
N
N
Y
Y
L
Y
N
N
N
Y
Y
L
Y
N
N
N
Y
Y
H
Y
N
N
N
Y
Y
Hi-Z
H
N
N
RSTN
Y
PU
N
VBAT
LX
VSS(DCDC)
FB
VDD(PMU)
XTAL_32K_P
XTAL_32K_N
VDD(RADIO)
VSS_RF
RFIN
VSS_RF
LB
LA
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[1] External Pullup required
[2] Tie to ground for functional mode
Table 7:
Abbreviation used in the Table 6
Properties
Abbreviation
Descriptions
High impendence
Default status after POR
Hi-Z
H
High level
Low level
L
Pullup/ pulldown Enable after
POR
Y
Enabled
N
Disabled
Pullup/ pulldown selection after
POR
PU
PD
FS
SS
N
Pullup
Pulldown
Slew rate after POR
Passive Pin Filter after POR
Open drain enable after reset
Open drain enable control
Pin interrupt
Fast slew rate
Slow slew rate
Disabled
Y
Enabled
N
Disabled
Y
Enabled
Disabled[1]
N
Y
Enabled
N
Yes
Y
No
Fast capability
N
Not support fast capability
Support fast capability
Y
[1] All PIO except 10/11 can do pseudo-open drain
8. Functional description
8.1 Application CPU
The Arm Cortex-M4 includes three AHB-Lite buses, one system bus and the I-code and
D-code buses. One bus is dedicated for instruction fetch (I-code), and one bus is
dedicated for data access (D-code). The use of two core buses allows for simultaneous
operations if concurrent operations target different devices.
A multi-layer AHB matrix connects the CPU buses and other bus masters to peripherals in
a flexible manner that optimizes performance by allowing peripherals on different slave
ports of the matrix to be accessed simultaneously by different bus masters. Note that
while the AHB bus itself supports word, halfword, and byte accesses, not all AHB
peripherals need or provide that support.
APB peripherals are connected to the AHB matrix via two APB buses using separate
slave ports from the multilayer AHB matrix. This allows for better performance by reducing
collisions between the CPU and the DMA controller, and also for peripherals on the
asynchronous bridge to have a fixed clock that does not track the system clock. Note that
APB, by definition, does not directly support byte or halfword accesses.
JN5189
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JN5189(T)/JN5188(T)
The CPU, AHB and DMA sub-systems are all synchronous and can operate at 48 MHz
(FRO), 32 MHz (FRO), 32 MHz (XTAL), 24 MHz (FRO), 16 MHz (XTAL), 12 MHz (FRO).
8.1.1 Arm Cortex-M4 processor
The Arm Cortex-M4 is a general purpose, 32-bit microprocessor, which offers high
performance and very low-power consumption. The Arm Cortex-M4 offers many features,
including a Thumb-2 instruction set, low interrupt latency, hardware divide,
interruptible/continuable multiple load and store instructions, automatic state save and
restore for interrupts, tightly integrated interrupt controller with wake-up interrupt
controller, and multiple core buses capable of simultaneous accesses.
A 3-stage pipeline is employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
8.1.2 Memory Protection Unit
The Cortex-M4 includes a Memory Protection Unit (MPU) which can be used to improve
the reliability of an embedded system by protecting critical data within the user
application.
The MPU allows separating processing tasks by disallowing access to each other's data.
Access to memory regions can be disabled and also be defined as read-only. It detects
unexpected memory accesses that could potentially break the system.
The MPU separates the memory into distinct regions and implements protection by
preventing disallowed accesses. The MPU supports up to eight regions, each of which is
divided into eight sub-regions. Accesses to memory locations that are not defined in the
MPU regions, or not permitted by the region setting, will trigger memory management fault
exception.
8.1.3 System Tick Timer (SysTick)
The Arm Cortex-M4 core includes a System Tick timer (SysTick) that generates a
dedicated SYSTICK exception. The clock source for the SysTick can be the system clock,
or a divided version of this.
8.1.4 Nested Vector Interrupt controller (NVIC)
The NVIC is an integral part of the Cortex-M4 that efficiently supports many interrupt
sources with configurable priority levels.
8.1.4.1 Features
• Nested Vectored Interrupt Controller that is an integral part of the CPU
• Tightly coupled interrupt controller provides low interrupt latency
• Controls system exceptions and peripheral interrupts
• 56 vectored interrupts
• 8 programmable interrupt priority levels with hardware priority level masking
• Relocatable vector table using Vector Table Offset Register VTOR
• Software interrupt generation
• Support for Non-Maskable Interrupt (NMI) from any interrupt
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8.1.4.2 General description
The tight coupling of the NVIC to the CPU allows for low interrupt latency and efficient
processing of late arriving interrupts.
8.2 Memory
The JN5189 incorporates several distinct memory regions.
The registers incorporated into the CPU, such as NVIC, SysTick, and sleep mode control,
are located on the private peripheral bus.
The system memory map is shown in the following figure:
JN5189
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32-bit Words
0xFFFF_FFFF
Reserved
(Do not access)
0xE00F_FFFF
Private Peripheral
Bus (External)
0xE004_0000
0xE003_FFFF
Private Peripheral
Bus (Internal)
768 KBytes
0xE000_0000
Reserved
(Do not access)
0x400B_1FFF
4 Kbytes
4 Kbytes
64 Kbytes
Zigbee/Thread MAC
0x400B_1000
0x400B_0FFF
Zigbee/Thread MODEM
0x400B_0000
0x400A_FFFF
Reserved
(Do not access)
0x400A_0000
Reserved
(Do not access)
0x4008_FFFF
4 Kbytes
4 Kbytes
4 Kbytes
Hash
SPI 1
SPI 0
0x4008_F000
0x4008_EFFF
0x4008_E000
0x4008_DFFF
0x4008_D000
0x4008_CFFF
USART 1
USART 0
4 Kbytes
4 Kbytes
4 Kbytes
0x4008_C000
0x4008_BFFF
0x4008_B000
0x4008_AFFF
32-bit Words
DMIC
ADC
0x4008_A000
0x4008_9FFF
0x4001_FFFF
4 Kbytes
Reserved
(Do not access)
0x4008_9000
0x4008_8FFF
32-bit Words
40 KBytes
Reserved
(Do not access)
Reserved
(Do not access)
0x4001_6000
0x4001_5000
0x4001_4000
0x4001_3000
0x4001_2000
0x4001_1000
0x4001_0000
0x4000_F000
0x4000_E000
0x4000_D000
0x4000_C000
0x4000_B000
0x4000_A000
0x4000_9000
0x4000_8000
0x4000_7000
0x4000_6000
0x4000_5000
0x4000_4000
0x4000_3000
0x4000_2000
0x4000_1000
0x4000_0000
0x4003_FFFF
4 Kbytes
4 Kbytes
Reserved
(Do not access)
Reserved
0x4008_8000
0x4008_7FFF
Reserved
4 KBytes
4 KBytes
4 KBytes
4 KBytes
4 KBytes
4 KBytes
4 KBytes
4 KBytes
4 KBytes
4 KBytes
4 KBytes
4 KBytes
4 KBytes
4 KBytes
4 KBytes
4 KBytes
4 KBytes
4 KBytes
4 KBytes
4 KBytes
4 KBytes
4 KBytes
116 KBytes
(Do not access)
0x4002_3000
0x4002_2FFF
0x4008_7000
0x4008_6FFF
(Do not access)
CTIMER 1
CTIMER 0
4 KBytes
4 KBytes
0x4002_2000
0x4002_1FFF
AES-256
4 Kbytes
4 KBytes
RFP MODEM
0x4008_6000
0x4008_5FFF
0x4002_1000
0x4002_0FFF
PMC
DMA Controller
SPIFI Registers
General Purpose I/O
Asynchronous
System Configuration
0x4008_5000
0x4008_4FFF
4 KBytes
GPIO Group
Interrupt (GINT0)
GPIO Pattern
Interrupt (PINT)
IO CONFIG
(IOCON)
0x4002_0000
4 KBytes
0x4008_4000
0x4008_3FFF
APB Bridge 1 Memory Map
16 KBytes
0x4008_0000
Reserved
(Do not access)
INPUT MUX
Random Number
Generator
0x4003_FFFF
APB Bridge 1
(Asynchronous)
128 KBytes
128 KBytes
0x4002_0000
0x4001_FFFF
PWM
APB Bridge 0
(Synchronous)
Reserved
RTC
0x4000_0000
WWDT
0x103F_FFFF
0x1000_0000
Quad SPIFI
4 MBytes
64 KBytes
0x0402_FFFF
(Memory-Mapped Space)
Flash Controller
SRAM 11 (16 KB)
SRAM 10 (16 KB)
SRAM 9 (16 KB)
SRAM 8 (16 KB)
0x0402_C000
0x0402_BFFF
Reserved
Code Patch
Module
0x0402_FFFF
0x0402_0000
0x0401_5FFF
0x0400_0000
0x0402_8000
0x0402_7FFF
SRAM-CTRL1
(4*16KB)
0x0402_4000
0x0402_3FFF
0x0402_0000
IR Modulator
ISO7816
I2C 2
Reserved
SRAM-CTRL0
88 KBytes
128 KBytes
640 KBytes
0x0401_5FFF
(2*4KB, 2*8KB, 4*16KB)
SRAM 7 (4 KB)
SRAM 6 (4 KB)
SRAM 5 (8 KB)
SRAM 4 (8 KB)
SRAM 3 (16 KB)
SRAM 2 (16 KB)
SRAM 1 (16 KB)
SRAM 0 (16 KB)
0x0401_5000
0x0401_4FFF
0x0401_4000
0x0401_3FFF
0x0401_2000
0x0401_1FFF
Reserved
(Do not access)
I2C 1
0x0301_FFFF
0x0300_0000
ROM
I2C 0
0x0401_0000
0x0400_FFFF
0x0400_C000
0x0400_BFFF
0x0400_8000
0x0400_7FFF
Reserved (do not
access)
Reserved
(Do not access)
Reserved (do not
access)
0x0009_FFFF
0x0000_0000
FLASH Memory
0x0400_4000
0x0400_3FFF
0x0400_0000
Synchronous System
Configuration
Main Memory Map (AHB)
APB Bridge 0 Memory Map
SRAMs Memory Map
1) The private peripheral bus includes CPU peripherals such as the NVIC, SysTick, and the core control registers.
Fig 4. System memory map
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8.2.1 SRAM
IEEE 802.15.4 low power wireless MCU
JN5189(T)/JN5188(T)
The main SRAM is comprised of up to a total 152 KB on-chip static RAM memory. The
main SRAM is implemented as several SRAM instances to allow for more control of power
usage when less SRAM is required (2 4 KB instances, 2 8 KB instances and 8 16 KB
instances). Each SRAM has a separate clock control and power switch.
See Table 2 for SRAM size of each parts.
8.2.2 SRAM usage
Although always contiguous on all JN5189 devices, the SRAM instances are divided
between two AHB matrix ports. This allows user programs to potentially obtain better
performance by dividing RAM usage among the ports. For example, simultaneous access
to SRAM0 by the CPU and SRAM1 by the system DMA controller does not result in any
bus stalls for either master.
Generally speaking, the CPU will read or write all peripheral data at some point, even
when all such data is read from or sent to a peripheral by DMA. So, minimizing stalls is
likely to involve putting data to/from different peripherals in RAM on each port.
Alternatively, sequences of data from the same peripheral could be alternated between
RAM on each port. This could be helpful if DMA fills or empties a RAM buffer, then signals
the CPU before proceeding on to a second buffer. The CPU would then tend to access the
data while the DMA is using RAM on the other port. On the JN5188, all the RAM is
accessed through one AHB matrix slave port.
8.2.3 FLASH
The JN5189 embeds flash for code and data storage. It is accessed through a flash
controller that simplifies the use of the flash.
• JN5189 embeds a total of 640 KB of Flash, JN5188 a total of 320 KB
• Flash sector is 512 bytes
• 100 kcycles page endurance guaranteed
• Software is provided to manage data storage in the flash and provides wear leveling
features
• Data retention 10 years
8.2.4 AHB multilayer matrix
The JN5189 uses a multi-layer AHB matrix to connect the CPU buses and other bus
masters to peripherals in a flexible manner that optimizes performance by allowing
peripherals that are on different slave ports of the matrix to be accessed simultaneously
by different bus masters.
8.3 System clocks
The following system clocks are used to drive the on-chip subsystems of the JN5189:
• The low power wake timers are driven by a low frequency 32 kHz clock.
• The main digital systems are driven from a high frequency clock source.
• The system controller state machines are driven from a 1 MHz FRO.
JN5189
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These system clocks are used within the device for the digital functionality. Some
functional blocks can also source a clock from the interface and this is explained in when
the digital blocks are presented.
8.3.1 32 kHz clock
There are two possible sources for the 32kHz clock.
There is an internal FRO that gives 32.768 kHz with accuracy of ±2%; this requires no
external components.
A 32 kHz XTAL is also supported. The XTAL is connected to XTAL_32K_P and
XTAL_32K_N pins. The cell has configurable internal capacitors and therefore, except for
the XTAL itself, no other external components are typically required. Very accurate XTALs
are available. This option is recommended for accurate timings.
8.3.2 High frequency system clock
There are two possible sources for the high-speed system clock.
There is an internal high speed FRO that supports clock frequencies of 48 MHz, 32 MHz,
24 MHz and 12 MHz. This does not require any external components and has an
accuracy of ±2%.
A 32 MHz XTAL is also supported. The cell has configurable internal capacitors and
therefore, except for the XTAL itself, no other external components are typically required.
An accurate XTAL must be used for the radio operation. The system clock can be chosen
to be sourced from the FRO or XTAL and this choice is separate to the operation of the
radio using the XTAL clock. When selecting the XTAL as the source for the high frequency
system clock, it is possible to select 32 MHz or 16 MHz.
The high frequency system clock is used for the processor and the system buses.
8.3.3 1 MHz FRO
A 1 MHz FRO is used by the core system controller and the state machine involved in the
device start-up and shut-down. High accuracy of this clock is not necessary and it has a
tolerance of 15%.
8.4 Resets and brownout
A system reset initializes the device to a pre-defined state and forces the CPU to start
program execution from the reset vector. The reset process that the JN5189 goes through
is as follows.
When power is first applied or when the external reset is released, the FRO1MHz is
started, then the DCDC converter is started. After that, the system power domain is
started. When these domains are stable, the flash and main core domain LDOs are
enabled. When these are stable, the high speed FRO is enabled and the elements
necessary for CPU operation are enabled. Configuration data is read from the flash and
the boot process begins.
Depending on the configuration and flash contents then the application may be executed,
or the device may enter In System Programming (ISP) mode.
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The initial power-up sequence will not begin if the device power is too low; in this case the
Power-on reset module will keep the device in a reset state until there is sufficient voltage.
Additionally, the brown-out detect block will keep the device in reset until a safe operating
voltage is reached.
Once the device is operating, the brownout module can be used to interrupt the processor
in case operating voltage changes occur. This allows software to manage a clean
response to the event. The brownout threshold is configurable to support a range of
applications.
Several resets are supported that can affect all or most of the device. These are
presented in the following sub-sections.
8.4.1 External reset
An external reset is generated by a low level on the RSTN pin. Reset pulses longer than
the minimum pulse width will generate a reset during active or power-down modes.
Shorter pulses are not guaranteed to generate a reset. The JN5189 is held in reset while
the RSTN pin is low. When the applied signal reaches the reset threshold voltage on its
positive edge, the internal reset process starts.
The JN5189 has an internal pull-up resistor connect to the RSTN pin. This pin is the input
for an external reset only.
8.4.2 Software reset
A system reset can be triggered at any time through software control, causing a full chip
reset and invalidating the RAM contents. For example, this can be executed within a
user's application upon detection of a system failure.
8.4.3 Watchdog timer
The watchdog timer can cause a full chip reset if it reaches its timeout point and it is
configured to generate a reset, rather than an interrupt. In normal operation, the software
will periodically service the watchdog to prevent this timeout occurring. Typically, a
watchdog timeout indicates an unexpected lock-up within the system.
8.4.4 Arm system reset
The CPU can cause a reset by requesting a System reset. This reset causes a reset of
the CPU and the core digital functionality, digital peripherals and the 32 MHz XTAL. The
power domains within the device, such as the DCDC converter and core LDO are
unaffected so that the CPU will restart quicker than if a software reset is performed.
8.5 System configuration (SYSCON)
The device has many system level features which support the operation of the device,
such as clock control. In addition there is functionality provided to allow the software to
manage the system, such as controlling wake-up sources. These features include:
• System and bus configuration
• Clock select and control
• Reset control
• Wake-up control
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• Brown-out (BOD) configuration
• High-accuracy frequency measurement function for on-chip and off-chip clocks, using
a selection of on-chip clocks as reference clock
• Device ID register
8.6 Power management
This section provides an overview of power related information about JN5189 devices.
These devices include a variety of adjustable regulators, power switches, and clock
switches to allow fine tuning power usage to match requirements at different performance
levels and reduced power modes. All devices include an on-chip API in the boot ROM to
adjust power consumption in reduced power modes, and provide entry to those modes.
8.6.1 Power supply
The device is powered by VBAT, which requires a 10 F decoupling capacitor to ground.
To give efficient operation, the device has an on-chip DCDC buck converter; it is turned on
when the device is in active and sleep modes and, using external connections, it provides
the supply voltage to the PMU and Radio. The converter is powered from VBAT and the
external output of the DCDC converter, FB, requires a 10 F decoupling capacitor to
ground. For the DCDC converter to function correctly, a filtered version of FB must be
input to LX, This is achieved with a 4.7 H inductor. The DCDC converter output, FB, must
be routed to device pins VDD(radio) and VDD(pmu) so that the whole system is powered
correctly.
The two VDD power inputs supply the power to most of the device, either directly or via
on-chip regulators and power switches. These are used to manage power consumption
based on the required mode of operation.
There is an always-on power domain which is powered by VBAT and includes the core
functions to control device start-up and the functionality required in the very low power
modes. This domain always has power as long as sufficient voltage is supplied to VBAT.
A further domain is important for supporting the power down mode. It includes the RTC,
wake-up timer and some clock, reset and wakeup control. This domain is always has
power as long as sufficient voltage is supplied to VDD and provided that the device is not
in deep power-down mode.
See Figure 10 “Application diagram – battery powered solution” for the power
connections.
8.6.2 Power modes
A variety of power modes are supported for the optimization of power consumption,
including active, sleep, deep-sleep, power-down and deep power-down. Upon power-up
or reset, the device enters active mode. After processing is complete, the software puts
the chip into sleep mode or power-down mode, to save power consumption. The device is
woken up either by a reset or an interrupt trigger like a GPIO interrupt, timer timeout, or
other wake-up sources.
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An API is provided so that software can easily use the power modes. The API performs all
the configuration necessary for the different power modes, including setting power
domains to the correct state and voltage, shutting down the flash controller safely,
enabling the wake up mechanisms. The following sections introduces modes supported in
order from highest to lowest power consumption.
8.6.2.1 Active mode
The part is in active mode after a Power-On Reset (POR) and when it is fully powered and
operational after booting.
8.6.2.2 Sleep mode
Sleep mode saves a significant amount of power by stopping CPU execution without
affecting peripherals or requiring significant wake-up time. The sleep mode affects the
relevant CPU only. The clock to the core is shut off. Peripherals and memories are active
and operational.
8.6.2.3 Deep-sleep mode
Deep-sleep mode is highly configurable and can reduce power consumption, compared to
Sleep mode by turning off more functions. Additionally, core voltages are reduced to save
power. Wake-up times are longer than for Sleep mode due to the time needed to restart
the functions. The clock to the CPU is shut down. The clock to the peripherals may also
be disabled. The SRAM and registers maintain their internal states.
Entry to these modes can be accomplished by the CPU using the power profiles API,
selected peripherals can be left running for safe operation of the part (e.g. RTC, WWDT
and BOD, depending upon the mode). The flash is placed in standby mode and system
clocks may be disabled.
8.6.2.4 Power-down mode
In Power-down mode the core of the device and the flash is powered down, most clocks
are stopped. Power consumption is very low with the cost of a longer wake-up time. The
processor and most digital peripherals are powered off. USART0, SPI0 and I2C0 can
operate with limited functionality in power down mode and have the ability to wake the
device. Low power sleep timers can be enabled to generate a wake-up at a certain time in
the future. Wakeup is also possible by GPIOs, analog comparator, RTC, BOD VBAT and
NTAG field detect. All, or part, of the SRAM can be optionally retained at the cost of extra
current consumption.
8.6.2.5 Deep power-down mode
Deep Power-down mode shuts down virtually all on-chip power consumption, but requires
a significantly longer wake-up time. For maximal power savings, the entire system (CPU,
memories and all peripherals) is shut down except for the PMU. Wake-up is possible from
reset, NTAG field detect, and optionally GPIO. On wake-up, the part reboots.
8.6.2.6 Wake-up sources
All interrupts to the CPU can be used as a wake-up from sleep.
The following table shows the possible wake-up sources from deep-sleep, power-down
and deep power-down.
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Table 8.
Power mode wake-up sources
Wake-up source
Deep sleep Power-down Deep power-down
WWDT
BOD
Yes
Yes
Yes
Yes
GINT
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
IR Modulator
PINT [3:0]
SPIFI
TIMER [1:0]
USART0
USART1
I2C0
Yes
Yes
Yes
I2C1
SPI0
SPI1
PWM[11:0]
I2C2
RTC
Yes
Yes
NFCTAG
ADC_SEQA
ADC_THCMP_OVR
DMIC
Yes
HWVAD
ISO7816
ANA_COMP
WAKE_UP_TIMER[1:0]
GPIO
Yes
Yes
Yes
Yes
8.7 Digital I/O
8.7.1 Features
• All 22 Digital I/Os can be configured a GPIO ports
• GPIO pins can be configured as input or output by software
• All GPIO pins default to inputs with interrupt disabled at reset
• Pin registers allow pins to be sensed and set individually
• Group Interrupt to generate a single interrupt from AND or OR function of the digital
IOs.
• Pin/ Pattern Interrupt allowing 4 IOs to be able to create an interrupt based on pin
values or a combination of the values
• 2 IOs supporting true I2C mode or standard digital IO with configurable pull-up and
drive strength
• 20 standard IO cells configurable for drive strength, pull-up resistor, pull-down
resistor, pseudo open-drain
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8.7.2 General description
The 22 digital IOs have multiplexed functionality, supporting one or more digital
peripherals and also a basic General Purpose IO function (GPIO). In GPIO mode it is
possible to configure the IO as an input or as an output.
As an input it is possible to configure IO wake a device from powerdown and deep
powerdown. The input value can also be read.
Using the Pin Interrupt/ Pattern Match function (PINT) it is possible to configure up to 4
digital IOs to be able to generate an interrupt based for active high or low functionality.
Alternatively the 4 IOs can be combined in various ways to generate an interrupt. These
interrupt are able to wake the CPU from sleep mode.
Additionally, a Group Interrupt function (GINT) allows any selection of upto all 22 IOs to
be combined into a AND or OR function in order to generate the group interrupt. The
polarity of each IO used in the function can be configured.
Two of the digital IO cells support true I2C functionality and standard digital IO
functionality, These support a pull-up resistor, drive strength control.
The other 20 digital IOs cells are configurable to support drive strength options, pull-up or
pull-down functions and the ability to operate in a pseudo open-drain mode.
The output value of each IO can be held during a power-down cycle if required.
Two DIO pins can optionally be used to provide control signals for RF circuitry (e.g.
switches and PA) in high-power range extenders. PIO4_8_10_14_20/RFTX is asserted
when the radio is in the transmit state and similarly, PIO5_11_15_21/RFRX is asserted
when the radio is in the receiver state. From software and test perspective, it is
recommended to use PIO4 or PIO20 for RFTX and PIO5 or PIO21 for RFRX.
8.8 DMA controller
The DMA controller allows peripheral to memory, memory to peripheral, and memory
single source and destination.
• 19 channels which are connected to peripheral DMA requests. These come from the
USART, SPI-bus, I2C-bus, PDM and SPIFI interfaces. Any otherwise unused
channels can also be used for functions such as memory-to-memory moves.
• DMA operations can be triggered by on-chip or off-chip events. Each DMA channel
can select one trigger input from 18 sources. Trigger sources include ADC interrupts,
timer interrupts, pin interrupts, and the SCT DMA request lines
• Priority is user selectable for each channel (up to eight priority levels)
• Continuous priority arbitration
• Address cache with four entries (each entry is a pair of addresses)
• Efficient use of data bus
• Supports single transfers up to 1,024 words
• Address increment options allow packing and/or unpacking data
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8.9 PWM
IEEE 802.15.4 low power wireless MCU
JN5189(T)/JN5188(T)
The PWM module supports the generation of up to 10 PWM waveforms, each with its own
prescaler, to support a range of applications.
• 1 PWM module with 10 independent outputs
• Option for 1 channel to drive up to 1 channel driving the 10 outputs simultaneously
• Programmable 10-bit prescaler for eac.h channel
• 16-bit auto-reload down counter for each channel
• 16-bit compare register for each channel (toggling point in 1 full period)
• Predictable PWM initial output state for each channel (configurable initial waveform
polarity – HIGH or LOW)
• Configurable level (HIGH or LOW) of PWM output when PWM is disabled
• Programmable overflow interrupt generation for each channel
8.10 Timers
Within the JN5189 there are several different timer blocks available. These timers are
used in different ways as outlined here.
• Counter/Timers: The two blocks are the main functional timers for the application,
running off a high speed clock and able to create interrupts from match registers.
• Watchdog Timer: slow speed timer with the ability to interrupt the processor or cause
device reset. Often used to identify when application software is locked up or taking
too long.
• Real-time clock: this block has two timers real time clock and high-resolution/wake-up
timer. The real time clock has a 1Hz clock is often run continually as a clock. The
high-resolution/ wake up timer is a simple counter that can generate an input to wake
the device from sleep, deep-sleep and power-down. Maximum timeout is 64 seconds.
• Low Power Wake-up Timers: this block has two timers running on a 32kHz clock.
Predominantly used to wake the device from power-down, with a maximum time
period in excess of one year.
• Tick Timer: within the processor this is often used for a regular heart beat to trigger
software scheduling.
The device has different power modes and the following table shows when the timers can
be used.
Table 9.
Allowed timer usage in different power modes
Timer block
Active mode Sleep mode
Deep-sleep
mode
Power-down
mode
Deep power-down
mode
Counter/timer
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Watchdog timer
Real-time clock
Low Power wake-up timers
Tick timer
X
X
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8.10.1 Counter/Timers
There are two Counter/Timer blocks that support a range of functions such as timers or
counting events from an IO pin. The match registers allow for configurable interrupts when
the counter reaches certain values. The match events can also be indicated on device
pins.
8.10.1.1 Features
• 2 counter/timer instances, CT32B0 and CT32B1
• Each is a 32-bit counter/timer with a programmable 32-bit prescaler. Both timers
include external capture and match pin connections
• Counter or timer operation
• For each timer, up to 2 32-bit capture channels that can take a snapshot of the timer
value when an input signal transitions. A capture event may also optionally generate
an interrupt
• The timer and prescaler may be configured to be cleared on a designated capture
event. This feature permits easy pulse-width measurement by clearing the timer on
the leading edge of an input pulse and capturing the timer value on the trailing edge
• Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match
– Stop timer on match with optional interrupt generation
– Reset timer on match with optional interrupt generation
• For each timer with pin connections, up to 2 external outputs corresponding to match
registers with the following capabilities:
– Set LOW on match
– Set HIGH on match
– Toggle on match
– Do nothing on match
– Two match registers can be used to trigger DMA transfers.
8.10.1.2 General description
Each counter/timer is designed to count cycles of the APB bus clock or an externally
supplied clock and can optionally generate interrupts or perform other actions at specified
timer values based on four match registers. Each counter/timer also includes one capture
input to trap the timer value when an input signal transitions, optionally generating an
interrupt.
Capture inputs: The capture signal can be configured to load the capture register with
the value in the counter/timer and optionally generate an interrupt. The capture signal is
generated by one of the pins with a capture function. Each capture signal is connected to
one capture channel of the timer.
The counter/timer block can select a capture signal as a clock source instead of the APB
bus clock.
Match outputs: When a match register equals the Timer Counter (TC), the
corresponding match output can either toggle, go LOW, go HIGH, or do nothing.
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Applications
• Interval timer for counting internal events
• Pulse Width Modulator via match outputs
• Pulse Width Demodulator via capture input
• Free running timer
8.10.2 Watchdog timer
The purpose of the Watchdog Timer is to reset or interrupt the microcontroller within a
programmable time if it enters an erroneous state. When enabled, a watchdog reset is
generated if the user program fails to feed (reload) the Watchdog within a predetermined
amount of time.
When a watchdog window is programmed, an early watchdog feed is also treated as a
watchdog event. This allows preventing situations where a system failure may still feed
the watchdog. For example, application code could be stuck in an interrupt service that
contains a watchdog feed. Setting the window such that this would result in an early feed
will generate a watchdog event, allowing for system recovery.
• Internally resets chip if not reloaded during the programmable time-out period
• Optional windowed operation requires reload to occur between a minimum and
maximum time-out period, both programmable
• Optional warning interrupt can be generated at a programmable time prior to
watchdog time-out
• Clock fed to the watchdog function is selectable from 32 kHz clock, 32 MHz clock and
FRO 1 MHz clock, This selected clock can be optionally pre-scaled before input to the
block.
• Programmable 24-bit timer with internal fixed pre-scaler
• Selectable time period
• “Safe” watchdog operation. Once enabled, requires a hardware reset or a watchdog
reset to be disabled
• Incorrect feed sequence causes immediate watchdog event if enabled
• The watchdog reload value can optionally be protected such that it can only be
changed after the “warning interrupt” time is reached
• Flag to indicate watchdog reset
• The watchdog timer can be configured to run in Deep-sleep mode
• Debug mode
8.10.3 Real-Time Clock (RTC)
The Real-Time Clock provides two timers that are typically used as a Real-Time clock
counter and a higher-resolution timer.
8.10.3.1 Features
• The RTC has the following clock inputs generated from the 32 kHz FRO or 32 kHz
XTAL:
– 1 Hz clock for RTC timing
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– 1 kHz clock for high-resolution RTC timing
• 32-bit, 1 Hz RTC counter and associated match register for alarm generation
• Separate 16-bit high-resolution/wake-up timer clocked at 1 kHz for 1 ms resolution
giving a maximum time-out period of over one minute.
• RTC alarm and high-resolution/wake-up timer time-out each generate independent
interrupt requests. Either time-out can wake up the part from Low-power modes
(Sleep mode, Deep-sleep mode or Power-down mode)
8.10.3.2 General description
The RTC contains two timers:
• Real time clock
The real-time clock is a 32-bit up-counter which can be cleared or initialized by
software. Once enabled, it counts continuously at a 1 Hz clock rate as long as the
device is powered up and the RTC remains enabled.
The main purpose of the RTC is to count seconds and generate an alarm interrupt to
the processor whenever the counter value equals the value programmed into the
associated 32-bit match register.
If the part is in one of the reduced-power modes (Sleep, Deep-sleep, Power-down) an
RTC alarm interrupt can also wake up the part to exit the Power mode and begin
normal operation.
• High-resolution/wake-up timer
The time interval required for many applications, including waking the part up from a
Low-power mode, will often demand a greater degree of resolution than the
one-second minimum interval afforded by the main RTC counter. For these
applications, a higher frequency secondary timer has been provided.
This secondary timer is an independent, stand-alone wake-up or general-purpose
timer for timing intervals of up to 64 seconds with approximately one millisecond of
resolution.
The high-resolution/wake-up timer is a 16-bit down counter which is clocked at a 1
kHz rate when it is enabled. Writing any non-zero value to this timer will automatically
enable the counter and launch a countdown sequence. When the counter is being
used as a wake-up timer, this write can occur just prior to entering a reduced power
mode.
When a starting count value is loaded, the high-resolution/wake-up timer will turn on,
count from the pre-loaded value down to zero, generate an interrupt and/or a wake-up
command, and then turn itself off until re-launched by a subsequent software write.
8.10.4 Low Power Wake-up Timers
Two low power wake-up timers are available on the JN5189, driven from the 32 kHz
internal clock. They may run in power-down mode when the majority of the rest of the
device is powered down, to time low-power periods or other long period timings that may
be required by the application. The wake-up timers do not run during deep power-down
and may optionally be disabled in power-down mode through software control. When a
wake-up timer expires, it typically generates an interrupt; if the device is in deep sleep or
power down mode then the interrupt may be used as an event to end the low power
mode. Features include:
JN5189
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• 28-bit and 41-bit down counter
• Optionally runs during power-down periods
• Clocked by 32 kHz system clock; either 32 kHz RC oscillator, or 32 kHz XTAL
oscillator
• Time-out period in excess of 1 year is possible
A wake-up timer consists of a 28-bit or 41-bit down counter clocked from the selected 32
kHz clock. An interrupt or wake-up event can be generated when the counter reaches
zero. On reaching zero, the counter will continue to count down until stopped, which
allows the latency in responding to the interrupt to be measured. If an interrupt or wake-up
event is required, the timer interrupt should be enabled before loading the count value for
the period. Once the counter value has been loaded and the counter started, the
count-down begins. The counter can be stopped at any time through software control - the
counter will remain at the value that it contained when it was stopped and no interrupt will
be generated. The status of the timers can be read to indicate if the timers are running
and/or have expired; this is useful when the timer interrupts are masked.
8.11 USART
There are 2 USART interfaces to provide Synchronous and Asynchronous serial
communications with external devices. A range of features and flexible baud rate control
supports a range of applications.
• 2 USART interfaces, 1 with flow control
• 7, 8 or 9 data bits and 1 or 2 stop bits
• Synchronous mode with master or slave operation. Includes data phase selection and
continuous clock option
• Multiprocessor/multidrop (9-bit) mode with software address compare
• RS-485 transceiver output enable
• Parity generation and checking: odd, even, or none
• Software selectable oversampling from 5 to 16 clocks in asynchronous mode
• One transmit and one receive data buffer
• The USART function supports separate transmit and receive FIFO with 4 entries each
• RTS/CTS supported on one USART. This allows for hardware signaling for automatic
flow control. Software flow control can be performed using delta CTS detect, transmit
disable control, and any GPIO as an RTS output
• Break generation and detection
• Receive data is 2 of 3 sample "voting". status flag set when one sample differs
• Built-in baud rate generator with auto-baud function
• A fractional rate divider is shared among all USARTs
• Interrupts available for FIFO receive level reached, FIFO transmit level reached,
receiver idle, change in receiver break detect, framing error, parity error, overrun,
underrun, delta CTS detect, and receiver sample noise detected
• Loopback mode for testing of data and flow control
• USART transmit and receive functions can operate with the system DMA controller
JN5189
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• Special operating mode allows operation at up to 9600 baud using the 32 kHz RTC
oscillator as the USART clock. This mode can be used, with USART0, while the
device is in Power-down mode and can wake-up the device when a character is
received
8.12 Serial Peripheral Interfaces-bus (SPI-bus)
The SPI-bus allows high-speed synchronous data transfer between the JN5189 and
peripheral devices. Two SPI-buses are supported which can independently operate as a
master or slave to support a range of system configurations.
• 2 SPI-bus interfaces: SPI0 and SPI1 can be both configured as master or slave
interfaces
• Data transmits of 1 to 16 bits supported directly. Larger frames supported by software
• The SPI-bus function supports separate transmit and receive FIFOs with 4 16-bit
entries each
• Support DMA transfers: SPIn transmit and receive functions can operate with the
system DMA controller
• Data can be transmitted to a slave without the need to read incoming data. This can
be useful while setting up an SPI-bus memory
• Up to 3 slave select input/outputs with selectable polarity and flexible usage
Remark: Texas Instruments SSI and National Microwire modes are not supported.
8.13 I2C-bus interfaces
The JN5189 supports the industry standard I2C-bus, a 2-wire synchronous serial interface
that can operate as a master or slave, providing a simple and efficient method of data
exchange between devices. The system uses serial data and clock to perform
bidirectional data transfers.
• 2 I2C-bus interfaces, one with I2C compliant IO cells
• Independent master, slave and monitor functions
• Bus speeds supported:
– Standard mode, up to 100 kbits/s
– Fast-mode, up to 400 kbits/s
– Fast-mode Plus, up to 1 Mbits/s (on specific I2C-bus pins)
– High speed mode, 3.4 Mbits/s as a slave only (on specific I2C-bus pins)
• Supports both multi-master and multi-master with slave functions
• Multiple I2C-bus slave addresses supported in hardware
• One slave address can be selectively qualified with a bit mask or an address range in
order to respond to multiple I2C-bus addresses
• 10-bit addressing supported with software assist
• Supports System Management Bus (SMBus)
• Separate DMA requests for master, slave, and monitor functions
• No chip clocks are required in order to receive and compare an address as a slave, so
this event can wake up the device from Power-down mode with I2C0
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• Automatic modes optionally allow less software overhead for some use cases
8.14 DMIC interface
The DMIC subsystem supports mono or dual-channel digital PDM microphones
Additionally, hardware voice activity detector (HWVAD), is provided to support low power
voice applications.
• DMIC (dual/stereo digital microphone interface)
– PDM (Pulse-Density Modulation) data input for left and/or right channels on 1 or 2
buses.
– Flexible decimation.
– 16 entry FIFO for each channel.
– DC blocking or unaltered DC bias can be selected.
– Data can be transferred using DMA
• HWVAD (Hardware-based voice activity detector):
– Optimized for PCM signals with 16 kHz sampling frequency.
– Configurable detection levels.
– Noise envelope estimator register output for further software analysis
8.15 12-bit general purpose ADC
The JN5189 has a 12-bit, multi-channel, general purpose ADC. Sampling is controlled by
a configurable sequencer that can support a range of sampling options. With connections
to the DMA sub-system complex applications using the ADC are possible.
• Conversion rate 100 ksamples/s for 12-bit resolution
• Single-ended analog input mode
• 8 input channels, (6 external, 1 internal temperature sensor, 1 internal supply voltage
monitoring)
• Selectable (max 32 clock-cycles) sampling time
• Power-down mode performing minimal power dissipation
• Peak to peak single-ended input range from 0 V to 3.6 V
• INL (Integral Non Linearity), full scale: 1.1 LSB typ.
• DNL (Differential Non Linearity): 0.85 LSB typ.
• ENOB (Effective Number Of Bit), 10% - 90% full scale, Fin = 25 kHz: 10.5 typ.
• SNR (Signal to Noise Ratio), Fin = 25 kHz: 65 dB typ.
• THD (Total Harmonic Distortion), 10% - 90% full scale, Fin = 25 kHz: 70 dB typ.
• SFDR (Spurious Free Dynamic Range), 10% - 90% full scale, Fin = 25 kHz: 75 dB typ.
• A sequencer to control use of ADC
– Sequencer triggered by software or PINT function, or PWM signal
– Sample any combination of the 8 ADC channels
– Digital comparator function with two pairs of configurable low and high thresholds
– Associate each ADC channel to one pair of low/high thresholds
JN5189
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– Single step and bursts
– Interrupts for data available, data overrun, threshold events
8.16 Temperature sensor
The JN5189 provides a temperature sensor which is connected to one of the ADC
channels. It provides an application with a temperature measurement.
• calibrated to give accurate measurement
• simple to use with software driver
8.17 Analog comparator
The JN5189 provides an analog comparator that can compare two device pins or one pin
against an internal reference.
• 1 analog comparator with 2 external inputs
• The negative source of the comparator can be set to an internal bandgap reference
• Can be enabled/disabled to save power
• Can be used to wake-up the device, from sleep, deep-sleep or power-down
• Rail to rail inputs
• The comparator provides 2 power modes to compromise between speed and power
consumption
• The external pins can be routed to the + or inputs of the comparator
• Hysteresis can be set to 0 mV or 40 mV
• The comparator output can be routed to an GPIO
8.18 Infra-Red Modulator
The Infra-red modulator can generate patterns suitable to drive an infra-red source, The
modulator is configurable to support several different IR protocols.
• 1 Infra-Red modulator instance
• Support Phillips RC5, RC6 & RCMM protocols
• Support SONY SIRC protocol
• Support 36 kHz sub-carrier frequency
• Support 40 kHz sub-carrier frequency
8.19 Serial Wire Debug (SWD)
Debug and trace functions are integrated into the Arm Cortex-M4. Serial wire debug and
trace functions are supported. The Arm Cortex-M4 is configured to support up to 8
breakpoints and 4 watch points.
8.19.1 Features
• Supports Arm Serial Wire Debug mode for Cortex-M4
• Trace port provides Cortex-M4 CPU instruction trace capability. Output via a serial
wire viewer
JN5189
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• Direct debug access to all memories, registers, and peripherals
• No target resources are required for the debugging session
• Breakpoints: the Cortex-M4 includes 8 instruction breakpoints that can also be used
to remap instruction addresses for code patches. Two literal comparators that can
also be used to remap addresses for patches to literal values.
• Watchpoints: the Cortex-M4 includes 4 data watchpoints that can also be used as
triggers
• Instrumentation Trace Macrocell allows additional software controlled trace for the
Cortex-M4
8.19.2 Basic configuration
The serial wire debug pins are enabled by default.
8.20 Wireless transceiver
The wireless transceiver comprises a 2.4 GHz radio, modem, a baseband processor and
PHY controller. These blocks, with protocol software provided as a library, implement an
IEEE802.15.4 standards-based wireless transceiver that transmits and receives data over
the air in the unlicensed 2.4 GHz band. To support the IEEE802.15.4 protocol an AES
engine is also provided, in the JN5189, to accelerate the required encryption features.
RADIO
AGC
IF
AMP
LNA
ADC
CALIBRATION
TRANSFORMER
REFERENCE
AND BIAS
DAC
DIVIDER
BY 2
SIGMA
DELTA
PA
PLL
Fig 5. Radio architecture
JN5189
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The main features of the radio are:
• Single ended shared RF input for receive and transmit operations
• Each power domain has its own independent LDO
• A low noise PLL serving either the receiver or the transmitter. A 2-point modulation is
used in TX
The single-ended antenna is connected to the integrated transformer. The integrated
transformer has 2 outputs, one for the receive chain one for the TX chain.
The RX chain consists in an LNA, a mixer, an IF amplifier, an anti-aliasing filter and an
ADC.
The LNA has some gain steps that are controlled by the AGC system.
The IF amplifier is the first gain stage after the mixer and provides some filtering. It has
some gain steps that are controlled by the AGC system.
The anti-aliasing filter is the main channel filter. It also provides some gain steps that are
controlled by the AGC system.
On the transmit side, the PA is built as 2 main blocks: one containing the RF pre-driver,
one containing the power amplifier. The power amplifier has its own high power LDO.
The 32 MHz crystal oscillator provides the frequency synthesizer with a reference
frequency. The synthesizer contains programmable feedback dividers, phase detector,
charge pump and internal Voltage Controlled Oscillator (VCO). The VCO has no external
components, and includes calibration circuitry to compensate for differences in internal
component values due to process and temperature variations. The VCO is controlled by a
Phase-Locked Loop (PLL) that has an internal loop filter. A programmable charge pump is
also used to tune the loop characteristic.
The radio when enabled is automatically calibrated for optimum performance.
2 DIO pins can optionally be used to provide control signals for RF circuitry (e.g. switches
and PA) in high-power range extenders. DIOx/RFTX is asserted when the radio is in the
transmit state and similarly, DIOy/RFRX is asserted when the radio is in the receiver state.
8.20.1 Radio features
• 50 single ended input (no external balun required)
• Flexible output power up to +11 dBm, programmable with 46 dB range
• IEEE 802.15.4 Sensitivity level -100 dBm
• Excellent linearity and phase noise to improve co-existence with WiFi interferences
• Ultra-fast AGC strategy
• Radio consumption in RX mode 4.3 mA
• Radio consumption in TX mode at 0 dBm: 7.36 mA
• Radio consumption in TX mode at +10 dBm: 20.28 mA
• Antenna diversity control
• Option to use one or two GPIOs to control external LNA / PA devices
JN5189
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8.20.2 Modem
IEEE 802.15.4 low power wireless MCU
JN5189(T)/JN5188(T)
The modem performs all the necessary modulation and spreading functions required for
digital transmission and reception of data at 250 kbits/s in the 2.4 GHz radio frequency
band in compliance with the IEEE802.15.4 standard.
RX
gain
Symbol
RX data
interface
Data
Conditioning
AGC
Demodulation
TX
Detection
(Despreading)
IF signal
VCO
TX data
interface
Spreading
Modulation
Sigma-delta
modulator
Fig 6. Modem system diagram
Features provided to support network channel selection algorithms include Energy
Detection (ED), Link Quality Indication (LQI) and fully programmable Clear Channel
Assessment (CCA).
The modem provides a digital Receive Signal Strength Indication (RSSI) that facilitates
the implementation of the IEEE802.15.4 ED function and LQI function. The ED and LQI
are both related to receiver power. LQI is associated with a received packet, whereas ED
is an indication of signal power-on air at a particular moment.
The CCA capability of the modem supports all modes of operation defined in the
IEEE802.15.4 standard, namely Energy above ED threshold, Carrier Sense and Carrier
Sense and/or energy above ED threshold.
8.20.3 Baseband processor
The baseband processor provides all time-critical functions of the IEEE802.15.4 MAC
layer. Dedicated hardware guarantees air interface timing is precise. The MAC layer
hardware/software partitioning enables software to implement the sequencing of events
required by the protocol and to schedule timed events with millisecond resolution, and the
hardware to implement specific events with microsecond timing resolution. The protocol
software layer performs the higher-layer aspects of the protocol, sending management
and data messages between End Device and Co-ordinator nodes, using the services
provided by the baseband processor.
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IEEE 802.15.4 low power wireless MCU
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Baseband Processor
Data Converter
Micro Interface
Packet Store
Access
Modem Data
Interface
RX PKT
Filter
Memory
Controller
FCS
Gen/
Check
AHB Master Bus
Framing
and Auto
Ack Gen
Timers
AHB Slave
Radio
Controller
Interface
Bus
Control & Status
Interrupt
Supervisor State Machine
Fig 7.
Baseband processor system diagram
8.20.3.1 Transmit
A transmission is performed by software writing the data to be transferred into the TX
frame buffer in RAM, together with parameters such as the destination address and the
number of retries allowed, as well as programming one of the protocol timers to indicate
the time at which the frame is to be sent. This time will be determined by the software
tracking the higher-layer aspects of the protocol such as superframe timing and slot
boundaries. Once the packet is prepared and protocol timer set, the supervisor block
controls the transmission. When the scheduled time arrives, the supervisor controls the
sequencing of the radio and modem to perform the type of transmission required, fetching
the packet data directly from RAM. It can perform all the algorithms required by
IEEE802.15.4 such as CSMA/CA without processor intervention including retries and
random back-offs.
When the transmission begins, the header of the frame is constructed from the
parameters programmed by the software and sent with the frame data through the
serializer to the modem. At the same time, the radio is prepared for transmission. During
the passage of the bit-stream to the modem, it passes through a CRC checksum
generator that calculates the checksum on-the-fly, and appends it to the end of the frame.
8.20.3.2 Reception
During reception, the radio is set to receive on a particular channel. On receipt of data
from the modem, the frame is directed into the RX frame buffer in RAM where both header
and frame data can be read by the protocol software. An interrupt may be provided on
receipt of the frame. An additional interrupt may be provided after the transmission of an
acknowledgement frame in response to the received frame, if an acknowledgement frame
has been requested and the auto acknowledge mechanism is enabled. As the frame data
is being received from the modem, it is passed through a checksum generator; at the end
of the reception the checksum result is compared with the checksum at the end of the
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message to ensure that the data has been received correctly. During reception, the
modem determines the Link Quality, which is made available at the end of the reception
as part of the requirements of IEEE 802.15.4.
8.20.3.3 Auto acknowledge
Part of the protocol allows for transmitted frames to be acknowledged by the destination
sending an acknowledge packet within a very short window after the transmitted frame
has been received. The baseband processor can automatically construct and send the
acknowledgment packet without processor intervention and hence avoid the protocol
software being involved in time-critical processing within the acknowledge sequence. The
baseband processor can also request an acknowledge for packets being transmitted and
handle the reception of acknowledged packets without processor intervention.
8.20.3.4 Security
The transmission and reception of secured frames using the Advanced Encryption
Standard (AES) algorithm is handled by the stack software. The baseband processor and
modem does not perform any encryption or decryption. To transmit an encrypted packet,
the data in the packet must be encrypted and written into the RAM and then the baseband
processor can be directed to transmit the encrypted data. Similarly, in receive, the
encrypted data is written into the RAM by the baseband processor. The stack software
must then perform the decryption.
The AES engine provided on chip supports hardware accelerated AES operations and
can be used by the stack software or the application.
8.20.4 Antenna diversity
Antenna diversity is a technique that maximizes the performance of an antenna system. It
allows the radio to switch between two antennas that have very low correlation between
their received signals. Typically, this is achieved by spacing two antennae around 0.25
wavelengths apart or by using two orthogonal polarizations. So, if performance is poor,
the radio system can switch to the other antenna, with a different probability of success.
In Zigbee or Thread operation, using transmit diversity mode, if a packet is transmitted
and no acknowledgment is received, the radio system can switch to the other antenna for
the retry. Alternatively, antenna diversity can be enabled so that antenna switching will
occur in receive mode when waiting for a packet. Receive diversity operates a combined
HW timer and SW power threshold mode. In general, the antenna is switched every 60
ms. However, if two preamble symbols are detected, then the antenna switching stops;
the software will check whether the signal strength exceeds a threshold. If the signal is too
weak, then the antenna selected is switched and the automatic switching will restart. If the
signal is strong, the packet reception will continue. The overall system performance
depends upon various factors such as the attenuation / isolation between the two
antennas, the RF characteristics of the signals received on each antenna.
The JN5189 provides an output (ADO) on DIO7, DIO9 or DIO19 that is asserted on odd
numbered retries and optionally its complement (ADE) on DIO6, that can be used to
control an antenna switch; this enables antenna diversity to be implemented easily (see
the following two figures).
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antenna A
A
antenna B
B
SEL
ADO
RF switch: single-pole,
double-throw (SPDT)
SELB
ADE
COM
device RF port
Fig 8. Simple antenna diversity implementation using external RF switch
ADE
ADO
TX active
RX active
st
nd
st
1
TX-RX cycle
2
TX-RX cycle (1 retry)
Fig 9. Antenna diversity ADO and ADE signals for TX with acknowledgment
If only one DIO pin can be used, then either ADE or ADO can be connected to the first
switch control pin and the same signal inverted on the second pin with an inverter on the
PCB.
8.21 AES engine
The AES provides an on-chip hardware AES encryption and decryption engine to protect
the image content and to accelerate processing for data encryption or decryption, data
integrity, and proof of origin. Data can be encrypted or decrypted by the AES engine using
the secret encrypted key in the OTP or a software supplied key
• 1 instance of Advanced Encryption Standard (AES)
• Support 128-bit keys for encryption and decryption
• Support 192-bit keys for encryption and decryption
• Support 256-bit keys for encryption and decryption
• Support for several protocols
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– ECB (Electronic Code Book)
– CBC (Cipher Block Chaining)
– CFB (Cipher Feedback)
– OFB (Output Feedback)
– CTR (Counter)
• DMA support with DMA triggers for input data and output data
8.22 SPI-bus Flash Interface (SPIFI)
The SPI-bus Flash Interface provides support for a master Quad SPI-bus capable of
interfacing to a range of SPI devices for high throughput transfer of data between the
JN5189 and an external device, such as a memory device.
• 1 Quad SPI-bus Flash Interface (SPIFI) interface to external flash.
• Supports 1-bit, 2-bit, and 4-bit bidirectional serial protocols
• Half-duplex protocol compatible with various vendors and devices
• Operates at up to 32 MHz
• DMA support for transferring data to and from the SPIFI module
8.23 Hash module
The Hash function creates a fixed size signature from a block of data. It can be used as
part of a scheme to check if data corruption has occurred.
• Support SHA-1
• Support SHA-256
• DMA support for efficient operation
8.24 ISO7816 smart card interface
The ISO smart card interface block, with suitable external analogue device, can support
Smart Card reader applications.
• Compliant with ISO7816 standard
• Support of class A (5 V), Class B (3 V) and Class C (1.8 V) contact smart cards
• Support of ISO7816 UART interface
• Supports the asynchronous protocols (T=0 and T=1) in accordance with ISO7816
• Supports synchronous cards
8.25 Random Number Generator
The JN5189 integrates a random number generator (RNG) for security purposes. The
RNG generates, with suitable software, true non-deterministic random numbers for
generating keys, initialization vectors and other random number requirements.
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8.26 NTAG I2C
See Table 2 for parts that have NTAG I2C plus device; this is the NXP device NT3H2211.
For devices supporting the internal NTAG device, two device pins are used to connect the
JN5189 to the external NFC antenna and matching components. Internally a dedicated
I2C interface is used to communicate to the NTAG tag. The NFC tag can be accessed via
the NFC antenna even when the device is not powered. One use of the feature is to allow
commissioning of a device before it is installed. The field detect line from the NTAG is able
to interrupt the processor in active mode and also cause wake-up from all power down
modes.
8.26.1 Features
• RF interface NFC forum type 2 tag compliant, operating frequency of 13.56 MHz
• Data transfer of 106 kbit/s
• Operating distance of up to 100 mm (depending on various parameters, such as field
strength and antenna geometry)
• 4 bytes (one page) written including all overhead in 4.8 ms via EEPROM or 0.8 ms via
SRAM (Pass-through mode)
• Data integrity of 16-bit CRC, parity, bit coding, bit counting
• True anticollision
• Unique 7 byte serial number (cascade level 2 according to ISO/IEC 14443-3)
• Tag Memory: 1912 bytes freely available with User Read/Write area (478 pages with 4
bytes per pages)
• Field programmable RF read-only locking function with static and dynamic lock bits
configurable from both I2C-bus and NFC interfaces
• 64 bytes SRAM volatile memory without write endurance limitation
• Data retention time of 20 years
• Write endurance 200,000 cycles
• I2C-bus slave interface supports standard (100 kHz) and Fast (up to 400 kHz) mode
• 16 bytes (one block) written in 4.5 ms (EEPROM) or 0.4 ms (SRAM - Pass-through
mode) including all overhead
• Configurable field detection pin that can be triggered upon the following events:
– A RF field presence
– The first start-of-frame
– The selection of the tag only
• 64 byte SRAM buffer for fast transfer of data (Pass-through mode) between the RF
and the I2C-bus interfaces located outside the user memory
• Wake up signal at the field detect pin when:
– New data has arrived from one interface
– Wake up possible from sleep, deep-sleep, power-down and deep power-down
– Data has been read by the receiving interface
• Clear arbitration between RF and I2C-bus interfaces:
– First come, first serve strategy
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IEEE 802.15.4 low power wireless MCU
JN5189(T)/JN5188(T)
– Status flag bits to signal if one interface is busy writing to or reading data from the
EEPROM
• Fast read command for faster data reading
• Security:
– Manufacturer-programmed 7-byte UID for each device
– Capability container with one time programmable bits
– Field programmable read-only locking function per page (per 32 pages for the
extended memory section)
– ECC-based originality signature
– 32-bit password protection to prevent unauthorized memory operations from NFC
perspective may be enabled for parts of, or complete memory
– Access to password protected data area may be restricted from I2C perspective
– Pass-through and mirror mode operation may be password protected
– Protected data can be safeguarded against limited number of negative password
authentication attempts
8.26.2 General description
The internal NTAG I2C-bus is offering a contactless interface to JN5189T/JN5188T. That
passive NFC Forum compliant contactless interface can communicate with
JN5189T/JN5188T microcontroller through a dedicated internal I2C-bus interface.
An SRAM mapped into the memory allows a fast data transfer between the NFC antenna
and the I2C-bus interface and vice versa, without the write cycle limitations of the
EEPROM memory.
The NTAG I2C-bus features a configurable field detection pin, which provides a trigger to
the microcontroller depending on the activities at the NFC interface.
Remark: To support the energy harvesting and power the platform through the NFC field,
an external NTAGPlus must be populated on the target board.
9. Application design-in information
9.1 JN5189 module reference designs
For customers wishing to integrate the JN5189 device directly into their system, NXP
provides a range of Module Reference Designs.
To ensure the correct performance, it is strongly recommended that where possible the
design details provided by the reference designs are used in their exact form for all end
designs; this includes component values, pad dimensions, track layouts etc. In order to
minimize all risks, it is recommended that the entire layout of the appropriate reference
module, if possible, be replicated in the end design.
For full details, see web site or Contact technical support.
JN5189
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9.2 Schematic diagram
The PCB schematic and layout rules detailed in this data sheet must be followed. Failure
to do so will likely result in the JN5189 failing to meet the performance specification
detailed in this data sheet and the worst case may result in the device not functioning in
the end application.
A schematic diagram of the reference module is shown in Figure 10. Details of component
values and PCB layout constraints can be found in Table 10.
The paddle should be connected directly to ground. Any pads that require connection to
ground should do so by connecting directly to the paddle.
The JN5189 will enter UART programming mode if IN System Programming Entry (PIO5)
pin 8 is low during RESET release.
The preferred communication interface is USART0 pins (PIO8/USART0_TXD pin11 and
PIO9/USART0_RXD pin12).
VBAT
VBAT (Pin 28)
LX (Pin 29)
VDDE (Pin 20)
1.9 to 3.6 V
C1
C10
C12
10 μF
47 pF
100 nF
C11
100 nF
DC/DC
CONVERTER
I/O
L4
4.7 μH
FB (Pin 31)
LA (Pin 40)
LB (Pin 39)
NFC antenna
C19
10 μF
PMU/CPU/
MEMORY
VDD_PMU (Pin 32)
JN5189T
VDD_RADIO (Pin 35)
2.4 GHz
antenna
L2
RF_IO (Pin 37)
3.3 nH
C14
C13
100 nF
47 pF
RADIO
TRANSCEIVER
R5
0 Ω
C25
2 pF
C24
1.2 pF
32 kHz
OSCILLATOR
32 MHz
OSCILLATOR
XTAL_32k_N
(Pin 34)
(Pin 33)
XTAL_32k_P
XTAL_P
(Pin 1)
XTAL_N
(Pin 2)
C20
NC
C21
NC
X2
Y1
Fig 10. Application diagram – battery powered solution
For single-ended antennas or connectors, a balun is not required. However, an external
filtering is needed. In receiver, the RFIO pin shows a 50 impedance and external
filtering (R5, C25, L2, C24) is needed in transmission to filter efficiently harmonics. These
components are critical and must be placed close to the JN5189 pins and analog ground.
The reference PCB is designed to present an accurate match to a 50 resistive network
as well as provide a DC path to the final output stage or antenna. Users wishing to match
to other active devices such as amplifiers must design their networks to match to 50 at
the output of the JN5189.
JN5189
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NXP Semiconductors
IEEE 802.15.4 low power wireless MCU
JN5189(T)/JN5188(T)
The paddle must be connected directly to the ground. Any pads that require connection to
the ground should do so by connecting directly to the paddle.
Table 10. Component descriptions about Figure 10
Component
Function
Value
RF
Note
RF filtering capacitor
1.2 pF
COG type
C24
C25
L2
RF filtering capacitor
RF filtering inductor
Optional RF tuning area
2 pF
3.3 nH
0
COG type
MURATA (LQW15AN3N3B)
R5
Not needed on ref design. Maybe needed to put an
inductor for RF path tuning
Power
10 μF
C1
Power source decoupling
Power source decoupling
Power source decoupling
DC-DC feedback filter inductor
DC-DC feedback filter capacitor
Radio and PMU decoupling
Radio and PMU decoupling
MURATA (GRM21BR71A106KA73L)
Locate less than 5mm from U1 pin 28
COG type
C10
C12
L4
100 nF
47 pF
4.7 μH
10 μF
TDK (MLZ2012M4R7H)
C19
C13
C14
C11
X7R MURATA (GRM21BR71A106KA73L)
Locate less than 5mm from U1 pins32/35
COG type
100 nF
47 pF
DigitL4 and IO power
decoupling
100 nF
Locate less than 5mm from U1 pin 20
Clock
Y1
X2
32 MHz crystal
32 MHz, 6 pF NDK (NX2016SA 32 MHZ EXS00A-CS11213 6 pF)
32.768 kHz crystal (option)
32.768 kHz, 6 NDK (NX2012SA 32.768 kHZ EXS00A-MU01089
pF
6pF)
C20-C21
optional 32.768 kHz crystal load
capacitance
NC
10. Limiting values
Table 11. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VBAT
Parameter
Conditions
Min
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
Max
3.96
3.96
1.6
Unit
V
Supply voltage DCDC input
IO supply voltage
Radio supply voltage
PMU supply voltage
IO pins voltage
VDDE
V
VDD(Radio)
VDD(PMU)
VIO
V
1.6
V
3.96
3.96
0
V
VRST
RSTN voltage
V
[1]
VRFIO
VADC
Voltage on pin RFIO
ADC pins voltage
LA and LB pin voltage
VDC
V
3.96
4.6
VLx
Vpeak
JN5189
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Table 11. Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
JN5189
JN5189T
HBM
Min
-40
-40
Max
150
Unit
C
C
V
Tstg
Storage temperature
125
[2]
[3]
VESD
Electrostatic discharge voltage
3000
500
CDM
V
[1] Primary input of RF transformer connected to the ground. No DC voltage.
[2] Testing for HBM discharge is performed as specified in JEDEC Standard JS-001.
[3] Testing for CDM discharge is performed as specified in JEDEC Standard JESD22-C101.
11. Recommended operating conditions
Table 12. Operating conditions
Symbol
VBAT
VDDE
TJ
Parameter
Conditions
Min
1.9
1.9
-40
-40
Max
3.6
Unit
V
DCDC supply voltage
IO supply voltage
JN5189 temperature
JN5189T temperature
3.6
V
125
125
C
C
TJ
TAG not activated for
Temp > 105 C
TAG activated
-40
105
C
12. Thermal characteristics
Table 13. Thermal characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rth(j-a)
Thermal resistance from junction
to ambient
28
K/W
K/W
C
Rth(j-c)
Tj(max)
Tj(max)
Thermal resistance from junction
to case
4
JN5189 maximum junction
temperature
125
125
105
JN5189T maximum junction
temperature
TAG not activated for
Temp > 105 C
C
TAG activated
C
JN5189
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13. Static characteristics
13.1 Power consumption in Low-power mode
Table 14. Typical current consumption in Low-power mode characteristics
VBAT = 1.9 V to 3.6 V, Tamb = 25 °C
Symbol Parameter Conditions
Min Typ Max Unit
IDD
supply
current
Deep power-down (everything is powered off, wake-up on HW reset
only)
250
nA
Deep power-down-IO (everything is powered
off, wake-up on HW reset only or an event on
any of the 22 GPIOs and NTAG interrupt)
350
nA
Power-down (wake-up on HW reset or an IO event, wake-up timer
ON, 32 kHz FRO on, no SRAM retention)
800
1025
1120
nA
nA
nA
Power-down-4K (wake-up on HW reset or an IO event, wake-up
timer on, 32 kHz FRO on, with 4 KB SRAM retention])
[1]
Power-down-8K (wake-up on HW reset or an IO event, wake-up
timer on, 32 kHz FRO on, with 8 KB SRAM retention)
[2]
[2]
Power down - RTC 1 kHz
200
200
200
200
300
440
nA
nA
nA
nA
nA
nA
Power down - RTC 1 Hz
Power down - per wake-up timer0 or timer1 / 32 kHz FRO
Power down - per wake-up timer0 or timer1 / 32 kHz XTAL
Power down - BOD VBAT
[2]
[2] [3]
Power down - wake up on COM interfaces
[1] Values achieved when application uses the optimized voltage configuration for power down. Any additional
4 KB RAM increases leakage current in typical condition by 105 nA.
[2] Will be added to the power down current consumption if used.
[3] Need to have retention on RAMBank7 (4 KB).
13.2 Power consumption in Active mode
Table 15. Typical current consumption in Active mode characteristics
VBAT = 1.9 V to 3.6 V, Tamb = 25 °C.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IDD
supply current
radio in RX mode (IEEE 802.15.4)
radio in TX mode (IEEE 802.15.4)
output power 0 dBm
4.3
mA
7.36
9.44
mA
mA
mA
output power +3 dBm
output power +10 dBm
20.28
JN5189
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Table 16. Typical CPU current consumption characteristics
VBAT = 1.9 V to 3.6 V, Tamb = 25 °C.
Symbol
Parameter
Conditions
Min Typ Max Unit
[1]
[1]
[1]
IDD
supply
current
Current consumption measured on VBAT; CPU core running
CoreMark from embedded Flash memory, system clock 12
MHz
1.9
2.5
2.9
mA
mA
mA
Current consumption measured on VBAT; CPU core running
CoreMark from embedded Flash memory, system clock 32
MHz
Current consumption measured on VBAT; CPU core running
CoreMark from embedded Flash memory, system clock 48
MHz
[1]
[1]
[1]
IDD(ADC)
IDD(sintf)
IDD(DMA)
ADC supply Continuous single channel acquisition at 190 KSps
current
149.7
282.7
367.9
A
A
A
SPI supply
current
SPI bus supply current; continuous transmit at 2 MHz SPI
CLK
DMA supply Continuous transfer memory to memory of buffer size 1024
current bytes
[1] Radio and Modem are powered off. FRO at 32 kHz, XO at 32 kHz and XO at 32 MHz are powered off.
FRO48M, FRO32M and FRO12M are on. Current consumption including FRO at 1 MHz, FRO at 192 MHz
and Flash read access. All unused peripheral clocks are disabled. All unused IOs are in input mode.
13.3 IO characteristics
Table 17. IO characteristics
VDD = 1.9 V to 3.6 V, Tj = -40 °C to +125 °C, unless otherwise specified.
Symbol
Parameter
Min
40
Typ
50
Max
60
Unit
k
[1]
[1]
Rpu(int)(PIO)
Internal pull-up resistance on pins PIOx
Rpu(int)(RSTN) Internal pull-up resistance on pin RSTN
40
50
60
k
Rpdn(int)(PIO)
Internal pull-down resistance on pins PIOx
40
50
60
k
IO
VIH
High-level input voltage
Low-level input voltage
0.7 *
VDDE
VDDE
V
V
VIL
0.27 *
VDDE
Output on pins PIO LS, with 1 mA load[2][4]
VOH
High-level output voltage
VDD = 3.6 V
VDD = 3.0 V
VDD = 2.4 V
VDD = 1.9 V
3.4
2.8
2.2
1.65
0
VDDE
VDDE
VDDE
VDDE
0.4
V
V
V
V
V
VOL
Low-level output voltage
Output on pins PIO LS, with 2 mA load[2][4]
VOH
High-level output voltage
VDD = 3.6 V
VDD = 3.0 V
VDD = 2.4 V
VDD = 1.9 V
3.3
2.65
2
VDDE
VDDE
VDDE
VDDE
0.4
V
V
V
V
V
1.4
0
VOL
Low-level output voltage
JN5189
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Table 17. IO characteristics …continued
VDD = 1.9 V to 3.6 V, Tj = -40 °C to +125 °C, unless otherwise specified.
Symbol Parameter
Output on pins PIO HS, with 3 mA load[3][4]
Min
Typ
Max
Unit
VOH
High-level output voltage
VDD = 3.6 V
VDD = 3.0 V
VDD = 2.4 V
VDD = 1.9 V
3.35
2.75
2.1
1.6
0
VDDE
VDDE
VDDE
VDDE
0.4
V
V
V
V
V
VOL
Low-level output voltage
Output on pins PIO HS, with 5 mA load[3][4]
VOH
High-level output voltage
VDD = 3.6 V
VDD = 3.0 V
VDD = 2.4 V
VDD = 1.9 V
3.2
2.6
2.05
1.35
0
VDDE
VDDE
VDDE
VDDE
0.4
V
V
V
V
V
VOL
Low-level output voltage
Output on pins PIO I2C, with 1 mA load[4][5]
VOH
High-level output voltage
VDD = 3.6 V
VDD = 3.0 V
VDD = 2.4 V
VDD = 1.9 V
3.45
2.82
2.30
1.52
0
VDDE
VDDE
VDDE
VDDE
0.4
V
V
V
V
V
VOL
Low-level output voltage
Output on pins PIO I2C, with 2 mA load[4][5]
VOH
High-level output voltage
VDD = 3.6 V
VDD = 3.0 V
VDD = 2.4 V
VDD = 1.9 V
3.30
2.66
2.10
1.15
0
VDDE
VDDE
VDDE
VDDE
0.4
V
V
V
V
V
VOL
Low-level output voltage
Currents
ILIL
Low-level input leakage current
High-level input leakage current
4.5
4.5
nA
nA
ILIH
[1] All PIO except RSTN (reset), PIO10 and PIO11 (I2C function).
[2] PIO 0 to 9 and 12 to 16.
[3] PIO 17 to 21.
[4] Values from simulation.
[5] PIO 10 and 11. IO cell in GPIO mode.
JN5189
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14. Dynamic characteristics
14.1 AC characteristics
14.1.1 Reset and Supply Voltage Monitor
Table 18. Externally applied reset
VDDE = 1.9 V to 3.6 V, Tj = -40 °C to +125 °C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
[1]
[2]
trst
Reset time
External reset pulse width to
initiate reset sequence
500
ns
Vrh
Reset high voltage
Reset low voltage
External threshold voltage, for
reset to be sampled high
(inactive)
0.7 x
VDDE
V
V
[2]
Vrl
External threshold voltage for
reset to be low (active)
0.7 x
VDDE
Vth(POR)
Power-on reset threshold
voltage
Rise time > 10 ms
rising
1.85
1.75
V
V
falling
tSTAB
Stabilisation time
Supply current
Time after release of reset until
application runs
1.9
ms
IDD
Chip current when held in
reset, VDDE = 3 V
132
46
A
A
Irst(bod vbat)
Brownout reset current
Chip current when held in
reset when voltage is above
power-on-reset threshold but
below brownout threshold
[3]
Vth
Threshold voltage
Supply (VBAT) threshold
voltage monitor
1.69
1.74
1.84
1.94
2.03
2.13
2.23
2.32
2.42
2.52
2.61
2.71
2.81
2.91
3.00
3.10
3.20
1.75
1.8
1.9
2
1.81
1.86
1.96
2.06
2.17
2.27
2.37
2.48
2.58
2.68
2.79
2.89
2.99
3.09
3.2
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3
3.1
3.2
3.3
3.3
3.4
JN5189
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Table 18. Externally applied reset …continued
VDDE = 1.9 V to 3.6 V, Tj = -40 °C to +125 °C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
25
Max
31.25
62.5
Unit
mV
mV
mV
mV
Vhys
Hysteresis voltage
Supply voltage (VBAT)
monitor; configurable in 4
levels
18.75
37.50
56.25
75.00
50
75
93.75
125
[3]
100
[1] Assumes internal pull-up resistor value of 100 k worst case and 5 pF external capacitance.
[2] Minimum voltage to avoid being reset.
[3] Device setting from reset
t
rst
V
rh
RST_IN
V
rl
internal RESET
t
t
STAB
STAB
Fig 11. Reset signal timing
14.1.2 Analog to Digital Converters
Table 19. Analog to Digital Converters
VDDE = 1.9 V to 3.6 V; Tj = -40 °C to +125 °C; unless otherwise specified.
Symbol
Vi
Parameter
Conditions
switchable
Min
0
Typ
Max
Unit
Input voltage
VBAT
3.62
V
FSR
IADCx
INL
Full scale range
Current on pins ADCx[1]
Integral non-linearity
Differential non-linearity
Offset error
After calibration
3.56
3.6
100
1.1
0.85
A
LSB
LSB
mV
mV
ksps
s
DNL
EO
After calibration
After calibration
Single channel
-4.5
-40
78.4
4.5
20
EG
Gain error
0
fS
Sampling frequency
Conversion time
100
10
190
tconv
Ci(a)
Analog input
capacitance
4
pF
SFDR
Spurious-free dynamic
range
For Fin = 25 kHz
75
dBc
[1] With x = 0, 1, 2, 3, 4, or 5.
JN5189
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14.1.3 Comparator
Table 20. Comparator
VDDE = 1.9 V to 3.6 V; Tj = −40 °C to +125 °C; unless otherwise specified.
Symbol
Parameter
Min
0
Typ
2
Max
Unit
s
s
mV
V
[1]
tresp
Response time -low power mode
Response time - standard mode
Hysteresis voltage
1.3
50
Vhys
Vref_ext
Vref_int
VI(cm)
External reference voltage
Internal reference voltage
Common-mode input voltage
VDDE
0.8
0.8
V
V
[1] Response time to trigger caused by square wave input.
14.1.4 32 kHz free running oscillator
Table 21. 32 kHz free running oscillator
VDDE = 1.9 V to 3.6 V; Tj = −40°C to +125°C; unless otherwise specified.
Symbol
freq
Parameter
Min
Typ
32.768
Max
Unit
kHz
%
FRO center frequency
FRO accuracy
FRO current
-2
fffro
IDD
2
200
nA
14.1.5 1 MHz free running oscillator
Table 22. 1 MHz free running oscillator
VDDE = 1.9 V to 3.6 V; Tj = −40°C to +125°C; unless otherwise specified.
Symbol
freq
Parameter
Min
Typ
1
Max
Unit
MHz
%
FRO center frequency
FRO accuracy
FRO current
fffro
IDD
-15
18
15
A
14.1.6 32 kHz crystal oscillator
Table 23. 32 kHz crystal oscillator
VDDE = 1.9 V to 3.6 V; Tj = −40°C to +125°C; unless otherwise specified.
Symbol
freq
Parameter
Min
Typ
32.768
Max
Unit
kHz
ppm
s
XTAL center frequency
XTAL accuracy
Start-up time
fffro
-500
500
tstartup
IDD
1
XTAL current
200
nA
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14.1.7 32 MHz crystal oscillator
Table 24. 32 MHz crystal oscillator
VDDE = 1.9 V to 3.6 V; Tj = −40°C to +125°C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
freq
XTAL center
frequency
32
MHz
fffro
tstartup
IDD
XTAL accuracy
Start-up time
XTAL current
-40
150
69
40
ppm
s
Time to reach 50 ppm accuracy
A
14.1.8 High-speed free running oscillator
Table 25. High-speed free running oscillator
VDDE = 1.9 V to 3.6 V; Tj = −40°C to +125°C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
48
32
12
Max
Unit
MHz
MHz
MHz
%
freq
FRO center
frequency
48 MHz clock output
32 MHz clock output
12 MHz clock output
fffro
FRO accuracy
-2
2
14.1.9 Temperature sensor
Table 26. Temperature sensor
VDDE = 1.9 V to 3.6 V; Tj = −40°C to +125°C; unless otherwise specified.
Symbol
Tsen
Parameter
Conditions
Min
Typ
Max
Unit
°C
sensor temperature range
sensor gain
40
10.12
+125
Gsen
At ADC output after conversion
LSB/°C
%
TsenSlope Temperature sensor slope After calibration at 25 °C
2.5
Tsen25
Tsen
TTN
Temperature accuracy at
25°C
2
°C
Sensor temperature
accuracy
Full range -40 to +125 °C
After calibration at 25 °C
-4.5
4.5
°C
Temperature sensor
thermal noise
0.07
°C·RMS
14.2 Flash memory
Table 27. Flash memory
VDDE = 1.9 V to 3.6 V; Tj = −40 °C to +125 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
cycles
cycles
cycles
cycles
year
[1]
[2]
[1]
[2]
Nendu
Endurance
Page erase/program
Page erase/program
Mass erase/program
Mass erase/program
Powered
100000
10000
100000
10000
10
tret
Retention time
Unpowered
10
year
JN5189
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Table 27. Flash memory
VDDE = 1.9 V to 3.6 V; Tj = −40 °C to +125 °C; unless otherwise specified.
Symbol
terase
Parameter
Conditions
Min
Typ
1.878
21
Max
Unit
ms
s
Erase time
1 Page (512 Bytes)
1 Page (512 Bytes)
1 Page (512 Bytes)
tblank
Blank status time
Programming time
tprog
1.09
ms
[1] Number of erase/program cycles, for Junction temperature range -40°C to 85°C
[2] Number of erase/program cycles, for Junction temperature range -40°C to 125°C
14.3 IO pins
Table 28. Dynamic characteristic: I/O pins[1]
VDDE = 1.9 V to 3.6 V; Tj = −40 °C to +125 °C; unless otherwise specified.
Symbol
PIO I2C[2]
tR
Parameter
Conditions
Min
Typ
Max
Unit
Rise time
Slow speed, 3.3 V
Slow speed 1.9 V
Fast speed 3.3 V
Fast speed 1.9 V
Slow speed, 3.3 V
Slow speed 1.9 V
Fast speed 3.3 V
Fast speed 1.9 V
12
14
1.7
3.2
14
18
1.1
2
22
28
5
ns
ns
ns
ns
ns
ns
ns
ns
7.5
29
34
2.6
4.7
tF
Fall time
PIO HS[3]
tR
Rise time
Fall time
Slow speed, 3.3 V
Slow speed 1.9 V
Fast speed 3.3 V
Fast speed 1.9 V
Slow speed, 3.3 V
Slow speed 1.9 V
Fast speed 3.3 V
Fast speed 1.9 V
1.6
2.4
0.8
1.2
1.1
1.6
0.6
0.9
4
6
ns
ns
ns
ns
ns
ns
ns
ns
3
4
tF
3.3
5
3
3.5
PIO LS[4][5]
tR
Rise time
Fall time
Slow speed, 3.3 V
Slow speed 1.9 V
Fast speed 3.3 V
Fast speed 1.9 V
Slow speed, 3.3 V
Slow speed 1.9 V
Fast speed 3.3 V
Fast speed 1.9 V
2.2
3.3
1.6
2.5
1.2
1.9
0.7
1.1
5
7.5
4
ns
ns
ns
ns
ns
ns
ns
ns
6.5
3.5
5
tF
3
3.5
[1] Simulated data.
[2] PIO I2C values are for PIO10 and PIO11. IO cell in GPIO mode. Slow speed is EHS=0; Fast speed is
EHS=1
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[3] Values are for PIO17-21. Slow speed is SLEW(1:0) = 00b. Fast speed is SLEW(1:0) = 11b
[4] Values are for PIO0-9 and PIO12-16. Slow speed is SLEW(1:0) = 00b. Fast speed is SLEW(1:0) = 11b
[5] Pin capacitance load = 10 pF
[6] The slew rate is configured in the IOCON block. See JN5189(T)/JN5188(T) User Manual.
VDDE
Output Signal
80%
80%
20%
20%
GND
tR
tF
Fig 12. Output timing measurement condition
14.4 Wake-up timing
Table 29. Wake-up timing
VDDE = 1.9 V to 3.6 V; Tj = −40 °C to +125 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
[1]
tstartup
CPU startup time
Time for CPU to be running application
code when VBAT > VBAT_BOD threshold
1.9
350
0.2
ms
XTAL startup time
Time to 32M XTAL ready for radio
operation
s
s
s
s
s
twake
Sleep wake-up time
Time to CPU to be running after wake-up
trigger
power-down wake-up
time
Time to CPU to be running after wake-up
trigger with RAM held
392
836
936
power-down wake-up
time
Time to CPU to be running after wake-up
trigger without RAM held
deep power-down
wake-up
Time to CPU to be running after wake-up
trigger
[1] Time to start of executing simple application.
14.5 SPI timing
Table 30. SPI master timing
VDDE = 1.9 V to 3.6 V; Tj = −40 °C to +125 °C; unless otherwise specified; CL = 10 pF balanced loading on all pins; Input slew
= 1 ns; SLEW set to standard mode for all pins; Parameters samples at the 90% and 10% level of the rising or falling edge.
Symbol
tDS
Parameter
Min
10
Typ
Max
Unit
ns
Data set-up time
Data hold time
Data output valid time
SCK frequency
tDH
5
ns
tV(Q)
-2
15
8
ns
tcy(SCK)
0.01
MHz
JN5189
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Table 30. SPI master timing
VDDE = 1.9 V to 3.6 V; Tj = −40 °C to +125 °C; unless otherwise specified; CL = 10 pF balanced loading on all pins; Input slew
= 1 ns; SLEW set to standard mode for all pins; Parameters samples at the 90% and 10% level of the rising or falling edge.
Symbol
Parameter
Min
45
1
Typ
50
Max
55
Unit
%
Duty cycle
[1]
[2]
tSS
tSH
SSEL low before SCK edge
SSEL low after last SCK edge
SCK cycles
SCK cycles
0.5
[1] Pre-delay can be configured to increase this time in steps of 1 SCK cycle
[2] Post-delay can be configured to increase this time in steps of 1 SCK cycle
Table 31. SPI slave timing
VDDE = 1.9 V to 3.6 V; Tj = −40 °C to +125 °C; unless otherwise specified; CL = 10 pF balanced loading on all pins; Input slew
= 1 ns; SLEW set to standard mode for all pins; Parameters samples at the 90% and 10% level of the rising or falling edge.
Symbol
tDS
Parameter
Min
12
5
Typ
Max
35
8
Unit
ns
Data set-up time
tDH
Data hold time
ns
tV(Q)
tcy(SCK)
tSS
Data output valid time
SCK frequency
0
ns
1
MHz
ns
[1]
[2]
SSEL low before SCK edge
SSEL low after last SCK edge
tSH
0.5
ns
[1] Pre-delay can be configured to increase this time in steps of 1 SCK cycle
[2] Post-delay can be configured to increase this time in steps of 1 SCK cycle
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IEEE 802.15.4 low power wireless MCU
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T
cy(clk)
SCK (CPOL = 0)
SCK (CPOL = 1)
t
t
SS
SH
SSEL
MOSI (CPHA = 0)
MISO (CPHA = 0)
t
t
v(Q)
v(Q)
IDLE
IDLE
DATA VALID (MSB)
DATA VALID
DATA VALID (MSB)
DATA VALID (MSB)
DATA VALID (LSB)
t
t
DH
DS
DATA VALID (MSB)
DATA VALID
DATA VALID (LSB)
MOSI (CPHA = 1)
MISO (CPHA = 1)
t
t
v(Q)
v(Q)
DATA VALID
DATA VALID (MSB)
DATA VALID (MSB)
IDLE
IDLE
DATA VALID (LSB)
t
t
DH
DS
DATA VALID (MSB)
DATA VALID (LSB)
DATA VALID
DATA VALID (MSB)
Fig 13. SPI master interface timings
JN5189
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IEEE 802.15.4 low power wireless MCU
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T
cy(clk)
SCK (CPOL = 0)
SCK (CPOL = 1)
t
t
SH
SS
SSEL
MISO (CPHA = 0)
MOSI (CPHA = 0)
t
t
v(Q)
v(Q)
IDLE
IDLE
DATA VALID (MSB)
DATA VALID
DATA VALID (MSB)
DATA VALID (MSB)
DATA VALID (LSB)
t
t
DH
DS
DATA VALID (MSB)
DATA VALID
DATA VALID (LSB)
MISO (CPHA = 1)
MOSI (CPHA = 1)
t
t
v(Q)
v(Q)
DATA VALID (MSB)
DATA VALID (MSB)
DATA VALID
DATA VALID (LSB)
IDLE
IDLE
t
t
DH
DS
DATA VALID (MSB)
DATA VALID (LSB)
DATA VALID
DATA VALID (MSB)
Fig 14. SPI slave interface timings
14.6 USART timing
Table 32. USART master timing (in synchronous mode)
VDDE = 1.9 V to 3.6 V; Tj = −40 °C to +125 °C; unless otherwise specified; CL = 30 pF balanced loading on all pins; Input slew
= 1 ns; SLEW set to standard mode for all pins; Parameters samples at the 90% and 10% level of the rising or falling edge.
Symbol
tSU(D)
Parameter
Min
45
5
Typ
Max
Unit
ns
Data set-up time
Data hold time
th(D)
ns
tV(Q)
Data output valid time
SCLK frequency
0
25
5
ns
tcy(SCLK)
MHz
Table 33. USART slave timing (in synchronous mode)
VDDE = 1.9 V to 3.6 V; Tj = −40 °C to +125 °C; unless otherwise specified; CL = 30 pF balanced loading on all pins; Input slew
= 1 ns; SLEW set to standard mode for all pins; Parameters samples at the 90% and 10% level of the rising or falling edge.
Symbol
tSU(D)
Parameter
Min
5
Typ
Max
Unit
ns
Data set-up time
Data hold time
th(D)
5
ns
tV(Q)
Data output valid time
SCLK frequency
0
55
5
ns
tcy(SCLK)
MHz
JN5189
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T
cy(clk)
Un_SCLK (CLKPOL = 0)
Un_SCLK (CLKPOL = 1)
TXD
t
t
vQ)
v(Q)
START
BIT0
BIT1
t
t
su(D) h(D)
BIT1
START
RXD
BIT0
Fig 15. USART interface timings
14.7 SPIFI timing
Table 34. SPIFI timing
VDDE = 1.9 V to 3.6 V; Tj = −40 °C to +125 °C; unless otherwise specified; CL = 10 pF balanced loading on all pins; EHS=1
for all pins; Parameters samples at the 90% and 10% level of the rising or falling edge; simulated values.
Symbol
tcy(clk)
tDS
Parameter
Min
30.0
3
Typ
Max
5
Unit
Clock cycle time
Data set-up time
Data hold time
ns
ns
tDH
3
ns
tV(Q)
Data output valid time
Data output hold time
Duty cycle
ns
tH(Q)
-10.5
40
60
ns
%
tSS
tSH
SSEL set-up time, time SSEL is low
before first SCK edge
0.5
SCK cycles
SSEL hold time, time SSEL is low after
last SCK
0.5
SCK cycles
JN5189
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IEEE 802.15.4 low power wireless MCU
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SPIFI_SSEL
SPIFI_SCK
T
cy(clk)
t
SH
t
SS
t
t
h(Q)
v(Q)
DATA VALID
DATA VALID
SPIFI data out
SPIFI data in
t
t
DH
DS
DATA VALID
DATA VALID
Fig 16. SPIFI interface timings
14.8 PWM timing
Table 35. PWM timing
VDDE = 1.9 V to 3.6 V; Tj = −40 °C to +125 °C; unless otherwise specified; CL = 10 pF balanced loading on all pins; Input slew
= 1ns; SLEW set to standard mode for all pins; parameters samples at the 90% and 10% level of the rising or falling edge;
simulated skew (over process, voltage and temperature) of any two PWM output signals; values guaranteed by design.
Symbol
Parameter
Min
Typ
Max
Unit
tSK
Output skew time
0
10
ns
14.9 DMIC timing
Table 36. DMIC timing
VDDE = 1.9 V to 3.6 V; Tj = −40 °C to +125 °C; unless otherwise specified; CL = 10 pF balanced loading on all pins; Input slew
= 1ns; SLEW set to standard mode for all pins; parameters samples at the 90% and 10% level of the rising or falling edge;
bypass bit = 0; based on simulated values and for 1.9 V to 3.6 V.
Symbol
Parameter
Conditions
Min
Typ
Max
2
Unit
MHz
%
tcy(SCK)
DMIC CLK frequency
Duty cycle
CL = 10 pF using 32MHz XTAL clock
source
48
52
tDS
tDH
Data set-up time
Data hold time
25
1
ns
ns
JN5189
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CLOCK
t
DH
t
SU
DATA
Fig 17. DMIC interface timings
14.10 ISO7816
Table 37. Clock of ISO7816
VDDE = 1.9 V to 3.6 V; Tj = −40 °C to +125 °C; unless otherwise specified; guaranteed by design; Not tested in production.
Symbol
VOH
Parameter
Min
Typ
Max
VBAT
Unit
V
High-level output voltage
Low-level output voltage
Duty cycle
0.7 x VBAT
VOL
0
48
2
0.3 x VBAT
52
V
%
Freq
CLK frequency
12
MHz
Table 38. Input output of ISO7816
VDDE = 1.9 V to 3.6 V; Tj = −40 °C to +125 °C; unless otherwise specified; guaranteed by design; Not tested in production.
Symbol
VOH
VOL
VIH
Parameter
Conditions
Min
Typ
Max
VBAT
Unit
V
High-level output voltage CL = 10 pF
Low-level output voltage CL = 10 pF
High-level input voltage
0.7 x VBAT
0
0.3 x VBAT
VBAT + 0.1
0.3
V
0.75 x VBAT
V
VIL
Low-level input voltage For VBAT from 0 V to 3.6 V
High-level output current
0
10
V
IOH
1000
A
A
s
IOL
Low-level output current
600
1000
tr(O)
Output rise time
CL= 30 pF; 10 % to 90 %;
0 V to VBAT
1.2
tf(O)
Output fall time
CL= 30 pF; 10 % to 90 %;
0 V to VBAT
1.2
s
tr(I)
tf(I)
Input rise time
Input fall time
100
100
ns
ns
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14.11 I2C timing
Table 39. I2C timing
VDDE = 1.9 V to 3.6 V; Tj = −40°C to +125°C; unless otherwise specified; guaranteed by design. Not tested in production.
Symbol
Parameter
Conditions
Min
0
Typ
Max
100
400
1
Unit
kHz
kHz
MHz
ns
fSCL
SC clock frequency
Standard-mode
Fast-mode
0
Fast-mode plus
0
tf
Fall time, of both SDA and Standard-mode
SCL signals
300
300
120
[8]
Fast-mode
20 x VDDE/5.5
ns
Fast-mode plus
4.7
1.3
0.5
4
ns
tLOW
tHIGH
tHD;DAT
tSU;DAT
Low period of the SCL
clock
Standard-mode
Fast-mode
s
s
Fast-mode plus
Standard-mode
Fast-mode
s
High period of the SCL
clock
s
0.6
0.26
0
s
Fast-mode plus
Standard-mode
Fast-mode
s
Data hold time
Data setup time
ns
0
ns
Fast-mode plus
Standard-mode
Fast-mode
0
ns
250
100
50
ns
ns
Fast-mode plus
ns
[1] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission
and the acknowledge.
[2] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the
VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.
[3] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA
output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the
SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf.
[4] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors
are used, designers should allow for this when considering bus timing.
[5] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less
than the maximum of tVD;DAT or tVD;ACK by a transition time. This maximum must only be met if the device
does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be
valid by the set-up time before it releases the clock.
[6] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in
transmission and the acknowledge.
[7] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT
= 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW
period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the
next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode
I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up
time.
[8] Valid for I2C IO cells. When I2C functionality is supported on standard IO cells this Min time is 0.
JN5189
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IEEE 802.15.4 low power wireless MCU
JN5189(T)/JN5188(T)
t
f
t
SU;DAT
70 %
30 %
70 %
30 %
SDA
SCL
t
HD;DAT
t
f
t
HIGH
70 %
30 %
70 %
30 %
70 %
30 %
70 %
30 %
t
LOW
1 / f
SCL
S
Fig 18. I2C interface timings
14.12 GPIO pin timing
Table 40. GPIO pin timing
VDDE = 1.9 V to 3.6 V; Tj = −40 °C to +125 °C; unless otherwise specified; Input slew = 1 ns; parameters samples at the 90%
and 10% level of the rising or falling edge.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
[1]
[2]
GPIO pin interrupt pulse
width (digital glitch filter
disabled) - Synchronous
path
1.5
Bus
clock
cycles
[3]
GPIO pin interrupt pulse
width (digital glitch
filterdisabled) -
20
ns
Asynchronous path
[1] This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry in run
modes (Min CPU clock at 12 MHz)
[2] The greater of synchronous and asynchronous timing must be met
[3] This is the minimum pulse width that is guaranteed to be recognized
14.13 Radio transceiver
This JN5189 meets all the requirements of the IEEE 802.15.4 standard over 1.9 V to 3.6 V
and offers the improved RF characteristics shown in Table 42. All RF characteristics are
measured single ended.
This part also meets the following regulatory body approvals, when used with NXP’s
Module Reference Designs. Compliant with FCC part 15 rules, IC Canada and ETSI ETS
300-328, refer to the JN5189 Module Reference Design package on the Wireless
Connectivity area of the NXP web site Ref. 2.
The PCB schematic and layout rules detailed in Section 9 “Application design-in
information” must be followed. Failure to do so will likely result in the JN5189 failing to
meet the performance specification detailed herein and worst case may result in device
not functioning in the end application.
Table 41. RF port characteristics
Single-ended; Impedance = 50 Ω; VDD = 1.9 V to 3.6 V; Tj = -40°C to +125°C; unless otherwise specified.
Symbol
Parameter
Min
Typ
Max
Unit
Frange
Frequency range
2.4
2.485
GHz
JN5189
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Product data sheet
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NXP Semiconductors
IEEE 802.15.4 low power wireless MCU
JN5189(T)/JN5188(T)
Table 42. Radio transceiver characteristics: +25 °C
VDD = 1.9 V to 3.6 V; unless otherwise specified.
Symbol
Receiver
SRX
Parameter
Conditions
Min
Typ
Max
Unit
Receiver sensitivity
Noise Figure
1 % PER, as per IEEE 802.15.4
Max gain
99.7
7.3
10
dBm
dB
[1]
[2]
NF
PinMaxRX
Maximum receiver input 1 % PER, measured as sensitivity
power
dBm
Coch
Co-channel Interference 1 % PER, with wanted signal 3 dB above
-2.1
dB
rejection
sensitivity as per IEEE 802.15.4
Adjacent -5 MHz
Adjacent +5 MHz
Alternate -10 MHz
Alternate +10 MHz
-15 MHz
Rej-5M
Interference rejection,
1% PER, with wanted
signal 3 dB above
sensitivity as per IEEE
802.15.4[2]
35.6
36
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Rej+5M
Rej-10M
Rej+10M
Rej-15M
Rej+15M
46.3
46.7
51.5
52.3
57.1
59.6
62.1
62.7
58
+15 MHz
RejProp-5M Proprietary mode
Adjacent -5 MHz
Adjacent +5 MHz
Alternate -10 MHz
Alternate +10 MHz
-15 MHz
interference rejection.
1% PER, with wanted
signal 3 dB above
sensitivity as per IEEE
802.15.4[3]
RejProp+5M
RejProp-10M
RejProp+10M
RejProp-15M
RejProp+15M
RejCW-5M
+15 MHz
60.8
59
CW interference
Adjacent -5 MHz
Adjacent +5 MHz
Alternate -10 MHz
Alternate +10 MHz
-15 MHz
rejection. 1% PER, with
wanted signal 3 dB
above sensitivity as per
IEEE 802.15.4[4]
RejCW+5M
RejCW-10M
RejCW+10M
RejCW-15M
RejCW+15M
RejOOB
59.7
62
62.6
61.1
61.5
61.6
+15 MHz
Out-of-band rejection
1 % PER with wanted signal 3 dB above
sensitivity, CW interferers at 868 MHz (KNX),
RF/2, 2100 MHz (WCDMA), 2500 MHz
(LTE), or RF/3 (3GPP-Japan)
[5]
[5]
IMP2,4
IMP3,6
Inter-modulation
protection
1% PER with wanted signal 3 dB above
sensitivity, modulated interferers at 2 and 4
channels separation
44
dB
dB
1% PER with wanted signal 3 dB above
sensitivity, modulated interferers at 3 and 6
channels separation
46.5
JN5189
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NXP Semiconductors
IEEE 802.15.4 low power wireless MCU
JN5189(T)/JN5188(T)
Table 42. Radio transceiver characteristics: +25 °C …continued
VDD = 1.9 V to 3.6 V; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
PinBlockin Blocking input power
g
Desired channel IEEE 802.15.4, level =
measured sensitivity + 6dB, channels 11 &
26. Unwanted channel CW at 2380 MHz or
2503.5 MHz
-20.6
dBm
Desired channel IEEE 802.15.4, level =
measured sensitivity + 6dB, channels 11 &
26. Unwanted channel CW at 2300 MHz,
2330 MHz & 2360 MHz
-19.5
-18.7
dBm
dBm
Desired channel IEEE 802.15.4, level =
measured sensitivity + 6dB, channels 11 &
26. Unwanted channel CW at 2523.5 MHz,
2553.5 MHZ, 2583.5 MHz, 2613.5 MHz,
2643.5 MHz, 2673.5 MHz
[6]
RSSIvar
PspRX
RSSI variation
Desired channel IEEE 802.15.4, over the
RSSI range -100 dBm to 8 dBm
2
dB
Receiver spurious
emission, measured
30 MHz to 1 GHz, 100 kHz RBW, 300 kHz
VBW, Filter type 3 dB (Gaussian), Peak
-87.1
dBm
conducted into 50 ohms detector, Trace Mode Max hold
1 GHz to 12.75 GHz, 1 MHz RBW, 3MHz
VBW, Filter type 3dB (Gaussian), Peak
detector, Trace mode Max hold
-70.9
dBm
LOLeakRX Local oscillator leakage
power
-98
dBm
dB
RejWIFI
WIFI rejection
1% PER, with wanted signal IEEE 802.15.4
-75 dBm 2470 MHz, WIFI signal IEEE
802.11n 2447 MHz (20MHz mode)
55.6
Transmitter
PoutMax
Pout
Maximum output power
11.2
dBm
dBm
Output power +10 dBm In-band tilt
accuracy
9.9
0.3
PoutRange
Output power control
range
45.7
dB
EVM
Error vector magnitude With IEEE 802.15.4 channel at +10 dBm
6.3
%
%
OEVM
Offset error vector
magnitude
With IEEE 802.15.4 channel at +10 dBm
0.33
EVMProp
Error Vector Magnitude With proprietary mode at +10 dBm
23.2
3.2
%
%
OEVMProp Offset error Vector
Magnitude
With proprietary mode at +10 dBm
PSD
Power spectral density
Relative density at greater than 3.5 MHz
offset as per IEEE 802.15.4 at +10 dBm
-37.4
-38.2
dBc
Absolute density at greater than 3.5 MHz
offset at +10 dBm as per IEEE 802.15.4 at
+10 dBm
dBm
PSDProp
Proprietary mode power Relative density at greater than 3.5 MHz
-61.2
-62.2
dBc
spectral density
offset with proprietary mode at +10 dBm
Absolute density at greater than 3.5 MHz
offset with proprietary mode at +10 dBm
dBm
JN5189
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Product data sheet
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70 of 92
NXP Semiconductors
IEEE 802.15.4 low power wireless MCU
JN5189(T)/JN5188(T)
Table 42. Radio transceiver characteristics: +25 °C …continued
VDD = 1.9 V to 3.6 V; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
TXH2
2nd Harmonic of
Transmit Carrier
Frequency
With IEEE 802.15.4 channel at +10 dBm
-62.4
dBm/
MHz
TXH3
3rd Harmonic of
Transmit Carrier
Frequency
With IEEE 802.15.4 channel at +10 dBm
-73
dBm/
MHz
PspTX
Transmitter spurious
emission, measured
conducted into 50 ohms
30 MHz to 1 GHz, Peak detector, RBW=100
kHz
-80
dBm
dBm
dBm
1 GHz to 26 GHz, Peak detector, RBW
1MHz, based on FCC at +10 dBm
-22.1
-37.1
1 GHz to 26 GHz, Peak detector, RBW
1MHz, based on FCC with proprietary mode
at +10 dBm
1 GHz to 12.75 GHz, Peak detector, RBW
1MHz, based on ETSI at +10 dBm
-39.8
-44
dBm
dBm
1 GHz to 12.75 GHz, Peak detector, RBW
1MHz, based on ETSI with proprietary mode
at +10 dBm
1 GHz to 26 GHz, Average detector, RBW =
1 MHz, based on FCC at +10 dBm
-27.9
-45.3
dBm
dBm
1 GHz to 26 GHz, Average detector, RBW =
1 MHz with proprietary mode, based on FCC
at +10 dBm
Transmitter spurious
emission, ETSI
exceptions
1.8 GHz to 1.9 GHz
5.15 GHz to 5.3 GHz
-64.3
-67.3
dBm
dBm
[1] Considering an integrated BW of 2 MHz, and a minimum SNR of 4 dB for the demodulator.
[2] Interference rejection is defined as the value, when 1 % PER is seen with the wanted signal 3 dB above
sensitivity, with a modulated interferer as per IEEE 802.15.4.
[3] Proprietary mode interference rejection is defined as the value, when 1 % PER is seen with the wanted
signal 3 dB above sensitivity, with a proprietary mode interferer.
[4] CW Interference rejection is defined as the value, when 1 % PER is seen with the wanted signal 3 dB
above sensitivity, with a CW interferer.
[5] The intermodulation protection level is the difference between the wanted channel power and one of the
two interferers power. Both interferers are modulated as per IEEE 802.15.4 and have the same power.
[6] This RSSI variation over temperature is obtained with the use of the embedded thermometer and the
integrated API (see application note).
Table 43. Radio transceiver characteristics: -40 °C
VDD = 1.9 V to 3.6 V; unless otherwise specified.
Symbol
Receiver
SRX
Parameter
Conditions
Min
Typ
Max
Unit
Receiver sensitivity
Noise Figure
1 % PER, as per IEEE 802.15.4
Max gain
101.3
5.7
10
dBm
dB
[1]
NF
PinMaxRX
Maximum receiver input 1 % PER, measured as sensitivity
power
dBm
JN5189
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Product data sheet
Rev. 1.2 — June 2020
71 of 92
NXP Semiconductors
IEEE 802.15.4 low power wireless MCU
JN5189(T)/JN5188(T)
Table 43. Radio transceiver characteristics: -40 °C …continued
VDD = 1.9 V to 3.6 V; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
[2]
Coch
Co-channel Interference 1 % PER, with wanted signal 3 dB, above
-2
dB
rejection
sensitivity as per IEEE 802.15.4
Adjacent -5 MHz
Adjacent +5 MHz
Alternate -10 MHz
Alternate +10 MHz
-15 MHz
Rej-5M
Interference rejection,
1% PER, with wanted
signal 3 dB above
sensitivity as per IEEE
802.15.4[2]
35.9
35.8
46.5
46.6
51.6
52.1
56.4
60.4
60.6
61.3
56.5
59.2
56.8
60.4
60.4
60.9
59.9
60.7
61.7
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Rej+5M
Rej-10M
Rej+10M
Rej-15M
Rej+15M
+15 MHz
RejProp-5M Proprietary mode
Adjacent -5 MHz
Adjacent +5 MHz
Alternate -10 MHz
Alternate +10 MHz
-15 MHz
interference rejection.
1% PER, with wanted
signal 3 dB above
sensitivity as per IEEE
802.15.4[3]
RejProp+5M
RejProp-10M
RejProp+10M
RejProp-15M
RejProp+15M
RejCW-5M
+15 MHz
CW interference
Adjacent -5 MHz
Adjacent +5 MHz
Alternate -10 MHz
Alternate +10 MHz
-15 MHz
rejection. 1% PER, with
wanted signal 3 dB
above sensitivity as per
IEEE 802.15.4[4]
RejCW+5M
RejCW-10M
RejCW+10M
RejCW-15M
RejCW+15M
RejOOB
+15 MHz
Out-of-band rejection
1 % PER with wanted signal 3 dB above
sensitivity, CW interferers at 868 MHz
(KNX), RF/2, 2100 MHz (WCDMA), 2500
MHz (LTE), or RF/3 (3GPP-Japan)
[5]
[5]
IMP2,4
IMP3,6
Inter-modulation
protection
1% PER with wanted signal 3 dB above
sensitivity, modulated interferers at 2 and
4 channels separation
42.5
46.5
-22
dB
dB
1% PER with wanted signal 3 dB above
sensitivity, modulated interferers at 3 and
6 channels separation
PinBlockin Blocking input power
g
Desired channel IEEE 802.15.4, level =
measured sensitivity + 6dB, channels 11
& 26. Unwanted channel CW at 2380
MHz or 2503.5 MHz
dBm
Desired channel IEEE 802.15.4, level =
measured sensitivity + 6dB, channels 11
& 26. Unwanted channel CW at 2300
MHz, 2330 MHz & 2360 MHz
-21.2
-20.4
dBm
dBm
Desired channel IEEE 802.15.4, level =
measured sensitivity + 6dB, channels 11
& 26. Unwanted channel CW at 2523.5
MHz, 2553.5 MHZ, 2583.5 MHz, 2613.5
MHz, 2643.5 MHz, 2673.5 MHz
[6]
RSSIvar
RSSI variation
Desired channel IEEE 802.15.4, over the
RSSI range -101 dBm to +9 dBm
2
dB
JN5189
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Product data sheet
Rev. 1.2 — June 2020
72 of 92
NXP Semiconductors
IEEE 802.15.4 low power wireless MCU
JN5189(T)/JN5188(T)
Table 43. Radio transceiver characteristics: -40 °C …continued
VDD = 1.9 V to 3.6 V; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
PspRX
Receiver spurious
emission, measured
30 MHz to 1 GHz, 100 kHz RBW, 300
kHz VBW, Filter type 3 dB (Gaussian),
-83.3
dBm
conducted into 50 ohms Peak detector, Trace Mode Max hold
1 GHz to 12.75 GHz, 1 MHz RBW, 3MHz
VBW, Filter type 3dB (Gaussian), Peak
detector, Trace mode Max hold
-62.7
dBm
LOLeakRX Local oscillator leakage
power
-98
dBm
dB
RejWIFI
WIFI rejection
1 % PER, with wanted signal IEEE
53.7
802.15.4 -75 dBm 2470 MHz, WIFI signal
IEEE 802.11n 2447 MHz (20MHz mode)
Transmitter
PoutMax
Pout
Maximum output power
11.5
dBm
dBm
Output power +10 dBm In-band tilt
accuracy
10.2
0.3
PoutRange
Output power control
range
45.7
dB
EVM
Error vector magnitude With IEEE 802.15.4 channel at +10 dBm
6.6
%
%
OEVM
Offset error vector
magnitude
With IEEE 802.15.4 channel at +10 dBm
0.36
EVMProp
Error Vector Magnitude With proprietary mode at +10 dBm
22.5
3.1
%
%
OEVMProp Offset error Vector
Magnitude
With proprietary mode at +10 dBm
PSD
Power spectral density
Relative density at greater than 3.5 MHz
offset as per IEEE 802.15.4 at +10 dBm
-37.3
-37.7
dBc
Absolute density at greater than 3.5 MHz
offset at +10 dBm as per IEEE 802.15.4
at +10 dBm
dBm
PSDProp
Proprietary mode power Relative density at greater than 3.5 MHz
-61.2
-61.9
-61.6
dBc
spectral density
offset with proprietary mode at +10 dBm
Absolute density at greater than 3.5 MHz
offset with proprietary mode at +10 dBm
dBm
TXH2
TXH3
2nd Harmonic of
Transmit Carrier
Frequency
With IEEE 802.15.4 channel at +10 dBm
dBm/
MHz
3rd Harmonic of
Transmit Carrier
Frequency
With IEEE 802.15.4 channel at +10 dBm
-73
dBm/
MHz
JN5189
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Product data sheet
Rev. 1.2 — June 2020
73 of 92
NXP Semiconductors
IEEE 802.15.4 low power wireless MCU
JN5189(T)/JN5188(T)
Table 43. Radio transceiver characteristics: -40 °C …continued
VDD = 1.9 V to 3.6 V; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
PspTX
Transmitter spurious
emission, measured
conducted into 50 ohms
30 MHz to 1 GHz, Peak detector,
RBW=100kHz
-76.7
dBm
1 GHz to 26 GHz, Peak detector, RBW
1MHz, based on FCC at +10 dBm
-21.6
-37.3
dBm
dBm
1 GHz to 26 GHz, Peak detector, RBW
1MHz, based on FCC with proprietary
mode at +10 dBm
1 GHz to 12.75 GHz, Peak detector,
RBW 1MHz, based on ETSI at +10 dBm
-39.6
-44
dBm
dBm
1 GHz to 12.75 GHz, Peak detector,
RBW 1MHz, based on ETSI with
proprietary mode at +10 dBm
1 GHz to 26 GHz, Average detector,
RBW = 1 MHz, based on FCC at +10
dBm
-27.3
-46.1
dBm
dBm
1 GHz to 26 GHz, Average detector,
RBW = 1 MHz with proprietary mode,
based on FCC at +10 dBm
Transmitter spurious
emission, ETSI
exceptions
1.8 GHz to 1.9 GHz
5.15 GHz to 5.3 GHz
-63.9
-66.4
dBm
dBm
[1] Considering an integrated BW of 2 MHz, and a minimum SNR of 4 dB for the demodulator.
[2] Interference rejection is defined as the value, when 1% PER is seen with the wanted signal 3 dB above
sensitivity, with a modulated interferer as per IEEE 802.15.4.
[3] Proprietary mode interference rejection is defined as the value, when 1 % PER is seen with the wanted
signal 3 dB above sensitivity, with a proprietary mode interferer.
[4] CW Interference rejection is defined as the value, when 1 % PER is seen with the wanted signal 3 dB
above sensitivity, with a CW interferer.
[5] The intermodulation protection level is the difference between the wanted channel power and one of the
two interferers power. Both interferers are modulated as per IEEE 802.15.4 and have the same power.
[6] This RSSI variation over temperature is obtained with the use of the embedded thermometer and the
integrated API (see application note).
Table 44. Radio transceiver characteristics: +125 °C
VDD = 1.9 V to 3.6 V; unless otherwise specified.
Symbol
Receiver
SRX
Parameter
Conditions
Min
Typ
Max
Unit
receiver sensitivity
Noise Figure
1 % PER, as per IEEE
802.15.4
97.1
dBm
[1]
[2]
NF
Max gain
9.9
dB
PinMaxRX
Maximum receiver input
power
1 % PER, measured as
sensitivity
10
dBm
Coch
Co-channel Interference
rejection
1 % PER, with wanted
signal 3 dB, above
sensitivity as per IEEE
802.15.4
-2.4
dB
JN5189
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Product data sheet
Rev. 1.2 — June 2020
74 of 92
NXP Semiconductors
IEEE 802.15.4 low power wireless MCU
JN5189(T)/JN5188(T)
Table 44. Radio transceiver characteristics: +125 °C …continued
VDD = 1.9 V to 3.6 V; unless otherwise specified.
Symbol
Rej-5M
Parameter
Conditions
Min
Typ
35.4
35.8
46.3
46.5
51.7
52.1
54.7
56.8
59.9
63.3
60.3
65.4
56.1
57.6
62.9
64
Max
Unit
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Interference rejection, 1%
PER, with wanted signal 3 dB
above sensitivity as per IEEE
802.15.4[2]
Adjacent -5 MHz
Adjacent +5 MHz
Alternate -10 MHz
Alternate +10 MHz
-15 MHz
Rej+5M
Rej-10M
Rej+10M
Rej-15M
Rej+15M
+15 MHz
RejProp-5M
RejProp+5M
RejProp-10M
RejProp+10M
RejProp-15M
RejProp+15M
RejCW-5M
RejCW+5M
RejCW-10M
RejCW+10M
RejCW-15M
RejCW+15M
RejOOB
Proprietary mode
Adjacent -5 MHz
Adjacent +5 MHz
Alternate -10 MHz
Alternate +10 MHz
-15 MHz
interference rejection. 1%
PER, with wanted signal 3 dB
above sensitivity as per IEEE
802.15.4[3]
+15 MHz
CW interference rejection.
1% PER, with wanted signal
3 dB above sensitivity as per
IEEE 802.15.4[4]
Adjacent -5 MHz
Adjacent +5 MHz
Alternate -10 MHz
Alternate +10 MHz
-15 MHz
62.3
65.3
60.8
+15 MHz
Out-of-band rejection
1 % PER with wanted
signal 3 dB above
sensitivity, CW
interferers at 868 MHz
(KNX), RF/2, 2100 MHz
(WCDMA), 2500 MHz
(LTE), or RF/3
(3GPP-Japan)
[5]
[5]
IMP2,4
IMP3,6
Inter-modulation protection
1% PER with wanted
signal 3 dB above
sensitivity, modulated
interferers at 2 and 4
channels separation
44.8
47
dB
dB
1% PER with wanted
signal 3 dB above
sensitivity, modulated
interferers at 3 and 6
channels separation
JN5189
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© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 1.2 — June 2020
75 of 92
NXP Semiconductors
IEEE 802.15.4 low power wireless MCU
JN5189(T)/JN5188(T)
Table 44. Radio transceiver characteristics: +125 °C …continued
VDD = 1.9 V to 3.6 V; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
PinBlocking
Blocking input power
Desired channel IEEE
802.15.4, level =
-20
dBm
measured sensitivity + 6
dB, channels 11 & 26.
Unwanted channel CW
at 2380 MHz or 2503.5
MHz
Desired channel IEEE
802.15.4, level =
-17.2
-16.3
dBm
dBm
measured sensitivity + 6
dB, channels 11 & 26.
Unwanted channel CW
at 2300 MHz, 2330 MHz
& 2360 MHz
Desired channel IEEE
802.15.4, level =
measured sensitivity +
6dB, channels 11 & 26.
Unwanted channel CW
at 2523.5 MHz, 2553.5
MHZ, 2583.5 MHz,
2613.5 MHz, 2643.5
MHz, 2673.5 MHz
[6]
RSSIvar
PspRX
RSSI variation
Desired channel IEEE
802.15.4, over the RSSI
range -97 dBm to +5
dBm
2
dB
Receiver spurious emission, 30 MHz to 1 GHz, 100
Measured conducted into 50 kHz RBW, 300 kHz
-87.7
dBm
ohms
VBW, Filter type 3 dB
(Gaussian), Peak
detector, Trace Mode
Max hold
1 GHz to 12.75 GHz, 1
MHz RBW, 3MHz VBW,
Filter type 3dB
-64.9
dBm
(Gaussian), Peak
detector, Trace mode
Max hold
LOLeakRX
RejWIFI
Local oscillator leakage
power
-98
dBm
dB
WIFI rejection
1 % PER, with wanted
signal IEEE 802.15.4
-75 dBm 2470 MHz,
WIFI signal IEEE
51.1
802.11n 2447 MHz
(20MHz mode)
Transmitter
PoutMax
Pout
Maximum output power
10.4
dBm
dBm
Output power +10 dBm
accuracy
In-band tilt
9.1 0.4
JN5189
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Product data sheet
Rev. 1.2 — June 2020
76 of 92
NXP Semiconductors
IEEE 802.15.4 low power wireless MCU
JN5189(T)/JN5188(T)
Table 44. Radio transceiver characteristics: +125 °C …continued
VDD = 1.9 V to 3.6 V; unless otherwise specified.
Symbol
PoutRange
EVM
Parameter
Conditions
Min
Typ
46
Max
Unit
dB
Output power control range
Error vector magnitude
With IEEE 802.15.4
channel at +10 dBm
6.6
%
OEVM
Offset error vector magnitude With IEEE 802.15.4
channel at +10 dBm
0.36
23
%
%
EVMProp
OEVMProp
PSD
Error Vector Magnitude
With proprietary mode at
+10 dBm
Offset error Vector Magnitude With proprietary mode at
+10 dBm
3.2
%
Power spectral density
Relative density at
greater than 3.5 MHz
offset as per IEEE
802.15.4 at +10 dBm
-37.5
dBc
Absolute density at
greater than 3.5 MHz
offset at +10 dBm as per
IEEE 802.15.4 at +10
dBm
-39.5
dBm
PSDProp
Proprietary mode power
spectral density
Relative density at
greater than 3.5 MHz
offset with proprietary
mode at +10 dBm
-60.6
-62.8
dBc
Absolute density at
greater than 3.5 MHz
offset with proprietary
mode at +10 dBm
dBm
TXH2
TXH3
2nd Harmonic of Transmit
Carrier Frequency
With IEEE 802.15.4
channel at +10 dBm
-63.3
-73
dBm/MH
z
3rd Harmonic of Transmit
Carrier Frequency
With IEEE 802.15.4
channel at +10 dBm
dBm/MH
z
JN5189
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Product data sheet
Rev. 1.2 — June 2020
77 of 92
NXP Semiconductors
IEEE 802.15.4 low power wireless MCU
JN5189(T)/JN5188(T)
Table 44. Radio transceiver characteristics: +125 °C …continued
VDD = 1.9 V to 3.6 V; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
PspTX
Transmitter spurious
emission, measured
conducted into 50 ohms
30 MHz to 1 GHz, Peak
detector, RBW=100kHz
-76.3
dBm
1 GHz to 26 GHz, Peak
detector, RBW 1MHz,
based on FCC at +10
dBm
-23.3
-39
dBm
dBm
1 GHz to 26 GHz, Peak
detector, RBW 1MHz,
based on FCC with
proprietary mode at +10
dBm
1 GHz to 12.75 GHz,
Peak detector, RBW
1MHz, based on ETSI at
+10 dBm
-41.3
-44.3
dBm
dBm
1 GHz to 12.75 GHz,
Peak detector, RBW
1MHz, based on ETSI
with proprietary mode at
+10 dBm
1 GHz to 26 GHz,
Average detector, RBW
= 1 MHz, based on FCC
at +10 dBm
-29.2
-46.3
dBm
dBm
1 GHz to 26 GHz,
Average detector, RBW
= 1 MHz with proprietary
mode, based on FCC at
+10 dBm
Transmitter spurious
emission, ETSI exceptions
1.8 GHz to 1.9 GHz
5.15 GHz to 5.3 GHz
-64.7
-67.1
dBm
dBm
[1] Considering an integrated BW of 2 MHz, and a minimum SNR of 4 dB for the demodulator.
[2] Interference rejection is defined as the value, when 1 % PER is seen with the wanted signal 3 dB above
sensitivity, with a modulated interferer as per IEEE 802.15.4.
[3] Proprietary mode interference rejection is defined as the value, when 1 % PER is seen with the wanted
signal 3 dB above sensitivity, with a proprietary mode interferer.
[4] CW Interference rejection is defined as the value, when 1 % PER is seen with the wanted signal 3 dB
above sensitivity, with a CW interferer.
[5] The intermodulation protection level is the difference between the wanted channel power and one of the
two interferers power. Both interferers are modulated as per IEEE 802.15.4 and have the same power.
[6] This RSSI variation over temperature is obtained with the use of the embedded thermometer and the
integrated API (see application note).
JN5189
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© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 1.2 — June 2020
78 of 92
NXP Semiconductors
IEEE 802.15.4 low power wireless MCU
JN5189(T)/JN5188(T)
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Fig 19. Package outline SOT618-1 HVQFN40
JN5189
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JN5189(T)/JN5188(T)
16. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
16.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
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IEEE 802.15.4 low power wireless MCU
JN5189(T)/JN5188(T)
16.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 20) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 45 and 46
Table 45. SnPb eutectic process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
235
≥ 350
220
< 2.5
2.5
220
220
Table 46. Lead-free process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 20.
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IEEE 802.15.4 low power wireless MCU
JN5189(T)/JN5188(T)
maximum peak temperature
MSL limit, damage level
temperature
minimum peak temperature
minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 20. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10366 “Lead
less package surface mount reflow soldering description”.
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IEEE 802.15.4 low power wireless MCU
JN5189(T)/JN5188(T)
17. Abbreviations
Table 47. Abbreviations
Acronym
ADC
ADE
ADO
AES
AGC
API
Description
Analog to Digital Converter
Antenna diversity Even
Antenna diversity Odd
Advanced Encryption Standard
Automatic Gain Control
Application Program Interface
Analog Peripheral Timer
Bill Of Material
APT
BOM
BOR
CCA
CCM
CDM
CLK
CPU
CRC
CSMA/CA
CTS
CW
Brown-Out Reset
Clear Channel Assessment
Counter with CBC-MAC
Charged Device Model
CLocK
Central Processing Unit
Cyclic redundancy Check
Carrier Sense Multiple Access with Collision Avoidance
Clear-To-Send
Continuous Wave
DALI
DC
Digitally Addressable Lighting Interface
Direct current
DIO
Digital Input Output
DMA
DO
Direct memory Access
Digital Output
ED
Energy Detection
EEPROM
ESR
FIFO
GP
Electrically-Erasable Programmable Read Only Memory
Equivalent Series Resistance
First In First Out
General Purpose
GPIO
HBM
HS
General Purpose Input Output
Human Body Model
High Speed
HVQFN
ID
Heatsink Very-thin Quad Flat No-Leads
IDentification
IF
Intermediate frequency
Input Output
IO
IPC
Interconnecting and Packaging Electronic Circuits
Joint Test Action Group
Low Noise Amplifier
JTAG
LNA
LQI
Link Quality Indication
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JN5189(T)/JN5188(T)
Table 47. Abbreviations …continued
Acronym
LSB
Description
Low Significant Bit
MAC
MSB
MSIF
MSL
Media Access Control
Most Significant Bit
Master Serial InterFace
Moisture sensitivity level
Not ACKnowledge
NACK
NFET
NRZ
Negative Field Effect Transistor
Non-Return-to-Zero
NVIC
OOK
OTA
Nested Vector Interrupt Controller
On-Off Key
Over-The-Air
OTP
One Time Programmable
Power Amplifier
PA
PAN
Personal Area Network
Printed-Circuit Board
Persistent Data Manager
PHYsical
PCB
PDM
PHY
PLL
Phase-Locked Loop
POR
PPF
Power-On Reset
Palladium Pre Plated
Pulse Width Modulation
Random Access Memory
Remote Control
PWM
RAM
RC
RF
Radio Frequency
RF4CE
RoHS
RSSI
RTS
Radio frequency for Consumer Electronic
Restriction of Hazardous Substances
Receive Signal Strength Indication
Request-To-Send
RTOS
RTZ
Real-Time Operating System
Return-To-Zero
RX
Received
SCL
Serial CLock
SDA
Serial DatA
SDK
Software Developer’s Kit
System Management bus
Surface Mount Devices
Switched Mode Power Supply
Single-Pole Double-Throw
Serial Peripheral Interface -bus
Slave Transmitter Stop Detect
Slave Serial InterFace
SMbus
SMDs
SMPS
SPDT
SPI-bus
STSD
SSIF
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IEEE 802.15.4 low power wireless MCU
JN5189(T)/JN5188(T)
Table 47. Abbreviations …continued
Acronym
SVM
Description
Supply Voltage Monitor
SYNTHesizer
SYNTH
SysTick
TAF
System Tick timer
Transmitter Arbitration Failure
Tightly-Coupled Memory
Transmit
TCM
TX
UART
VCO
Universal Asynchronous Receiver Transmitter
Voltage Controlled Oscillator
Vector Table Offset Register
Wideband Power Detector
VTOR
WPD
18. References
[1] IEEE Std 802.15.4-2011 IEEE Standard for Information Technology Part 15.4 —
Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications
for Low-Rate Wireless Personal Area Networks (LR-WPANs).
[2] Wireless Connectivity —
http://www.nxp.com/products/wireless-connectivity:WIRELESS-CONNECTIVITY
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IEEE 802.15.4 low power wireless MCU
JN5189(T)/JN5188(T)
19. Revision history
Table 48. Revision history
Document ID
JN5189 v1.2
Modifications:
Release date
202006
Data sheet status
Change notice
Supersedes
Product data sheet
-
-
• Updated to support Thread as well as Zigbee across the whole book.
• Updated AES security processor feature in Section 2.2 “Radio features”.
• Updated SPIFI, NTAG feature in Section 2.3 “Microcontroller features”.
• Updated Section 3 “Applications”.
• Updated Figure 1 “High level hardware block diagram”.
• Corrected typos and made descriptions aligned in Table 4 “Pin descriptions” and Table 5
“Pin descriptions”.
• Added a note to the Figure 4 “System memory map”.
• Corrected pin name in Section 8.4.1 “External reset”.
• Updated Section 8.6.2.3 “Deep-sleep mode”.
• Removed the ADC_SEQB in the Table 8 “Power mode wake-up sources”.
• Updated to “DNL (Differential Non Linearity): ±0.85 LSB typ.” in Section 8.15 “12-bit general
purpose ADC”.
• Updated Section 8.22 “SPI-bus Flash Interface (SPIFI)”.
• Updated Section 8.23 “Hash module”.
• Updated general descriptions and security features in Section 8.26 “NTAG I2C”.
• Updated NTAG security features in the Section 8.26.1 “Features”.
• Updaed digital I/O descriptions in Section 8.7.2 “General description”.
• Updated Figure 10 “Application diagram – battery powered solution”.
• Updated VIL in Table 17 “IO characteristics”.
• Updated the IDD typical values in the Table 23 “32 kHz crystal oscillator” and Table 24
“32 MHz crystal oscillator”.
JN5189 v1.1
Modifications:
20200222
Product data sheet
-
-
• Initial public release.
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IEEE 802.15.4 low power wireless MCU
JN5189(T)/JN5188(T)
20. Legal information
20.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
20.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
20.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
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Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
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IEEE 802.15.4 low power wireless MCU
JN5189(T)/JN5188(T)
21. Tables
Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .4
Table 2. Ordering information details . . . . . . . . . . . . . . . .4
Table 3. Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 4. Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . .6
Table 5. Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . .13
Table 6. Pin properties . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 7: Abbreviation used in the Table 6. . . . . . . . . . . .21
Table 8. Power mode wake-up sources . . . . . . . . . . . . .30
Table 9. Allowed timer usage in different power modes.32
Table 10. Component descriptions about Figure 10. . . . .50
Table 11. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .50
Table 12. Operating conditions . . . . . . . . . . . . . . . . . . . .51
Table 13. Thermal characteristics . . . . . . . . . . . . . . . . . .51
Table 14. Typical current consumption in Low-power mode
characteristics . . . . . . . . . . . . . . . . . . . . . . . . .52
Table 15. Typical current consumption in Active mode
characteristics . . . . . . . . . . . . . . . . . . . . . . . . .52
Table 16. Typical CPU current consumption characteristics
53
Table 17. IO characteristics . . . . . . . . . . . . . . . . . . . . . . .53
Table 18. Externally applied reset . . . . . . . . . . . . . . . . . .55
Table 19. Analog to Digital Converters . . . . . . . . . . . . . .56
Table 20. Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Table 21. 32 kHz free running oscillator . . . . . . . . . . . . .57
Table 22. 1 MHz free running oscillator . . . . . . . . . . . . . .57
Table 23. 32 kHz crystal oscillator . . . . . . . . . . . . . . . . . .57
Table 24. 32 MHz crystal oscillator . . . . . . . . . . . . . . . . . 58
Table 25. High-speed free running oscillator . . . . . . . . . 58
Table 26. Temperature sensor . . . . . . . . . . . . . . . . . . . . 58
Table 27. Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 28. Dynamic characteristic: I/O pins[1] . . . . . . . . . . 59
Table 29. Wake-up timing . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 30. SPI master timing. . . . . . . . . . . . . . . . . . . . . . . 60
Table 31. SPI slave timing . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 32. USART master timing (in synchronous mode). 63
Table 33. USART slave timing (in synchronous mode) . . 63
Table 34. SPIFI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 35. PWM timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 36. DMIC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 37. Clock of ISO7816. . . . . . . . . . . . . . . . . . . . . . . 66
Table 38. Input output of ISO7816. . . . . . . . . . . . . . . . . . 66
Table 39. I2C timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 40. GPIO pin timing . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 41. RF port characteristics . . . . . . . . . . . . . . . . . . 68
Table 42. Radio transceiver characteristics: +25 °C . . . . 69
Table 43. Radio transceiver characteristics: -40 °C . . . . 71
Table 44. Radio transceiver characteristics: +125 °C . . . 74
Table 45. SnPb eutectic process (from J-STD-020D) . . . 81
Table 46. Lead-free process (from J-STD-020D) . . . . . . 81
Table 47. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 48. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 86
22. Figures
Fig 1. High level hardware block diagram . . . . . . . . . . . .5
Fig 2. Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . .6
Fig 3. Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . .13
Fig 4. System memory map. . . . . . . . . . . . . . . . . . . . . .24
Fig 5. Radio architecture . . . . . . . . . . . . . . . . . . . . . . . .40
Fig 6. Modem system diagram. . . . . . . . . . . . . . . . . . . .42
Fig 7.
Baseband processor system diagram. . . . . . . . .43
Fig 8. Simple antenna diversity implementation using
external RF switch . . . . . . . . . . . . . . . . . . . . . . . .45
Fig 9. Antenna diversity ADO and ADE signals for TX with
acknowledgment . . . . . . . . . . . . . . . . . . . . . . . . .45
Fig 10. Application diagram – battery powered solution .49
Fig 11. Reset signal timing. . . . . . . . . . . . . . . . . . . . . . . .56
Fig 12. Output timing measurement condition . . . . . . . . .60
Fig 13. SPI master interface timings . . . . . . . . . . . . . . . .62
Fig 14. SPI slave interface timings. . . . . . . . . . . . . . . . . .63
Fig 15. USART interface timings . . . . . . . . . . . . . . . . . . .64
Fig 16. SPIFI interface timings. . . . . . . . . . . . . . . . . . . . .65
Fig 17. DMIC interface timings. . . . . . . . . . . . . . . . . . . . .66
Fig 18. I2C interface timings. . . . . . . . . . . . . . . . . . . . . . .68
Fig 19. Package outline SOT618-1 HVQFN40 . . . . . . . .79
Fig 20. Temperature profiles for large and small
components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
JN5189
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 1.2 — June 2020
89 of 92
NXP Semiconductors
IEEE 802.15.4 low power wireless MCU
JN5189(T)/JN5188(T)
23. Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . 1
8.9
8.10
8.10.1
PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Counter/Timers. . . . . . . . . . . . . . . . . . . . . . . . 33
2
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Benefits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Radio features . . . . . . . . . . . . . . . . . . . . . . . . . 2
Microcontroller features . . . . . . . . . . . . . . . . . . 2
Low power features . . . . . . . . . . . . . . . . . . . . . 3
2.1
2.2
2.3
2.4
8.10.1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.10.1.2 General description . . . . . . . . . . . . . . . . . . . . 33
8.10.2
8.10.3
8.10.3.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.10.3.2 General description . . . . . . . . . . . . . . . . . . . . 35
8.10.4
8.11
8.12
8.13
8.14
8.15
8.16
8.17
8.18
8.19
8.19.1
8.19.2
8.20
8.20.1
8.20.2
8.20.3
8.20.3.1 Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.20.3.2 Reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.20.3.3 Auto acknowledge . . . . . . . . . . . . . . . . . . . . . 44
8.20.3.4 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.20.4
8.21
8.22
8.23
8.24
8.25
Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 34
Real-Time Clock (RTC) . . . . . . . . . . . . . . . . . 34
3
4
5
6
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering information. . . . . . . . . . . . . . . . . . . . . 4
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Low Power Wake-up Timers . . . . . . . . . . . . . 35
USART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Serial Peripheral Interfaces-bus (SPI-bus). . . 37
I2C-bus interfaces. . . . . . . . . . . . . . . . . . . . . . 37
DMIC interface . . . . . . . . . . . . . . . . . . . . . . . . 38
12-bit general purpose ADC. . . . . . . . . . . . . . 38
Temperature sensor . . . . . . . . . . . . . . . . . . . . 39
Analog comparator. . . . . . . . . . . . . . . . . . . . . 39
Infra-Red Modulator . . . . . . . . . . . . . . . . . . . . 39
Serial Wire Debug (SWD) . . . . . . . . . . . . . . . 39
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Basic configuration. . . . . . . . . . . . . . . . . . . . . 40
Wireless transceiver. . . . . . . . . . . . . . . . . . . . 40
Radio features . . . . . . . . . . . . . . . . . . . . . . . . 41
Modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Baseband processor . . . . . . . . . . . . . . . . . . . 42
7
7.1
Pinning information. . . . . . . . . . . . . . . . . . . . . . 6
HVQFN40 - with NTAG. . . . . . . . . . . . . . . . . . . 6
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
HVQFN40 - without NTAG . . . . . . . . . . . . . . . 13
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 13
Pin properties . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1.1
7.1.2
7.2
7.2.1
7.2.2
7.3
8
8.1
Functional description . . . . . . . . . . . . . . . . . . 21
Application CPU . . . . . . . . . . . . . . . . . . . . . . . 21
Arm Cortex-M4 processor. . . . . . . . . . . . . . . . 22
Memory Protection Unit . . . . . . . . . . . . . . . . . 22
System Tick Timer (SysTick) . . . . . . . . . . . . . 22
Nested Vector Interrupt controller (NVIC). . . . 22
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
General description. . . . . . . . . . . . . . . . . . . . . 23
Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SRAM usage. . . . . . . . . . . . . . . . . . . . . . . . . . 25
FLASH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
AHB multilayer matrix . . . . . . . . . . . . . . . . . . . 25
System clocks. . . . . . . . . . . . . . . . . . . . . . . . . 25
32 kHz clock . . . . . . . . . . . . . . . . . . . . . . . . . . 26
High frequency system clock . . . . . . . . . . . . . 26
1 MHz FRO. . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Resets and brownout . . . . . . . . . . . . . . . . . . . 26
External reset . . . . . . . . . . . . . . . . . . . . . . . . . 27
Software reset. . . . . . . . . . . . . . . . . . . . . . . . . 27
Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 27
Arm system reset . . . . . . . . . . . . . . . . . . . . . . 27
System configuration (SYSCON) . . . . . . . . . . 27
Power management . . . . . . . . . . . . . . . . . . . . 28
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . 28
Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 28
Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Deep-sleep mode . . . . . . . . . . . . . . . . . . . . . . 29
Power-down mode . . . . . . . . . . . . . . . . . . . . . 29
Deep power-down mode. . . . . . . . . . . . . . . . . 29
Wake-up sources . . . . . . . . . . . . . . . . . . . . . . 29
Digital I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
General description. . . . . . . . . . . . . . . . . . . . . 31
DMA controller . . . . . . . . . . . . . . . . . . . . . . . . 31
8.1.1
8.1.2
8.1.3
8.1.4
8.1.4.1
8.1.4.2
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.3
8.3.1
8.3.2
8.3.3
8.4
8.4.1
8.4.2
8.4.3
8.4.4
8.5
Antenna diversity . . . . . . . . . . . . . . . . . . . . . . 44
AES engine . . . . . . . . . . . . . . . . . . . . . . . . . . 45
SPI-bus Flash Interface (SPIFI) . . . . . . . . . . . 46
Hash module . . . . . . . . . . . . . . . . . . . . . . . . . 46
ISO7816 smart card interface . . . . . . . . . . . . 46
Random Number Generator. . . . . . . . . . . . . . 46
NTAG I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
General description . . . . . . . . . . . . . . . . . . . . 48
8.26
8.26.1
8.26.2
9
9.1
9.2
Application design-in information. . . . . . . . . 48
JN5189 module reference designs . . . . . . . . 48
Schematic diagram . . . . . . . . . . . . . . . . . . . . 49
10
11
12
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 50
Recommended operating conditions . . . . . . 51
Thermal characteristics . . . . . . . . . . . . . . . . . 51
8.6
8.6.1
8.6.2
8.6.2.1
8.6.2.2
8.6.2.3
8.6.2.4
8.6.2.5
8.6.2.6
8.7
13
Static characteristics . . . . . . . . . . . . . . . . . . . 52
Power consumption in Low-power mode . . . . 52
Power consumption in Active mode . . . . . . . . 52
IO characteristics . . . . . . . . . . . . . . . . . . . . . . 53
13.1
13.2
13.3
14
14.1
14.1.1
14.1.2
14.1.3
14.1.4
Dynamic characteristics. . . . . . . . . . . . . . . . . 55
AC characteristics . . . . . . . . . . . . . . . . . . . . . 55
Reset and Supply Voltage Monitor. . . . . . . . . 55
Analog to Digital Converters . . . . . . . . . . . . . 56
Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . 57
32 kHz free running oscillator. . . . . . . . . . . . . 57
8.7.1
8.7.2
8.8
JN5189
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 1.2 — June 2020
90 of 92
NXP Semiconductors
IEEE 802.15.4 low power wireless MCU
JN5189(T)/JN5188(T)
14.1.5
14.1.6
14.1.7
14.1.8
14.1.9
14.2
14.3
14.4
14.5
14.6
14.7
14.8
14.9
14.10
14.11
14.12
14.13
1 MHz free running oscillator . . . . . . . . . . . . . 57
32 kHz crystal oscillator . . . . . . . . . . . . . . . . . 57
32 MHz crystal oscillator. . . . . . . . . . . . . . . . . 58
High-speed free running oscillator . . . . . . . . . 58
Temperature sensor . . . . . . . . . . . . . . . . . . . . 58
Flash memory. . . . . . . . . . . . . . . . . . . . . . . . . 58
IO pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Wake-up timing. . . . . . . . . . . . . . . . . . . . . . . . 60
SPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
USART timing. . . . . . . . . . . . . . . . . . . . . . . . . 63
SPIFI timing . . . . . . . . . . . . . . . . . . . . . . . . . . 64
PWM timing . . . . . . . . . . . . . . . . . . . . . . . . . . 65
DMIC timing . . . . . . . . . . . . . . . . . . . . . . . . . . 65
ISO7816 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
I2C timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
GPIO pin timing . . . . . . . . . . . . . . . . . . . . . . . 68
Radio transceiver . . . . . . . . . . . . . . . . . . . . . . 68
15
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 79
16
Soldering of SMD packages . . . . . . . . . . . . . . 80
Introduction to soldering . . . . . . . . . . . . . . . . . 80
Wave and reflow soldering . . . . . . . . . . . . . . . 80
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 80
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 81
16.1
16.2
16.3
16.4
17
18
19
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 83
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 86
20
Legal information. . . . . . . . . . . . . . . . . . . . . . . 87
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 87
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
20.1
20.2
20.3
21
22
23
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
JN5189
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 1.2 — June 2020
91 of 92
Information in this document is provided solely to enable system and software implementers to use
NXP products. There are no express or implied copyright licenses granted hereunder to design or
fabricate any integrated circuits based on the information in this document. NXP reserves the right to
make changes without further notice to any products herein.
How to Reach Us:
Home Page:
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NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any
particular purpose, nor does NXP assume any liability arising out of the application or use of any
product or circuit, and specifically disclaims any and all liability, including without limitation
consequential or incidental damages. “Typical” parameters that may be provided in NXP data sheets
and/or specifications can and do vary in different applications, and actual performance may vary over
time. All operating parameters, including “typicals” must be validated for each customer application
by customer‚ customer’s technical experts. NXP does not convey any license under its patent rights
nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which
can be found at the following address: nxp.com/SalesTermsandConditions.
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vulnerabilities. Customers are responsible for the design and operation of their applications and
products to reduce the effect of these vulnerabilities on customer’s applications and products, and
NXP accepts no liability for any vulnerability that is discovered. Customers should implement
appropriate design and operating safeguards to minimize the risks associated with their applications
and products.
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© 2020 NXP B.V.
Document Number: JN5189
Rev.1.2
06/2020
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