HSTL16918DGG [NXP]
9-bit to 18-bit HSTL-to-LVTTL memory address latch; 9位至18位的HSTL到LVTTL存储器地址锁存器
| 型号： | HSTL16918DGG |
| 厂家： | 
NXP |
| 描述： | 9-bit to 18-bit HSTL-to-LVTTL memory address latch |
| 文件： | 总8页 (文件大小：67K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
HSTL16918
9-bit to 18-bit HSTL-to-LVTTL
memory address latch
Product data
2001 Jun 16
Philips
Semiconductors
Philips Semiconductors
Product data
9-bit to 18-bit HSTL-to-LVTTL memory address latch
HSTL16918
FEATURES
PIN CONFIGURATION
• Inputs meet JEDEC HSTL Std. JESD 8–6, and outputs meet
Level III specifications
48
47
46
V
2Q1
1Q1
1
2
3
CC
• ESD classification testing is done to JEDEC Standard JESD22.
V
CC
Protection exceeds 2000 V to HBM per method A114.
GND
1Q2
• Latch-up testing is done to JEDEC Standard JESD78, which
45 2Q2
44 GND
43 1Q3
D1
D2
4
5
exceeds 100 mA.
• Packaged in 48-pin plastic thin shrink small outline package
V
6
7
8
9
(TSSOP48)
CC
42
41
D3
D4
2Q3
V
CC
DESCRIPTION
The HSTL16918 is a 9-bit to 18-bit D-type latch designed for
40 1Q4
39
GND
3.15 to 3.45 V V operation. The D inputs accept HSTL levels and
CC
2Q4
38 GND
1LE 10
the Q outputs provide LVTTL levels.
GND 11
The HSTL16918 is particularly suitable for driving an address bus to
two banks of memory. Each bank of nine outputs is controlled with
its own latch-enable (LE) input.
37
36
V
12
1Q5
2Q5
REF
GND 13
2LE 14
GND 15
D5 16
35 GND
34 1Q6
33 2Q6
Each of the nine D inputs is tied to the inputs of two D-type latches
that provide true data (Q) at the outputs. While LE is LOW the Q
outputs of the corresponding nine latches follow the D inputs. When
LE is taken HIGH, the Q outputs are latched at the levels set up at
the D inputs.
32
31
30
D6 17
V
CC
The HSTL16918 is characterized for operation from 0 to +70 °C.
D7 18
1Q7
2Q7
V
19
CC
29 GND
28 1Q8
D8 20
D9 21
27
26
GND 22
2Q9 23
1Q9 24
2Q8
V
CC
25
V
CC
SW00768
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
HSTL16918DGG
DWG NUMBER
48-pin plastic thin shrink small outline package
(TSSOP48)
0 to +70 °C
SOT362-1
2
2001 Jun 16
853-2258 26484
Philips Semiconductors
Product data
9-bit to 18-bit HSTL-to-LVTTL memory address latch
HSTL16918
PIN DESCRIPTION
LOGIC DIAGRAM (positive logic)
PIN
SYMBOL
FUNCTION
12
10
V
REF
4, 5, 7, 8, 16, 17,
18, 20, 21
D[1–9]
1Q[1–9]
2Q[1–9]
Inputs
1LE
D1
4
2, 46, 43, 40, 37,
34, 31, 28, 24
1D
C1
Outputs
2
1Q1
1, 45, 42, 39, 36,
33, 30, 27, 23
14
10
14
12
1LE
2LE
2LE
Latch enable
1D
C1
1
V
REF
Reference voltage
Supply voltage
2Q1
6, 19, 25, 26, 32,
41, 47, 48
V
CC
3, 9, 11, 13, 15,
22, 29, 35, 38, 44
GND
Ground
TO EIGHT OTHER CHANNELS
SW00769
FUNCTION TABLE
INPUTS
OUTPUT
LE
L
D
H
L
Q
H
L
L
1
H
X
Q
0
NOTE:
1. Output level before the indicated steady-state input conditions
were established.
3
2001 Jun 16
Philips Semiconductors
Product data
9-bit to 18-bit HSTL-to-LVTTL memory address latch
HSTL16918
1
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range (unless otherwise noted).
SYMBOL
PARAMETER
Supply voltage range
CONDITIONS
RATING
–0.5 to +4.6
–0.5 to V +0.5
UNIT
V
V
CC
2
V
I
Input voltage range
V
CC
2
V
Output voltage range
Input clamp current
Output clamp current
–0.5 to V +0.5
V
O
CC
I
IK
V < 0
–50
±50
mA
mA
mA
mA
°C/W
°C
I
3
I
V < 0 or V > V
O O CC
OK
I
O
Continuous output current
V
O
= 0 to V
CC
±50
Continuous current through each V or GND
±100
CC
4
θ
Package thermal impedance
89
JA
T
stg
Storage temperature range
–65 to +150
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. This current flows only when the output is in the high state and V > V
.
O
CC
4. The package thermal impedance is calculated in accordance with JESD 51.
1
RECOMMENDED OPERATING CONDITIONS
LIMITS
Nom
SYMBOL
PARAMETER
UNIT
Min
Max
3.45
0.9
V
CC
Supply voltage
Reference voltage
Input voltage
3.15
0.68
0
V
V
V
REF
0.75
V
I
1.5
V
V
AC high-level input voltage
AC low-level input voltage
DC high-level input voltage
DC low-level input voltage
High-level output current
All inputs
All inputs
All inputs
All inputs
V
V
+ 200 mV
V
IH
REF
V
V
V
– 200 mV
V
IL
REF
V
IH
+ 100 mV
V
REF
V
– 100 mV
–24
V
IL
REF
I
mA
mA
°C
OH
I
OL
Low-level output current
24
T
amb
Operating free-air temperature range
0
+70
NOTE:
1. All unused inputs of the device must be held at V or GND to ensure proper device operation.
CC
4
2001 Jun 16
Philips Semiconductors
Product data
9-bit to 18-bit HSTL-to-LVTTL memory address latch
HSTL16918
ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range (unless otherwise noted).
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
= 3.15 V; I = –18 mA
UNIT
Max
1
Min
Typ
V
IK
V
–1.2
V
V
CC
I
V
OH
V
= 3.15 V; I = –24 mA
2.4
CC
OH
V
V
= 3.15 V; I = 24 mA
0.5
±5
V
OL
CC
OL
Control inputs
Data inputs
V
= 3.45 V; V = 0 or 1.5 V
µA
µA
µA
mA
pF
pF
pF
CC
CC
I
I
V
= 3.45 V; V = 0 or 1.5 V
±5
I
I
V
REF
V
= 3.45 V; V = 0.68 V or 0.9 V
REF
90
CC
I
V
CC
= 3.45 V; V = 0 or 1.5 V
50
2
100
CC
I
Control inputs
Data inputs
Outputs
V
V
= 0 or 3.3 V; V = 0 or 3.3 V
I
CC
CC
C
I
= 0 or 3.3 V; V = 0 or 3.3 V
2.5
4
I
C
V
= 0 V; V = 0 V
CC O
O
NOTE:
1. All typical values are at V = 3.3 V; T
= 25 °C.
CC
amb
TIMING REQUIREMENTS
Over recommended operating free-air temperature range (unless otherwise noted).
V
= 3.3 V ±0.15 V
CC
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
Min
3
Max
t
w
Pulse duration
Setup time
Hold time
LE LOW (Figure 1)
D before LE ↑ (Figure 2)
D after LE ↑ (Figure 2)
D after LE ↓
ns
ns
ns
ns
t
su
2
t
h
1
1
t
ldr
Data race condition timeĂ
0
NOTE:
1. This is the maximum time after LE switches LOW that the data input can return to the latched state from the opposite state without producing
a glitch on the output.
SWITCHING CHARACTERISTICS
Over recommended operating free-air temperature range; V
= 0.75 V.
REF
V
= 3.3 V ±0.15 V
CC
FROM
(INPUT)
TO
(OUTPUT)
SYMBOL
PARAMETER
UNIT
Min
1.9
1.9
Max
3.4
D
Q
Q
ns
ns
t
pd
Propagation delay (Figure 3)
LE
4.2
SIMULTANEOUS SWITCHING CHARACTERISTICS
Over recommended operating free-air temperature range; V
= 0.75 V
REF
V
= 3.3 V ±0.15 V
CC
FROM
(INPUT)
TO
(OUTPUT)
SYMBOL
PARAMETER
UNIT
Min
1.9
1.9
Max
4.4
D
Q
Q
ns
ns
Propagation delay; all outputs switching
(Figure 3)
t
pd
LE
5.2
5
2001 Jun 16
Philips Semiconductors
Product data
9-bit to 18-bit HSTL-to-LVTTL memory address latch
HSTL16918
VOLTAGE WAVEFORMS
LOAD CIRCUIT
FROM OUTPUT
UNDER TEST
t
w
1.25 V
0.25 V
C
= 80 PF
L
500 Ω
INPUT
V
V
REF
REF
(see Note)
SW00770
SW00773
Figure 1. Pulse duration
NOTE: C includes probe and jig capacitance.
L
Figure 4. Load circuit
1.25 V
0.25 V
1.25 V
LE
V
REF
t
su
t
h
DATA INPUT
V
V
REF
REF
0.25 V
SW00771
Figure 2. Setup and Hold times
1.25 V
0.25 V
INPUT
(Note 1)
V
V
REF
REF
t
t
PHL
PLH
V
V
OH
OUTPUT
1.5 V
1.5 V
OL
SW00772
Figure 3. Propagation delay times
NOTES:
1. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 1 ns, t ≤ 1 ns.
O
r
f
2. The outputs are measured one at a time with one transition per
measurement.
3. t
and t are the same as t .
PLH pd
PHL
6
2001 Jun 16
Philips Semiconductors
Product data
9-bit to 18-bit HSTL-to-LVTTL memory address latch
HSTL16918
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
7
2001 Jun 16
Philips Semiconductors
Product data
9-bit to 18-bit HSTL-to-LVTTL memory address latch
HSTL16918
Data sheet status
Product
status
Definitions
[1]
Data sheet status
[2]
Objective data
Development
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
Preliminary data
Product data
Qualification
Production
This data sheet contains data from the preliminary specification. Supplementary data will be
published at a later date. Philips Semiconductors reserves the right to change the specification
without notice, in order to improve the design and supply the best possible product.
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply.
Changes will be communicated according to the Customer Product/Process Change Notification
(CPCN) procedure SNW-SQ-650A.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on
the Internet at URL http://www.semiconductors.philips.com.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 2001
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 06-01
Document order number:
9397 750 08474
Philips
Semiconductors
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