HEF4515BP [NXP]
1-of-16 decoder/demultiplexer with input latches; 1 - 16解码器/解复用器的输入锁存器
| 型号： | HEF4515BP |
| 厂家： | 
NXP |
| 描述： | 1-of-16 decoder/demultiplexer with input latches |
| 文件： | 总7页 (文件大小：78K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4515B
MSI
1-of-16 decoder/demultiplexer with
input latches
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF4515B
MSI
1-of-16 decoder/demultiplexer with input latches
present at An are stored in the latches and the outputs
remain stable. When E is LOW, the selected output,
determined by the contents of the latch, is LOW. At
E HIGH, all outputs are HIGH. The enable input (E) does
not affect the state of the latch. When the HEF4515B is
used as a demultiplexer, E is the data input and A0 to
A3 are the address inputs.
DESCRIPTION
The HEF4515B is a 1-of-16 decoder/demultiplexer, having
four binary weighted address inputs (A0 to A3), a latch
enable input (EL), and an active LOW enable input (E).
The 16 outputs (O0 to O15) are mutually exclusive active
LOW. When EL is HIGH, the selected output is determined
by the data on An. When EL goes LOW, the last data
Fig.1 Functional diagram.
HEF4515BP(N):
24-lead DIL; plastic
(SOT101-1)
HEF4515BD(F):
HEF4515BT(D):
24-lead DIL; ceramic (cerdip)
(SOT94)
24-lead SO; plastic
(SOT137-1)
( ): Package Designator North America
Fig.2 Pinning diagram.
APPLICATION INFORMATION
Some examples of applications for the HEF4515B are:
• Digital multiplexing.
PINNING
• Address decoding.
A0 to A3
E
address inputs
• Hexadecimal/BCD decoding.
enable input (active LOW)
latch enable input
EL
FAMILY DATA, IDD LIMITS category MSI
O0 to O15
outputs (active LOW)
See Family Specifications
January 1995
2
Philips Semiconductors
Product specification
HEF4515B
MSI
1-of-16 decoder/demultiplexer with input latches
Fig.3 Logic diagram.
Fig.4 Logic diagram (one latch).
January 1995
3
Philips Semiconductors
Product specification
HEF4515B
MSI
1-of-16 decoder/demultiplexer with input latches
TRUTH TABLE
INPUTS
OUTPUTS
E
A0 A1 A2 A3 O0 O1 O2
O3 O4 O5
O6
O7 O8 O9 O10 O11 O12 O13 O14 O15
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
X
L
X
L
X
L
H
L
H
H
L
H
H
H
L
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
H
H
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
H
H
H
Notes
1. EL = HIGH; H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage); X = state is immaterial
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL
TYP. MAX.
Propagation delays
An, EL → On
5
260
95
520
190
130
550
190
130
350
130
90
ns
233 ns + (0,55 ns/pF) CL
84 ns + (0,23 ns/pF) CL
57 ns + (0,16 ns/pF) CL
243 ns + (0,55 ns/pF) CL
84 ns + (0,23 ns/pF) CL
57 ns + (0,16 ns/pF) CL
148 ns + (0,55 ns/pF) CL
54 ns + (0,23 ns/pF) CL
37 ns + (0,16 ns/pF) CL
173 ns + (0,55 ns/pF) CL
59 ns + (0,23 ns/pF) CL
42 ns + (0,16 ns/pF) CL
HIGH to LOW
10
15
5
tPHL
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
65
270
95
LOW to HIGH
10
15
5
tPLH
tPHL
tPLH
65
E → On
175
65
HIGH to LOW
10
15
5
45
200
70
400
140
100
LOW to HIGH
January 1995
10
15
50
4
Philips Semiconductors
Product specification
HEF4515B
MSI
1-of-16 decoder/demultiplexer with input latches
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL MIN. TYP. MAX.
V
Output transition
times
5
10
15
5
90
35
25
85
35
25
60
20
15
60
20
15
60
20
15
180 ns
65 ns
50 ns
170 ns
70 ns
50 ns
ns
40 ns
14 ns
11 ns
35 ns
14 ns
11 ns
+
+
+
+
+
+
(1,0 ns/pF) CL
(0,42 ns/pF) CL
(0,28 ns/pF) CL
(1,0 ns/pf) CL
HIGH to LOW
tTHL
tTLH
tsu
LOW to HIGH
10
15
5
(0,42 ns/pF) CL
(0,28 ns/pF) CL
Set-up time
120
40
30
0
An → EL
10
15
5
ns
ns
Hold time
ns
see also waveforms
Fig.5
An → EL
10
15
5
thold
0
ns
0
ns
Minimum EL pulse
width; HIGH
120
40
30
ns
10
15
tWELH
ns
ns
VDD
V
TYPICAL FORMULA FOR P (µW)
2
Dynamic power
dissipation per
package (P)
5
10
15
1100 fi + ∑ (foCL) × VDD
where
2
5500 fi + ∑ (foCL) × VDD
fi = input freq. (MHz)
2
16 000 fi + ∑ (foCL) × VDD
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
5
Philips Semiconductors
Product specification
HEF4515B
MSI
1-of-16 decoder/demultiplexer with input latches
Fig.5 Waveforms showing minimum pulse width for EL, set-up and hold times for An to EL. Set-up and hold
times are shown as positive values but may be specified as negative values.
January 1995
6
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