HCT9046 [NXP]
PLL with bandgap controlled VCO; PLL与带隙控制VCO
| 型号： | HCT9046 |
| 厂家： | 
NXP |
| 描述： | PLL with bandgap controlled VCO |
| 文件： | 总40页 (文件大小：243K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74HCT9046A
PLL with bandgap controlled VCO
1999 Jan 11
Product specification
Supersedes data of March 1994
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
• Tone decoding
FEATURES
GENERAL DESCRIPTION
• Data synchronization and
conditioning
• Low power consumption
The 74HCT9046A is a high-speed
Si-gate CMOS device. It is specified
in compliance with “JEDEC standard
no. 7A”.
• Centre frequency up to
17 MHz (typ.) at VCC = 5.5 V
• Voltage-to-frequency conversion
• Motor-speed control.
• Choice of two phase
comparators(1):
QUICK REFERENCE DATA
– EXCLUSIVE-OR (PC1)
– Edge-triggered JK flip-flop (PC2)
• No dead zone of PC2
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 6 ns.
SYMBOL
fc
PARAMETER
CONDITIONS
TYP.
16
UNIT
MHz
• Charge pump output on PC2,
whose current is set by an external
resistor Rb
VCO centre frequency
C1 = 40 pF;
R1 = 3 kΩ;
VCC = 5 V
• Centre frequency tolerance ±10%
CI
input capacitance
3.5
20
pF
pF
CPD
power dissipation
capacitance per
package
notes 1 and 2
• Excellent
voltage-controlled-oscillator (VCO)
linearity
• Low frequency drift with supply
voltage and temperature variations
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW)
a) PD = CPD × VCC2 × fi + Σ(CL × VCC2 × fo) where:
• On chip bandgap reference
• Glitch free operation of VCO, even
at very low frequencies
b) fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
Σ(CL × VCC2 × fo) = sum of the outputs.
• Inhibit control for ON/OFF keying
and for low standby power
consumption
2. Applies to the phase comparator section only (inhibit = HIGH). For power
dissipation of the VCO and demodulator sections see Figs 26 to 28.
• Operation power supply voltage
range 4.5 to 5.5 V
ORDERING INFORMATION
• Zero voltage offset due to op-amp
buffering
PACKAGE
EXTENDED
TYPE NUMBER
• Output capability: standard
• ICC category: MSI.
PINS PIN POSITION
MATERIAL
plastic
CODE
SOT38Z
SOT109A
74HCT9046AN
74HCT9046AD
16
16
DIL16
SO16
plastic
APPLICATIONS
• FM modulation and demodulation
where a small centre frequency
tolerance is essential
• Frequency synthesis and
multiplication where a low jitter is
required (e.g. Video
picture-in-picture)
• Frequency discrimination
(1) Rb connected between pin 15 and
ground: PC2 mode, with PCPOUT at
pin 2.
Pin 15 left open or connected to VCC
:
PC1 mode with PC1OUT at pin 2.
1999 Jan 11
2
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
PINNING
SYMBOL
PIN
DESCRIPTION
GND
1
2
ground (0 V) (phase comparators)
PC1OUT
/
phase comparator 1 output/phase
comparator pulse output
PCPOUT
COMPIN
VCOOUT
INH
3
4
comparator input
V
R
GND
/
1
2
3
4
5
6
7
8
16
15
14
13
CC
b
VCO output
PC1
PCP
OUT
5
inhibit input
OUT
SIG
COMP
VCO
IN
IN
C1A
6
capacitor C1 connection A
capacitor C1 connection B
ground (0 V) (VCO)
VCO input
PC2
OUT
INH
OUT
C1B
7
9046A
GND
8
12 R2
11 R1
VCOIN
DEMOUT
R1
9
C1
A
10
11
12
13
demodulator output
resistor R1 connection
resistor R2 connection
C1
B
10 DEM
OUT
IN
VCO
9
GND
R2
MBD037 - 1
PC2OUT
phase comparator 2 output
(current source adjustable with Rb)
SIGIN
Rb
14
15
16
signal input
bias resistor (Rb) connection
supply voltage
Fig.1 Pin configuration.
VCC
LOGIC/FUNCTIONAL SYMBOLS AND DIAGRAMS
Φ
PLL
9046A
PC1
PCP
/
OUT
OUT
2
COMP
3
14
15
IN
SIG
IN
Φ
PC1
PCP
/
OUT
OUT
COMP
R
b
3
14
6
2
IN
PC2
13
OUT
SIG
IN
PC2
13
OUT
C1
A
C1
A
C1
B
R1
6
7
7
C1
VCO
DEM
4
11
12
15
9
B
OUT
OUT
DEM
VCO
10
4
R1
R2
11
12
9
OUT
OUT
VCO
R
b
R2
VCO
VCO
10
IN
IN
5
INH
5
INH
MBD038 - 1
MBD039 - 1
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
1999 Jan 11
3
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
C1
COMP
3
SIG
14
C1
A
C1
VCO
OUT
B
IN
IN
6
7
4
9046A
PC1
PCP
/
OUT
OUT
R2 12
R3
PHASE
COMPARATOR
1
2
R2
R1
VCO
PC2
13
15
OUT
R1 11
PHASE
COMPARATOR
2
R
b
R4
C2
R
b
5
INH
10
9
DEM
VCO
IN
OUT
R
s
MBD040 - 1
Fig.4 Functional diagram.
1999 Jan 11
4
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f
f
IN
OUT
4
C1
C1
3
14
SIG
6
7
C1
VCO
COMP
IN
A
B
OUT
IN
PC1
PCP
/
PC1
OUT
OUT
2
V
ref2
R2
12
11
10
R3
VCO
V
R2
R1
PCP
logic
1
up
D
Q
Q
ref1
CP
R1
R
D
PC2
13
15
logic
1
OUT
D
Q
Q
CHARGE
PUMP
DEM
OUT
CP
R4
C2
down
V
V
ref2
R
ref1
D
R
s
R
b
R
b
BAND
GAP
V
ref2
9
5
INH
VCO
IN
MBD102 - 1
Fig.5 Logic diagram.
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
frequency will not shift over the
supply voltage range.
• The inhibit function differs. For the
HCT4046A a HIGH level at the
inhibit input (INH) disables the VCO
and demodulator, while a LOW
level turns both on. For the
74HCT9046A a HIGH level on the
inhibit input disables the whole
circuit to minimize standby power
consumption.
FUNCTIONAL DESCRIPTION
The 74HCT9046A is a
phase-locked-loop circuit that
• A current switch charge pump
output on PC2 allows a virtually
ideal performance of PC2. The gain
of PC2 is independent of the
voltage across the low-pass filter.
Further a passive low-pass filter in
the loop achieves an active
performance now. The influence of
the parasitic capacitance of the
PC2 output plays no role here,
resulting in a true correspondence
of the output correction pulse and
the phase difference even up to
phase differences as small as a few
nanoseconds.
comprises a linear VCO and two
different phase comparators (PC1
and PC2) with a common signal input
amplifier and a common comparator
input (see Fig.4). The signal input can
be directly coupled to large voltage
signals (CMOS level), or indirectly
coupled (with a series capacitor) to
small voltage signals. A self-bias
input circuit keeps small voltage
signals within the linear region of the
input amplifiers. With a passive
low-pass filter, the '9046A' forms a
second-order loop PLL.
VCO
The VCO requires one external
capacitor C1 (between C1A and C1B)
and one external resistor R1
(between R1 and GND) or two
external resistors R1 and R2
(between R1 and GND, and R2 and
GND). Resistor R1 and capacitor C1
determine the frequency range of the
VCO. Resistor R2 enables the VCO
to have a frequency offset if required
(see Fig.5).
• Because of its linear performance
without dead zone, higher
impedance values for the filter,
hence lower C-values, can now be
chosen. Correct operation will not
be influenced by parasitic
capacitances as in the instance
with voltage source output of the
4046A.
The principle of this
phase-locked-loop is based on the
familiar HCT4046A. However extra
features are built in, allowing very
high performance phase-locked-loop
applications. This is done, at the
expense of PC3, which is skipped in
this HCT9046A. The PC2 is equipped
with a current source output stage
here. Further a bandgap is applied for
all internal references, allowing a
small centre frequency tolerance. The
details are summed up in the next
section called: “Differences with
respect to the familiar HCT4046A”.
If one is familiar with the HCT4046A
already, it will do to read this section
only.
The high input impedance of the VCO
simplifies the design of the low-pass
filters by giving the designer a wide
choice of resistor/capacitor ranges. In
order not to load the low-pass filter, a
demodulator output of the VCO input
voltage is provided at pin 10
(DEMOUT). The DEMOUT voltage
equals that of the VCO input. If
DEMOUT is used, a load resistor (Rs)
should be connected from pin 10 to
GND; if unused, DEMOUT should be
• No PC3 on pin 15 but instead a
resistor connected to GND, which
sets the load/unload currents of the
charge pump (PC2).
• Extra GND pin at pin 1 to allow an
excellent FM demodulator
performance even at 10 MHz and
higher.
left open. The VCO output (VCOOUT
can be connected directly to the
comparator input (COMPIN), or
connected via a frequency-divider.
The VCO output signal has a duty
factor of 50% (maximum expected
)
• Combined function of pin 2. If
pin 15 is connected to VCC (no bias
resistor Rb) pin 2 has its familiar
function viz. output of PC1. If at
pin 15 a resistor (Rb) is connected
to GND it is assumed that PC2 has
been chosen as phase comparator.
Connection of Rb is sensed by
internal circuitry and this changes
the function of pin 2 into a lock
detect output (PCPOUT) with the
same characteristics as PCPOUT of
pin 1 of the well known
DIFFERENCES WITH RESPECT TO
THE FAMILIAR HCT4046A
• A centre frequency tolerance of
maximum ±10%.
deviation 1%), if the VCO input is held
at a constant DC level. A LOW level at
the inhibit input (INH) enables the
VCO and demodulator, while a HIGH
level turns both off to minimize
• The on board bandgap sets the
internal references resulting in a
minimal frequency shift at supply
voltage variations and temperature
variations.
standby power consumption.
• The value of the frequency offset is
determined by an internal
74HCT4046A.
reference voltage of 2.5 V instead
of VCC − 0.7 V. In this way the offset
1999 Jan 11
6
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
The frequency capture range (2fc) is
Phase comparators
defined as the frequency range of
input signals on which the PLL will
lock if it was initially out-of-lock. The
frequency lock range (2fL) is defined
as the frequency range of the input
signals on which the loop will stay
locked if it was initially in lock. The
capture range is smaller or equal to
the lock range.
The signal input (SIGIN) can be
directly coupled to the self-biasing
amplifier at pin 14, provided that the
signal swing is between the standard
HC family input logic levels.
Capacitive coupling is required for
signals with smaller swings.
PHASE COMPARATOR 1 (PC1)
With PC1, the capture range depends
on the low-pass filter characteristics
and can be made as large as the lock
range. This configuration remains
locked even with very noisy input
signals. Typical behaviour of this type
of phase comparator is that it may
lock to input frequencies close to the
harmonics of the VCO centre
This circuit is an EXCLUSIVE-OR
network. The signal and comparator
input frequencies (fi) must have a
50% duty factor to obtain the
maximum locking range. The transfer
characteristic of PC1, assuming
ripple (fr = 2fi) is suppressed, is:
frequency.
V
VDEMOUT
where:
=
CC (Φ SIGIN – ΦCOMPIN
)
----------
π
PHASE COMPARATOR 2 (PC2)
This is a positive edge-triggered
phase and frequency detector. When
the PLL is using this comparator, the
loop is controlled by positive signal
transitions and the duty factors of
SIGIN and COMPIN are not important.
PC2 comprises two D-type flip-flops,
control gating and a 3-state output
stage with sink and source transistors
acting as current sources, henceforth
called charge pump output of PC2.
The circuit functions as an up-down
counter (Fig.5) where SIGIN causes
an up-count and COMPIN a down
count. The current switch charge
pump output allows a virtually ideal
performance of PC2, due to appliance
of some pulse overlap of the up and
down signals. See Fig.8a.
VDEMOUT is the demodulator output
at pin 10.
VDEMOUT = VPC1OUT (via low-pass).
The phase comparator gain is:
V
Kp
=
CC (V ⁄ r)
----------
π
The average output voltage from
PC1, fed to the VCO input via the
low-pass filter and seen at the
demodulator output at pin 10
(VDEMOUT), is the resultant of the
phase differences of signals (SIGIN)
and the comparator input (COMPIN)
as shown in Fig.6. The average of
VDEMOUT is equal to 1⁄2VCC when
there is no signal or noise at SIGIN
and with this input the VCO oscillates
at the centre frequency (fc). Typical
waveforms for the PC1 loop locked at
fc are shown in Fig.7. This figure also
shows the actual waveforms across
the VCO capacitor at pins 6 and 7
(VC1A and VC1B) to show the relation
between these ramps and the
VCOOUT voltage.
1999 Jan 11
7
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
MBD101 - 1
V
CC
V
DEMOUT(AV)
1/2V
CC
0
o
o
o
0
90
180
Φ
PCIN
VCC
VDEMOUT = VPC1OUT = ---------- (Φ SIGIN – ΦCOMPIN
)
π
ΦPCIN
= (ΦSIGIN – ΦCOMPIN)
Fig.6 Phase comparator 1; average output voltage as a function of input phase difference.
SIGN
IN
COMP
VCO
IN
OUT
PC1
VCO
V
OUT
V
CC
IN
GND
pin 6
C1A
V
pin 7
C1B
MBD100
Fig.7 Typical waveforms for PLL using phase comparator 1; loop-locked at fc.
8
1999 Jan 11
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
The pump current IP is independent
from the supply voltage and is set by
the internal bandgap reference of
2.5 V.
Thus for PC2 no phase difference
connected to the filter capacitance C2
via this fictive R3' (see Fig.8b). Then
during the PC2 output pulse the
charge current equals:
exists between SIGIN and COMPIN
over the full frequency range of the
VCO. Moreover, the power
dissipation due to the low-pass filter is
reduced because both output drivers
are OFF for most of the signal input
cycle. It should be noted that the PLL
lock range for this type of phase
comparator is equal to the capture
range and is independent of the
low-pass filter. With no signal present
at SIGIN the VCO adjust, via PC2, to
its lowest frequency.
V
CC – VC2 (0)
----------------------------------
R3'
2.5
Rb
IP
=
IP = 17 ×
(A )
-------
With the initial voltage VC2(0) at:
2.5
Rb is the external bias resistor
between pin 15 and ground.
1⁄2VCC = 2.5 V, I P
=
--------
R3'
The current and voltage transfer
function of PC2 are shown in Fig.9.
As shown before the charge current
of the current switch of the 9046A is:
The phase comparator gain is:
IP
2.5
I P = 17 ×
-------
Rb
By using current sources as charge
pump output on PC2, the dead zone
or backlash time could be reduced to
zero. Also, the pulse widening due to
the parasitic output capacitance plays
no role here. This enables a linear
transfer function, even in the vicinity
of the zero crossing. The differences
between a voltage switch charge
pump and a current switch charge
pump are shown in Fig.11.
Kp
=
(A ⁄ r)
-------
2π
Hence:
R
Typical waveforms for the PC2 loop
locked at fc are shown in Fig.10.
R3' = b (Ω )
------
17
When the frequencies of SIGIN and
COMPIN are equal but the phase of
SIGIN leads that of COMPIN, the up
output driver at PC2OUT is held ‘ON’
for a time corresponding to the phase
difference (ΦPCIN). When the phase of
SIGIN lags that of COMPIN, the down
or sink driver is held ‘ON’.
Using this equivalent resistance R3'
for the filter design the voltage can
now be expressed as a transfer
function of PC2; assuming ripple
(fr = fi) is suppressed, as:
5
4π
The design of the low-pass filter is
somewhat different when using
current sources. The external resistor
R3 is no longer present when using
PC2 as phase comparator. The
current source is set by Rb. A simple
capacitor behaves as an ideal
integrator now, because the capacitor
is charged by a constant current. The
transfer function of the voltage switch
charge pump may be used. In fact it is
even more valid, because the transfer
function is no longer restricted for
small changes only. Further the
current is independent from both the
supply voltage and the voltage across
the filter. For one that is familiar with
the low-pass filter design of the
4046A a relation may show how Rb
relates with a fictive series resistance,
called R3'.
KPC2
=
(V ⁄ r)
------
When the frequency of SIGIN is higher
than that of COMPIN, the source
output driver is held ‘ON’ for most of
the input signal cycle time and for the
remainder of the cycle time both
drivers are ‘OFF’ (3-state). If the
SIGIN frequency is lower than the
COMPIN frequency, then it is the sink
driver that is held ‘ON’ for most of the
cycle. Subsequently the voltage at the
capacitor (C2) of the low-pass filter
connected to PC2OUT varies until the
signal and comparator inputs are
equal in both phase and frequency. At
this stable point the voltage on C2
remains constant as the PC2 output is
in 3-state and the VCO input at pin 9
is a high impedance. Also in this
condition the signal at the phase
Again this illustrates the supply
voltage independent behaviour of
PC2.
Examples of PC2 combined with a
passive filter are shown in Figs 12
and 13. Figure 12 shows that PC2
with only a C2 filter behaves as a
high-gain filter. For stability the
damped version of Fig.13 with series
resistance R4 is preferred.
Practical design values for Rb are
between 25 and 250 kΩ with
R3' = 1.5 to 15 kΩ for the filter design.
Higher values for R3' require lower
values for the filter capacitance which
is very advantageous at low values
the loop natural frequency ωn.
comparator pulse output (PCPOUT
)
This relation can be derived by
assuming first that a voltage
controlled switch PC2 of the 4046A is
has a minimum output pulse width
equal to the overlap time, so can be
used for indicating a locked condition.
1999 Jan 11
9
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
V
CC
up
V
CC
I
P
PC2
OUT
up
I
P
PC2
OUT
R3'
I
VC2
OUT
C2
down
P
down
C2
∆ Φ
= Φ
PCIN
MBD099
pulse overlap of
MBD046 - 1
approximately 15 ns
a.
b.
a. At every ∆Φ, even at zero ∆Φ both switches are closed simultaneously for a short period (typically 15 ns).
b. Comparable voltage-controlled switch.
Fig.8 The current switch charge pump output of PC2.
MSB306 - 1
V
CC
I
P
V
DEMOUT(AV)
I
x R
P
Φ
Φ
Φ
SIGIN COMPIN
=
PCIN
1/2V
0
CC
I
P
0
2
0
2
2
0
2
π
π
π
π
Φ
Φ
PCIN
PCIN
a.
b.
Two kinds of transfer functions may be regarded:
IP
a. The current transfer: pump current ------- Φ PCIN
2π
b. The voltage transfer; this transfer can be observed at PC2OUT by connecting a resistor (R = 10 kΩ) between PC2OUT and 1⁄2VCC
;
5
VDEMOUT = VPC2OUT = ------ Φ PCIN
4π
Fig.9 Phase comparator 2.
1999 Jan 11
10
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
SIG
IN
COMP
IN
VCO
OUT
UP
OPC
IN
DOWN
CURRENT AT
PC2
OUT
high impedance OFF state,
(zero current)
PC2
PCP
/VCO
IN
OUT
OUT
MBD047 - 1
The pulse overlap of the up and down signals (typically 15 ns).
Fig.10 Timing diagram for PC2.
2.75
2.75
VCO
VCO
IN
IN
(1)
2.50
2.50
2.25
(1)
(2)
2.25
25
0
25
25
0
25
phase error (ns)
phase error (ns)
MBD043
a.
b.
a. Response with traditional voltage-switch charge-pump PC2OUT (4046A).
(1) Due to parasitic capacitance on PC2OUT
(2) Backlash time (dead zone).
.
b. Response with current switch charge-pump PC2OUT as applied in the HCT9046A.
Fig.11 The response of a locked-loop in the vicinity of the zero crossing of the phase error.
11
1999 Jan 11
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
LOOP FILTER COMPONENT SELECTION
A
I
P
I
F
P
(jω)
17
C2
INPUT
OUTPUT
1/
Aτ
1
R
b
ω
1/
Aτ
MBD045 - 1
1
a.
b.
c.
Rb
a. τ1 = ------ × C2 = R3' × C2
17
1
1
b. Amplitude characteristic: F(jω) = ---------------------------- ≈ -----------
1 ⁄ A + jωτ1 j ωτ1
c. Pole zero diagram.
Fig.12 Simple loop filter for PC2 without damping.
A
I
P
I
F
P
(jω)
17
1/
O
R4
Aτ
1
INPUT
OUTPUT
1/
R
τ
b
2
m
C2
ω
1/
1 /
Aτ
τ
2
1
MBD044 - 1
a.
b.
c.
Rb
a. τ1 = ------ × C2 = R3' × C2
17
τ2 = R4 × C2
1 + jωτ2
----------------------------
1 ⁄ A + jωτ1
b. Amplitude characteristic: F(jω)
=
c. Pole zero diagram.
A = DC gain limit, due to leakage.
Fig.13 Simple loop filter for PC2 with damping.
12
1999 Jan 11
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
RECOMMENDED OPERATING CONDITIONS FOR 74HCT
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
MIN.
4.5
TYP. MAX. UNIT
VCC
VI
5.0
−
5.5
V
DC input voltage
0
0
VCC
VCC
+85
V
VO
DC output voltage
−
V
Tamb
operating ambient temperature
see DC and AC Characteristics −40
−40
−
°C
−
+125 °C
500 ns
tr, tf
input rise and fall times (pin 5)
VCC = 4.5 V
−
6
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V).
SYMBOL
VCC
PARAMETER
DC supply voltage
CONDITIONS
MIN.
−0.5
MAX.
+7
UNIT
V
IIK
DC input diode current
for VI < −0.5 V
−
±20
mA
or VI > VCC + 0.5 V
IOK
DC output diode current
for VO < −0.5 V
−
±20
mA
or VO > VCC + 0.5 V
IO
DC output source or sink current
DC VCC or GND current
storage temperature
for −0.5 V < VO < VCC + 0.5 V
−
±25
mA
mA
°C
ICC; IGND
Tstg
−
±50
−65
+150
Ptot
total power dissipation per package note 1
plastic DIL
above +70 °C: derate linearly
with 12 mW/K
−
−
750
500
mW
mW
plastic mini-pack (SO)
above +70 °C: derate linearly
with 8 mW/K
Note
1. Temperature range: −40 to +125 °C.
1999 Jan 11
13
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
DC CHARACTERISTICS FOR 74HCT
Voltages are referenced to GND (ground = 0 V).
T
amb (°C)
−40 to +85 −40 to +125 UNIT
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
TEST CONDITIONS
SYMBOL PARAMETER
+25
VCC
(V)
VI
(V)
OTHER
Phase comparator section
VIH
DC coupled
HIGH level input
voltage SIGIN,
COMPIN
3.15 2.4
−
3.15
−
3.15
−
V
V
4.5
−
−
VIL
DC coupled LOW
level input
voltage SIGIN,
COMPIN
−
2.1
4.5
1.35
−
1.35
−
1.35
4.5
VOH
HIGH level
output voltage
PCPOUT, PCnOUT
4.4
−
4.4
3.84
−
−
4.4
3.7
−
−
V
V
V
V
4.5
4.5
4.5
4.5
5.5
5.5
4.5
VIH
or
VIL
IO = −20 µA
IO = −4.0 mA
IO = −20 µA
IO = −4.0 mA
3.98 4.32
−
−
−
VIH
or
VIL
VOL
LOW level
output voltage
PCPOUT, PCnOUT
−
−
−
−
−
0
0.1
0.1
0.33
±38
±5.0
−
0.1
0.4
VIH
or
VIL
0.15 0.26
−
−
VIH
or
VIL
II
input leakage
current SIGIN,
COMPIN
−
±30
±0.5
−
−
−
±45 µA
±10.0 µA
VCC
or
GND
IOZ
3-state
OFF-state
current PC2OUT
−
−
−
VIH
or
VIL
VO = VCC or
GND
RI
input resistance
SIGIN, COMPIN
250
−
−
−
kΩ
VI at self-bias
operating point;
∆VI = 0.5 V;
see Figs 14 to 16
Rb
IP
bias resistance
25
−
250
−
−
−
−
−
−
−
kΩ
4.5
−
charge pump
current
±0.53 ±1.06 ±2.12 −
mA 4.5
−
Rb = 40 kΩ
1999 Jan 11
14
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
Tamb (°C)
−40 to +85 −40 to +125 UNIT
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
TEST CONDITIONS
SYMBOL
PARAMETER
+25
VCC
(V)
VI
(V)
OTHER
VCO section
VIH
DC coupled
HIGH level input
voltage INH
2.0
−
1.6
1.2
4.5
−
2.0
−
−
2.0
−
−
V
V
V
V
V
V
V
4.5
to 5.5
−
−
VIL
DC coupled LOW
level input
voltage INH
0.8
−
0.8
−
0.8
−
4.5
to 5.5
VOH
HIGH level
output voltage
VCOOUT
4.4
4.4
3.84
−
4.4
3.7
−
4.5
4.5
4.5
4.5
4.5
5.5
VIH
or
VIL
IO = −20 µA
IO = −4.0 mA
IO = 20 µA
3.98 4.32
−
−
−
VIH
or
VIL
VOL
LOW level
output voltage
VCOOUT
−
−
−
−
0
0.1
0.1
0.33
0.47
±1.0
0.1
0.4
0.54
VIH
or
VIL
0.15 0.26
−
−
VIH
or
VIL
IO = 4.0 mA
IO = 4.0 mA
VOL
LOW level
output voltage
C1A, C1B
−
−
0.40
−
−
VIH
or
VIL
II
input leakage
current INH and
VCOIN
±0.1
−
−
±1.0 µA
VCC
or
GND
R1
R2
C1
resistance
resistance
capacitance
3
−
−
−
300
300
−
−
−
−
−
−
−
−
−
−
−
−
kΩ
kΩ
pF
4.5
4.5
4.5
−
−
−
3
40
no
limit
VVCOIN
operating
voltage range at
VCOIN
1.1
1.1
1.1
−
−
−
3.4
3.9
4.4
−
−
−
−
−
−
−
−
−
−
−
−
V
V
V
4.5
5.0
5.5
−
−
−
over the
range
specified
for R1
1999 Jan 11
15
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
Tamb (°C)
−40 to +85 −40 to +125 UNIT
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
TEST CONDITIONS
SYMBOL
PARAMETER
+25
VCC
(V)
VI
(V)
OTHER
Demodulator section
Rs
resistance
50
−
300
−
−
−
−
−
−
−
−
−
−
−
−
kΩ
mV
Ω
4.5
−
−
−
at Rs >
300 kΩ the
leakage
current can
influence
VDEMOUT
VOFF
offset voltage
VCOIN to
VDEMOUT
−
±20
25
−
4.5
4.5
VI = VVCOIN
= 1⁄2VCC
values
taken over
Rs range,
see Fig.17
;
RD
dynamic output
resistance at
DEMOUT
−
−
VDEMOUT =
1⁄2VCC
Quiescent supply current
ICC
quiescent supply
current
(disabled)
−
−
−
8.0
−
−
80.0
450
−
−
160.0 µA
5.5
4.5
−
−
pin 5 at VCC
∆ICC
additional
100
360
490
µA
other inputs
at VCC or
GND
quiescent supply
current per input
pin for unit load
coefficient is 1;
note 1;
VI = VCC − 2.1 V
Note
1. The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given above. To determine ∆ICC per
input, multiply this value by the unit load coefficient shown in Table 1.
Table 1 Unit load coefficient table.
INPUT
UNIT LOAD COEFFICIENT
INH
1.00
1999 Jan 11
16
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
MGA956 - 1
MBD108
800
I
I
I
R
(kΩ)
∆ V
I
600
400
200
0
V
=
CC
4.5 V
self-bias operating point
5.5 V
V
I
1/2V
0.25
1/2V
1/2V
0.25
CC
CC
CC
V
(V)
I
Fig.14 Typical input resistance curve at SIGIN,
COMPIN.
Fig.15 Input resistance at SIGIN; COMPIN with
∆VI = 0.5 V at self-bias point.
MGA958
MGA957
60
5
V
= 5.5 V
V
CC
OFF
(mV)
40
4.5 V
I
I
(µA)
20
0
V
= 4.5 V
0
CC
4.5 V
5.5 V
5.5 V
20
40
5
1/2 V
CC
2
1/2 V
1/2 V 2
CC
(V)
1/2 V
CC
0.25
1/2 V
CC
1/2 V 0.25
CC
CC
V
V
(V)
I
VCOIN
___ Rs = 50 kΩ.
- - - Rs = 300 kΩ.
Fig.16 Input current at SIGIN; COMPIN with
Fig.17 Offset voltage at demodulator output as a
function of VCOIN and Rs.
∆VI = 0.5 V at self-bias point.
1999 Jan 11
17
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
Tamb (°C)
TEST CONDITION
SYMBOL
PARAMETER
+25
−40 to +85
−40 to +125 UNIT
VCC
WAVEFORMS
(V)
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
Phase comparator section
tPHL/tPLH
tPHL/tPLH
tPZH/tPZL
propagation delay
SIGIN, COMPIN to
PC1OUT
−
−
−
23
35
30
40
68
56
−
−
−
50
85
70
−
−
−
60
ns
ns
ns
4.5
Fig.18
Fig.18
Fig.19
propagation delay
SIGIN, COMPIN to
PCPOUT
102
84
4.5
4.5
3−state output
enable time SIGIN,
COMPIN to
PC2OUT
tPHZ/tPLZ
3−state output
enable time SIGIN,
COMPIN to
−
36
65
−
81
−
98
ns
4.5
Fig.19
PC2OUT
t
THL/tTLH
output transition
time
−
−
7
15
−
−
19
−
−
22
ns
4.5
4.5
Fig.18
Vi(p-p)
AC coupled input
sensitivity
15
−
−
−
mV
fi = 1 MHz
(peak-to-peak
value) at SIGNIN or
COMPIN
1999 Jan 11
18
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
T
amb (°C)
TEST CONDITION
SYMBOL
PARAMETER
+25
−40 to +85
−40 to +125 UNIT
VCC
WAVEFORMS
(V)
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
VCO section
∆f/T
frequency stability
with temperature
change
−
−
−
0.06
−
−
−
%/K 4.5
VVCOIN =1⁄2VCC
recommended
range:
;
R1 = 10 kΩ;
R2 = 10 kΩ;
C1 = 1 nF;
Figs 20 to 22
∆fc
centre frequency
tolerance
−10
−
+10
−
−
−
−
−
−
−
−
%
5.0
VVCOIN = 3.9 V;
R1 = 10 kΩ;
R2 = 10 kΩ;
C1 = 1 nF
VVCOIN =1⁄2VCC
R1 = 4.3 kΩ;
R2 = ∞;
fc
VCO centre
frequency
(duty factor = 50%)
11.0 15.0
−
MHz 4.5
;
C1 = 40 pF;
Figs 23 and 31
∆fVCO
VCO frequency
linearity
−
−
0.4
50
−
−
−
−
−
−
−
−
−
−
%
%
4.5
4.5
R1 = 100 kΩ;
R2 = ∞;
C1 = 100 pF;
Figs 24 and 25
δVCO
duty factor at
VCOOUT
1999 Jan 11
19
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
SIG , COMP
IN
(1)
IN
V
M
t
INPUTS
t
PHL
PLH
PCP
OUT
, PC1 ,
OUT
(1)
V
M
OUTPUTS
MBD106
t
t
TLH
THL
(1) VM
= .
1⁄2VCC; VI = GND to VCC
Fig.18 Waveforms showing input (SIGIN and COMPIN) to output (PCPOUT and PC1OUT) propagation delays and
the output transition times.
SIG
IN
(1)
V
M
INPUT
COMP
(1)
IN
V
M
INPUT
t
t
PLZ
PHZ
90%
t
t
PZL
PZH
PC2
(1)
OUT
OUTPUT
V
M
10%
MGA941
(1) VM
= .
1⁄2VCC; VI = GND to VCC
Fig.19 Waveforms showing the 3-state enable and disable times for PC2OUT
.
1999 Jan 11
20
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
MBD115
MBD116
20
15
10
5
∆
(%)
f
∆ f
(%)
10
0
0
V
=
5
CC
V
=
CC
10
20
5.5 V
4.5 V
5.5 V
4.5 V
10
15
50
0
50
100
T
150
50
0
50
100
T
150
( C)
o
o
( C)
amb
amb
a.
b.
a. R1 = 3 kΩ; R2 = ∞; C1 = 100 pF.
b. R1 = 10 kΩ; R2 = ∞; C1 = 100 pF.
Fig.20 Frequency stability of the VCO as a function of ambient temperature with supply voltage as a parameter.
MBD124
MBD117
10
15
10
5
5.5 V
V
=
∆
(%)
f
CC
∆ f
(%)
4.5 V
5
0
5
V
=
CC
0
5.5 V
5
10
15
4.5 V
10
20
50
0
50
100
T
150
50
0
50
100
T
150
( C)
o
o
( C)
amb
amb
a.
b.
a. R1 = 300 kΩ; R2 = ∞; C1 = 100 pF.
b. R1 = ∞; R2 = 3 kΩ; C1 = 100 pF.
Fig.21 Frequency stability of the VCO as a function of ambient temperature with supply voltage as a parameter.
1999 Jan 11
21
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
MBD118
MBD119
8
10
f
∆
f
∆
(%)
(%)
4
0
5
0
V
=
4
8
CC
V
=
CC
4.5 V
5.5 V
5
5.5 V
4.5 V
12
10
50
0
50
100
T
150
50
0
50
100
150
o
o
( C)
T
( C)
amb
amb
a.
b.
a. R1 = ∞; R2 = 10 kΩ; C1 = 100 pF.
b. R1 = ∞; R2 = 300 kΩ; C1 = 100 pF.
Fig.22 Frequency stability of the VCO as a function of ambient temperature with supply voltage as a parameter.
1999 Jan 11
22
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
MBD113
MBD112
30
30
f
f
VCO
(kHz)
VCO
(MHz)
V
=
CC
4.5 V
5.5 V
20
10
0
20
V
=
CC
4.5 V
10
5.5 V
0
0
2
4
6
0
2
4
6
V
(V)
V
(V)
VCOIN
VCOIN
a.
b.
MBD120 - 1
MBD111 - 1
800
400
handbook, halfpage
handbook, halfpage
f
f
VCO
VCO
(kHz)
600
(Hz)
V
= 5.5 V
CC
V
= 5.5 V
CC
300
4.5 V
frequency
4.5 V
frequency
400
200
200
100
0
0
0
0
2
4
6
2
4
6
V
(V)
V
(V)
VCOIN
VCOIN
d.
c.
a. R1 = 4.3 kΩ; C1 = 39 pF.
b. R1 = 4.3 kΩ; C1 = 100 nF.
c. R1 = 300 kΩ; C1 = 39 pF.
d. R1 = 300 kΩ; C1 = 100 nF.
Fig.23 Graphs showing VCO frequency as a function of the VCO input voltage (VVCOIN).
1999 Jan 11
23
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
MBD114
4
MGA937 - 1
C1 = 1 µF
4.5 V
5.5 V
f
f
VCO
(%)
f
2
C1 =
39 pF
0
f
c
f'
c
4.5 V
f
1
4
8
V
V
min
max
1/2V
5.5 V
CC
V
VCOIN
2
3
1
10
10
10
R1 (kΩ)
f
1 + f2
f′c
=
--------------
2
f′c – fc
linearity = --------------- × 100%
fc
R2 = ∞ and ∆V = 0.5 V.
Fig.24 Definition of VCO frequency linearity:
Fig.25 Frequency linearity as a function of R1, C1
and VCC
∆V = 0.5 V over the VCC range.
.
MBD110
MBD121
1
1
V
=
V
=
CC
5.5 V
CC
5.5 V
P
P
D
D
(W)
(W)
C1 = 39 pF
C1 = 1 µF
4.5 V
C1 = 1 µF
4.5 V
C1 = 39 pF
1
1
10
10
5.5 V
C1 = 39 pF
5.5 V
4.5 V
C1 = 1 µF
4.5 V
C1 = 39 pF
2
2
10
10
0
100
200
300
0
100
200
300
R1 (kΩ)
R2 (kΩ)
R2 = ∞.
R1 = ∞.
Fig.26 Power dissipation as a function of
component values.
Fig.27 Power dissipation as a function of
component values.
1999 Jan 11
24
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
APPLICATION INFORMATION
This information is a guide for the approximation of values
of external components to be used with the 74HCT9046A
in a phase-locked-loop system.
MBD109
3
10
P
DEM
Values of the selected components should be within the
rages shown in Table 2.
(W)
V
=
CC
4.5 V
5.5 V
Table 2 Survey of components.
4
10
COMPONENT
VALUE
R1
R2
between 3 kΩ and 300 kΩ
between 3 kΩ and 300 kΩ
parallel value >2.7 kΩ
>40 pF
R1 + R2
C1
5
10
2
3
10
10
10
R
(kΩ)
s
Fig.28 Typical power dissipation.
Table 3 Design considerations for VCO section.
PHASE
SUBJECT
DESIGN CONSIDERATION
VCO frequency characteristic
COMPARATOR
VCO frequency without
extra offset
With R2 = ∞ and R1 within the range 3 kΩ < R1 < 300 kΩ, the
characteristics of the VCO operation will be as shown in Fig.29a.
(Due to R1, C1 time constant a small offset remains when R2 = ∞).
PC1, PC2
Selection of R1 and C1
Given fc, determine the values of R1 and C1 using Fig.31.
PC1
PC2
Given fmax and fc determine the values of R1 and C1 using Fig.31; use
Fig.33 to obtain 2fL and then use this to calculate fmin
.
VCO frequency
VCO frequency characteristic
with extra offset
PC1, PC2
PC1, PC2
With R1 and R2 within the ranges 3 kΩ < R1 < 300 kΩ < R2 < 300 kΩ,
the characteristics of the VCO operation is as shown in Fig.29b.
Selection of R1, R2 and C1
Given fc and fL determine the value of product R1C1 by using Fig.33.
Calculate foff from the equation foff = fc − 1.6fL.
Obtain the values of C1 and R2 by using Fig.32.
Calculate the value of R1 from the value of C1 and the product R1C1.
PLL conditions with no PC1
VCO adjusts to fc with ΦPCIN = 90° and VVCOIN = 1⁄2VCC
.
signal at the SIGIN input
PC2
VCO adjusts to foffset with ΦPCIN = −360° and VVCOIN = minimum.
1999 Jan 11
25
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
MGA938 - 1
f
VCO
f
max
f
c
2f
due to
R1,C1
L
f
min
1.1 V
1/2V
V
1.1 V
VCO
V
CC
CC
CC
IN
a.
MGA939 - 1
f
VCO
f
max
f
c
due to
R1,C1
2f
L
f
min
f
off
0.6f
L
due to
R2,C1
1.1 V
1/2V
V
1.1 V
VCO
V
CC
CC
CC
IN
b.
a. Operating without offset; fc = centre frequency; 2fL = frequency lock range.
b. Operating with offset; fc = centre frequency; 2fL = frequency lock range.
Fig.29 Frequency characteristic of VCO.
1999 Jan 11
26
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
Filter design considerations for PC1 and PC2 of the HCT9046A
Figure 30 shows some examples of passive and active filters to be used with the phase comparators of the HCT9046A.
Transfer functions of phase comparators and filters are given in Table 4.
Table 4 Transfer functions of phase comparators and filters.
PHASE
COMPARATOR
Fig.30 FILTER TYPE
TRANSFER FUNCTION
EXPLANATION
PC1
a.
passive filter
without
damping
1
V
F(jω)
=
=
--------------------
K PC1
=
CCV ⁄ r
----------
1 + jωτ1
π
b.
c.
d.
passive filter
with damping
τ1 = R3 × C2;
τ2 = R4 × C2;
τ3 = R4 × C3;
A = 105 = DC gain amplitude
1 + jωτ2
---------------------------------------
1 + jω (τ1 + τ2)
F(jω)
F (j ω )
F (j ω )
active filter
with damping
1 + jωτ2
1 + jωτ2
=
≈
≈
--------------------
----------------------------
jωτ1
1 ⁄ A + jωτ1
PC2
passive filter
with damping
1 + jωτ2
5
1 + jωτ2
K PC2
=
V ⁄ r
------
=
--------------------
----------------------------
4π
jωτ1
1 ⁄ A + jωτ1
τ1 = R3' × C2;
τ2 = R4 × C2;
τ3 = R4 × C3;
R3' = Rb/17;
A = 105 = limit DC gain
e.
active filter
with damping
1 + jωτ2
1 + jωτ2
F(jω)
=
≈
----------------------------
--------------------
jωτ1
1 ⁄ A + jωτ1
Rb = 25 to 250 kΩ
A = 105 = DC gain amplitude
1999 Jan 11
27
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
AMPLITUDE
CHARACTERISTIC
POLE ZERO
DIAGRAM
PC1
CIRCUIT
F
(jω)
R3
X
1/
τ
1
1/τ
C2
1
a.
F
(jω)
R3
1/τ
1/τ
3
2
O
X
1
C3
R4
1/ τ
2
1/ τ
τ
2
τ
τ
2
1
1
C2
b.
A
C3
1/τ
1/τ
2
3
C2
1/A τ
X
O
1
R4
1/τ
2
1/A τ
R3
1
A
c.
PC2
A
R3'
1/τ
1/τ
3
2
O
X 1/ Aτ
1
R4
C2
AR3'
1/τ
2
1/Aτ
1
d.
A
C3
R4
1/τ
1/τ
3
2
C2
O
X 1/ Aτ
1
1/τ
2
1/Aτ
R3'
1
A
MBD107 - 1
e.
Fig.30 Passive and active filters for HCT9046A.
28
1999 Jan 11
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
General design consideration.
PHASE
SUBJECT
DESIGN CONSIDERATION
COMPARATOR
PLL locks on harmonics at
centre frequency
PC1
PC2
PC1
PC2
PC1
PC2
yes
no
high
low
Noise rejection at signal
input
fr = 2fi; large ripple content at ΦPCIN = 90°
fr = fi; small ripple content at ΦPCIN = 0°
AC ripple content when PLL
is locked
1999 Jan 11
29
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
MBD103 - 1
8
10
f
c
(Hz)
R1 = 3 kΩ
7
10
R1 = 10 kΩ
6
5
4
10
10
10
R1 = 150 kΩ
R1 = 300 kΩ
V
=
CC
5.5 V
4.5 V
3
10
10
5.5 V
4.5 V
2
5.5 V
4.5 V
5.5 V
4.5 V
10
3
4
5
6
7
2
1
10
10
10
10
10
10
10
C1 (pF)
R2 = ∞; VVCOIN
=
1⁄2VCC; INH = GND; Tamb = 25 °C.
Fig.31 Typical value of VCO centre frequency (fc) as a function of C1.
1999 Jan 11
30
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
MBD104
8
10
f
off
(Hz)
R2 = 3 kΩ
7
10
R2 = 10 kΩ
6
5
4
10
10
10
R2 = 150 kΩ
R2 = 300 kΩ
V
=
CC
4.5 V - 5.5 V
3
10
10
4.5 V - 5.5 V
2
4.5 V - 5.5 V
4.5 V - 5.5 V
10
2
3
4
5
6
7
1
10
10
10
10
10
10
10
C1 (pF)
R1 = ∞; VVCOIN
=
1⁄2VCC; INH = GND; Tamb = 25 °C.
Fig.32 Typical value of frequency offset as a function of C1.
1999 Jan 11
31
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
MBD105 - 1
8
10
2f
L
(Hz)
7
10
6
10
5
10
4
10
3
10
2
10
V
=
CC
5.5 V
4.5 V
10
10
7
6
5
4
3
2
1
10
10
10
10
10
10
1
R1C1 (s)
2fL
Kv = ------------------------------------ 2 π (r ⁄ s ⁄ V)
VVCOINrange
VVCOIN = 1.1 to (VCC − 1.1) V.
Fig.33 Typical frequency lock range 2fL as a function of the product R1 and C1.
1999 Jan 11
32
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
seen that the damping ratio ζ = 0.707
will produce an overshoot of less than
20% and settle to within 5% at ωnt = 5.
PLL design example
The gain of the phase comparator
PC2 is:
The frequency synthesizer used in
the design example shown in Fig.34
has the following parameters:
5
Kp
=
= 0.4V ⁄ r
------------
4 × π
The required settling time is 1 ms.
This results in:
Output frequency: 2 MHz to 3 MHz.
Frequency steps: 100 kHz.
Settling time: 1 ms.
Using PC2 with the passive filter as
shown in Fig.34 results in a high gain
loop with the same performance as a
loop with an active filter. Hence loop
filter equations as for a high gain loop
should be used. The current source
output of PC2 can be simulated then
with a fictive filter resistance:
= 5 × 103r ⁄ s
5
--
t
5
ωn
=
=
--------------
0.001
Rewriting the equation for natural
frequency results in:
Overshoot: <20%.
Kp × Kv × Kn
The open loop gain is:
H (s) × G (s) = Kp × Kf × Ko × Kn
τ1
=
-------------------------------
(ωn) 2
and the closed loop:
Φu
K p × K f × K o × K n
Rb
The maximum overshoot occurs at
max = 30; hence Kn = 1⁄30:
=
------
-----------------------------------------------------
R3' =
------
Φi
1 + Kp × Kf × Ko × Kn
17
N
where:
0.4 × 2.24 × 106
Kp = phase comparator gain
Kf = low-pass filter transfer gain
Ko = Kv/s VCO gain
The transfer functions of the filter is
given by:
τ 1
=
= 0.0012
-----------------------------------------
50002 × 30
1 + sτ2
K f =
-----------------
When C2 = 470 nF, it follows:
sτ2
Kn = 1⁄n divider ratio.
τ1
0.0012
470 × 10–9
R3' =
=
= 2550
---------------------------
-------
C2
Where:
τ1 = R3' × C2.
The programmable counter ratio Kn
can be found as follows:
Hence the current source bias
resistance Rb = 17 × 2550 = 43 kΩ.
fOUT
2 MHz
---------------------
100 kHz
τ2 = R4 × C2.
N min
=
=
= 20
= 30
-----------
fstep
The characteristic equation is:
1 + Kp × Kf × Ko × Kn
With ζ = 0.707 (0.5 × τ2 × ωn) it
follows:
fOUT
3 MHz
---------------------
100 kHz
Nmax
=
=
-----------
fstep
This results in:
0.707
0.5 × 5000
τ2
=
= 0.00028
---------------------------
1 + sτ2
K
1 + Kp
vK = 0
----------------- -----
The VCO is set by the values of R1,
R2 and C1; R2 = 10 kΩ (adjustable).
n
sτ1
s
τ2
0.00028
470 × 10–9
R4 =
=
= 600 Ω
---------------------------
-------
C2
or:
The values can be determined using
the information in Table 3.
τ
s 2 + sKpKvK 2 + K K K ⁄ τ = 0
----
For extra ripple suppression a
capacitor C3 can be connected in
parallel with R4, with an extra
τ3 = R4 × C3.
nτ1
p
v
n
1
With fc = 2.5 MHz and fL = 500 kHz
this gives the following values
(VCC = 5.0 V):
This can be written as:
s2 + 2ζ ωns + (ωn) 2 = 0
R1 = 30 kΩ.
R2 = 30 kΩ.
C1 = 100 pF.
For stability reasons τ3 should be
<0.1τ2, hence C3 < 0.1C2, or
C3 = 39 nF.
with the natural frequency ωn defined
Kp × Kv × Kn
as: ωn
=
------------------------------- and the
τ1
The VCO gain is:
damping value given as:
2fL × 2π
Kv
=
=
----------------------------------------------
ζ = 0.5 × τ2 × ωn
(VCC – 1.1) – 1.1
6
1 MHz
----------------
2.8
× 2 π ≈ 2.24 × 10 r ⁄ s ⁄ V
In Fig.35 the output frequency
response to a step of input frequency
is shown.
The overshoot and settling time
percentages are now used to
determine ωn. From Fig.35 it can be
1999 Jan 11
33
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
K
K
K
o
p
f
100 kHz
PHASE
COMPARATOR
PC2
R3'
4
13
9
OSCILLATOR
"HCU04"
DIVIDE BY 10
"190"
14
f
VCO
12
OUT
(1)
3
R4
C2
15
R
11
6
7
5
C3
Φ
u
b
R1 R2
K
n
1 MHz
C1
PROGRAMMABLE
DIVIDER
MBD098
"4059"
R1 = 30 kΩ.
R2 = 30 kΩ.
C1 = 100 pF.
R3' = 2550 Ω.
Rb = 43 kΩ.
R4 = 600 Ω.
C2 = 470 nF.
C3 = 39 nF.
(1) R3' = fictive resistance
Rb
R3' =
------
17
Fig.34 Frequency synthesizer.
MGA959
1.6
−0.6
= 0.3
0.5
0.707
1.0
ζ
1.4
1.2
−0.4
−0.2
0
(t)
(t)
∆ Φ
e
∆ ω
e
∆ ω /ω
∆ Φ /ω
n
e
n
e
= 5.0
ζ
1.0
0.8
= 2.0
ζ
0.2
0.6
0.4
0.2
0.4
0.6
0.8
0
1.0
0
1
2
3
4
5
6
7
8
ω
t
n
Fig.35 Type 2, second order frequency step response.
34
1999 Jan 11
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
Since the output frequency is proportional to the VCO
control voltage, the PLL frequency response can be
observed with an oscilloscope by monitoring pin 9 of the
VCO. The average frequency response, as calculated by
the Laplace method, is found experimentally by smoothing
this voltage at pin 9 with a simple RC filter, whose time
constant is long compared with the phase detector
sampling rate but short compared with the PLL response
time.
MGA952
3.1
proportional
to output
frequency
(MHz)
N = 30
3.0
N stepped from 29 to 30
2.9
Further information
step input
For an extensive description and application example
please refer to “Application note” ordering number
9398 649 90011. Also available a “Computer design
program for PLLs” ordering number 9398 961 10061.
2.1
N stepped from 21 to 20
2.0
1.9
0
0.5
1.0
1.5
2.0
2.5
time (ms)
Fig.36 Frequency compared to the time response.
1999 Jan 11
35
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
PACKAGE OUTLINES
DIP16: plastic dual in-line package; 16 leads (300 mil); long body
SOT38-1
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
16
9
M
H
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
w
UNIT
mm
b
b
c
D
E
e
e
L
M
M
H
1
1
E
max.
max.
min.
max.
1.40
1.14
0.53
0.38
0.32
0.23
21.8
21.4
6.48
6.20
3.9
3.4
8.25
7.80
9.5
8.3
4.7
0.51
3.7
2.54
0.10
7.62
0.30
0.254
0.01
2.2
0.021
0.015
0.013
0.009
0.86
0.84
0.32
0.31
0.055
0.045
0.26
0.24
0.15
0.13
0.37
0.33
inches
0.19
0.020
0.15
0.087
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-10-02
95-01-19
SOT38-1
050G09
MO-001AE
1999 Jan 11
36
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
H
v
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.050
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-01-23
97-05-22
SOT109-1
076E07S
MS-012AC
1999 Jan 11
37
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
SOLDERING
Introduction
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
WAVE SOLDERING
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mount components are mixed on
one printed-circuit board. However, wave soldering is not
always suitable for surface mount ICs, or for printed-circuit
boards with high population densities. In these situations
reflow soldering is often used.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
Through-hole mount packages
SOLDERING BY DIPPING OR BY SOLDER WAVE
• For packages with leads on two sides and a pitch (e):
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joints for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg(max)). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
MANUAL SOLDERING
Apply the soldering iron (24 V or less) to the lead(s) of the
package, either below the seating plane or not more than
2 mm above it. If the temperature of the soldering iron bit
is less than 300 °C it may remain in contact for up to
10 seconds. If the bit temperature is between
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
300 and 400 °C, contact may be up to 5 seconds.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Surface mount packages
REFLOW SOLDERING
MANUAL SOLDERING
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
1999 Jan 11
38
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
Suitability of IC packages for wave, reflow and dipping soldering methods
SOLDERING METHOD
WAVE
REFLOW(1) DIPPING
suitable(2)
not suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable(3)
MOUNTING
PACKAGE
Through-hole mount DBS, DIP, HDIP, SDIP, SIL
−
suitable
Surface mount
BGA, SQFP
suitable
suitable
suitable
suitable
suitable
−
−
−
−
−
PLCC(4), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
not recommended(4)(5)
not recommended(6)
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.
3. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1999 Jan 11
39
Philips Semiconductors – a worldwide company
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Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Tel. +90 212 279 2770, Fax. +90 212 282 6707
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
Tel. +1 800 234 7381, Fax. +1 800 943 0087
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Uruguay: see South America
Vietnam: see Singapore
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 62 5344, Fax.+381 11 63 5777
For all other countries apply to: Philips Semiconductors,
Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1999
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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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Printed in The Netherlands
245002/00/03/pp40
Date of release: 1999 Jan 11
Document order number: 9397 750 05007
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