GTL2006_技术文档

INTEGRATED CIRCUITS

GTL2006

13-bit GTL–/GTL/GTL+ to LVTTL translator

Product data

2004 Jun 21

Supersedes data of 2003 Dec 18

Philips

Semiconductors

Philips Semiconductors

Product data

13-bit GTL–/GTL/GTL+ to LVTTL translator

GTL2006

FEATURES

PIN CONFIGURATION

• Operates as a GTL–/GTL/GTL+ to LVTTL sampling receiver or

V

1

2

3

4

5

6

7

8

9

28

27

V

REF

CC

LVTTL to GTL–/GTL/GTL+ driver

1AO

1BI

• 3.0 V to 3.6 V operation

• LVTTL I/O not 5 V tolerant

• Series termination on the LVTTL outputs of 30 Ω

2AO

5A

26 2BI

25 7BO1

6A

24

7BO2

• ESD protection exceeds 2000 V HBM per JESD22-A114,

8AI

11BI

11A

9BI

23 8BO

22 11BO

21 5BI

20 6BI

19 3BI

200 V MM per JESD22-A115 and 250 V CDM per JESD22-C101

• Latch-up testing is done to JESDEC Standard JESD78 which

exceeds 500 mA

• Package offered: TSSOP28

3AO 10

4AO 11

18

17

16

15

4BI

DESCRIPTION

10AI1 12

10BOI

The GTL2006 is a 13-bit translator to interface between the 3.3 V

LVTTL chip set I/O and the Xeon processor GTL–/GTL/GTL+ I/O.

The GTL2006 is designed for platform health management in dual

processor applications.

10AI2

13

10BO2

9AO

GND

14

SW01091

Figure 1. Pin configuration

PIN DESCRIPTION

PIN NUMBER SYMBOL

NAME AND FUNCTION

1

V

REF

GTL reference voltage

2–6, 8,

10–13, 15

Data inputs/outputs

(LVTTL)

nAn

7, 9, 16,

17–27

Data inputs/outputs

(GTL–/GTL/GTL+)

nBn

14

28

GND

Ground (0 V)

V

CC

Positive supply voltage

QUICK REFERENCE DATA

TYPICAL

CONDITIONS

SYMBOL

PARAMETER

UNIT

T

amb

= 25 °C

B to A

5.5

A to B

5.5

t

Propagation delay

PLH

PHL

C = 50 pF; V = 3.3 V

ns

L

CC

An to Bn or Bn to An

I/O pin capacitance

C

Outputs disabled; V = 0 V or 3.0 V

7.8

4.5

pF

I/O

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

ORDER CODE

TOPSIDE MARK

GTL2006

DWG NUMBER

28-Pin Plastic TSSOP

–40 °C to +85 °C

GTL2006PW

SOT361-1

Standard packing quantities and other packaging data are available at www.philipslogic.com/packaging.

2

2004 Jun 21

Philips Semiconductors

Product data

13-bit GTL–/GTL/GTL+ to LVTTL translator

GTL2006

FUNCTION TABLES

INPUT

OUTPUT

INPUT

OUTPUT

1BI/2BI/3BI/4BI/9BI

1AO/2AO/3AO/4AO/9AO

8AI

L

8BO

L

H

INPUT

OUTPUT

10AI1/10AI2

9BI

L

10BO1/10BO2

L

H

L

H

INPUT

INPUT/OUTPUT

OUTPUT

5BI/6BI

5A/6A (OPEN DRAIN)

7BO1/7BO2

1

L

H

L

H

2

L

H

INPUT

INPUT/OUTPUT

11A (OPEN DRAIN)

H

OUTPUT

11BI

L

11BO

L

H

2

L

H

L

H = HIGH voltage level

L = LOW voltage level

NOTES:

1. The enable on 7BO1/7BO2 include a delay that prevents the transient condition where 5BI/6BI go from LOW to HIGH, and the LOW to HIGH

on 5A/6A lags up to 100 ns from causing a low glitch on the 7BO1/7BO2 outputs.

2. Open Drain Input/Output terminal is driven to logic LOW state by other driver.

3

2004 Jun 21

Philips Semiconductors

Product data

13-bit GTL–/GTL/GTL+ to LVTTL translator

GTL2006

LOGIC SYMBOL

GTL2006

1

GTL V

REF

27

26

2

3

1BI

1AO

GTL

INPUTS

LVTTL

OUTPUTS

2BI

2AO

25

24

4

5

5A (OPEN DRAIN)

6A (OPEN DRAIN)

7BO1

7BO2

LVTTL I/O

GTL

OUTPUTS

23

22

6

7

LVTTL INPUT 8AI

GTL INPUT 11BI

8BO

11BO

1

DELAY

1

8

9

LVTTL I/O 11A (OPEN DRAIN)

GTL INPUT 9BI

21

5BI

DELAY

20

19

18

6BI

3BI

4BI

GTL

INPUTS

10

11

3AO

LVTTL

OUTPUTS

4AO

17

16

10BO1

10BO2

12

13

10AI1

LVTTL

INPUTS

GTL

OUTPUTS

10AI2

15

9AO LVTTL OUTPUT

SW01092

NOTE:

1. The enable on 7BO1/7BO2 include a delay that prevents the transient condition where 5BI/6BI go from LOW to HIGH, and the LOW to HIGH

on 5A/6A lags up to 100 ns from causing a low glitch on the 7BO1/7BO2 outputs.

Figure 2. Logic symbol

4

2004 Jun 21

Philips Semiconductors

Product data

13-bit GTL–/GTL/GTL+ to LVTTL translator

GTL2006

APPLICATION INFORMATION

V

TT

56 Ω

R

56 Ω

V

CC

1.5 kΩ to 1.2 kΩ

1.5 kΩ

2R

V

CC

PLATFORM

HEALTH

MANAGEMENT

CPU1

V

CC

REF

CPU1 IERR_L

IERR_L

1AO

2AO

5A

1BI

2BI

CPU1 THRMTRIP L

CPU1 PROCHOT L

CPU2 PROCHOT L

THRMTRIP L

FORCEPR_L

PROCHOT L

7BO1

6A

7BO2

8BO

NMI

8AI

11BI

11A

9BI

FORCEPR_L

NMI_L

CPU1 SMI L

11B0

5BI

6BI

FORCEPR_L

PROCHOT L

CPU2 IERR_L

3AO

3BI

IERR_L

THRMTRIP L

NMI

4AO

CPU2 THRMTRIP L

CPU1 SMI L

4BI

10AI1

10AI2

10BO1

10BO2

9AO

CPU2 SMI L

SMI_BUFF_L

CPU2 SMI L

CPU2

GND

GTL2006

SOUTHBRIDGE NMI

OPTIONAL SIGNAL LINE

SOUTHBRIDGE SMI_L

SW01094

Figure 3. Application diagram

5

2004 Jun 21

Philips Semiconductors

Product data

13-bit GTL–/GTL/GTL+ to LVTTL translator

GTL2006

Frequently Asked Questions

Question 1: On the GTL2006 LVTTL inputs, specifically 10AI1 and

10AI2, when the GTL2006 is unpowered, these inputs may be pulled

up to 3.3 V S/B and we want to make sure that there is no leakage

path to the power rail under this condition. Are the LVTTL inputs

HIGH Impedance when the device is unpowered and will there be

any leakage?

Question 6: Please explain the timing specification of Bn to Bn in

the AC Characteristics table. Which specific inputs/outputs does it

cover, and why is the H > L transition so slow?

Answer 6: The Bn to Bn refers to the 4BI to 7BO1 path and to the

6BI to 7BO2 path. The times are disable and enable times since a

LOW on 5BI or 6BI should not be reflected as a LOW on 7BO1 or

7BO2.

Answer 1: When the device is unpowered, the LVTTL inputs will

be in a high-impedance state and will not leak to V if they are

pulled high while the device is unpowered.

DD

The t

corresponds to the disable time, and the t

corresponds

PLH

PHL

to the enable time. The enable time is deliberately slow to prevent

glitches/false LOWs on the 7BOn outputs, because a LOW on 5BI

drives a LOW on 5A, which is an open-drain I/O and may have a

slow rise time. And a LOW on 6BI drives a LOW on 6A that is an

open-drain I/O that may also have a slow rise time.

Question 2: Do all the LVTTL inputs have the same unpowered

characteristic?

Answer 2: Yes.

Question 3: What is the condition of the other GTL I/O and LVTTL

output pins when the device is unpowered?

Question 6A: Now that I try to examine the circuit from the

data sheet, I am just a little bit concerned. Let me try to describe the

function first:

Answer 3: The open drain outputs, both GTL and LVTTL, will not

leak to the power supply if they are pulled high while the device is

unpowered. The GTL inputs will also not leak to the power supply

under the same conditions. The LVTTL totem pole outputs, however,

are not open drain type outputs and there will be current flow on

This circuit is used for monitoring and driving the CPU PROCHOT#.

The monitor device is a Heceta7 part and its output is bi-directional,

CPU1_PROCHOT# and is connected to 5A.

these pins if they are pulled high when V is at ground.

DD

The CPU has an output called PROCHOT#, which goes to 5BI and

an input call FRCPROCHOT# that comes from 7BO1.

Question 4: When this sequence occurs:

1) Pin 11BI is driven LOW (at time t0)

2) Pin 11A is driven LOW (at time t1)

When the CPU is generating PROCHPT# (5BI), we do not want the

CPU input FRCPROCHOT# (7BO1) to also see this signal.

Scenario 1: CPU driving PROCHOT#

3) Pin 11BI stops driving LOW (at time t2)

– 5BI input is HIGH and goes LOW; output 5A is HIGH and goes

LOW following 5BI. The output 7BO should stay HIGH.

4)Pin 11A stops driving LOW (at time t3)

Are there wired-OR glitches at pin 11BO at time t1 and t2?

Answer 4: The output of 11BI is physically wired to the 11A pin.

There will be no glitch at t1 when the external driver turns on and

drives LOW, unless the external driver is a long distance away and

the pull-up is a low value. If the pull-up R = Z of the line and the

current were equally shared, the bounce would be to / the pull-up

– 5BI input is LOW and goes HIGH; output 5A is LOW and goes

HIGH following 5BI. The output 7BO1 should stay HIGH.

Scenario 2: Heceta7 driving CPU1_PROCHOT#

– 5A input is HIGH and goes LOW; output 7BO1 is HIGH and goes

LOW following 5A. The input 5BI should stay HIGH.

O

1

2

1

voltage, presumably V . The input is a / V threshold input, so

DD

2

DD

– 5A input is LOW and goes HIGH; output 7BO1 is LOW and goes

HIGH following 5A. The output 5BI should stay HIGH.

the glitch may propagate to the 11BO. If the glitch is very short it

may not propagate, or if the pull-up were higher the amplitude would

be too small to propagate, or if the external driver were sinking more

than half of the total current, it would not propagate. If the external

driver is weak and a long way away you will most likely see a glitch

on 11BO, because there will be a large glitch on 11A.

Now I can see the reason for the delay in the enable path so that we

keep the output disabled to account for the potentially slow riser time

on 5A. In my mind, there should also be a delay block shown in the

path 5BI to 5A so that the 5BI H-to-L can disable the driver for 7BO1

before the signal appears on the 5A input/output, thus appearing as

an input to the driver for 7BO1.

Question 5: Can you give us some guideline on how high the

pull-up resistor value at pin 11A needs to be to avoid glitches on

11BO?

Answer 5: The 11A pin is a TTL pin, generally the pull-up resistor

used on TTL pins are chosen to minimize power rather than to

match the line impedance. Most line impedances are in the range of

Have you characterized what sort of glitch you get on the 7BO1

output on an H-to-L transition on 5BI?

Answer 6A: The disable for 7BO1 comes directly from the internal

5BI signal, and by design it always disables the LOW on 7BO1

before the LOW on the 5BI can propagate to the 5AI/O and back to

the 7BO1.

50 Ω. If the pull-up is 3 × Z , that is 150 Ω; even if all the current is

O

being sunk by the GTL2006, the initial bounce on 11A would only be

1

/ V , and would only last for the round trip time to the external

3

DD

Question 7: Can I operate the GTL2006 at V of 1.2 V and

TT

driver, provided that the external driver can sink all of the current,

V

REF

of 0.6 V?

1

the bounce will return LOW. The / V is not a high level to the

3

DD

Answer 7: Yes; you can operate V up to 3.6 V and V

TT

REF

GTL2006 11A pin, so no bounce would show up on the 11BO pin.

Normal choices for the pull-up on 11A would be in the 1 kΩ to

several kΩ range, depending on speed and current considerations.

between 0.5 V to 1.8 V at any V to adjust the high and low noise

TT

margins to your application. You don’t have to follow the

GTL–/GTL/GTL+ specifications. The GTL V and V will be 50 mV

IL

IH

around V

within the range of 0.5 V to 1.8 V.

REF

6

2004 Jun 21

Philips Semiconductors

Product data

13-bit GTL–/GTL/GTL+ to LVTTL translator

GTL2006

1

ABSOLUTE MAXIMUM RATINGS

In accordance with the Absolute Maximum System (IEC 134); voltages are referenced to GND (ground = 0 V).

SYMBOL

PARAMETER

DC supply voltage

CONDITIONS

RATING

UNIT

V

–0.5 to +4.6

–50

V

mA

V

CC

IK

I

DC input diode current

V < 0 V

I

A port (LVTTL)

B port(GTL)

–0.5 to +4.6

–50

3

V

I

DC input voltage

V

I

DC output diode current

V

O

< 0 V

mA

V

OK

Output in Off or HIGH state; A port

–0.5 to +4.6

32

3

V

O

DC output voltage

Output in Off or HIGH state; B port

V

A port

B port

A port

mA

°C

I

OL

Current into any output in the LOW state

30

I

Current into any output in the HIGH state

Storage temperature range

–32

OH

T

stg

–60 to +150

+125

T

Maximum junction temperature

J(MAX)

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the

device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not implied. Exposure to

absolute-maximum-rated conditions for extended periods may affect device reliability.

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction

temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.

3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.

RECOMMENDED OPERATING CONDITIONS

SYMBOL

PARAMETER

Supply voltage

CONDITIONS

MIN

3.0

0.85

1.14

1.35

0.5

0.76

0.87

0

TYP

3.3

0.9

1.2

1.5

MAX

3.6

UNIT

V

CC

V

GTL–

GTL

0.95

1.26

1.65

1.8

V

TT

Termination voltage

V

GTL+

Overall

GTL–

GTL

2

/ V

3

TT

0.6

0.8

1.0

3.3

0.63

0.84

1.10

3.6

V

REF

Supply voltage

GTL+

A port

B port

A port

B port

A port

B port

A port

B port

V

I

Input voltage

V

0

V

TT

3.6

2

—

V

IH

HIGH-level input voltage

V

+ 50 mV

—

REF

—

0.8

V

IL

LOW-level input voltage

V

– 50 mV

–16

16

REF

I

HIGH-level output current

LOW-level output current

—

mA

°C

OH

—

I

OL

—

15

T

amb

Operating free-air temperature range

–40

85

7

2004 Jun 21

Philips Semiconductors

Product data

13-bit GTL–/GTL/GTL+ to LVTTL translator

GTL2006

DC ELECTRICAL CHARACTERISTICS

Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

LIMITS

–40 °C to +85 °C

SYMBOL

PARAMETER

TEST CONDITIONS

UNIT

1

MIN

V –0.2

CC

TYP

MAX

V

= 3.0 V to 3.6 V I = –100 µA

—

7.8

4.5

—

CC

; OH

V

A port

V

OH

= 3.0 V I = –16 mA

2.1

—

; OH

A port

B port

= 3.0 V I = 16 mA

0.8

; OL

V

OL

= 3.0 V I = 15 mA

0.4

; OL

= 3.6 V; V = V

± 1

I

CC

A port

= 3.6 V; V = 0 V

± 1

12

I

µA

I

B port

= 3.6 V; V = V or GND

I TT

I

A or B port

= 3.6 V;V = V or GND; I = 0 mA

mA

CC

I

CC

O

3

∆I

CC

A port or control inputs

= 3.6 V; V = V – 0.6 V

500

—

µA

I

CC

A port

B port

= 3.0 V or 0 V

O

C

pF

IO

= V or 0 V

—

TT

NOTES:

1. All typical values are measured at V = 3.3 V and T

= 25 °C.

amb

CC

2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

3. This is the increase in supply current for each input that is at the specified LVTTL voltage level rather than V or GND

CC

.

AC CHARACTERISTICS (3.3 V ± 0.3 V RANGE)

LIMITS (GTL–)

LIMITS (GTL)

= 3.3 V ± 0.3 V

LIMITS (GTL+)

V = 3.3 V ± 0.3 V

CC

V

= 3.3 V ± 0.3 V

V

CC

SYMBOL

PARAMETER

WAVEFORM

UNIT

V

REF

= 0.6 V

V

REF

= 0.8 V

V = 1.0 V

REF

1

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

t

2

4

5.5

8

10

2

4

5.5

8

10

2

4

5.5

8

10

PLH

PHL

An to Bn

1

2

ns

t

2

5.5

10

2

5.5

10

2

5.5

10

PLH

PHL

Bn to An

t

2

6

11

2

6

11

2

6

11

PLH

PHL

9BI to 10BOn

11BI to 11BO

Bn to An (I/O)

Bn to Bn

t

2

8

14

13

21

2

8

14

13

21

2

8

14

13

21

PLH

2

t

PHL

t

2

5

10

2

5

10

2

5

10

PLZ

3

t

PZH

t

4

120

7

205

11

350

4

120

7

205

11

350

4

120

7

205

11

350

PLH

PHL

NOTES:

1. All typical values are at V = 3.3 V and T

= 25 °C.

amb

CC

2. Includes 7.6 ns RC rise time of test load pull-up on 11A, 1.5 kΩ pull-up and 21 pF load on 11A has about 23 ns RC rise time.

8

2004 Jun 21

Philips Semiconductors

Product data

13-bit GTL–/GTL/GTL+ to LVTTL translator

GTL2006

AC WAVEFORMS

V

= 1.5 V at V ≥ 3.0 V for A ports; V = V

for B ports

REF

M

CC

M

V

TT

t

pulse

V

H

Input

V

REF

V

REF

V

M

V

M

0 V

V

0 V

t

PHL

PLH

VOLTAGE WAVEFORMS PULSE DURATION

V

= 1.5 V for A port and V

for B port

OH

M

H

REF

= 3 V for A port and V for B port

TT

1.5 V

Output

3.0 V

V

OL

Input

1.5 V

PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.

O

r

f

0 V

t

PHL

PLH

SW00469

V

OH

OL

Waveform 2.

V

REF

Output

VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES

A port to B port

INPUT

3 V

1.5 V

SW01093

0 V

Waveform 1.

t

PLZ

PZL

OUTPUT

3.5 V

1.5 V

V

+ 0.3 V

OL

SW02235

Waveform 3.

9

2004 Jun 21

Philips Semiconductors

Product data

13-bit GTL–/GTL/GTL+ to LVTTL translator

GTL2006

PERFORMANCE CURVES

1100

1000

V

= 3.0 V

V

= 3.3 V

CC

T

amb

= –40 °C

T

amb

= +25 °C

V

(mV)

V

ref

(mV)

ref

1000

900

VTH+

VTH–

VTH+

VTH–

900

800

700

800

700

600

500

600

500

400

0.5

0.6

0.7

0.8

0.9

1.0

0.5

0.6

0.7

0.8

0.9

1.0

V

ref

(V)

V

ref

(V)

1100

1000

V

= 3.6 V

CC

T

amb

= +85 °C

V

(mV)

ref

VTH+

VTH–

900

800

700

600

500

400

0.5

0.6

0.7

0.8

0.9

1.0

V

ref

(V)

SW02255

Figure 4. GTL V

and V

versus V

TH– REF

TH+

10

2004 Jun 21

Philips Semiconductors

Product data

13-bit GTL–/GTL/GTL+ to LVTTL translator

GTL2006

TEST CIRCUIT

V

CC

V

TT

CC

V

O

I

50 Ω

PULSE

GENERATOR

D.U.T.

V

O

I

50 pF

PULSE

GENERATOR

R

T

R

= 500 Ω

L

D.U.T.

C

L

R

T

C

30 pF

L

Test circuit for switching times

DEFINITIONS

SW02066

R

L

C

L

R

T

= Load resistor

Figure 7. Load circuit for B outputs

= Load capacitance includes jig and probe capacitance

= Termination resistance should be equal to Z of pulse generators.

OUT

SW00471

Figure 5. Load circuitry for A outputs

2 × V

CC

V

CC

R

= 500 Ω

V

O

L

I

PULSE

GENERATOR

D.U.T.

50 pF

R

T

R

L

C

L

Test Circuit for open drain LVTTL I/O

DEFINITIONS

R

L

C

L

R

T

= Load resistor

= Load capacitance includes jig and probe capacitance

= Termination resistance should be equal to Z

of pulse generators.

OUT

SW02067

Figure 6. Load circuitry for open drain LVTTL I/O

11

2004 Jun 21

Philips Semiconductors

Product data

13-bit GTL–/GTL/GTL+ to LVTTL translator

GTL2006

TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm

SOT361-1

12

2004 Jun 21

Philips Semiconductors

Product data

13-bit GTL–/GTL/GTL+ to LVTTL translator

GTL2006

REVISION HISTORY

Rev

Date

Description

_2

20040621

Product data (9397 750 13063). Supersedes data of 2003 Dec 18.

Modifications:

• All figures numbered.

• Figure 2, “Logic symbol” modified.

• Page 6, Frequently asked Questions: add questions/answers 4, 5, 6, 6A, and 7.

• Page 8, AC Characteristics (3.3 V ± 0.3 Range); t

• Add “Performance curves” section on page 10.

An to Bn, GTL+ maximum: change from ‘1. ns’ to ‘10 ns’.

PHL

_1

20031218

Product data (9397 750 12562); ECN 853-2440 01-A14985 dated 15 December 2003.

13

2004 Jun 21

Philips Semiconductors

Product data

13-bit GTL–/GTL/GTL+ to LVTTL translator

GTL2006

Data sheet status

Product

status

Definitions

[1]

Level

Data sheet status

[2] [3]

I

Objective data

Development

This data sheet contains data from the objective specification for product development.

Philips Semiconductors reserves the right to change the specification in any manner without notice.

II

Preliminary data

Product data

Qualification

Production

This data sheet contains data from the preliminary specification. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the specification without notice, in

order to improve the design and supply the best possible product.

III

This data sheet contains data from the product specification. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notification (CPCN).

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL

http://www.semiconductors.philips.com.

[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see

the relevant data sheet or data handbook.

Limitingvaluesdefinition— Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting

values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given

in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no

representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be

expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree

to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described

or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated

viaaCustomerProduct/ProcessChangeNotification(CPCN).PhilipsSemiconductorsassumesnoresponsibilityorliabilityfortheuseofanyoftheseproducts,conveys

nolicenseortitleunderanypatent, copyright, ormaskworkrighttotheseproducts, andmakesnorepresentationsorwarrantiesthattheseproductsarefreefrompatent,

copyright, or mask work right infringement, unless otherwise specified.

Koninklijke Philips Electronics N.V. 2004

Contact information

For additional information please visit

http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

Date of release: 06-04

9397 750 13063

For sales offices addresses send e-mail to:

sales.addresses@www.semiconductors.philips.com.

Document order number:

Philips

Semiconductors

14

2004 Jun 21


型号：	GTL2006
厂家：	NXP
描述：	13-bit GTL-/GTL/GTL+ to LVTTL translator 13位GTL- / GTL / GTL +至LVTTL翻译
文件：	总14页 (文件大小：130K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

GTL2006 [NXP]

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