GTL16612DL,512 [NXP]
IC GTL SERIES, DUAL 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 3.90 MM, PLASTIC, MO-118, SOT371-1, SSOP-56, Bus Driver/Transceiver;
| 型号： | GTL16612DL,512 |
| 厂家： | 
NXP |
| 描述： | IC GTL SERIES, DUAL 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 3.90 MM, PLASTIC, MO-118, SOT371-1, SSOP-56, Bus Driver/Transceiver 信息通信管理 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总13页 (文件大小：98K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
GTL16612
18-bit GTL/GTL+ to LVTTL/TTL
bidirectional universal translator (3-State)
Product data
2002 Dec 13
Supersedes data of 2000 Jun 19
Philips
Semiconductors
Philips Semiconductors
Product specification
18-bit GTL/GTL+ to LVTTL/TTL bidirectional
universal translator (3-State)
GTL16612
FEATURES
• 18-bit bidirectional bus interface
DESCRIPTION
The GTL16612 is a high-performance BiCMOS product designed for
V
CC
operation at 3.3 V with I/O compatibility up to 5 V.
• Translates between GTL/GTL+ logic levels (B ports) and
This device is an 18-bit universal transceiver featuring non-inverting
3-State bus compatible outputs in both send and receive directions.
Data flow in each direction is controlled by output enable (OEAB and
OEBA), latch enable (LEAB and LEBA), and clock (CPAB and
CPBA) inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is High. When LEAB is Low, the A
data is latched if CPAB is held at a High or Low logic level. If LEAB
is Low, the A-bus data is stored in the latch/flip-flop on the
Low-to-High transition of CPAB. When OEAB is Low, the outputs are
active. When OEAB is High, the outputs are in the high-impedance
state. The clocks can be controlled with the clock-enable inputs
(CEBA/CEAB).
LVTTL/TTL logic levels (A ports)
• 5 V I/O tolerant on the LVTTL/TTL side (A ports)
• No bus current loading when LVTTL/TTL output is tied to 5 V bus
• 3-State buffers
• Output capability: +64 mA/-32 mA on the LVTTL/TTL side
(A ports); +40 mA on the GTL/GTL+ side (B ports)
• TTL input levels on control pins
• Power-up reset
• Power-up 3-State
Data flow for B-to-A is similar to that of A-to-B but uses OEBA,
LEBA and CPBA.
• Positive edge triggered clock inputs
• Latch-up protection exceeds 500 mA per JESD78
• ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
QUICK REFERENCE DATA
TYPICAL
CONDITIONS
UNIT
SYMBOL
PARAMETER
T
amb
= 25 °C
3.3 V
t
t
Propagation delay
An to Bn or Bn to An
PLH
PHL
C = 50 pF
L
1.9
ns
C
Input capacitance (Control pins)
I/O pin capacitance
V = 0 V or V
CC
4
8
pF
pF
IN
I
C
Outputs disabled; V = 0 V or V
CC
I/O
I/O
I
Total supply current
Outputs disabled
12
mA
CCZ
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
-40 to +85 °C
ORDER CODE
GTL16612DL
DWG NUMBER
SOT371-1
56-Pin Plastic SSOP
56-Pin Plastic TSSOP
-40 to +85 °C
GTL16612DGG
SOT364-1
Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.
2
2002 Dec 13
Philips Semiconductors
Product specification
18-bit GTL/GTL+ to LVTTL/TTL bidirectional
universal translator (3-State)
GTL16612
PIN CONFIGURATION
PIN DESCRIPTION
PIN NUMBER
SYMBOL
NAME AND FUNCTION
OEAB
LEAB
A0
1
2
3
4
5
6
7
8
9
56
CEAB
1, 27
OEAB/OEBA A-to-B/ B-to-A Output enable
input (active Low)
55
54
53
52
CPAB
B0
29, 56
2, 28
CEBA/CEAB B-to-A/A-to-B clock enable
LEAB/LEBA A-to-B/B-to-A Latch enable input
GND
A1
GND
B1
55,30
CPAB/CPBA A-to-B/B-to-A Clock input
(active rising edge)
A2
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
B2
NC
V
CC
3, 5, 6, 8, 9, 10,
12, 13, 14, 15,
16, 17, 19, 20,
21, 23, 24, 26
A3
B3
A0-A17
Data inputs/outputs (A side)
A4
B4
A5 10
GND 11
A6 12
B5
GND
B6
54, 52, 51, 49,
48, 47, 45, 44,
43, 42, 41, 40,
38, 37, 36, 34,
33, 31
B0-B17
GND
Data inputs/outputs (B side)
Ground (0 V)
A7 13
B7
A8 14
B8
A9 15
B9
4, 11, 18, 25,
32, 39, 46, 53
A10 16
A11 17
GND 18
A12 19
A13 20
A14 21
B10
B11
GND
B12
B13
B14
7, 22
35
V
Positive supply voltage
GTL reference voltage
No connection
CC
V
REF
50
NC
22
V
V
CC
REF
A15 23
A16 24
B15
B16
GND 25
A17 26
GND
B17
OEBA 27
LEBA 28
CPBA
CEBA
SW00485
3
2002 Dec 13
Philips Semiconductors
Product specification
18-bit GTL/GTL+ to LVTTL/TTL bidirectional
universal translator (3-State)
GTL16612
LOGIC SYMBOL (Positive Logic)
1
OEAB
56
CEAB
55
CPAB
2
LEAB
28
LEBA
30
CPBA
29
CEBA
27
OEBA
CE
1D
C1
3
A0
54
B0
CLK
CE
1D
C1
CLK
To 17 other channels
SW00254
FUNCTION TABLE
INPUTS
OUTPUT
B
1
1
1
1
CEAB
OEAB
LEAB
CPAB
A
X
L
X
X
X
H
H
L
H
L
L
L
L
L
L
L
L
X
H
H
L
L
L
L
L
L
X
X
X
X
X
↑
↑
H
L
Z
L
H
X
X
L
H
2
B
B
O
2
O
L
L
H
X
X
H
2
3
L
B
O
O
L
B
X = Don’t care
H = High voltage level
L = Low voltage level
↑ = Low to High
Z = High impedance “off” state
1. A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, CPBA, and CEBA.
2. Output level before the indicated steady-state input conditions were established.
3. Output level before the indicated steady-state input conditions were established, provided that CPAB was Low before LEAB went Low.
4
2002 Dec 13
Philips Semiconductors
Product specification
18-bit GTL/GTL+ to LVTTL/TTL bidirectional
universal translator (3-State)
GTL16612
1, 2
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
CONDITIONS
RATING
-0.5 to +4.6
-50
UNIT
V
V
CC
I
IK
DC supply voltage
DC input diode current
V < 0
I
mA
A port
-0.5 to +7.0
-0.5 to +4.6
-50
3
V
DC input voltage
V
I
B port
I
DC output diode current
V
O
< 0; A port
mA
V
OK
Output in Off or High state; A port
-0.5 to +7.0
-0.5 to +4.6
128
3
V
O
DC output voltage
Output in Off or High state; B port
V
A port
B port
A port
mA
mA
mA
°C
I
OL
Current into any output in the LOW state
80
I
Current into any output in the HIGH state
Storage temperature range
-64
OH
T
stg
-65 to +150
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
3.3 V RANGE LIMITS
SYMBOL
PARAMETER
DC supply voltage
TEST CONDITIONS
UNIT
V
MIN
3.0
1.14
1.35
0.74
0.9
0
MAX
3.6
V
CC
GTL
1.26
1.65
0.87
1.10
V
TT
Termination voltage
GTL reference voltage
Input voltage
V
+
GTL
GTL
V
REF
V
V
V
+
GTL
B port
Except B port
B port
V
TT
V
I
0
5.5
V
REF
+50 mV
V
IH
HIGH-level input voltage
Except B port
B port
2.0
V -50 mV
REF
V
IL
LOW-level input voltage
V
Except A port
A port
0.8
-32
40
I
HIGH-level output current
LOW-level output current
mA
mA
°C
OH
B port
I
OL
A port
64
T
amb
Operating free-air temperature range
-40
+85
5
2002 Dec 13
Philips Semiconductors
Product specification
18-bit GTL/GTL+ to LVTTL/TTL bidirectional
universal translator (3-State)
GTL16612
DC ELECTRICAL CHARACTERISTICS (3.3 V "0.3 V RANGE)
LIMITS
Temp = -40 to +85 °C
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS
1
MIN
TYP
MAX
V
Input clamp voltage
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
= 3.0 V; I = -18 mA
-0.85
-1.2
V
V
IK
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
IK
= 3.0 to 3.6 V; I
= -100 µA
V
CC
-0.2
V
CC
OH
V
OH
High-level output voltage
A port
A port
= 3.0 V; I
= -32 mA
2.0
2.3
0.07
0.25
0.3
0.4
0.4
0.1
0.1
0.1
0.5
0.1
OH
= 3.0 V; I = 100 µA
0.2
0.4
0.5
0.55
0.5
1
OL
= 3.0 V; I = 16 mA
OL
V
= 3.0 V; I = 32 mA
V
OL
Low-level output voltage
OL
= 3.0 V; I = 64 mA
OL
= 3.0 V; I = 40 mA
B port
V
OL
= 3.6 V; V = V or GND
I
CC
Control pins
µA
= 0 or 3.6 V; V = 5.5 V
10
I
= 3.6 V; V = 5.5 V
20
I
I
Input leakage current
4
I
I/O Data pins
A port
= 3.6 V; V = V
10
µA
I
CC
= 3.6 V; V = 0
-5
I
= 3.6 V; V = V or GND
B port
5
µA
µA
I
TT
I
Output off current
= 0 V; V or V = 0 to 4.5 V
0.1
130
-140
100
OFF
I
O
= 3 V; V = 0.8 V
75
I
I
Bus Hold current, A outputs
Current into an output in the
µA
HOLD
= 3 V; V = 2.0 V
-75
I
I
EX
V
V
= 5.5 V; V = 3.0 V
A port
10
125
100
µA
µA
O
CC
High state when V > V
O
CC
≤ 1.2 V; V = 0.5 V to V ; V = GND or V
Power up/down 3-State
CC
O
CC
I
CC
I
1.0
PU/PD
3
output current
OE = Don’t care
Outputs high
Outputs low
Disabled
I
5.0
10.5
6.0
9.0
CCH
A-Port
I
18.5
11.5
17.5
12.0
CCL
5
I
V
CC
= 3.6 V
V = GND or V
I
O
= 0
mA
mA
CCZ
I
CC,
I
Outputs high
Outputs low
9.7
CCH
B-Port
I
7.0
CCL
Additional supply current per
V
= 3 V to 3.6 V; One input at V -0.6 V,
CC CC
∆I
CC
0.04
0.2
2
input pin
Other inputs at V or GND
CC
NOTES:
1. All typical values are at V = 3.3 V and T
2. This is the increase in supply current for each LVTTL input at the specified voltage level other than V or GND
= 25 °C.
CC
amb
CC
3. This parameter is valid for any V between 0 V and 1.2 V with a transition time of up to 10 msec. From V = 1.2 V to V = 3.3 V 0.3 V
CC
CC
CC
a transition time of 100 µsec is permitted. This parameter is valid for T
= 25°C only.
amb
4. Unused pins at V or GND.
CC
5. I
is measured with outputs pulled up to V or pulled down to ground.
CCZ
CC
6
2002 Dec 13
Philips Semiconductors
Product specification
18-bit GTL/GTL+ to LVTTL/TTL bidirectional
universal translator (3-State)
GTL16612
AC CHARACTERISTICS (A PORT)
GND = 0 V; t = t = 2.5 ns; C = 50 pF; R = 500 Ω; T
= -40 to +85 °C.
r
f
L
L
amb
GTL
GTL+
= 3.3 V 0.3 V
V
= 3.3 V 0.3 V
V
CC
GTL16612 An Port
CC
UNIT
V
= 0.8 V
V
REF
= 1.0 V
REF
1
1
SYMBOL
PARAMETER
WAVEFORM
MIN
1.6
3.0
1.6
1.6
1.9
1.8
1.5
1.4
1.3
1.2
TYP
MAX
5.0
6.3
4.2
4.3
4.7
5.2
4.2
4.8
3.8
3.5
MIN
1.6
3.0
1.6
1.6
1.9
1.8
1.5
1.4
1.3
1.2
TYP
MAX
5.0
6.3
4.2
4.3
4.7
5.2
4.2
4.8
3.8
3.5
t
t
t
t
t
t
t
t
t
t
Bn to An
2
2
3
3
1
1
5
5
6
6
3.0
4.9
2.7
2.8
3.4
3.8
2.6
2.9
2.4
2.2
3.0
4.9
2.7
2.8
3.4
3.8
2.6
2.9
2.4
2.2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PHZ
PZL
PLZ
Bn to An
LEBA to An
LEBA to An
CPBA to An
CPBA to An
OEBA to An
OEBA to An
OEBA to An
OEBA to An
NOTE:
1. Typical values are at V = 3.3 V, T
= +25 °C.
amb
CC
AC CHARACTERISTICS (B PORT)
GND = 0 V; t = t = 2.5 ns; C = 30 pF; R = 25 Ω; T
= -40 to +85 °C.
r
f
L
L
amb
GTL
GTL+
V
= 3.3 V 0.3 V
V
= 3.3 V 0.3 V
GTL16612 Bn Port
CC
CC
UNIT
V
= 0.8 V
V
= 1.0 V
REF
REF
1
1
SYMBOL
PARAMETER
WAVEFORM
MIN
1.4
1.3
1.7
2.1
1.8
2.3
1.1
1.6
TYP
MAX
3.7
4.0
4.4
5.4
4.5
5.4
3.3
4.4
MIN
1.3
1.4
1.8
2.3
1.9
2.4
1.4
1.0
TYP
MAX
3.7
4.2
4.6
5.5
4.8
5.8
3.5
4.5
t
t
t
t
t
t
t
t
An to Bn
2
2
3
3
1
1
7
7
2.4
2.5
3.0
3.5
3.1
3.6
2.1
2.8
2.4
2.6
3.0
3.6
3.1
3.8
2.0
2.9
ns
ns
ns
ns
ns
ns
ns
ns
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
An to Bn
LEAB to Bn
LEAB to Bn
CPAB to Bn
CPAB to Bn
OEAB to Bn
OEAB to Bn
NOTE:
1. Typical values are at V = 3.3 V, T
= +25 °C.
amb
CC
7
2002 Dec 13
Philips Semiconductors
Product specification
18-bit GTL/GTL+ to LVTTL/TTL bidirectional
universal translator (3-State)
GTL16612
AC SETUP REQUIREMENTS (3.3 V 0.3 V RANGE)
A Port: GND = 0 V; Input t = t = 2.5 ns; C = 50 pF; R = 500 Ω; T
= -40 to +85 °C; V
= 0.8 V or 1.0 V.
r
f
L
L
amb
REF
B Port: GND = 0 V; Input t = t = 2.5 ns; C = 30 pF; R = 25 Ω; V
= 0.8 V or 1.0 V.
r
f
L
L
REF
LIMITS
= 3.3 V 0.3 V
V
CC
SYMBOL
PARAMETER
WAVEFORM
UNIT
MIN
1.5
1.5
2.0
3.0
1.0
1.0
1.0
1.0
1.5
1.5
1.0
1.0
1.5
1.0
2.0
2.0
MAX
t (H)
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
Setup time, High or Low
Bn to CPBA
t (L)
s
t (H)
s
Setup time, High or Low
An to CPAB
t (L)
s
t (H)
h
Hold time, High or Low
Bn to CPBA, or An to CPAB
t (L)
h
t (H)
s
Setup time, High or Low
Bn to LEBA, or An to LEAB
t (L)
s
t (H)
h
Hold time, High or Low
Bn to LEBA, or An to LEAB
t (L)
h
t (H)
s
Setup time, High or Low
CEAB to CPAB, or CEBA to CPBA
t (L)
s
t (H)
h
Hold time, High or Low
CEAB to CPAB, or CEBA to CPBA
t (L)
h
t (H)
w
Pulse width, High or Low
CPBA or CPAB
t (L)
w
Pulse width, High
LEBA or LEAB
t (H)
w
3
1.5
ns
8
2002 Dec 13
Philips Semiconductors
Product specification
18-bit GTL/GTL+ to LVTTL/TTL bidirectional
universal translator (3-State)
GTL16612
AC WAVEFORMS
V
M
V
X
V
Y
= 1.5 V at V w 3.0 V. V = 1.5 V for A ports and control pins; V = 0.8 V for B ports in GTL mode; V = 1.0 V for B ports in GTL+ mode.
CC M M M
= V + 0.3 V at V w 3.0 V.
OL
CC
= V
- 0.3 V at V w 3.0 V.
OH
CC
1/f
MAX
3.0 V or V
whichever is
less
,
CC
3.0 V or V
whichever is
less
,
OEBA
CC
V
V
M
M
CPBA or
CPAB
V
V
M
t
M
t
0V
t
t
PHZ
PZH
t
(L)
t (H)
W
W
V
PHL
PLH
OH
V
OH
V
Y
V
An or Bn
M
V
An or Bn
M
V
M
V
OL
SW00223
SW00181
Waveform 1. Propagation delay, clock input to output, clock
pulse width, and maximum clock frequency
Waveform 5. 3-State output enable time to high level
and output disable time from high level
3.0 V or V
whichever is
less
,
CC
3.0V or V
whichever is
less
,
CC
OEBA
V
V
M
M
V
V
M
An or Bn
M
t
0V
t
t
t
PLZ
PLH
PHL
PZL
V
OH
An or Bn
V
M
V
X
V
V
M
M
An or Bn
V
OL
V
OL
SW00224
SW00176
Waveform 2. Propagation delay, transparent mode
Waveform 6. 3-State output enable time to low level
and output disable time from low level
3.0V or V
whichever is
less
,
CC
3.0 V or V
whichever is
less
,
CC
OEAB
V
V
V
M
M
M
V
V
M
LEAB or
LEBA
M
0V
t (H)
W
t
t
PHL
t
PLH
PLH
t
PHL
V
OH
Bn
An or Bn
V
V
M
M
V
V
M
M
V
OL
V
OL
SW00495
SW00177
Waveform 3. Propagation delay, enable to output,
and enable pulse width
Waveform 7. Output enable time on open collector output
with pullup
An or Bn
CEAB or CEBA
3.0 V or V
,
CC
whichever is
less
V
V
M
V
V
M
M
M
0V
t (H)
S
t (H)
h
t (L)
h
t (L)
S
3.0 V or V
,
CC
whichever is
less
CPAB or CPBA,
LEAB or LEBA
V
V
M
M
0V
SW00222
Waveform 4. Data setup and hold times
9
2002 Dec 13
Philips Semiconductors
Product specification
18-bit GTL/GTL+ to LVTTL/TTL bidirectional
universal translator (3-State)
GTL16612
TEST CIRCUIT
6.0 V or V x 2
CC
V
CC
V
t
W
IN
Open
GND
90%
90%
R
500 Ω
=
L
NEGATIVE
PULSE
V
V
M
M
10%
V
V
OUT
IN
10%
90%
PULSE
GENERATOR
D.U.T.
0 V
t
t
(t
(t
)
t
t
(t
R
)
THL
F
TLH
R
T
R
500 Ω
=
L
C
L
)
(t
)
TLH
R
THL
F
V
IN
90%
M
POSITIVE
PULSE
Test Circuit for A Outputs
V
V
M
10%
10%
1.2 V
t
W
0 V
25 Ω
TEST POINT
FROM OUTPUT
UNDER TEST
C
= 30 pF
L
(INCLUDES PROBE AND JIG CAPACITANCE)
Load Circuit for B Outputs
SWITCH POSITION
TEST
SWITCH
6 V
t
t
PLZ/ PZL
t
t
Open
GND
PLH/ PHL
t
/t
PHZ PZH
DEFINITIONS
INPUT PULSE REQUIREMENTS
Rep. Rate
R = Load resistor; see AC CHARACTERISTICS for value.
L
FAMILY
Amplitude
3.0 V or V
t
t
R
t
F
W
C = Load capacitance includes jig and probe capacitance:
L
See AC CHARACTERISTICS for value.
CC
whichever
is less
74GTL16
v10 MHz 500 ns v2.5 ns v2.5 ns
R
T
=
Termination resistance should be equal to Z
pulse generators.
of
OUT
SW00255
10
2002 Dec 13
Philips Semiconductors
Product specification
18-bit GTL/GTL+ to LVTTL/TTL bidirectional
universal translator (3-State)
GTL16612
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm
SOT364-1
11
2002 Dec 13
Philips Semiconductors
Product specification
18-bit GTL/GTL+ to LVTTL/TTL bidirectional
universal translator (3-State)
GTL16612
REVISION HISTORY
Rev
Date
Description
_4
20021213
Product data (9397 750 10862); ECN 853-2166 29245 of 03 December 2002
Modifications:
• New package release.
_3
20000619
Product data (9397 750 07217); ECN 853-2166 23903 of 19 June 2000.
12
2002 Dec 13
Philips Semiconductors
Product specification
18-bit GTL/GTL+ to LVTTL/TTL bidirectional
universal translator (3-State)
GTL16612
Data sheet status
Product
status
Definitions
[1]
Level
Data sheet status
[2] [3]
I
Objective data
Development
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Product data
Qualification
Production
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described
or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated
via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys
no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent,
copyright, or mask work right infringement, unless otherwise specified.
Koninklijke Philips Electronics N.V. 2002
Contact information
All rights reserved. Printed in U.S.A.
For additional information please visit
http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
Date of release: 12-02
For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.
Document order number:
9397 750 10862
Philips
Semiconductors
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