ESJW05_技术文档

74LVT14

3.3 V hex inverter Schmitt trigger

Rev. 02 — 25 April 2008

Product data sheet

1. General description

The 74LVT14 is a high-performance BiCMOS product designed for V_CCoperation at 3.3 V.

It is capable of transforming slowly changing input signals into sharply deﬁned, jitter free

output signals. In addition, it has a greater noise margin than conventional inverters.

Each circuit contains a Schmitt trigger followed by a Darlington level shifter and a phase

splitter driving a TTL totem-pole output. The Schmitt trigger uses positive feedback to

effectively speed-up slow input transitions, and provide different input threshold voltages

for positive-going and negative-going inputs. The threshold differential (typically 600 mV)

is determined internally by resistor ratios and is insensitive to temperature and supply

voltage variations.

2. Features

I Different positive and negative going input threshold voltages

I Tolerant of slow input transitions

I High noise immunity

I TTL input and output switching levels

I Output capability: +32 mA/−20 mA

I Latch-up protection exceeds 500 mA per JESD78 class II level A

I ESD protection:

N HBM JESD22-A114E exceeds 2000 V

N MM JESD22-A115-A exceeds 200 V

3. Ordering information

Table 1.

Ordering information

Type number

Package

Temperature range Name

Description

Version

74LVT14D

−40 °C to +85 °C

SO14

plastic small outline package; 14 leads;

body width 7.5 mm

SOT108-1

74LVT14DB

74LVT14PW

74LVT14BQ

SSOP14

TSSOP14

plastic shrink small outline package; 14 leads;

body width 5.3 mm

SOT337-1

SOT402-1

plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1

thin quad ﬂat package; no leads; 14 terminals;

body 2.5 × 4.5 × 0.85 mm

74LVT14

NXP Semiconductors

3.3 V hex inverter Schmitt trigger

4. Functional diagram

1

3

2

4

1A

2A

3A

4A

5A

6A

1Y

2Y

3Y

4Y

5Y

6Y

2

1

3

5

6

4

6

5

9

8

9

11

13

10

12

10

12

11

13

A

Y

mna204

001aac497

mna025

Fig 1. Logic symbol

Fig 2. IEC logic symbol

Fig 3. Logic diagram

5. Pinning information

5.1 Pinning

74LVT14

terminal 1

index area

74LVT14

2

3

4

5

6

13

12

11

10

9

1Y

6A

6Y

5A

5Y

4A

1

2

3

4

5

6

7

14

2A

2Y

3A

3Y

1A

1Y

V

CC

13

12

11

10

9

6A

6Y

5A

5Y

4A

4Y

2A

(1)

GND

2Y

3A

3Y

001aah921

GND

8

Transparent top view

001aah920

(1) The die substrate is attached to this pad using a

conductive die attach material. It cannot be used as a

supply pin or input.

Fig 4. Pin conﬁguration for SO14 and (T)SSOP14

Fig 5. Pin conﬁguration for DHVQFN14

74LVT14_2

Product data sheet

Rev. 02 — 25 April 2008

2 of 13

74LVT14

NXP Semiconductors

3.3 V hex inverter Schmitt trigger

5.2 Pin description

Table 2.

Symbol

1A to 6A

1Y to 6Y

GND

Pin description

Description

1, 3, 5, 9, 11, 13

data input

2, 4, 6, 8, 10, 12

data output

7

ground (0 V)

positive supply voltage

V_CC

14

6. Functional description

Table 3.

Function selection

Inputs

Output

nA

L

nY

H

L

[1] H = HIGH voltage level;

L = LOW voltage level.

7. Limiting values

Table 4.

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Limiting values ^[1]

Symbol

V_CC

V_I

Parameter

Conditions

Min

−0.5

−50

-

Max

+4.6

+7.0

-

Unit

V

supply voltage

[2]

input voltage

V

V_O

output voltage

output in OFF or HIGH state

V_I< 0 V

V

I_IK

input clamping current

output clamping current

output current

mA

°C

I_OK

V_O< 0 V

-

I_O

output in LOW state

output in HIGH state

64

−32

−65

-

T_stg

T_j

storage temperature

junction temperature

total power dissipation

+150

500

°C

[3]

P_tot

T_amb= −40 °C to +85 °C

mW

[1] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction

temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.

[2] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.

[3] For SO14 packages: above 70 °C derate linearly with 8 mW/K.

For SSOP14 and TSSOP14 packages: above 60 °C derate linearly with 5.5 mW/K.

For DHVQFN14 packages: above 60 °C derate linearly with 4.5 mW/K.

74LVT14_2

Product data sheet

Rev. 02 — 25 April 2008

3 of 13

74LVT14

NXP Semiconductors

3.3 V hex inverter Schmitt trigger

8. Recommended operating conditions

Table 5.

Recommended operating conditions

Symbol Parameter

Conditions

Min

2.7

0

Typ

Max

3.6

5.5

-

Unit

V

V_CC

V_I

supply voltage

-

input voltage

V

I_OH

HIGH-level output current

LOW-level output current

ambient temperature

input transition rise and fall rate

−20

-

mA

°C

I_OL

32

T_amb

∆t/∆V

in free air

−40

0

+85

10

output enabled

ns/V

9. Static characteristics

Table 6.

Static characteristics

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions

−40 °C to +85 °C

Unit

Min

1.5

Typ^[1]Max

V_T+

V_T−

V_H

positive-going threshold voltage V_CC= 3.3 V; see Figure 7

negative-going threshold voltage V_CC= 3.3 V; see Figure 7

1.7

1.1

0.6

-

2.0

1.3

-

V

0.9

0.4

−1.2

2.0

-

hysteresis voltage

V_CC= 3.3 V; see Figure 7

V_CC= 2.7 V; I_IK= –18 mA

V_IK

V_IH

V_IL

input clamping voltage

HIGH-level input voltage

LOW-level input voltage

HIGH-level output voltage

-

0.8

-

V_OH

V_CC= 2.7 V to 3.6 V; I_OH= −100 µA

V_CC= 2.7 V; I_OH= −6 mA

V_CC= 3.0 V; I_OH= −20 mA

V_CC= 2.7 V; I_OL= 100 µA

V_CC= 2.7 V; I_OL= 24 mA

V_CC= 3.0 V; I_OL= 32 mA

V_CC= 0 V or 3.6 V; V_I= 5.5 V

V_CC= 3.6 V; V_I= V_CCor GND

V_CC= 0 V; V_Ior V_O= 0 V to 4.5 V

V_CC= 3.6 V; V_I= GND or V_CC; I_O= 0 A

outputs HIGH

V_CC− 0.2 -

V

2.4

-

V

2.0

-

V

V_OL

LOW-level output voltage

input leakage current

-

0.2

0.5

10

±1

V

I_I

µA

I_OFF

I_CC

power-off leakage current

supply current

±100 µA

-

0.02

3

mA

outputs LOW

1.5

-

[2]

∆I_CC

additional supply current

input capacitance

per input pin; V_CC= 3.0 V to 3.6 V;

one input = V_CC− 0.6 V

other inputs at V_CCor GND

0.2

C_I

V_I= 0 V or 3.0 V

-

3

-

pF

[1] All typical values are measured at V_CC= 3.3 V (unless stated otherwise) and T_amb= 25 °C.

[2] This is the increase in the supply current for each input at the speciﬁed voltage level other than V_CCor GND.

74LVT14_2

Product data sheet

Rev. 02 — 25 April 2008

4 of 13

74LVT14

NXP Semiconductors

3.3 V hex inverter Schmitt trigger

10. Dynamic characteristics

Table 7.

Dynamic characteristics

Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 8.

Symbol Parameter

Conditions

−40 °C to +85 °C

Unit

Min

Typ^[1]

Max

t_PLH

LOW to HIGH propagation delay

nA to nY

V_CC= 2.7 V

-

6.9

5.7

ns

V_CC= 3.3 V + 0.3 V

nA to nY

1.0

3.8

t_PHL

HIGH to LOW propagation delay

V_CC= 2.7 V

-

4.1

4.5

ns

V_CC= 3.3 V + 0.3 V

1.0

3.2

[1] Typical values are measured at T_amb= 25 °C and V_CC= 3.3 V.

11. Waveforms

V

I

V

M

nA input

M

GND

t

PHL

PLH

V

OH

V

M

nY output

M

V

OL

mna344

See Table 8 for measurement points.

V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig 6. nA Input to nY output propagation delays

V

O

V

T+

V

I

V

H

V

T−

V

I

V

O

H

V

T+

T−

mna207

mna208

a. Transfer characteristics

b. Voltage levels

Fig 7. Deﬁnition of V_T+, V_T−and V_H

74LVT14_2

Product data sheet

Rev. 02 — 25 April 2008

5 of 13

74LVT14

NXP Semiconductors

3.3 V hex inverter Schmitt trigger

Table 8.

V_CC

Measurement points

Input

V_M

Output

V_M

2.7 V to 3.6 V

1.5 V

t

W

V

I

90 %

negative

pulse

V

M

10 %

0 V

t

r

f

t

f

r

V

I

90 %

positive

pulse

V

M

10 %

0 V

t

W

V

CC

V

O

I

PULSE

GENERATOR

DUT

R

T

C

L

R

L

001aaf615

Test data is given in given in Table 9.

Deﬁnitions for test circuit:

R_L= Load resistance;

C_L= Load capacitance including jig and probe capacitance;

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator.

Fig 8. Load circuitry for switching times

Table 9.

Supply

Test data

Input pulse requirements

Load

R_L

V_CC

V_I

Repetition rate t_W

≤ 10 MHz 500 ns

t_r, t_f

C_L

2.7 V to 3.3 V

2.7 V

≤ 2.5 ns

500 Ω

50 pF

74LVT14_2

Product data sheet

Rev. 02 — 25 April 2008

6 of 13

74LVT14

NXP Semiconductors

3.3 V hex inverter Schmitt trigger

12. Package outline

SO14: plastic small outline package; 14 leads; body width 3.9 mm

SOT108-1

D

E

A

X

c

y

H

v

M

A

E

Z

8

14

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

7

e

detail X

w

M

b

p

0

2.5

scale

5 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

p

Q

v

w

y

Z

θ

1

2

3

p

E

max.

0.25

0.10

1.45

1.25

0.49

0.36

0.25

0.19

8.75

8.55

4.0

3.8

6.2

5.8

1.0

0.4

0.7

0.6

0.7

0.3

mm

1.75

1.27

0.05

1.05

0.25

0.01

0.25

0.1

0.25

0.01

8^o

0^o

0.010 0.057

0.004 0.049

0.019 0.0100 0.35

0.014 0.0075 0.34

0.16

0.15

0.244

0.228

0.039 0.028

0.016 0.024

0.028

0.012

inches

0.041

0.01 0.004

0.069

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT108-1

076E06

MS-012

Fig 9. Package outline SOT108-1 (SO14)

74LVT14_2

Product data sheet

Rev. 02 — 25 April 2008

7 of 13

74LVT14

NXP Semiconductors

3.3 V hex inverter Schmitt trigger

SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm

SOT337-1

D

E

A

X

c

y

H

v

M

A

E

Z

8

14

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

7

1

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

p

1

2

3

E

max.

8^o

0^o

0.21

0.05

1.80

1.65

0.38

0.25

0.20

0.09

6.4

6.0

5.4

5.2

7.9

7.6

1.03

0.63

0.9

0.7

1.4

0.9

mm

2

0.25

0.65

1.25

0.2

0.13

0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT337-1

MO-150

Fig 10. Package outline SOT337-1 (SSOP14)

74LVT14_2

Product data sheet

Rev. 02 — 25 April 2008

8 of 13

74LVT14

NXP Semiconductors

3.3 V hex inverter Schmitt trigger

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm

SOT402-1

D

E

A

X

c

y

H

v

M

A

E

Z

8

14

Q

(A )

3

A

2

A

1

pin 1 index

θ

L

p

L

1

7

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

1

2

3

p

E

p

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.72

0.38

mm

1.1

0.65

0.25

1

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT402-1

MO-153

Fig 11. Package outline SOT402-1 (TSSOP14)

74LVT14_2

Product data sheet

Rev. 02 — 25 April 2008

9 of 13

74LVT14

NXP Semiconductors

3.3 V hex inverter Schmitt trigger

DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

14 terminals; body 2.5 x 3 x 0.85 mm

SOT762-1

B

A

D

A

1

E

c

detail X

terminal 1

index area

C

terminal 1

index area

e

1

y

e

b

v

M

C

A

B

C

1

w

M

2

6

L

1

7

8

E

h

e

14

13

9

D

h

X

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

A

(1)

UNIT

A

b

c

E

e

1

y

D

E

L

v

w

y

1

h

1

max.

0.05 0.30

0.00 0.18

3.1

2.9

1.65

1.35

2.6

2.4

1.15

0.85

0.5

0.3

mm

0.05

0.1

1

0.2

0.5

2

0.1

0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

02-10-17

03-01-27

SOT762-1

- - -

MO-241

- - -

Fig 12. Package outline SOT762-1 (DHVQFN14)

74LVT14_2

Product data sheet

Rev. 02 — 25 April 2008

10 of 13

74LVT14

NXP Semiconductors

3.3 V hex inverter Schmitt trigger

13. Abbreviations

Table 10. Abbreviations

Acronym

BiCMOS

DUT

Description

Integrated Bipolar junction transistors and CMOS

Device Under Test

ESD

ElectroStatic Discharge

HBM

Human Body Model

TTL

Transistor-Transistor Logic

14. Revision history

Table 11. Revision history

Document ID

74LVT14_2

Release date

20080425

Data sheet status

Change notice

Supersedes

Product data sheet

-

74LVT14_1

Modiﬁcations:

• The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Quick reference section removed.

• DHVQFN14 package added to Section 3 “Ordering information” and Section 12 “Package

outline”.

• Section 13 “Abbreviations” added.

74LVT14_1

19960828

Product speciﬁcation

-

74LVT14_2

Product data sheet

Rev. 02 — 25 April 2008

11 of 13

74LVT14

NXP Semiconductors

3.3 V hex inverter Schmitt trigger

15. Legal information

15.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of an NXP Semiconductors product can reasonably be expected

15.2 Deﬁnitions

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

15.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

16. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

74LVT14_2

Product data sheet

Rev. 02 — 25 April 2008

12 of 13

74LVT14

NXP Semiconductors

3.3 V hex inverter Schmitt trigger

17. Contents

1

2

3

4

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 1

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 2

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

6

Functional description . . . . . . . . . . . . . . . . . . . 3

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3

Recommended operating conditions. . . . . . . . 4

Static characteristics. . . . . . . . . . . . . . . . . . . . . 4

Dynamic characteristics . . . . . . . . . . . . . . . . . . 5

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 11

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11

7

8

9

10

11

12

13

14

15

Legal information. . . . . . . . . . . . . . . . . . . . . . . 12

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12

Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 12

15.1

15.2

15.3

15.4

16

17

Contact information. . . . . . . . . . . . . . . . . . . . . 12

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 25 April 2008

Document identifier: 74LVT14_2


型号：	ESJW05
厂家：	NXP
描述：	3.0A 5.0kV 150nS High Current High Voltage Silicon Rectifier Diodes
文件：	总13页 (文件大小：90K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ESJW05 [NXP]

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