CBTD3306GT [NXP]
Dual bus switch with level shifting Multiple package options; 双母线开关，电平转换多种封装选项
| 型号： | CBTD3306GT |
| 厂家： | 
NXP |
| 描述： | Dual bus switch with level shifting Multiple package options |
| 文件： | 总17页 (文件大小：149K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CBTD3306
Dual bus switch with level shifting
Rev. 5 — 28 April 2011
Product data sheet
1. General description
The CBTD3306 dual FET bus switch features independent line switches. Each switch is
disabled when the associated output enable (nOE) input is HIGH.
The CBTD3306 is characterized for operation from −40 °C to +85 °C.
2. Features and benefits
Designed to be used in 5 V to 3.3 V level shifting applications with internal diode
5 Ω switch connection between two ports
TTL-compatible input levels
Multiple package options
Latch-up protection exceeds 100 mA per JESD78B
ESD protection:
HBM JESD22-A114F exceeds 2000 V
CDM JESD22-C101E exceeds 1000 V
3. Ordering information
Table 1.
Ordering information
Type number
Package
Name
SO8
Description
Version
CBTD3306D
plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
SOT530-1
CBTD3306PW
TSSOP8
plastic thin shrink small outline package; 8 leads;
body width 4.4 mm
CBTD3306GT
CBTD3306GM
XSON8
plastic extremely thin small outline package; no leads; 8 terminals; SOT833-1
body 1 × 1.95 × 0.5 mm
XQFN8U
plastic extremely thin quad flat package; no leads; 8 terminals;
SOT902-1
body 1.6 × 1.6 × 0.5 mm
4. Marking
Table 2.
Marking codes
Type number
CBTD3306D
CBTD3306PW
CBTD3306GT
CBTD3306GM
Marking code
CBTD3306
D306
W06
W06
CBTD3306
NXP Semiconductors
Dual bus switch with level shifting
5. Functional diagram
2
1
5
7
3
6
1A
1OE
2A
1B
2B
2OE
002aab985
Fig 1. Logic diagram
6. Pinning information
6.1 Pinning
CBTD3306
CBTD3306
V
1
2
3
4
8
7
6
5
1OE
1A
CC
1
2
3
4
8
7
6
5
1OE
1A
V
CC
2OE
2B
2OE
2B
1B
1B
GND
2A
GND
2A
001aak832
001aak833
Fig 2. Pin configuration for SO8 (SOT96-1)
Fig 3. Pin configuration for TSSOP8 (SOT530-1)
CBTD3306
terminal 1
index area
CBTD3306
1OE
1A
1
2
3
4
8
7
6
5
V
1OE
1
CC
7
6
5
2OE
2B
2OE
2B
1A
1B
2
3
1B
2A
GND
2A
001aal405
001aal404
Transparent top view
Transparent top view
Fig 4. Pin configuration SOT833-1 (XSON8)
Fig 5. Pin configuration SOT902-1 (XQFN8U)
CBTD3306
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Product Specification
Rev. 5 — 28 April 2011
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CBTD3306
NXP Semiconductors
Dual bus switch with level shifting
6.2 Pin description
Table 3.
Symbol
1OE, 2OE
1A, 2A
1B, 2B
GND
Pin description
Pin
1, 7
2, 5
3, 6
4
Description
output enable input
data input/output (A port)
data input/output (B port)
ground (0 V)
VCC
8
positive supply voltage
7. Functional description
Table 4.
Input
nOE
L
Function selection[1]
Input/output
nA, nB
nA = nB
Z
H
[1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state.
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Tamb = −40 °C to +85 °C, unless otherwise specified.
Symbol
VCC
VI
Parameter
Conditions
Min
−0.5
−0.5
-
Max
+7.0
+7.0
128
-
Unit
V
supply voltage
input voltage
[2]
V
ISW
switch current
mA
mA
°C
IIK
input clamping current
storage temperature
VI/O = 0 V
−50
−65
Tstg
+150
[1] Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under Section 9. is not implied. Exposure to absolute-maximum-rated
conditions for extended periods may affect device reliability.
[2] The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
9. Recommended operating conditions
Table 6.
Operating conditions
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation.
Symbol
VCC
Parameter
Conditions
Min
4.5
2.0
-
Typ
Max
5.5
-
Unit
V
supply voltage
-
-
-
-
VIH
HIGH-level input voltage
LOW-level input voltage
ambient temperature
V
VIL
0.8
+85
V
Tamb
operating in free air
−40
°C
CBTD3306
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Product Specification
Rev. 5 — 28 April 2011
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NXP Semiconductors
Dual bus switch with level shifting
10. Static characteristics
Table 7.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions
Tamb = −40 °C to +85 °C
Unit
Min
Typ[1]
Max
−1.2
1
VIK
II
input clamping voltage
VCC = 4.5 V; II = −18 mA
-
-
-
-
-
-
V
input leakage current
supply current
VCC = 5.5 V; VI = GND or 5.5 V
μA
mA
ICC
VCC = 5.5 V; ISW = 0 mA;
VI = VCC or GND
1.5
Vpass
pass voltage
see Figure 6 to Figure 10
-
-
-
-
-
V
[2]
ΔICC
additional supply current per input pin; VCC = 5.5 V;
one input at 3.4 V, other inputs at
2.5
mA
VCC or GND
CI
input capacitance
control pin; VI = 3 V or 0 V
-
-
3.2
6.5
-
-
pF
pF
Cio(off)
off-state input/output
capacitance
port off; VI = 3 V or 0 V; nOE = VCC
[3]
[3]
[3]
RON
ON resistance
VCC = 4.5 V; VI = 0 V; II = 64 mA
VCC = 4.5 V; VI = 0 V; II = 30 mA
VCC = 4.5 V; VI = 2.4 V; II = 15 mA
-
-
-
3.6
3.6
17
5
5
Ω
Ω
Ω
35
[1] All typical values are at VCC = 5 V, Tamb = 25 °C.
[2] This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
[3] Measured by the voltage drop between the nA and the nB terminals at the indicated current through the switch. ON resistance is
determined by the lowest voltage of the two (nA or nB) terminals.
CBTD3306
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Product Specification
Rev. 5 — 28 April 2011
4 of 17
CBTD3306
NXP Semiconductors
Dual bus switch with level shifting
10.1 Typical pass voltage graphs
001aak834
001aak835
3.6
3.6
V
V
pass
pass
(V)
(V)
(1)
(2)
(1)
3.2
3.2
(2)
(3)
2.8
2.4
2.0
2.8
2.4
2.0
(3)
(4)
(4)
4.4
4.8
5.2
5.6
4.4
4.8
5.2
5.6
V
CC
(V)
V
CC
(V)
(1) ISW = 100 μA
(2) ISW = 6 mA
(3) ISW =12 mA
(4) ISW = 24 mA
(1) ISW = 100 μA
(2) ISW = 6 mA
(3) ISW =12 mA
(4) ISW = 24 mA
Fig 6. Pass voltage versus supply voltage;
Fig 7. Pass voltage versus supply voltage;
Tamb = 85 °C (typical)
Tamb = 70 °C (typical)
001aak836
001aak837
3.6
3.6
V
V
pass
pass
(V)
(V)
(1)
(1)
(2)
3.2
3.2
(2)
(3)
(3)
(4)
2.8
2.4
2.0
2.8
2.4
2.0
(4)
4.4
4.8
5.2
5.6
4.4
4.8
5.2
5.6
V
CC
(V)
V
CC
(V)
(1) ISW = 100 μA
(2) ISW = 6 mA
(3) ISW =12 mA
(4) ISW = 24 mA
(1) ISW = 100 μA
(2) ISW = 6 mA
(3) ISW =12 mA
(4) ISW = 24 mA
Fig 8. Pass voltage versus supply voltage;
Fig 9. Pass voltage versus supply voltage;
Tamb = 25 °C (typical)
Tamb = 0 °C (typical)
CBTD3306
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Product Specification
Rev. 5 — 28 April 2011
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CBTD3306
NXP Semiconductors
Dual bus switch with level shifting
001aak838
3.6
V
pass
(V)
3.2
(1)
(2)
2.8
2.4
2.0
(3)
(4)
4.4
4.8
5.2
5.6
V
(V)
CC
(1) ISW = 100 μA
(2) ISW = 6 mA
(3) ISW =12 mA
(4) ISW = 24 mA
Fig 10. Pass voltage versus supply voltage; Tamb = −40 °C (typical)
CBTD3306
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Product Specification
Rev. 5 — 28 April 2011
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NXP Semiconductors
Dual bus switch with level shifting
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13.
Symbol Parameter
Conditions
Tamb = −40 °C to +85 °C
Unit
ns
Min
Typ
Max
[1][2]
[2]
tpd
ten
tdis
propagation delay
nA, nB to nB, nA; see Figure 11
VCC = 5.0 V 0.5 V
-
-
0.25
enable time
disable time
nOE to nA or nB; see Figure 12
VCC = 5.0 V 0.5 V
1.0
1.0
-
-
5.4
4.9
ns
[2]
nOE to nA or nB; see Figure 12
VCC = 5.0 V 0.5 V
ns
[1] The propagation delay is the calculated RC time constant of the typical ON resistance of the switch and the specified load capacitance,
when driven by an ideal voltage source (zero output impedance).
[2]
t
pd is the same as tPLH and tPHL
.
ten is the same as tPZL and tPZH
.
tdis is the same as tPLZ and tPHZ
.
12. Waveforms
V
I
nA, nB
input
V
M
GND
t
t
PHL
PLH
V
OH
nB, nA
output
V
M
V
OL
001aak305
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 11. The data input (nA, nB) to output (nB, nA) propagation delay times
CBTD3306
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CBTD3306
NXP Semiconductors
Dual bus switch with level shifting
V
I
V
V
M
nOE input
output
M
GND
3.5 V
t
t
PZL
PLZ
V
M
LOW to OFF
OFF to LOW
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
output
HIGH to OFF
OFF to HIGH
V
M
GND
outputs
enabled
outputs
disabled
outputs
enabled
001aak298
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 12. Enable and disable times
Table 9. Measurement points
Supply voltage
VCC
Input
VI
Output
VM
VM
VX
VY
VCC = 5.0 V 0.5 V GND to 3.0 V
1.5 V
1.5 V
VOL + 0.3 V
VOH − 0.3 V
CBTD3306
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Product Specification
Rev. 5 — 28 April 2011
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CBTD3306
NXP Semiconductors
Dual bus switch with level shifting
13. Test information
t
W
V
I
90 %
negative
pulse
V
V
V
V
M
M
10 %
0 V
t
t
r
f
t
r
t
f
V
I
90 %
positive
pulse
M
M
10 %
0 V
t
W
V
EXT
R
V
CC
L
V
V
O
I
G
DUT
R
C
R
L
T
L
001aae331
Test data is given in Table 10.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Zo = 50 Ω.
The outputs are measured one at a time with one transition per measurement.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 13. Test circuit for measuring switching times
Table 10. Test data
Supply voltage
Input
VI
Load
CL
VEXT
tr, tf
RL
tPLH, tPHL
open
tPLZ, tPZL
tPHZ, tPZH
VCC = 5.0 V 0.5 V
GND to 3.0 V ≤ 2.5 ns
50 pF
500 Ω
7.0 V
open
CBTD3306
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Product Specification
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CBTD3306
NXP Semiconductors
Dual bus switch with level shifting
14. Package outline
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
4
e
w
M
detail X
b
p
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.20
0.014 0.0075 0.19
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches 0.069
0.01 0.004
Notes
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT96-1
076E03
MS-012
Fig 14. Package outline SOT96-1 (SO8)
CBTD3306
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Product Specification
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10 of 17
CBTD3306
NXP Semiconductors
Dual bus switch with level shifting
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 4.4 mm
SOT530-1
E
A
D
X
c
y
H
E
v
M
A
Z
8
5
A
2
(A )
A
3
A
1
pin 1 index
θ
L
p
L
detail X
1
4
e
w M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
A
A
A
b
c
D
E
e
H
L
L
UNIT
v
w
y
Z
θ
1
2
3
p
E
p
max.
0.15
0.05
0.95
0.85
0.30
0.19
0.20
0.13
3.1
2.9
4.5
4.3
6.5
6.3
0.7
0.5
0.70
0.35
8°
0°
mm
1.1
0.65
0.25
0.94
0.1
0.1
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-02-24
03-02-18
SOT530-1
MO-153
Fig 15. Package outline SOT530-1 (TSSOP8)
CBTD3306
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Product Specification
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CBTD3306
NXP Semiconductors
Dual bus switch with level shifting
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm
SOT833-1
b
1
2
3
4
4×
(2)
L
L
1
e
8
7
6
5
e
1
e
1
e
1
8×
A
(2)
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
A
1
UNIT
b
D
E
e
e
1
L
L
1
max max
0.25
0.17
2.0
1.9
1.05
0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.6
0.5
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
- - -
07-11-14
07-12-07
SOT833-1
- - -
MO-252
Fig 16. Package outline SOT833-1 (XSON8)
CBTD3306
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Product Specification
Rev. 5 — 28 April 2011
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CBTD3306
NXP Semiconductors
Dual bus switch with level shifting
XQFN8U: plastic extremely thin quad flat package; no leads;
8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm
SOT902-1
D
B
A
terminal 1
index area
E
A
A
1
detail X
e
L
1
e
C
y
y
C
1
L
M
M
∅ v
∅ w
C A
C
B
4
5
6
7
3
2
metal area
not for soldering
e
1
b
e
1
1
terminal 1
index area
8
X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
1
b
D
E
e
e
1
L
L
v
w
y
y
1
1
max
0.05 0.25 1.65 1.65
0.00 0.15 1.55 1.55
0.35 0.15
0.25 0.05
mm
0.5
0.55
0.5
0.1
0.05 0.05 0.05
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
MO-255
JEITA
05-11-25
07-11-14
SOT902-1
- - -
- - -
Fig 17. Package outline SOT902-1 (XQFN8U)
CBTD3306
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Product Specification
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CBTD3306
NXP Semiconductors
Dual bus switch with level shifting
15. Abbreviations
Table 11. Abbreviations
Acronym
CDM
ESD
Description
Charged Device Model
ElectroStatic Discharge
Field Effect Transistor
Human Body Model
FET
HBM
PRR
Pulse Rate Repetition
Transistor-Transistor Logic
TTL
16. Revision history
Table 12. Revision history
Document ID
CBTD3306 v.5
Modifications:
CBTD3306 v.4
CBTD3306 v.3
CBTD3306 v.2
CBTD3306 v.1
Release date
20110428
Data sheet status
Change notice
Supersedes
Product data sheet
-
CBTD3306 v.4
• Table 2: Marking code table corrected (errata).
20100325
20100223
20091015
20011108
Product data sheet
Product data sheet
Product data sheet
Product data
-
-
-
-
CBTD3306 v.3
CBTD3306 v.2
CBTD3306 v.1
-
CBTD3306
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Product Specification
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Dual bus switch with level shifting
17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
suitable for use in medical, military, aircraft, space or life support equipment,
17.2 Definitions
nor in applications where failure or malfunction of an NXP Semiconductors
product can reasonably be expected to result in personal injury, death or
severe property or environmental damage. NXP Semiconductors accepts no
liability for inclusion and/or use of NXP Semiconductors products in such
equipment or applications and therefore such inclusion and/or use is at the
customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
17.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. The product is not designed, authorized or warranted to be
CBTD3306
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product Specification
Rev. 5 — 28 April 2011
15 of 17
CBTD3306
NXP Semiconductors
Dual bus switch with level shifting
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
CBTD3306
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product Specification
Rev. 5 — 28 April 2011
16 of 17
CBTD3306
NXP Semiconductors
Dual bus switch with level shifting
19. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions. . . . . . . . 3
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Typical pass voltage graphs . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Test information. . . . . . . . . . . . . . . . . . . . . . . . . 9
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14
8
9
10
10.1
11
12
13
14
15
16
17
Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
17.1
17.2
17.3
17.4
18
19
Contact information. . . . . . . . . . . . . . . . . . . . . 16
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 28 April 2011
Document identifier: CBTD3306
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