BUK554-60H [NXP]
PowerMOS transistor Logic level FET; 功率MOS晶体管逻辑电平场效应管
| 型号： | BUK554-60H |
| 厂家： | 
NXP |
| 描述： | PowerMOS transistor Logic level FET |
| 文件： | 总7页 (文件大小：65K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level FET
BUK554-60H
GENERAL DESCRIPTION
QUICK REFERENCE DATA
N-channel enhancement mode logic
level field-effect power transistor in a
plastic envelope
The device is intended for use in
automotive and general purpose
switching applications.
SYMBOL
PARAMETER
MAX.
UNIT
VDS
ID
Ptot
Tj
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
60
39
125
175
42
V
A
W
˚C
mΩ
RDS(ON)
resistance;
VGS = 5 V
PINNING - TO220AB
PIN CONFIGURATION
SYMBOL
PIN
1
DESCRIPTION
d
tab
gate
2
drain
g
3
source
tab drain
s
1 2 3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDS
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Non-repetitive gate-source
voltage
-
-
-
-
-
60
60
15
20
V
V
V
V
VDGR
±VGS
±VGSM
RGS = 20 kΩ
-
tp ≤ 50 µs
ID
ID
IDM
Ptot
Tstg
Tj
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage temperature
Junction temperature
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
-
-
-
-
39
28
156
125
175
175
A
A
A
W
˚C
˚C
-
- 55
-
-
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
TYP. MAX. UNIT
Rth j-mb
Rth j-a
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
-
1.2
-
K/W
K/W
60
August 1996
1
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level FET
BUK554-60H
STATIC CHARACTERISTICS
Tmb = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
V(BR)DSS
Drain-source breakdown
voltage
VGS = 0 V; ID = 0.25 mA
60
-
-
V
VGS(TO)
IDSS
IDSS
IGSS
RDS(ON)
Gate threshold voltage
Zero gate voltage drain current VDS = 60 V; VGS = 0 V; Tj = 25 ˚C
Zero gate voltage drain current VDS = 60 V; VGS = 0 V; Tj =125 ˚C
Gate source leakage current
Drain-source on-state
resistance
VDS = VGS; ID = 1 mA
1.0
1.5
1
0.1
10
35
2.0
10
1.0
100
42
V
-
-
-
-
µA
mA
nA
mΩ
VGS = ±15 V; VDS = 0 V
VGS = 5 V; ID = 20 A
DYNAMIC CHARACTERISTICS
Tmb = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
gfs
Forward transconductance
VDS = 25 V; ID = 20 A
VGS = 0 V; VDS = 25 V; f = 1 MHz
10
18
-
S
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
-
-
-
1100 1750
420
160
pF
pF
pF
600
275
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 30 V; ID = 3 A;
VGS = 5 V; RGS = 50 Ω;
Rgen = 50 Ω
-
-
-
-
25
40
ns
ns
ns
ns
110
150
100
150
220
145
Ld
Ld
Ls
Internal drain inductance
Internal drain inductance
Internal source inductance
Measured from contact screw on
tab to centre of die
Measured from drain lead 6 mm
from package to centre of die
Measured from source lead 6 mm
from package to source bond pad
-
-
-
3.5
4.5
7.5
-
-
-
nH
nH
nH
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tmb = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
IDR
Continuous reverse drain
current
-
-
-
39
A
IDRM
VSD
Pulsed reverse drain current
Diode forward voltage
-
-
-
-
156
2.0
A
V
IF = 39 A ; VGS = 0 V
0.95
trr
Qrr
Reverse recovery time
Reverse recovery charge
IF = 39 A; -dIF/dt = 100 A/µs;
VGS = 0 V; VR = 30 V
-
-
60
0.30
-
-
ns
µC
AVALANCHE LIMITING VALUE
Tmb = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
WDSS
Drain-source non-repetitive
unclamped inductive turn-off
energy
ID = 39 A ; VDD ≤ 25 V ;
VGS = 5 V ; RGS = 50 Ω
-
-
90
mJ
August 1996
2
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level FET
BUK554-60H
Normalised Power Derating
Zth(j-mb) K/W
PD%
120
10
1
110
100
90
80
70
60
50
40
30
20
10
0
D =
0.5
0.2
0.1
0.05
0.1
0.02
0
t
p
t
p
P
0.01
D
D =
T
t
T
0.001
1E-07
1E-05
1E-03
tp / sec
1E-01
1E+01
0
20
40
60
80
Tmb /
100 120 140 160 180
C
Fig.1. Normalised power dissipation.
PD% = 100 PD/PD 25 ˚C = f(Tmb)
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
Normalised Current Derating
ID%
ID / A
120
110
100
90
80
70
60
50
40
30
20
10
0
100
10
8
6
80
60
40
20
0
VGS / V =
5
4.5
4
3.5
3
2.5
0
1
2
3
4
5
0
20
40
60
80
100 120 140 160 180
Tmb /
C
VDS / V
Fig.2. Normalised continuous drain current.
ID% = 100 ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
ID / A
RDS(ON) / Ohm
4 4.5
1000
100
10
0.1
0.08
0.06
0.04
0.02
0
2.5
3
3.5
VGS / V =
5
tp =
10 us
6
RDS(ON) = VDS/ID
100 us
1 ms
8
10
DC
10 ms
100 ms
1
0
20
40
60
80
100
1
10
100
VDS / V
ID / A
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
August 1996
3
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level FET
BUK554-60H
VGS(TO) / V
ID / A
80
60
40
20
0
max.
2
1
0
Tj / C =
-40
150
typ.
min.
25
0
2
4
6
8
10
-60
-20
20
60
Tj /
100
140
180
VGS / V
C
Fig.7. Typical transfer characteristics.
ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj
Fig.10. Gate threshold voltage.
GS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
V
SUB-THRESHOLD CONDUCTION
ID / A
gfs / S
1E-01
1E-02
1E-03
1E-04
1E-05
1E-06
-40
25
20
10
0
2 %
typ
98 %
Tj / C = 150
0
1
2
3
4
0
20
40
ID / A
60
80
VGS / V
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID); conditions: VDS = 25 V
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
a
C / pF
Normalised RDS(ON) = f(Tj)
2.0
1.5
1.0
0.5
0
10000
1000
100
Ciss
Coss
Crss
0
20
40
-60
-20
20
60
Tj /
100
140
180
VDS / V
C
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 20 A; VGS = 5 V
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
August 1996
4
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level FET
BUK554-60H
WDSS%
VGS / V
120
110
100
90
80
70
60
50
40
30
20
10
0
12
10
8
VDS / = 12
48
6
4
2
0
20
40
60
80
100
Tmb /
120
C
140
160
180
0
10
20
QG / nC
30
40
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); conditions: ID = 39 A; parameter VDS
Fig.15. Normalised avalanche energy rating.
WDSS% = f(Tmb); conditions: ID = 39 A
IF / A
100
80
60
40
20
0
VDD
+
L
VDS
-
VGS
-ID/100
Tj / C = 150
-40
25
T.U.T.
0
R 01
RGS
shunt
0
1
2
VSDS / V
Fig.16. Avalanche energy test circuit.
WDSS = 0.5 LID2 BVDSS/(BVDSS − VDD
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
)
August 1996
5
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level FET
BUK554-60H
MECHANICAL DATA
Dimensions in mm
Net Mass: 2 g
4,5
max
10,3
max
1,3
3,7
2,8
5,9
min
15,8
max
3,0 max
not tinned
3,0
13,5
min
1,3
1 2 3
max
(2x)
0,9 max (3x)
0,6
2,4
2,54 2,54
Fig.17. TO220AB; pin 2 connected to mounting base.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to mounting instructions for TO220 envelopes.
3. Epoxy meets UL94 V0 at 1/8".
August 1996
6
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level FET
BUK554-60H
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1996
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
August 1996
7
Rev 1.000
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