BUK104-50S [NXP]
PowerMOS transistor Logic level TOPFET; 功率MOS晶体管逻辑电平TOPFET
| 型号： | BUK104-50S |
| 厂家： | 
NXP |
| 描述： | PowerMOS transistor Logic level TOPFET |
| 文件： | 总14页 (文件大小：151K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK104-50L/S
BUK104-50LP/SP
DESCRIPTION
QUICK REFERENCE DATA
Monolithic temperature and
SYMBOL
PARAMETER
MAX.
UNIT
overload protected logic level power
MOSFET in a 5 pin plastic
VDS
ID
Continuous drain source voltage
Continuous drain current
50
15
V
A
W
˚C
envelope, intended as a general
purpose switch for automotive
systems and other applications.
Ptot
Tj
Total power dissipation
40
Continuous junction temperature
Drain-source on-state resistance
150
RDS(ON)
APPLICATIONS
VIS = 5 V
VIS = 7 V
125
100
mΩ
mΩ
General controller for driving
lamps
SYMBOL
PARAMETER
NOM.
UNIT
motors
solenoids
heaters
VPSN
Protection supply voltage
BUK104-50L
BUK104-50S
5
10
V
V
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Vertical power DMOS output
stage
Low on-state resistance
Logic and protection supply
from separate pin
Low operating supply current
Overload protection against
over temperature
Overload protection against
short circuit load
PROTECTION SUPPLY
DRAIN
FLAG
O/V
CLAMP
POWER
INPUT
MOSFET
Latched overload protection
reset by protection supply
Protection circuit condition
indicated by flag pin
5 V logic compatible input level
Separate input pin
LOGIC AND
PROTECTION
for higher frequency drive
ESD protection on input, flag
and protection supply pins
Over voltage clamping for turn
off of inductive loads
Both linear and switching
operation are possible
SOURCE
Fig.1. Elements of the TOPFET.
PINNING - SOT263
PIN CONFIGURATION
SYMBOL
PIN
1
DESCRIPTION
tab
D
S
input
flag
TOPFET
2
P
F
I
P
3
drain
leadform
263-01
4
protection supply
source
1 2 3 4 5
5
Fig. 2. Type numbers ending with
suffix P refer to leadform 263-01.
Fig. 3.
tab drain
January 1993
1
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK104-50L/S
BUK104-50LP/SP
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum Rating System (IEC 134)
SYMBOL PARAMETER
Voltages
CONDITIONS
MIN.
MAX.
UNIT
VDSS
Continuous off-state drain source
VIS = 0 V
-
50
V
voltage1
VIS
Continuous input voltage
Continuous flag voltage
Continuous supply voltage
-
-
-
0
0
0
11
11
11
V
V
V
VFS
VPS
Currents
VIS =
-
7
5
V
ID
Continuous drain current
Tmb ≤25 ˚C
Tmb ≤100 ˚C
Tmb ≤ 25 ˚C
-
-
-
15 13
9.5 8.5
60 54
A
A
A
ID
Continuous drain current
IDRM
Repetitive peak on-state drain current
Thermal
Ptot
Tstg
Tj
Total power dissipation
Storage temperature
Junction temperature2
Tmb = 25 ˚C
-
continuous
-
-55
-
40
150
150
W
˚C
˚C
Tsold
Lead temperature
during soldering
-
250
˚C
OVERLOAD PROTECTION LIMITING VALUES
With the protection supply
connected, TOPFET can protect
itself from two types of overload -
over temperature and short circuit
load.
An n-MOS transistor turns on
For internal overload protection to
remain latched while the control
circuit is high, external series input
resistance must be provided. Refer
to INPUT CHARACTERISTICS.
between the input and source to
quickly discharge the power
MOSFET gate capacitance.
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VIS =
7
5
-
V
VPSP
Protection supply voltage3
for valid protection
BUK104-50L 4.4
BUK104-50S 5.4
4
5
-
-
V
V
Over temperature protection
VPS = VPSN
VDDP(T)
Protected drain source supply voltage VIS = 10 V; RI ≥ 2 kΩ
VIS = 5 V; RI ≥ 1 kΩ
-
-
50
50
V
V
Short circuit load protection
VPS = VPSN; L ≤ 10 µH
VDDP(P)
PDSM
Protected drain source supply voltage4 VIS = 10 V; RI ≥ 2 kΩ
VIS = 5 V; RI ≥ 1 kΩ
-
-
-
25
45
0.8
V
V
kW
Instantaneous overload dissipation
ESD LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VC
Electrostatic discharge capacitor
voltage
Human body model;
C = 250 pF; R = 1.5 kΩ
-
2
kV
1 Prior to the onset of overvoltage clamping. For voltages above this value, safe operation is limited by the overvoltage clamping energy.
2 A higher Tj is allowed as an overload condition but at the threshold Tj(TO) the over temperature trip operates to protect the switch.
3 The minimum supply voltage required for correct operation of the overload protection circuits.
4 The device is able to self-protect against a short circuit load providing the drain-source supply voltage does not exceed VDDP(P) maximum.
For further information, refer to OVERLOAD PROTECTION CHARACTERISTICS.
January 1993
2
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK104-50L/S
BUK104-50LP/SP
OVERVOLTAGE CLAMPING LIMITING VALUES
At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients.
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
IDRRM
EDSM
Repetitive peak clamping drain current RIS ≥ 100 Ω1
-
-
15
A
Non-repetitive inductive turn-off
IDM = 15 A; RIS ≥ 100 Ω
200
mJ
energy2
EDRM
Repetitive inductive turn-off energy
RIS ≥ 100 Ω; Tmb ≤ 95 ˚C;
IDM = 4 A; VDD ≤ 20 V;
f = 250 Hz
-
20
50
mJ
IDIRM
Repetitive peak drain to input current3 RIS = 0 Ω; tp ≤ 1 ms
-
mA
REVERSE DIODE LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
IS
Continuous forward current
Tmb = 25 ˚C;
VIS = VPS = VFS = 0 V
-
15
A
THERMAL CHARACTERISTICS
SYMBOL PARAMETER
Thermal resistance
CONDITIONS
MIN. TYP. MAX. UNIT
Rth j-mb
Rth j-a
Junction to mounting base
Junction to ambient
-
-
-
2.5
60
3.1
-
K/W
K/W
in free air
STATIC CHARACTERISTICS
Tmb = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
V(CL)DSR
V(CL)DSR
Drain-source clamping voltage RIS = 100 Ω; ID = 10 mA
50
50
-
-
65
70
V
V
Drain-source clamping voltage RIS = 100 Ω; IDM = 1 A; tp ≤ 300 µs;
δ ≤ 0.01
Zero input voltage drain current VDS = 12 V; VIS = 0 V
IDSS
IDSR
IDSR
-
-
0.5
1
10
20
µA
µA
Drain source leakage current
Drain source leakage current
VDS = 50 V; RIS = 100 Ω;
VDS = 40 V; RIS = 100 Ω;
Tj = 125 ˚C
-
10
100
µA
RDS(ON)
Drain-source on-state
resistance
IDM = 7.5 A;
tp ≤ 300 µs; δ ≤ 0.01
VIS = 7 V
VIS = 5 V
-
-
75
95
100
125
mΩ
mΩ
1 The input pin must be connected to the source pin by a specified external resistance to allow the power MOSFET gate source voltage to
become sufficiently positive for active clamping. Refer to INPUT CHARACTERISTICS.
2 While the protection supply voltage is connected, during overvoltage clamping it is possible that the overload protection may operate at
energies close to the limiting value. Refer to OVERLOAD PROTECTION CHARACTERISTICS.
3 Shorting the input to source with low resistance inhibits the internal overvoltage protection by preventing the power MOSFET gate source
voltage becoming positive.
January 1993
3
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK104-50L/S
BUK104-50LP/SP
OVERLOAD PROTECTION CHARACTERISTICS
With adequate protection supply
voltage TOPFET detects when one
of the overload thresholds is
exceeded.
Provided there is adequate input
Refer also to OVERLOAD
PROTECTION LIMITING VALUES
and INPUT CHARACTERISTICS.
series resistance it switches off
and remains latched off until reset
by the protection supply pin.
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Short circuit load protection1 VPS = VPSN2; Tmb = 25 ˚C; L ≤ 10 µH;
RI ≥ 2 kΩ
VDD = 13 V; VIS = 10 V
VDD = 13 V; VIS = 10 V
EDS(TO)
td sc
Overload threshold energy
Response time
-
-
150
375
-
-
mJ
µs
Over temperature protection VPS = VPSN; RI ≥ 2 kΩ
Threshold junction temperature from ID ≥ 0.65 A3
Tj(TO)
150
-
-
˚C
TRANSFER CHARACTERISTICS
Tmb = 25 ˚C
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
gfs
Forward transconductance
VDS = 10 V; IDM = 7.5 A tp ≤ 300 µs;
δ ≤ 0.01
5
9
-
S
ID
Drain current4
VDS = 13 V;
VIS = 5 V
VIS = 10 V
-
25
40
-
-
A
A
PROTECTION SUPPLY CHARACTERISTICS
Tmb = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
Protection supply
CONDITIONS
MIN. TYP. MAX. UNIT
IPS,
Protection supply current
normal operation or
protection latched
BUK104-50L
IPSL
VPS = 5 V
VPS = 10 V
-
-
0.2
0.4
2.5
-
0.35
1.0
3.5
-
mA
mA
V
BUK104-50S
VPSR
Protection reset voltage5
Protection clamp voltage
1.5
1.0
Tj = 150 ˚C
V
V(CL)PS
IP = 1.35 mA
11
13
-
V
REVERSE DIODE CHARACTERISTICS
Tmb = 25 ˚C
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
VSDS
Forward voltage
IS = 15 A; VIS = VPS = VFS = 0 V;
tp = 300 µs
-
1.0
1.5
V
trr
Reverse recovery time
not applicable6
-
-
-
-
1 The short circuit load protection is able to save the device providing the instantaneous on-state dissipation is less than the limiting value for
PDSM, which is always the case when VDS is less than VDSP maximum.
2 At the appropriate nominal protection supply voltage for each type. Refer to QUICK REFERENCE DATA.
3 The over temperature protection feature requires a minimum on-state drain source voltage for correct operation. The specified minimum ID
ensures this condition.
4 During overload condition. Refer also to OVERLOAD PROTECTION LIMITING VALUES and CHARACTERISTICS.
5 The supply voltage below which the overload protection circuits will be reset.
6 The reverse diode of this type is not intended for applications requiring fast reverse recovery.
January 1993
4
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK104-50L/S
BUK104-50LP/SP
INPUT CHARACTERISTICS
Tmb = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
Normal operation
CONDITIONS
MIN. TYP. MAX. UNIT
VIS(TO)
Input threshold voltage
VDS = 5 V; ID = 1 mA
1.0
0.5
-
1.5
-
10
13
2.0
V
V
nA
V
Tmb = 150 ˚C
-
100
-
IIS
V(CL)IS
Input current
Input clamp voltage
VIS = 10 V
II = 1 mA
11
Overload protection latched
RISL
Input resistance1
VPS = 5 V
II = 5 mA;
-
-
-
-
55
95
35
60
-
-
-
-
Ω
Ω
Ω
Ω
Tmb = 150 ˚C
II = 5 mA;
VPS = 10 V
Tmb = 150 ˚C
Application information
External input resistances for
(see figure 29)
RIS
RI
internal overvoltage clamping2 RI = ∞ Ω;
VDS > 30 V
100
-
-
Ω
internal overload protection3
RIS = ∞ Ω;
VII = 5 V
VII = 10 V
1
2
-
-
-
-
kΩ
kΩ
SWITCHING CHARACTERISTICS
Tmb = 25 ˚C; RI = 50 Ω; RIS = 50 Ω (see figure 29); resistive load RL = 10 Ω. For waveforms see figure 28.
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
td on
tr
td off
tf
Turn-on delay time
Rise time
VDD = 15 V; VIS: 0 V
10 V
0 V
-
-
-
-
8
-
-
-
-
ns
ns
ns
ns
13
Turn-off delay time
Fall time
VDD = 15 V; VIS: 10 V
100
45
CAPACITANCES
Tmb = 25 ˚C; f = 1 MHz
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Ciss
Coss
Crss
Cpso
Input capacitance
VDS = 25 V; VIS = 0 V
VDS = 25 V; VIS = 0 V
VDS = 25 V; VIS = 0 V
VPS = 10 V
-
-
-
-
415
275
55
600
400
80
-
pF
pF
pF
pF
Output capacitance
Reverse transfer capacitance
Protection supply pin
capacitance
30
Cfso
Flag pin capacitance
VFS = 10 V; VPS = 0 V
-
20
-
pF
1 The resistance of the internal transistor which discharges the power MOSFET gate capacitance when overload protection operates.
The external drive circuit should be such that the input voltage does not exceed VIS(TO) minimum when the overload protection has
operated. Refer also to figure for latched input characteristics.
2 Applications using a lower value for RIS would require external overvoltage protection.
3 For applications requiring a lower value for RI, an external overload protection strategy is possible using the flag pin to ‘tell’ the control circuit to
switch off the input.
January 1993
5
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK104-50L/S
BUK104-50LP/SP
FLAG DESCRIPTION
TRUTH TABLE
CONDITION
NORMAL
The flag pin provides a means to
detect the presence of the
DESCRIPTION
FLAG
protection supply and indicate the
state of the overload detectors.
The flag is the open drain of an
n-MOS transistor and requires an
external pull-up resistor1. It is
suitable for both 5 V and 10 V logic.
Flag may be used to implement an
external protection strategy2 for
applications which require low input
drive impedance.
Normal operation and adequate
protection supply voltage
LOGIC LOW
LOGIC HIGH
LOGIC HIGH
LOGIC HIGH
OVER TEMP.
SHORT CIRCUIT
SUPPLY FAULT
Over temperature detected
Overload condition detected
Inadequate protection supply
voltage
FLAG CHARACTERISTICS
Tmb = 25 ˚C unless otherwise stated
SYMBOL PARAMETER
Flag ‘low’
CONDITIONS
MIN. TYP. MAX. UNIT
normal operation
IF = 1.6 mA
VFS = 10 V
VFS
IFSS
Flag voltage
-
-
0.15
15
0.4
-
V
mA
Flag saturation current
Flag ‘high’
overload or fault
VFS = 10 V
VFF = 5 V; RF = 3 kΩ;
IFS
VPSF
Flag leakage current
Protection supply threshold
voltage
-
-
10
µA
BUK104-50L
BUK104-50S
2.5
3.3
3.3
4.2
4
5
V
V
V(CL)FS
Flag clamping voltage
IF = 1 mA; VPS = 0 V
11
13
-
V
Application information
RF
Suitable external pull-up
resistance
VFF =5 V
VFF =10 V
1
2
10
20
50
100
kΩ
kΩ
ENVELOPE CHARACTERISTICS
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Ld
Ld
Ls
Internal drain inductance
Internal drain inductance
Internal source inductance
Measured from contact screw on
tab to centre of die
Measured from drain lead 6 mm
from package to centre of die
Measured from source lead 6 mm
from package to source bond pad
-
-
-
3.5
4.5
7.5
-
-
-
nH
nH
nH
1 Even if the flag pin is not used, it is recommended that it is connected to the protection supply via a pull-up resistor. It should not be left
floating.
2 Low pass filtering of the flag signal may be advisable to prevent false tripping.
January 1993
6
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK104-50L/S
BUK104-50LP/SP
Normalised Power Derating
Zth / (K/W)
BUK104-50L/S
PD%
120
10
1
110
100
90
80
70
60
50
40
30
20
10
0
D =
0.5
0.2
0.1
0.05
0.1
0.02
t
T
p
p
t
P
D =
D
0
t
T
0.01
0
20
40
60
80
Tmb /
100
120
140
1E-07
1E-05
1E-03
t / s
1E-01
1E+01
C
Fig.4. Normalised limiting power dissipation.
PD% = 100 PD/PD(25 ˚C) = f(Tmb)
Fig.7. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
Normalised Current Derating
ID%
ID / A
BUK104-50L/S
VIS / V =
120
110
100
90
80
70
60
50
40
30
20
10
0
50
40
30
20
10
0
10
9
8
7
6
5
4
3
2
0
20
40
60
80
Tmb /
100
120
140
0
4
8
12
16
VDS / V
20
24
28
32
C
Fig.5. Normalised continuous drain current.
ID% = 100 ID/ID(25 ˚C) = f(Tmb); conditions: VIS = 5 V
Fig.8. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VIS; tp = 250 µs & tp < td sc
BUK104-50L/S
ID & IDM / A
ID / A
BUK104-50L/S
100
10
1
20
15
10
5
VIS / V =
10
7
tp =
10 us
6
5
4
RDS(ON) = VDS/ID
100 us
1 ms
DC
10 ms
100 ms
3
Overload protection characteristics not shown
10
0.1
0
1
100
0
1
2
VDS / V
VDS / V
Fig.6. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.9. Typical on-state characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VIS; tp = 250 µs
January 1993
7
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK104-50L/S
BUK104-50LP/SP
RDS(ON) / mOhm
150
BUK104-50L/S
a
Normalised RDS(ON) = f(Tj)
VIS / V =
4
1.5
1.0
0.5
0
5
6
7
100
10
50
0
-60 -40 -20
0
20 40 60 80 100 120 140
0
2
4
6
8
10
ID / A
12
14
16
18
20
Tj /
C
Fig.10. Typical on-state resistance, Tj = 25 ˚C.
Fig.13. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 7.5 A; VIS ≥ 5 V
RDS(ON) = f(ID); parameter VIS; tp = 250 µs
BUK104-50L/S
ID / A
Tj(TO) / C
BUK104-50L/S
230
220
210
200
190
180
170
160
150
50
40
30
20
10
0
BUK104-50S
BUK104-50L
4
0
2
4
6
8
10
12
0
2
6
8
10
VIS / V
VPS / V
Fig.11. Typical transfer characteristics, Tj = 25 ˚C.
Fig.14. Typical over temperature protection threshold
Tj(TO) = f(VPS); conditions: VDS > 0.1 V
ID = f(VIS) ; conditions: VDS = 10 V; tp = 250 µs
PDSM%
120
gfs / S
BUK104-50L/S
10
9
8
7
6
5
4
3
2
1
0
100
80
60
40
20
0
-60
-40
-20
0
20
40
60
80
100 120 140
0
20
40
10
30
50
Tmb / C
ID / A
Fig.12. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID); conditions: VDS = 10 V; tp = 250 µs
Fig.15. Normalised limiting overload dissipation.
PDSM% =100 PDSM/PDSM(25 ˚C) = f(Tmb)
January 1993
8
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK104-50L/S
BUK104-50LP/SP
Energy & Time
VDDP(P) / V
50
BUK104-50L/S
BUK104-50L/S
0.5
0.4
0.3
0.2
0.1
0
40
30
20
10
0
max
Time / ms
Energy / J
60
Tj(TO)
140
0
2
4
6
8
10
-60
-20
20
100
180
220
VIS / V
Tmb / C
Fig.16. Maximum drain source supply voltage for
SC load protection. VDDP(P) = f(VIS); Tmb ≤ 150 ˚C
Fig.19. Typical overload protection characteristics.
Conditions: VDD = 13 V; VPS = VPSN, VIS = 7 V; SC load
VPSP / V
ESC(TO) / J
BUK104-50L/S
BUK104-50L/S
0.4
0.3
0.2
0.1
0
10
8
BUK104-50L
VIS / V =
5
min
10
BUK104-50S
6
5
4
10
BUK104-50L
2
BUK104-50S
0
0
2
4
6
8
10
0
2
4
6
8
10
VIS / V
VPS / V
Fig.17. Minimum protection supply voltage
for SC load protection. VPSP = f(VIS); Tmb ≥ 25 ˚C
Fig.20. Typical overload protection energy, Tj = 25 ˚C
ESC(TO) = f(VPS); conditions: VDS = 13 V, parameter VIS
TIME / ms
ID / A
BUK104-50L/S
BUK104-50L/S
10
20
15
10
5
typ.
1
PDSM
0.1
0
0.1
1
10
50
60
70
POWER / kW
VDS / V
Fig.18. Typical overload protection characteristics.
Fig.21. Typical clamping characteristics, 25 ˚C.
ID = f(VDS); conditions: RIS = 100 Ω; tp ≤ 50 µs
td sc = f(PDS); conditions: VPS ≥ VPSP; VIS ≥ 5 V
January 1993
9
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK104-50L/S
BUK104-50LP/SP
VIS(TO) / V
IS / A
BUK104-50L/S
20
15
10
5
max.
2
typ.
min.
1
0
0
-60 -40 -20
0
20
40
Tj /
60
C
80 100 120 140
0
1
0.5
1.5
VSD / V
Fig.22. Input threshold voltage.
VIS(TO) = f(Tj); conditions: ID = 1 mA; VDS = 5 V
Fig.25. Typical reverse diode current, Tj = 25 ˚C.
IS = f(VSDS); conditions: VIS = 0 V; tp = 250 µs
IPS / mA
BUK104-50L/S
EDSM%
120
1.0
0.5
0
110
100
90
80
70
60
50
40
30
20
10
0
0
2
4
6
8
10
12
14
0
20
40
60
80
Tmb / C
100
120
140
VPS / V
Fig.23. Typical DC protection supply characteristics.
IPS = f(VPS); normal or overload operation; Tj = 25 ˚C
Fig.26. Normalised limiting clamping energy.
E
DSM% = f(Tmb); conditions: ID = 15 A
IISL / mA
BUK104-50L/S
10
V(CL)DSR
150
100
50
VDS
VPS / V = 11
VDD
VDD
+
0
9
L
ID
8
7
VDS
VPS
+
0
-
D
VIS
RF
6
TOPFET
-ID/100
P
F
I
5
4
P
D.U.T.
0
RI = RIS
R 01
shunt
S
0
0
2
4
6
8
10
VIS / V
Fig.27. Clamping energy test circuit, RIS = 100 Ω.
EDSM = 0.5 LID2 V(CL)DSR/(V(CL)DSR − VDD
Fig.24. Typical latched input characteristics, 25 ˚C.
IISL = f(VIS); after overload protection latched
)
January 1993
10
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK104-50L/S
BUK104-50LP/SP
VIS / V & VDS / V
15
BUK104-50L/S
Idsr
1 mA
100 uA
10 uA
1 uA
VDS
VIS
10
typ.
5
0
100 nA
0
0.5
time / us
1
0
20
40
60
80
Tj / C
100
120
140
Fig.28. Typical resistive load switching waveforms
RI = RIS = 50 Ω; RL = 10 Ω; VDD = 15 V; Tj = 25 ˚C
Fig.31. Typical off-state leakage current.
IDSR = f(Tj); Conditions: VDS = 40 V; RIS = 100 Ω.
Ips normalised to 25 C
VII
1.5
D
RI
TOPFET
P
P
VIS
F
I
1
S
RIS
0.5
-60
-20
20
60
Tj / C
100
140
180
Fig.29. External input resistances RI and RIS,
generator voltage VII and input voltage VIS.
Fig.32. Normalised protection supply current.
IPS/IPS25 ˚C = f(Tj); VPS = VPSN
Capacitance / pF
BUK104-50L/S
10000
1000
100
Ciss
Coss
Crss
10
0
20
40
10
30
50
VDS / V
Fig.30. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VIS = 0 V; f = 1 MHz
January 1993
11
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK104-50L/S
BUK104-50LP/SP
MECHANICAL DATA
Dimensions in mm
Net Mass: 2 g
4.5
max
10.3
max
1.3
3.6
2.8
5.9
min
mounting
base
15.8
max
2.4
max
(2)
3.5 max
not tinned
0.5(1)
13.5
min
0.6
min
(4 x)
4 5
1 2
3
1.7
0.6
2.4
(4 x)
(1)
0.9 max
M
0.4
(5 x)
positional accuracy of the terminals
is controlled in this zone only.
NOTES (1)
(2)
terminal dimensions in this zone
are uncontrolled.
Fig.33. SOT263 ( 5-pin TO220 );
pin 3 connected to mounting base.
Note
1. Refer to mounting instructions for TO220 envelopes.
2. Epoxy meets UL94 V0 at 1/8".
January 1993
12
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK104-50L/S
BUK104-50LP/SP
MECHANICAL DATA
Dimensions in mm
Net Mass: 2 g
4.5
max
10.3
max
1.3
3.6
2.8
5.9
min
mounting
base
15.8
max
2.4
max
(2)
3.5 max
not tinned
5.6
0.5(1)
9.75
5
0.6
min
1 2 3 4 5
(4 x)
0.6
1.7
2.4
4.5
(4 x)
(1)
M
0.9 max
0.4
8.2
(5 x)
positional accuracy of the terminals
is controlled in this zone only.
NOTES (1)
(2)
terminal dimensions in this zone
are uncontrolled.
Fig.34. SOT263 leadform 263-01;
pin 3 connected to mounting base.
Note
1. Refer to mounting instructions for TO220 envelopes.
2. Epoxy meets UL94 V0 at 1/8".
January 1993
13
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK104-50L/S
BUK104-50LP/SP
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1996
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
January 1993
14
Rev 1.200
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