BF909,215_技术文档

BF909; BF909R

N-channel dual gate MOS-FETs

Rev. 02 — 19 November 2007

Product data sheet

IMPORTANT NOTICE

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- NXP Semiconductors, which will be used in future data sheets together with new contact

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In data sheets where the previous Philips references remain, please use the new links as

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NXP Semiconductors

Product speciﬁcation

N-channel dual gate MOS-FETs

BF909; BF909R

transistor consists of an amplifier MOS-FET with source

and substrate interconnected and an internal bias circuit to

ensure good cross-modulation performance during AGC.

FEATURES

• Specially designed for use at 5 V supply voltage

• High forward transfer admittance

• Short channel transistor with high forward transfer

admittance to input capacitance ratio

CAUTION

The device is supplied in an antistatic package. The

gate-source input must be protected against static

discharge during transport or handling.

• Low noise gain controlled amplifier up to 1 GHz

• Superior cross-modulation performance during AGC.

APPLICATIONS

PINNING

• VHF and UHF applications with 3 to 7 V supply voltage

such as television tuners and professional

communications equipment.

1

SYMBOL

DESCRIPTION

s, b

d

source

drain

2

3

g₂

g₁

gate 2

gate 1

DESCRIPTION

4

Enhancement type field-effect transistor in a plastic

microminiature SOT143 or SOT143R package. The

d

handbook, halfpage

3

4

3

2

g

2

g

2

g

1

2

1

s,b

Top view

MAM125 - 1

Top view

MAM124

BF909 marking code: %M3.

BF909R marking code: %M4.

Fig.1 Simplified outline (SOT143) and symbol.

Fig.2 Simplified outline (SOT143R) and symbol.

QUICK REFERENCE DATA

SYMBOL

V_DS

PARAMETER

drain-source voltage

CONDITIONS

MIN.

TYP.

MAX.

UNIT

−

7

V

I_D

drain current

40

mA

mW

°C

P_tot

T_j

total power dissipation

operating junction temperature

forward transfer admittance

input capacitance at gate 1

reverse transfer capacitance

noise ﬁgure

200

150

50

y_fs

36

−

43

3.6

35

2

mS

pF

C_ig1-s

C_rs

F

4.3

50

f = 1 MHz

f = 800 MHz

−

fF

−

2.8

dB

Rev. 02 - 19 November 2007

2 of 12

NXP Semiconductors

Product speciﬁcation

N-channel dual gate MOS-FETs

BF909; BF909R

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V_DS

I_D

drain-source voltage

drain current

−

7

V

40

mA

I_G1

I_G2

P_tot

gate 1 current

±10

gate 2 current

total power dissipation

BF909

see Fig.3

up to T_amb= 50 °C; note 1

up to T_amb= 40 °C; note 1

−

200

+150

150

mW

°C

BF909R

T_stg

T_j

storage temperature

operating junction temperature

−65

−

°C

Note

1. Device mounted on a printed-circuit board.

MLB935

250

handbook, halfpage

P

tot

(mW)

200

150

100

BF909R

BF909

50

0

50

100

150

200

o

T

( C)

amb

Fig.3 Power derating curves.

Rev. 02 - 19 November 2007

3 of 12

NXP Semiconductors

Product speciﬁcation

N-channel dual gate MOS-FETs

BF909; BF909R

THERMAL CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

VALUE

UNIT

R_{th j-a}

thermal resistance from junction to ambient

note 1

BF909

500

550

K/W

BF909R

R_{th j-s}

thermal resistance from junction to soldering point

note 2

BF909

T_s= 92 °C

T_s= 78 °C

290

360

K/W

BF909R

Notes

1. Device mounted on a printed-circuit board.

2. T_sis the temperature at the soldering point of the source lead.

STATIC CHARACTERISTICS

T_j= 25 °C; unless otherwise speciﬁed.

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

15

UNIT

V_(BR)G1-SS

V_(BR)G2-SS

V_(F)S-G1

gate 1-source breakdown voltage

gate 2-source breakdown voltage

forward source-gate 1 voltage

forward source-gate 2 voltage

gate 1-source threshold voltage

V_G2-S= V_DS= 0; I_G1-S= 10 mA

V_G1-S= V_DS= 0; I_G2-S= 10 mA

V_G2-S= V_DS= 0; I_S-G1= 10 mA

V_G1-S= V_DS= 0; I_S-G2= 10 mA

6

V

15

1.5

1

0.5

0.3

V_(F)S-G2

V_G1-S(th)

V_G2-S= 4 V; V_DS= 5 V;

I_D= 20 µA

V_G2-S(th)

I_DSX

gate 2-source threshold voltage

drain-source current

V_G1-S= V_DS= 5 V; I_D= 20 µA

0.3

12

1.2

20

V

V_G2-S= 4 V; V_DS= 5 V;

mA

R_G1= 120 kΩ; note 1

I_G1-SS

I_G2-SS

gate 1 cut-off current

gate 2 cut-off current

V_G1-S= 5 V; V_G2-S= V_DS= 0

V_G2-S= 5 V; V_G1-S= V_DS= 0

−

50

nA

Note

1. R_G1connects gate 1 to V_GG= 5 V; see Fig.18.

DYNAMIC CHARACTERISTICS

Common source; T_amb= 25 °C; V_DS= 5 V; V_G2-S= 4 V; I_D= 15 mA; unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

36

TYP.

43

MAX.

50

UNIT

mS

y_fs

C_ig1-s

C_ig2-s

C_os

C_rs

forward transfer admittance pulsed; T_j= 25 °C

input capacitance at gate 1

input capacitance at gate 2

drain-source capacitance

f = 1 MHz

−

3.6

2.3

35

2

4.3

3

pF

fF

3

reverse transfer capacitance f = 1 MHz

noise ﬁgure f = 800 MHz; G_S= G_Sopt; B_S= B_Sopt

50

2.8

F

dB

Rev. 02 - 19 November 2007

4 of 12

NXP Semiconductors

Product speciﬁcation

N-channel dual gate MOS-FETs

BF909; BF909R

MLB937

MLB936

30

110

handbook, halfpage

V

= 4 V

3 V 2.5 V

2 V

G2

S

I

V

D

unw

(mA)

(dBµV)

20

100

1.5 V

1 V

90

80

10

0

10

20

30

40

50

0.4

0.8

1.2

1.6

V

2.0

(V)

gain reduction (dB)

G1

S

V_DS= 5 V; V_GG= 5 V; f_w= 50 MHz.

_unw= 60 MHz; T_amb= 25 °C; R_G1= 120 kΩ.

f

V_DS= 5 V.

Fig.4 Unwanted voltage for 1% cross-modulation

as a function of gain reduction; typical

values; see Fig.18.

T_j= 25 °C.

Fig.5 Transfer characteristics; typical values.

MLB938

MLB939

200

30

handbook, halfpage

V

= 1.4 V

S

G1

I

V

= 4 V

S

G1

(µA)

G2

I

D

(mA)

1.3 V

1.2 V

1.1 V

150

3.5 V

20

3 V

100

50

0

2.5 V

2 V

1.0 V

0.9 V

10

0

1

2

3

2

4

6

8

10

(V)

V

(V)

S

G1

V

DS

V_DS= 5 V.

V_G2-S= 4 V.

T_j= 25 °C.

V_DS= 5 V.

T_j= 25 °C.

Fig.7 Gate 1 current as a function of gate 1

voltage; typical values.

Fig.6 Output characteristics; typical values.

Rev. 02 - 19 November 2007

5 of 12

NXP Semiconductors

Product speciﬁcation

N-channel dual gate MOS-FETs

BF909; BF909R

MLB941

MLB940

60

25

handbook, halfpage

I

D

V

= 4 V

S

G2

y

(mA)

20

fs

(mS)

3.5 V

3 V

40

15

10

5

2.5 V

20

2 V

0

10

20

30

20

40

60

I

(µA)

I

(mA)

G1

D

V_DS= 5 V.

V_DS= 5 V; V_G2-S= 4 V.

T_j= 25 °C.

Fig.8 Forward transfer admittance as a

Fig.9 Drain current as a function of gate 1 current;

typical values.

function of drain current; typical values.

MLB942

MLB943

16

30

handbook, halfpage

I

D

R

= 47 kΩ 68 kΩ

I

G1

D

(mA)

82 kΩ

(mA)

12

100 kΩ

20

120 kΩ

150 kΩ

180 kΩ

220 kΩ

8

4

10

0

2

4

6

0

2

4

6

8

V

(V)

GG

V

= V

(V)

DS

GG

V_DS= 5 V; V_G2-S= 4 V.

V_G2-S= 4 V.

R_G1connected to V_GG; T_j= 25 °C.

R_G1= 120 kΩ (connected to V_GG); T_j= 25 °C.

Fig.10 Drain current as a function of gate 1

supply voltage (= V_GG); typical values;

see Fig.18.

Fig.11 Drain current as a function of gate 1

(= V_GG) and drain supply voltage;

typical values; see Fig.18.

Rev. 02 - 19 November 2007

6 of 12

NXP Semiconductors

Product speciﬁcation

N-channel dual gate MOS-FETs

BF909; BF909R

MLB944

MLB945

20

40

handbook, halfpage

I

V

= 5 V

D

GG

I

G1

(µA)

(mA)

16

V

= 5 V

GG

4.5 V

30

4 V

4.5 V

3.5 V

3 V

4 V

12

8

3.5 V

3 V

20

10

4

0

2

4

6

2

4

6

V

(V)

S

V

(V)

S

G2

V_DS= 5 V; T_j= 25 °C.

_G1= 120 kΩ (connected to V_GG).

V_DS= 5 V; T_j= 25 °C.

R

R_G1= 120 kΩ (connected to V_GG).

Fig.12 Drain current as a function of gate 2 voltage;

typical values; see Fig.18.

Fig.13 Gate 1 current as a function of gate 2

voltage; typical values; see Fig.18.

MLB947

MLB946

3

2

10

rs

10

handbook, halfpage

y

ϕ

is

(mS)

rs

(deg)

(µS)

ϕ

rs

2

10

b

is

y

10

1

g

is

1

10

2

3

2

3

10

f (MHz)

V_DS= 5 V; V_G2= 4 V.

I_D= 15 mA; T_amb= 25 °C.

Fig.14 Input admittance as a function of frequency;

typical values.

Fig.15 Reverse transfer admittance and phase as

a function of frequency; typical values.

Rev. 02 - 19 November 2007

7 of 12

NXP Semiconductors

Product speciﬁcation

N-channel dual gate MOS-FETs

BF909; BF909R

MLB949

MLB948

2

10

fs

10

handbook, halfpage

y

os

y

fs

ϕ

y

(mS)

b

fs

os

(deg)

(mS)

1

ϕ

g

10

os

1

10

2

1

10

1

2

3

2

3

10

f (MHz)

V_DS= 5 V; V_G2= 4 V.

_D= 15 mA; T_amb= 25 °C.

V_DS= 5 V; V_G2= 4 V.

I

I_D= 15 mA; T_amb= 25 °C.

Fig.16 Forward transfer admittance and phase as

a function of frequency; typical values.

Fig.17 Output admittance as a function of

frequency; typical values.

V

AGC

R1

10 kΩ

C1

4.7 nF

C3 12 pF

R3

10 Ω

R

L

L1

C2

DUT

50 Ω

≈350 nH

C4

C5

2.2

pF

4.7 nF

R

R2

GEN

R

G1

50 Ω

4.7 nF

V

I

V

MLD151

GG

V

DS

Fig.18 Cross-modulation test set-up.

Rev. 02 - 19 November 2007

8 of 12

NXP Semiconductors

Product speciﬁcation

N-channel dual gate MOS-FETs

BF909; BF909R

Table 1 Scattering parameters: T_amb= 25 °C; V_DS= 5 V; V_G2-S= 4 V; I_D= 15 mA

s₁₁

s₂₁

s₁₂

s₂₂

f

MAGNITUDE ANGLE MAGNITUDE ANGLE MAGNITUDE ANGLE MAGNITUDE ANGLE

(MHz)

(ratio)

(deg)

(ratio)

(deg)

(ratio)

(deg)

(ratio)

(deg)

50

0.985

0.978

0.957

0.931

0.899

0.868

0.848

0.816

0.792

0.772

0.754

−6.4

−12.6

−25.0

−36.5

−47.6

−57.4

−66.6

−74.6

−82.2

−89.3

−95.6

4.064

3.997

3.886

3.682

3.484

3.260

3.053

2.829

2.652

2.470

2.328

172.3

164.9

150.8

137.3

123.8

111.7

101.0

90.3

0.001

0.002

0.005

0.006

0.007

0.006

0.005

0.006

86.9

82.7

74.3

68.9

59.6

57.9

58.5

65.5

83.3

114.9

138.7

0.985

0.982

0.973

0.960

0.947

0.936

0.927

0.919

0.913

0.910

0.909

−3.2

−6.4

100

200

300

400

500

600

700

800

900

1000

−12.6

−18.6

−24.2

−29.6

−34.8

−39.8

−44.6

−49.5

−54.6

79.9

69.5

59.5

Table 2 Noise data: T_amb= 25 °C; V_DS= 5 V; V_G2-S= 4 V; I_D= 15 mA

Γ_opt

f

F_min

(dB)

r_n

0.581

(MHz)

(ratio)

(deg)

67.71

800

2.00

0.603

Rev. 02 - 19 November 2007

9 of 12

NXP Semiconductors

Product speciﬁcation

N-channel dual gate MOS-FETs

BF909; BF909R

PACKAGE OUTLINES

3.0

2.8

handbook, full pagewidth

0.150

B

1.9

0.090

A

B

M

0.75

0.2

A

0.60

4

3

0.1

max

o

10

max

2.5

max

1.4

1.2

o

10

max

1

2

1.1

max

o

0.1 M

A

B

MBC845

30

max

0

0.1

0

0.1

0.88

0.48

1.7

TOP VIEW

Dimensions in mm.

Fig.19 SOT143.

3.0

2.8

handbook, full pagewidth

B

0.150

0.090

1.9

A

M

0.2

0.40

0.25

A

3

4

0.1

max

o

10

2.5

max

1.4

1.2

max

o

10

max

2

1

1.1

max

0.48

0.38

0.88

0.78

o

MBC844

30

max

1.7

B

0.1 M

TOP VIEW

Dimensions in mm.

Fig.20 SOT143R.

Rev. 02 - 19 November 2007

10 of 12

BF909; BF909R

NXP Semiconductors

N-channel dual gate MOS-FETs

Legal information

Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of an NXP Semiconductors product can reasonably be expected

Deﬁnitions

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

Contact information

For additional information, please visit: http://www.nxp.com

For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

Rev. 02 - 19 November 2007

11 of 12

BF909; BF909R

NXP Semiconductors

N-channel dual gate MOS-FETs

Revision history

Document ID

BF909_N_2

Modiﬁcations:

BF909_1

Release date

20071119

Data sheet status

Change notice

Supersedes

Product data sheet

-

BF909_1

• Fig.1 and 2 on page 2; Figure note changed

19950425 Product speciﬁcation

-

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 19 November 2007

Document identifier: BF909_N_2


型号：	BF909,215
厂家：	NXP
描述：	N-channel dual-gate MOSFET SOT-143 4-Pin 放大器光电二极管晶体管
文件：	总12页 (文件大小：323K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BF909,215 [NXP]

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