AV16823DL-T [NXP]
IC ALVT SERIES, DUAL 9-BIT DRIVER, TRUE OUTPUT, PDSO56, Bus Driver/Transceiver;
| 型号： | AV16823DL-T |
| 厂家： | 
NXP |
| 描述： | IC ALVT SERIES, DUAL 9-BIT DRIVER, TRUE OUTPUT, PDSO56, Bus Driver/Transceiver 振荡器 |
| 文件： | 总12页 (文件大小：103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74ALVT16823
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
Product specification
1998 Jun 12
Supersedes data of 1998 Mar 03
IC23 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
2.5V/3.3V 18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ALVT16823
FEATURES
DESCRIPTION
The 74ALVT16823 18-bit bus interface register is designed to
• Two sets of high speed parallel registers with positive
eliminate the extra packages required to buffer existing registers and
provide extra data width for wider data/address paths of buses
carrying parity.
edge-triggered D-type flip-flops
• 5V I/O Compatible
• Ideal where high speed, light loading, or increased fan-in are
The 74ALVT16823 has two 9-bit wide buffered registers with Clock
Enable (nCE) and Master Reset (nMR) which are ideal for parity bus
interfacing in high microprogrammed systems.
required with MOS microprocessors
• Live insertion/extraction permitted
• Power-up 3-State
The registers are fully edge-triggered. The state of each D input, one
set-up time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
• Power-up Reset
It is designed for V operation from 2.5 V to 3.0 V with I/O
compatibility to 5 V.
• No bus current loading when output is tied to 5 V bus
• Output capability: +64mA/–32mA
• Latch-up protection exceeds 500mA per Jedec Std 17
CC
• ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
• Bus hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
QUICK REFERENCE DATA
TYPICAL
CONDITIONS
= 25°C; GND = 0V
SYMBOL
PARAMETER
UNIT
T
amb
2.5V
3.3V
t
t
Propagation delay
nCP to nQx
PLH
PHL
C = 50pF
L
2.5
1.9
ns
C
Input capacitance
Output capacitance
Total supply current
V = 0V or V
CC
3
9
3
9
pF
pF
µA
IN
I
C
V
I/O
= 0V or 3.0V
OUT
CCZ
I
Outputs disabled
40
70
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
NORTH AMERICA
AV16823 DL
DWG NUMBER
SOT371–1
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
–40°C to +85°C
–40°C to +85°C
74ALVT16823 DL
74ALVT16823 DGG
AV16823 DGG
SOT364–1
PIN DESCRIPTION
PIN NUMBER
2, 27
SYMBOL
FUNCTION
1OE, 2OE
Output enable input (active-Low)
Data inputs
54, 52, 51, 49, 48, 47, 45, 44, 43
42, 41, 40, 38, 37, 36, 34, 33, 31
1D0-1D8
2D0-2D8
3, 5, 6, 8, 9, 10, 12, 13, 14
15, 16, 17, 19, 20, 21, 23, 24, 26
1Q0-1Q8
2Q0-2Q8
Data outputs
56, 29
55, 30
1CP, 2CP
1CE, 2CE
1MR, 2MR
GND
Clock pulse input (active rising edge)
Clock enable input (active-Low)
Master reset input (active-Low)
Ground (0V)
1, 28
4, 11, 18, 25, 32, 39, 46, 53
7, 22, 35, 50
V
CC
Positive supply voltage
2
1998 Jun 12
853-2069 19558
Philips Semiconductors
Product specification
2.5V/3.3V 18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ALVT16823
PIN CONFIGURATION
LOGIC SYMBOL (IEEE/IEC)
1MR
1OE
1Q0
GND
1Q1
1Q2
1
2
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1CP
1CE
1D0
GND
1D1
1D2
2
1
1OE
1MR
1CE
1CP
2OE
2MR
2CE
2CP
EN1
R2
3
55
56
27
28
30
29
G3
4
3C4
5
EN5
R6
6
V
7
V
G7
CC
CC
1Q3
1Q4
1Q5
GND
1Q6
1Q7
1Q8
2Q0
2Q1
2Q2
GND
2Q3
2Q4
2Q5
8
1D3
1D4
1D5
GND
1D6
1D7
1D8
2D0
2D1
2D2
GND
2D3
2D4
2D5
7C8
9
54
52
51
49
48
47
45
44
43
42
3
4D
1, 2
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
1Q0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
5
1Q1
6
1Q2
8
1Q3
9
1Q4
10
1Q5
12
1Q6
13
1Q7
14
1Q8
15
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2Q0
41
40
38
37
36
34
33
31
16
8D
5, 6
2Q1
17
2Q2
19
2Q3
V
V
CC
CC
20
2Q4
2Q6
2Q7
GND
2Q8
2OE
2MR
2D6
2D7
GND
2D8
2CE
2CP
21
2Q5
23
2Q6
24
2Q7
25
2Q8
SH00015
SH00014
LOGIC DIAGRAM
nCE
nD0
nD1
nD2
nD3
nD4
nD5
nD6
nD7
nD8
nCP
CP
nD
CP
Q
CP
CP
Q
CP
Q
CP
Q
CP
CP
Q
CP
Q
nD
nD
R
nD
nD
R
nD
R
nD
R
nD
R
nD
R
R
R
R
Q
Q
Q
nMR
nOE
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
nQ8
SH00016
n = 1 or 2
3
1998 Jun 12
Philips Semiconductors
Product specification
2.5V/3.3V 18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ALVT16823
FUNCTION TABLE
INPUTS
nCE
OUTPUTS
OPERATING MODE
nOE
nMR
nCP
nDx
nQ0 – nQ8
L
L
L
L
H
L
H
H
H
X
X
L
X
↑
X
h
l
L
H
Clear
Load and read data
L
↑
L
H
X
↑
X
X
NC
Z
Hold
X
High impedance
H = High voltage level
h
L
l
=
=
=
High voltage level one set-up time prior to the Low-to-High clock transition
Low voltage level
Low voltage level one set-up time prior to the Low-to-High clock transition
NC= No change
X
Z
↑
=
=
=
=
Don’t care
High impedance “off” state
Low to High clock transition
Not a Low-to-High clock transition
↑
V
CC
Data Input
To internal circuit
SW00044
1, 2
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
CONDITIONS
RATING
-0.5 to +4.6
-50
UNIT
V
V
CC
I
IK
DC supply voltage
DC input diode current
V < 0
I
mA
V
3
V
I
DC input voltage
-0.5 to +7.0
-50
I
DC output diode current
V
O
< 0
mA
V
OK
3
V
OUT
DC output voltage
Output in Off or High state
Output in Low state
-0.5 to +7.0
128
I
DC output current
mA
OUT
Output in High state
-64
T
stg
Storage temperature range
-65 to +150
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
4
1998 Jun 12
Philips Semiconductors
Product specification
2.5V/3.3V 18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ALVT16823
RECOMMENDED OPERATING CONDITIONS
2.5V RANGE LIMITS 3.3V RANGE LIMITS
SYMBOL
PARAMETER
UNIT
MIN
2.3
0
MAX
2.7
MIN
3.0
0
MAX
3.6
V
CC
DC supply voltage
Input voltage
V
V
V
I
5.5
5.5
V
High-level input voltage
Input voltage
1.7
2.0
V
IH
V
0.7
–8
8
0.8
–32
32
V
IL
I
High-level output current
Low-level output current
mA
OH
I
OL
mA
Low-level output current; current duty cycle ≤ 50%; f ≥ 1kHz
Input transition rise or fall rate; Outputs enabled
Operating free-air temperature range
24
10
+85
64
∆t/∆v
10
ns/V
T
amb
–40
–40
+85
°C
DC ELECTRICAL CHARACTERISTICS (3.3V "0.3V RANGE)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
UNIT
1
MIN
TYP
MAX
V
Input clamp voltage
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3.0V; I = –18mA
–0.85
–1.2
V
V
IK
IK
= 3.0 to 3.6V; I = –100µA
V
–0.2
V
CC
OH
CC
V
OH
High-level output voltage
= 3.0V; I = –32mA
2.0
2.3
0.07
0.25
0.3
OH
= 3.0V; I = 100µA
0.2
0.4
OL
= 3.0V; I = 16mA
OL
V
OL
Low-level output voltage
V
= 3.0V; I = 32mA
0.5
OL
= 3.0V; I = 64mA
0.4
0.55
OL
6
V
Power-up output low voltage
Input leakage current
Off current
V
V
V
V
V
V
V
V
= 3.6V; I = 1mA; V = V or GND
0.55
±1
V
RST
CC
CC
CC
CC
CC
CC
CC
CC
O
I
CC
= 3.6V; V = V or GND
Control pins
0.1
0.1
I
CC
= 0 or 3.6V; V = 5.5V
10
I
I
I
µA
= 3.6V; V = V
0.5
1
I
CC
4
Data pins
= 3.6V; V = 0V
0.1
-5
I
I
= 0V; V or V = 0 to 4.5V
0.1
±100
µA
µA
OFF
I
O
= 3V; V = 0.8V
75
130
–140
I
Bus Hold current
D inputs
= 3V; V = 2.0V
–75
I
I
HOLD
7
V = 0V to 3.6V; V = 3.6V
I
±500
CC
Current into an output in the
I
V
= 5.5V; V = 3.0V
10
1
125
µA
µA
EX
O
CC
High state when V > V
O
CC
Power up/down 3-State output
V
CC
≤ 1.2V; V = 0.5V to V ; V = GND or V
O CC I CC
I
±100
PU/PD
3
current
OE/OE = Don’t care
I
3-State output High current
3-State output Low current
V
V
V
V
V
V
= 3.6V; V = 3.0V; V = V or V
0.5
0.5
5
µA
µA
OZH
CC
CC
CC
CC
CC
CC
O
I
IL
IH
IH
I
= 3.6V; V = 0.5V; V = V or V
–5
OZL
O
I
IL
I
= 3.6V; Outputs High, V = GND or V I 0
CC, O =
0.06
3.9
0.1
5.5
0.1
CCH
I
I
Quiescent supply current
= 3.6V; Outputs Low, V = GND or V I 0
CC, O =
mA
mA
CCL
CCZ
I
5
I
= 3.6V; Outputs Disabled; V = GND or V
I 0
CC, O =
0.06
I
Additional supply current per
= 3V to 3.6V; One input at V –0.6V,
CC
∆I
0.04
0.4
CC
2
input pin
Other inputs at V or GND
CC
NOTES:
1. All typical values are at V = 3.3V and T
= 25°C.
amb
CC
2. This is the increase in supply current for each input at the specified voltage level other than V or GND
CC
3. This parameter is valid for any V between 0V and 1.2V with a transition time of up to 10msec. From V = 1.2V to V = 3.3V ± 0.3V a
CC
CC
CC
transition time of 100µsec is permitted. This parameter is valid for T
= 25°C only.
amb
4. Unused pins at V or GND.
CC
5. I
is measured with outputs pulled up to V or pulled down to ground.
CCZ
CC
6. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
7. This is the bus hold overdrive current required to force the input to the opposite logic state.
5
1998 Jun 12
Philips Semiconductors
Product specification
2.5V/3.3V 18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ALVT16823
AC CHARACTERISTICS (3.3V "0.3V RANGE)
GND = 0V, t = t = 2.5ns, C = 50pF, R = 500Ω , T
= –40°C to +85°C
R
F
L
L
amb
LIMITS
SYMBOL
PARAMETER
WAVEFORM
V
CC
= +3.3V±0.3V
UNIT
1
MIN
TYP
MAX
f
Maximum clock frequency
1
1
250
–
–
MHz
ns
MAX
t
t
Propagation delay
nCP to nQx
1.9
1.9
3.1
2.9
PLH
PHL
–
–
–
–
Propagation delay
nMR to nQx
t
2
2.0
3.0
ns
ns
ns
PHL
t
t
Output enable time
to High and Low level
4
5
1.8
2.7
4.2
4.0
PZH
PZL
t
t
Output disable time
from High and Low level
4
5
2.7
2.0
4.0
3.0
PHZ
PLZ
NOTE:
1. All typical values are at V = 3.3 V and T
= 25°C
amb
CC
AC SETUP REQUIREMENTS (3.3V "0.3V RANGE)
GND = 0V, t = t = 2.5ns, C = 50pF, R = 500Ω , T
= –40°C to +85°C
R
F
L
L
amb
LIMITS
SYMBOL
PARAMETER
WAVEFORM
V
CC
= +3.3V ±0.3V
UNIT
MIN
TYP
t (H)
t (L)
s
Setup time, High or Low
nDx to nCP
1.0
1.2
0.5
0.7
s
3
3
1
3
ns
ns
ns
ns
t (H)
Hold time, High or Low
nDx to nCP
0.1
0.1
–0.7
–0.5
h
t (L)
h
t (H)
nCP pulse width
High or Low
1.5
2.5
0.7
1.4
w
t (L)
w
t (H)
Setup time, High or Low
nCE to nCP
1.0
0.5
0.1
–0.5
s
t (L)
s
t (H)
t (L)
h
Hold time, High or Low
nCE to nCP
1.0
1.0
0.5
–0.1
h
3
2
2
ns
ns
ns
t (L)
w
nMR pulse width, Low
2.0
2.0
1.5
1.1
Recovery time
nMR to nCP
t
rec
6
1998 Jun 12
Philips Semiconductors
Product specification
2.5V/3.3V 18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ALVT16823
DC ELECTRICAL CHARACTERISTICS (2.5V "0.2V RANGE)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
UNIT
1
MIN
TYP
–0.85
MAX
V
Input clamp voltage
V
V
V
V
V
V
= 2.3V; I = –18mA
–1.2
V
V
IK
CC
CC
CC
CC
CC
CC
IK
= 2.3 to 3.6V; I = –100µA
V
–0.2
V
CC
OH
CC
V
OH
High-level output voltage
= 2.3V; I = –8mA
1.8
2.5
0.07
0.3
OH
= 2.3V; I = 100µA
0.2
0.5
0.4
OL
V
OL
Low-level output voltage
V
V
= 2.3V; I = 24mA
OL
= 2.3V; I = 8mA
OL
7
V
RST
Power-up output low voltage
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.7V; I = 1mA; V = V or GND
0.55
±1
O
I
CC
= 2.7V; V = V
or GND
CC
Control pins
0.1
0.1
0.1
0.1
0.1
100
–70
I
= 0 or 2.7V; V = 5.5V
10
I
I
Input leakage current
µA
I
= 3.6V; V = V
1
I
CC
4
Data pins
= 3.6V; V = 0
-5
I
I
Off current
= 0V; V or V = 0 to 4.5V
±100
µA
µA
µA
OFF
I
O
Bus Hold current
= 2.3V; V = 0.7V
I
I
HOLD
6
D inputs
= 2.3V; V = 1.7V
I
Current into an output in the
I
V
V
= 5.5V; V = 2.3V
10
1
125
µA
µA
EX
O
CC
High state when V > V
O
CC
Power up/down 3-State output
≤ 1.2V; V = 0.5V to V ; V = GND or V
;
CC
CC
O
CC
I
I
±100
PU/PD
3
current
OE/OE = Don’t care
I
3-State output High current
3-State output Low current
V
V
V
V
V
V
= 2.7V; V = 2.3V; V = V or V
0.5
0.5
5
µA
µA
OZH
CC
CC
CC
CC
CC
CC
O
I
IL
IH
IH
I
= 2.7V; V = 0.5V; V = V or V
–5
OZL
O
I
IL
I
= 2.7V; Outputs High, V = GND or V I 0
CC, O =
0.04
2.7
0.1
4.5
0.1
CCH
I
I
Quiescent supply current
= 2.7V; Outputs Low, V = GND or V I 0
CC, O =
mA
mA
CCL
CCZ
I
5
I
= 2.7V; Outputs Disabled; V = GND or V
I 0
CC, O =
0.04
I
Additional supply current per
= 2.3V to 2.7V; One input at V –0.6V,
CC
∆I
0.04
0.4
CC
2
input pin
Other inputs at V or GND
CC
NOTES:
1. All typical values are at V = 2.5V and T
= 25°C.
amb
CC
2. This is the increase in supply current for each input at the specified voltage level other than V or GND
CC
3. This parameter is valid for any V between 0V and 1.2V with a transition time of up to 10msec. From V = 1.2V to V = 2.5V ± 0.2V a
CC
CC
CC
transition time of 100µsec is permitted. This parameter is valid for T
= 25°C only.
amb
4. Unused pins at V or GND.
CC
5. I
is measured with outputs pulled up to V or pulled down to ground.
CCZ
CC
6. Not guaranteed.
7. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
AC CHARACTERISTICS (2.5V "0.2V RANGE)
GND = 0V, t = t = 2.5ns, C = 50pF, R = 500Ω , T
= –40°C to +85°C
R
F
L
L
amb
LIMITS
SYMBOL
PARAMETER
WAVEFORM
V
CC
= +2.5V±0.2V
UNIT
1
MIN
TYP
MAX
f
Maximum clock frequency
1
1
150
–
–
MHz
ns
MAX
t
t
Propagation delay
nCP to nQx
2.6
2.4
5.2
4.2
PLH
PHL
–
–
–
–
Propagation delay
nMR to nQx
t
2
2.5
4.5
ns
ns
ns
PHL
t
t
Output enable time
to High and Low level
4
5
2.3
3.2
5.6
5.3
PZH
PZL
t
t
Output disable time
from High and Low level
4
5
3.3
3.0
5.6
6.7
PHZ
PLZ
NOTE:
1. All typical values are at V = 3.3 V and T
= 25°C
amb
CC
7
1998 Jun 12
Philips Semiconductors
Product specification
2.5V/3.3V 18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ALVT16823
AC SETUP REQUIREMENTS (2.5V "0.2V RANGE)
GND = 0V, t = t = 2.5ns, C = 50pF, R = 500Ω, T
= –40°C to +85°C
R
F
L
L
amb
LIMITS
SYMBOL
PARAMETER
WAVEFORM
V
CC
= +2.5V ±0.2V
UNIT
MIN
TYP
t (H)
t (L)
s
Setup time, High or Low
nDx to nCP
1.0
1.8
0.5
1.3
s
3
3
1
3
ns
ns
ns
ns
t (H)
Hold time, High or Low
nDx to nCP
0.1
0.1
–1.4
–0.5
h
t (L)
h
t (H)
nCP pulse width
High or Low
2.0
3.0
0.8
2.1
w
t (L)
w
t (H)
Setup time, High or Low
nCE to nCP
1.0
0.5
0.2
–0.1
s
t (L)
s
t (H)
t (L)
h
Hold time, High or Low
nCE to nCP
1.0
1.0
0.2
–0.1
h
3
2
2
ns
ns
ns
t (L)
w
nMR pulse width, Low
2.0
2.0
0.8
1.3
Recovery time
nMR to nCP
t
rec
AC WAVEFORMS
For all waveforms, V = 1.5V or V /2 whichever is less
M
CC
The shaded areas indicate when the input is permitted to change for
predictable output performance.
3.0V or V
CC
whichever
is less
nDx,
nCE
V
V
V
V
V
M
M
M
M
1/f
MAX
0V
3.0V or V
3.0V or V
CC
whichever
is less
t (H)
t
(H)
t (L)
t (L)
h
CC
s
h
s
whichever
is less
nCP
nQx
V
t
V
M
M
t
nCP
0V
V
t
(H)
M
M
w
0V
t
(L)
PLH
w
PHL
V
OH
SH00019
V
V
M
M
0V
Waveform 3. Data Setup and Hold Times
SH00017
Waveform 1. Propagation Delay, Clock Input to Output,
Clock Pulse Width, and Maximum Clock Frequency
3.0V or V
whichever
is less
CC
nOE
V
V
M
M
t
0V
3.0V or V
CC
t
whichever
is less
PZH
PHZ
V
V
M
nMR
M
V
V
OH
0V
3.0V or V
–0.3V
OH
V
t
M
REC
t
(L)
w
CC
nQx
0V
whichever
is less
V
nCP
nQx
M
SH00020
0V
t
Waveform 4. 3-State Output Enable Time to High Level
and Output Disable Time from High Level
PHL
V
OH
V
M
0V
SH00018
Waveform 2. Master Reset Pulse WIdth, Master Reset to
Output Delay and Master Reset to Clock Recovery Time
8
1998 Jun 12
Philips Semiconductors
Product specification
2.5V/3.3V 18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ALVT16823
AC WAVEFORMS (Continued)
For all waveforms, V = 1.5V or V /2 whichever is less
M
CC
The shaded areas indicate when the input is permitted to change for
predictable output performance.
3.0V or V
CC
whichever
is less
V
V
M
M
nOE
nQx
0V
3.0V or V
whichever
is less
t
t
PLZ
PZL
CC
V
M
V
V
+0.3V
OL
OL
SH00021
Waveform 5. 3-State Output Enable Time to Low Level
and Output Disable Time from Low Level
TEST CIRCUIT AND WAVEFORM
6V or
x 2
V
t
W
V
CC
AMP (V)
90%
CC
90%
OPEN
GND
NEGATIVE
PULSE
V
V
M
10%
M
10%
V
V
OUT
IN
R
R
L
L
0V
(t
PULSE
GENERATOR
D.U.T.
t
t
(t
(t
)
t
t
)
THL
F
TLH
R
)
(t )
F
R
C
TLH
R
THL
T
L
AMP (V)
90%
M
90%
POSITIVE
PULSE
V
V
M
Test Circuit for 3-State Outputs
10%
10%
t
W
0V
SWITCH POSITION
V
M
= 1.5V or V / 2, whichever is less
CC
TEST
SWITCH
Input Pulse Definition
t
/t
GND
PHZ PZH
t
/t
6V or V x 2
PLZ PZL
CC
t
/t
open
PLH PHL
INPUT PULSE REQUIREMENTS
DEFINITIONS
FAMILY
R = Load resistor; see AC CHARACTERISTICS for value.
Amplitude
3.0V or V
whichever
is less
Rep. Rate
t
t
t
L
W
R
F
C = Load capacitance includes jig and probe capacitance;
L
CC
see AC CHARACTERISTICS for value.
74ALVT16
≤10MHz
500ns ≤2.5ns ≤2.5ns
R = Termination resistance should be equal to Z
T
of
OUT
pulse generators.
SW00162
9
1998 Jun 12
Philips Semiconductors
Product specification
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ALVT16823
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm
SOT371-1
10
1998 Jun 12
Philips Semiconductors
Product specification
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ALVT16823
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm
SOT364-1
11
1998 Jun 12
Philips Semiconductors
Product specification
18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
74ALVT16823
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 05-96
9397-750-04016
Document order number:
Philips
Semiconductors
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