ADC1610S105HN/C1 [NXP]
Single 16-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs; 一个16位ADC ; 65 MSPS, 80 MSPS, 105 Msps的或125 MSPS ; CMOS或DDR LVDS数字输出型号: | ADC1610S105HN/C1 |
厂家: | NXP |
描述: | Single 16-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs |
文件: | 总38页 (文件大小:276K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ADC1610S series
Single 16-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps;
CMOS or LVDS DDR digital outputs
Rev. 02 — 12 April 2010
Objective data sheet
1. General description
The ADC1610S is a single-channel 16-bit Analog-to-Digital Converter (ADC) optimized for
high dynamic performances and low power consumption at sample rates up to 125 Msps.
Pipelined architecture and output error correction ensure the ADC1610S is accurate
enough to guarantee zero missing codes over the entire operating range. Supplied from a
single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode,
because of a separate digital output supply. It supports the Low Voltage Differential
Signalling (LVDS) Double Data Rate (DDR) output standard. An integrated Serial
Peripheral Interface (SPI) allows the user to easily configure the ADC. The device also
includes a SPI programmable full-scale to allow flexible input voltage range from
1 V to 2 V (peak-to-peak). With excellent dynamic performance from the baseband to
input frequencies of 170 MHz or more, the ADC1610S is ideal for use in communications,
imaging and medical applications.
2. Features and benefits
SNR, 72.5 dBFS; SFDR, 88 dBc
Input bandwidth, 600 MHz
Sample rate up to 125 Msps
16-bit pipelined ADC core
Power dissipation, 430 mW at 80 Msps
Serial Peripheral Interface (SPI)
Duty cycle stabilizer
Clock input divider by 2 for less jitter
contribution
Single 3 V supply
Fast OuT of Range (OTR) detection
Flexible input voltage range: 1 V to 2 V INL ±1 LSB, DNL ±0.5 LSB
(peak-to-peak).
CMOS or LVDS DDR digital outputs
Power-down and Sleep modes
Offset binary, two’s complement, gray
code
HVQFN40 package
3. Applications
Wireless and wired broadband
Portable instrumentation
communications
Spectral analysis
Imaging systems
Ultrasound equipment
Software define radio
ADC1610S series
NXP Semiconductors
ADC1610S series; CMOS or LVDS DDR digital output
4. Ordering information
Table 1.
Ordering information
Type number
fs (Msps) Package
Name
Description
Version
ADC1610S125HN/C1 125
ADC1610S105HN/C1 105
ADC1610S080HN/C1 80
ADC1610S065HN/C1 65
HVQFN40 plastic thermal enhanced very thin quad flat package; no
SOT618-6
SOT618-6
SOT618-6
SOT618-6
leads; 40 terminals; body 6 × 6 × 0.85 mm
HVQFN40 plastic thermal enhanced very thin quad flat package; no
leads; 40 terminals; body 6 × 6 × 0.85 mm
HVQFN40 plastic thermal enhanced very thin quad flat package; no
leads; 40 terminals; body 6 × 6 × 0.85 mm
HVQFN40 plastic thermal enhanced very thin quad flat package; no
leads; 40 terminals; body 6 × 6 × 0.85 mm
5. Block diagram
SDIO/ODS
SCLK/DFS
CS
ADC1610S
ERROR
CORRECTION AND
DIGITAL
SPI INTERFACE
PROCESSING
OTR
CMOS:
D15 to D0
or
LVDS/DDR:
D15_M to D0_M
D15_P to D0_P
INP
INM
T/H
INPUT
STAGE
ADC CORE
16-BIT
PIPELINED
OUTPUT
DRIVERS
CMOS:
DAV
or
OUTPUT
DRIVERS
LVDS/DDR:
DAVP
DAVM
SYSTEM
REFERENCE AND
POWER
CLOCK INPUT
STAGE AND DUTY
CYCLE CONTROL
PWD
OE
MANAGEMENT
CLKP CLKM
VCM
SENSE
REFT
VREF
REFB
005aaa156
Fig 1. Block diagram
ADC1610S_SER_2
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 02 — 12 April 2010
2 of 38
ADC1610S series
NXP Semiconductors
ADC1610S series; CMOS or LVDS DDR digital output
6. Pinning information
6.1 Pinning
terminal 1
index area
terminal 1
index area
1
2
30
29
28
27
26
25
24
23
22
21
REFB
REFT
AGND
VCM
D2_D3_P
D2_D3_M
D4_D5_P
D4_D5_M
D6_D7_P
D6_D7_M
D8_D9_P
D8_D9_M
D10_D11_P
D10_D11_M
1
2
30
29
28
27
26
25
24
23
22
21
REFB
REFT
AGND
VCM
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
3
3
4
4
5
VDDA
AGND
INM
ADC1610S
HVQFN40
5
VDDA
AGND
INM
6
ADC1610S
HVQFN40
6
7
7
8
INP
8
INP
9
AGND
VDDA
9
AGND
VDDA
10
10
005aaa106
005aaa105
Transparent top view
Transparent top view
Fig 2. Pin configuration with CMOS digital outputs
selected
Fig 3. Pin configuration with LVDS/DDR digital
outputs selected
6.2 Pin description
Table 2.
Symbol
REFB
REFT
AGND
VCM
Pin description (CMOS digital outputs)
Pin
1
Type [1]
Description
O
O
G
O
P
G
I
bottom reference
2
top reference
3
analog ground
4
common-mode output voltage
analog power supply
analog ground
VDDA
AGND
INM
5
6
7
complementary analog input
analog input
INP
8
I
AGND
VDDA
VDDA
CLKP
CLKM
DEC
9
G
P
P
I
analog ground
10
11
12
13
14
15
16
analog power supply
analog power supply
clock input
I
complementary clock input
regulator decoupling node
power down, active HIGH; output enable, active LOW
out of range
O
I
PWD/OE
OTR
O
ADC1610S_SER_2
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 02 — 12 April 2010
3 of 38
ADC1610S series
NXP Semiconductors
ADC1610S series; CMOS or LVDS DDR digital output
Table 2.
Pin description (CMOS digital outputs)
Symbol
D15
Pin
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Type [1]
Description
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
P
data output bit 15 (MSB)
data output bit 14
D14
D13
data output bit 13
D12
data output bit 12
D11
data output bit 11
D10
data output bit10
D9
data output bit 9
D8
data output bit 8
D7
data output bit 7
D6
data output bit 6
D5
data output bit 5
D4
data output bit 4
D3
data output bit 3
D2
data output bit 2
D1
data output bit 1
D0
data output bit 0 (LSB)
output power supply
data valid output clock
not connected
VDDO
DAV
n.c.
O
-
SCLK/DFS
SDIO/ODS
CS
I
SPI clock / data format select
SPI data IO / output data standard
SPI chip select
I/O
I
SENSE
VREF
I
reference programming pin
voltage reference input/output
I/O
[1] P: power supply; G: ground; I: input; O: output; I/O: input/output.
ADC1610S_SER_2
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 02 — 12 April 2010
4 of 38
ADC1610S series
NXP Semiconductors
ADC1610S series; CMOS or LVDS DDR digital output
Table 3.
Symbol
Pin description (LVDS/DDR) digital outputs)
Pin[1] Type [2] Description
D14_D15_M 17
D14_D15_P 18
D12_D13_M 19
D12_D13_P 20
D10_D11_M 21
D10_D11_P 22
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
differential output data D14 and D15 multiplexed, complement
differential output data D14 and D15 multiplexed, true
differential output data D12 and D13 multiplexed, complement
differential output data D12 and D13 multiplexed, true
differential output data D10 and D11multiplexed, complement
differential output data D10 and D11 multiplexed, true
differential output data D8 and D9 multiplexed, complement
differential output data D8 and D9 multiplexed, true
differential output data D6 and D7 multiplexed, complement
differential output data D6 and D7 multiplexed, true
differential output data D4 and D5 multiplexed, complement
differential output data D4 and D5 multiplexed, true
differential output data D2 and D3 multiplexed, complement
differential output data D2 and D3 multiplexed, true
differential output data D0 and D1 multiplexed, complement
differential output data D0 and D1 multiplexed, true
data valid output clock, complement
D8_D9_M
D8_D9_P
D6_D7_M
D6_D7_P
D4_D5_M
D4_D5_P
D2_D3_M
D2_D3_P
D0_D1_M
D0_D1_P
DAVM
23
24
25
26
27
28
29
30
31
32
34
35
DAVP
data valid output clock, true
[1] Pins 1 to 16 and pins 36 to 40 are the same for both CMOS and LVDS DDR outputs (see Table 2)
[2] P: power supply; G: ground; I: input; O: output; I/O: input/output.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VO
output voltage
pins D15 to D0;
−0.4
+3.9
V
pins D15P to D0P;
pins D15M to D0M
VDDA
VDDO
Tstg
analog supply voltage
output supply voltage
storage temperature
ambient temperature
junction temperature
−0.4
−0.4
−55
−40
-
+3.9
+3.9
+125
+85
V
V
°C
°C
°C
Tamb
Tj
125
8. Thermal characteristics
Table 5.
Symbol
Rth(j-a)
Thermal characteristics
Parameter
Conditions
Typ
Unit
[1]
[1]
thermal resistance from junction to ambient
thermal resistance from junction to case
22.5
11.7
K/W
K/W
Rth(j-c)
[1] Value for six layers board in still air with a minimum of 25 thermal vias.
ADC1610S_SER_2
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 02 — 12 April 2010
5 of 38
ADC1610S series
NXP Semiconductors
ADC1610S series; CMOS or LVDS DDR digital output
9. Static characteristics
Table 6.
Symbol
Supplies
VDDA
Static characteristics[1]
Parameter
Conditions
Min
Typ
Max
Unit
analog supply voltage
output supply voltage
2.85
1.65
2.85
-
3.0
1.8
3.0
210
14
3.4
3.6
3.6
-
V
VDDO
CMOS mode
V
LVDS DDR mode
fclk = 125 Msps; fi =70 MHz
CMOS mode;
V
IDDA
IDDO
analog supply current
output supply current
mA
mA
-
-
f
clk = 125 Msps; fi =70 MHz
LVDS DDR mode:
fclk = 125 Msps; fi =70 MHz
-
-
-
-
-
43
-
-
-
-
-
mA
P
power dissipation
ADC1610S125;
analog supply only
630
550
430
380
mW
mW
mW
mW
ADC1610S105;
analog supply only
ADC1610S080;
analog supply only
ADC1610S065;
analog supply only
power-down mode
sleep mode
-
-
2
-
-
mW
mW
40
Clock inputs: pins CLKP and CLKM
LVPECL
Vi(clk)dif
LVDS
differential clock input voltage
peak-to-peak
peak-to-peak
peak-to-peak
-
±0.8
±0.70
±3.0
-
-
-
V
V
V
Vi(clk)dif
SINE wave
Vi(clk)dif
LVCMOS
VIL
differential clock input voltage
differential clock input voltage
-
±0.8
LOW-level input voltage
HIGH-level input voltage
-
-
-
0.3VDDA
-
V
V
VIH
0.7VDDA
Logic inputs, Power-down: pin PWD/OEB
VIL
LOW-level input voltage
-
0
-
V
LOW-medium level
Medium-HIGH level
-
0.3VDDA
-
V
-
0.6VDDA
-
V
VIH
IIL
HIGH-level input voltage
LOW-level input current
HIGH-level input current
-
VDDA
-
V
<tbd>
−10
-
-
<tbd>
+10
μA
μA
IIH
Serial peripheral interface: pins CS, SDIO/ODS, SCLK/DFS
VIL
VIH
IIL
LOW-level input voltage
HIGH-level input voltage
LOW-level input current
0
-
-
-
0.3VDDA
VDDA
V
0.7VDDA
V
−10
+10
μA
ADC1610S_SER_2
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 02 — 12 April 2010
6 of 38
ADC1610S series
NXP Semiconductors
ADC1610S series; CMOS or LVDS DDR digital output
Table 6.
Symbol
IIH
Static characteristics[1] …continued
Parameter
Conditions
Min
−50
-
Typ
Max
+50
-
Unit
μA
HIGH-level input current
input capacitance
-
CI
4
pF
Digital outputs, CMOS mode: pins D15 to D0, OTR, DAV
Output levels, VDDO = 3 V
VOL
VOH
IOL
LOW-level output voltage
HIGH-level output voltage
LOW-level output current
HIGH-level output current
output capacitance
IOL = <tbd>
OGND
-
0.2VDDO
V
IOH = <tbd>
0.8VDDO
-
VDDO
V
3-state; output level = 0 V
3-state; output level = VDDA
high impedance; OE = HIGH
-
-
-
<tbd>
<tbd>
3
-
-
-
μA
μA
pF
IOH
CO
Output levels, VDDO = 1.8 V
VOL
VOH
LOW-level output voltage
HIGH-level output voltage
IOL = <tbd>
IOH = <tbd>
OGND
-
-
0.2VDDO
VDDO
V
V
0.8VDDO
Digital outputs, LVDS mode: pins D15P to D0P, D15M to D0M, DAVP and DAVM
Output levels, VDDO = 3 V only, RL = 100 Ω
VO(offset)
VO(dif)
CO
output offset voltage
differential output voltage
output capacitance
output buffer current set to
3.5 mA
-
-
-
1.2
-
-
-
V
output buffer current set to
3.5 mA
350
mV
pF
<tbd>
Analog inputs: pins INP and INM
II
input current
−5
-
-
+5
-
μA
Ω
RI
input resistance
<tbd>
5
CI
input capacitance
common mode input voltage
input bandwidth
-
-
pF
V
VI(cm)
Bi
VINP = VINM
0.9
-
1.5
600
2
-
MHz
V
VI(dif)
differential input voltage
peak-to-peak
1
2
Common mode output voltage: pin VCM
VO(cm)
IO(cm)
common-mode output voltage
common-mode output current
-
-
VDDA / 2
<tbd>
-
-
V
μA
I/O reference voltage: pin VREF
VVREF
voltage on pin VREF
output
input
0.5
0.5
-
-
1
1
V
V
Accuracy
INL
integral non-linearity
differential non-linearity
offset error
-
±4
-
LSB
LSB
mV
%
DNL
guaranteed no missing codes
full-scale
-0.95
-
±0.5
±2
+0.95
-
Eoffset
EG
gain error
±0.5
ADC1610S_SER_2
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 02 — 12 April 2010
7 of 38
ADC1610S series
NXP Semiconductors
ADC1610S series; CMOS or LVDS DDR digital output
Table 6.
Symbol
Supply
PSRR
Static characteristics[1] …continued
Parameter
Conditions
Min
Typ
Max
Unit
power supply rejection ratio
100 mV (p-p) on VDDA
-
35
-
dBc
[1] Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 °C and CL = 5 pF; minimum and maximum values are across the full
temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDO = 1.8 V; VINP − VINM = −1 dBFS; internal reference mode; applied to
CMOS and LVDS interface; unless otherwise specified.
ADC1610S_SER_2
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 02 — 12 April 2010
8 of 38
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10. Dynamic characteristics
10.1 Dynamic characteristics
Table 7.
Symbol
Dynamic characteristics
Parameter
Conditions
ADC1610S065
ADC1610S080
ADC1610S105
ADC1610S125
Max
Unit
Min
Typ
Max Min
Typ
Max Min Typ Max Min Typ
Analog signal processing
α2H
second harmonic
level
fi = 3 MHz
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
89
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
89
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
88
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
90
-
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
bits
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
88
88
88
89
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
87
87
86
87
84
84
83
85
α3H
third harmonic level fi = 3 MHz
fi = 30 MHz
88
88
87
89
87
87
87
88
fi = 70 MHz
86
86
85
86
fi = 170 MHz
83
83
82
84
THD
ENOB
SNR
SFDR
total harmonic
distortion
fi = 3 MHz
87
87
86
88
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
86
86
86
87
85
85
84
85
82
82
81
83
effective number of fi = 3 MHz
bits
11.7
11.6
11.5
11.4
72.3
71.5
70.9
70.4
88
11.7
11.6
11.5
11.4
72.2
71.4
70.9
70.3
88
11.7
11.6
11.5
11.4
72.0
71.4
70.8
70.2
87
11.6
11.6
11.5
11.4
71.6
71.3
70.7
70.1
89
fi = 30 MHz
bits
fi = 70 MHz
fi = 170 MHz
bits
bits
signal-to-noise ratio fi = 3 MHz
fi = 30 MHz
dBFS
dBFS
dBFS
dBFS
dBc
dBc
dBc
dBc
fi = 70 MHz
fi = 170 MHz
spurious-free
dynamic range
fi = 3 MHz
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
87
87
87
88
86
86
85
86
83
83
82
84
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Table 7.
Symbol
Dynamic characteristics …continued
Parameter
Conditions
ADC1610S065
ADC1610S080
ADC1610S105
ADC1610S125
Max
Unit
Min
Typ
89
Max Min
Typ
89
Max Min Typ Max Min Typ
IMD
intermodulation
distortion
fi = 3 MHz
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
88
88
86
83
-
-
-
-
-
-
-
-
89
88
86
84
-
dBc
dBc
dBc
dBc
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
88
88
-
-
-
87
87
84
85
[1] Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 °C and CL = 5 pF; minimum and maximum values are across the full temperature range Tamb = −40 °C to +85 °C
at VDDA = 3 V, VDDO = 1.8 V; VINP − VINM = −1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified.
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10.2 Clock and digital output timing
Table 8.
Clock and digital output timing characteristics[1]
Symbol Parameter
Conditions
ADC1610S065
ADC1610S080
ADC1610S105
ADC1610S125
Min Typ Max
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Clock timing input: pins CLKP and CLKM
fclk
clock frequency
20
-
-
65
-
60
-
-
80
-
75
-
-
105
-
100
-
-
125
-
MHz
tlat(data)
data latency time clock cycles
14
14
14
14
clock
cycle
δclk
clock duty cycle
DCS_EN = 1
DCS_EN = 0
30
45
-
50
70
55
-
30
45
-
50
70
55
-
30
45
-
50
70
55
-
30
45
-
50
50
0.8
70
55
-
%
%
ns
50
50
50
td(s)
sampling delay
time
0.8
0.8
0.8
twake
wake-up time
-
<tbd>
-
-
<tbd>
-
-
<tbd>
-
-
<tbd>
-
ns
CMOS Mode Timing output: pins D15 to D0 and DAV
tPD
propagation delay DATA
DAV
-
3.9
4.2
7.7
6.7
-
-
-
3.9
4.2
6.5
5.5
-
-
-
3.9
4.2
4.7
3.8
-
-
-
3.9
4.2
4.3
3.5
-
-
ns
ns
ns
ns
ns
ns
ns
-
-
-
-
-
-
-
-
tsu
th
set-up time
-
-
-
-
-
-
-
-
hold time
-
-
-
-
-
-
-
-
tr
rise time[2]
DATA
DAV
0.5
0.5
0.5
2.4
2.4
2.4
0.5
0.5
0.5
2.4
2.4
2.4
0.5
0.5
0.5
2.4
2.4
2.4
0.5
0.5
0.5
2.4
2.4
2.4
-
-
-
-
tf
fall time[2]
DATA
-
-
-
-
LVDS DDR mode timing output: pins D15P to D0P, D15M to D0M, DAVP and DAVM
tPD
propagation delay DATA
DAV
-
3.9
4.2
5.1
2.0
100
100
100
100
-
-
3.9
4.2
3.5
2.0
100
100
100
100
-
-
3.9
4.2
2.1
-
-
3.9
4.2
1.4
-
ns
ns
ns
ns
ps
ps
ps
ps
-
-
-
-
-
-
-
-
tsu
th
set-up time
-
-
-
-
-
-
-
-
hold time
-
-
-
-
-
2.0
-
-
2.0
-
tr
rise time[3]
fall time[3]
DATA
DAV
50
50
50
50
200
200
200
200
50
50
50
50
200
200
200
200
50
50
50
50
100
100
100
100
200
200
200
200
50
50
50
50
100
100
100
100
200
200
200
200
tf
DATA
DAV
[1] Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 °C and CL = 5 pF; minimum and maximum values are across the full temperature range Tamb = −40 °C to +85 °C
at VDDA = 3 V, VDDO = 1.8 V; VINP − VINM = −1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified.
[2] Measured between 20 % to 80 % of VDDO
.
ADC1610S series
NXP Semiconductors
ADC1610S series; CMOS or LVDS DDR digital output
[3] Rise time measured from −50 mV to +50 mV; fall time measured from +50 mV to −50 mV.
N
N + 1
t
d(s)
N + 2
t
clk
CLKP
CLKM
t
PD
(N − 14)
(N − 13)
(N − 12)
(N − 11)
DATA
DAV
t
PD
t
su
t
h
t
clk
005aaa060
Fig 4. CMOS mode timing
N
N + 1
t
d(s)
N + 2
t
clk
CLKP
CLKM
t
PD
(N − 14)
(N − 13)
(N − 12)
(N − 11)
D _D
_P
x
x + 1
D
x
D
x + 1
D
x
D
x + 1
D
x
D
x + 1
D
x
D
x + 1
D
x
D
x + 1
D _D
_M
x
x + 1
t
su
t
t
t
su h
h
t
PD
DAVP
DAVM
t
clk
005aaa061
Fig 5. LDVS DDR mode timing
ADC1610S_SER_2
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10.3 SPI timings
Table 9.
Symbol
tw(SCLK)
tw(SCLKH)
tw(SCLKL)
tsu
SPI timings characteristics
Parameter
Conditions
Min Typ
Max
Unit
ns
SCLK pulse width
SCLK HIGH pulse width
SCLK LOW pulse width
set-up time
40
16
16
5
-
-
-
-
-
-
-
-
-
-
ns
-
ns
data to SCLK HIGH
CS to SCLK HIGH
data to SCLK HIGH
CS to SCLK HIGH
-
ns
5
-
ns
th
hold time
2
-
ns
2
-
ns
fclk(max)
maximum clock frequency
-
25
MHz
[1] Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 °C and CL = 5 pF; minimum and maximum
values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDO = 1.8 V
t
t
w(SCLKL)
su
t
h
t
h
su
t
t
w(SCLKH)
t
w(SCLK)
CS
SCLK
SDIO
W1
W0
A12
A11
D2
D1
D0
R/W
005aaa065
Fig 6. SPI timing
ADC1610S_SER_2
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ADC1610S series
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ADC1610S series; CMOS or LVDS DDR digital output
11. Application information
11.1 Device control
The ADC1610S can be controlled via SPI or directly via the I/O pins (Pin control mode).
11.1.1 SPI and Pin control modes
The device enters Pin control mode at power-up, and remains in this mode as long as pin
CS is held HIGH. In Pin control mode, the SPI pins SDIO, CS and SCLK are used as
static control pins.
SPI control mode is enabled by forcing pin CS LOW. Once SPI control mode has been
enabled, the device will remain in this mode. The transition from Pin control mode to SPI
control mode is illustrated in Figure 7.
CS
Pin control mode
SPI control mode
SCLK/DFS
SDIO/ODS
Data format
offset binary
Data format
two's complement
LVDS DDR
R/W
W1
W0
A12
CMOS
005aaa039
Fig 7. Control mode selection
When the device enters SPI control mode, the output data standard and data format are
determined by the level on pin SDIO as soon as a transition is triggered by a falling edge
on CS.
11.1.2 Operating mode selection
The active ADC1610S operating mode (Power-up, Power-down or Sleep) can be selected
via the SPI interface (see Table 20) or using in Pin control mode, as described in Table 10.
Table 10. Operating mode selection pin PWD/OEB
Pin PWD/OEB
0
Power mode
Power-down
Sleep
Output high-z
yes
yes
yes
no
1/3 VCCA
2/3 VCCA
VCCA
Power-up
Power-up
11.1.3 Selecting the output data standard
The output data standard (CMOS or LVDS DDR) can be selected via the SPI interface
(see Table 23) or using pin ODS in Pin control mode. LVDS DDR is selected when ODS is
HIGH, otherwise CMOS is selected.
ADC1610S_SER_2
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ADC1610S series
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ADC1610S series; CMOS or LVDS DDR digital output
11.1.4 Selecting the output data format
The output data format can be selected via the SPI interface (offset binary, two’s
complement or gray code; see Table 23) or using pin DFS in Pin control mode (offset
binary or two’s complement). Offset binary is selected when DFS is LOW. When DFS is
HIGH, two’s complement is selected.
11.2 Analog inputs
11.2.1 Input stage
The analog input of the ADC1610S supports differential or single-ended input drive.
Optimal performance is achieved using differential inputs with the common-mode input
voltage (VI(cm)) on pins INP and INM set to 0.5VDDA
.
The full-scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p)
via a programmable internal reference (see Section 11.3 and Table 22 further details).
The equivalent circuit of the sample and hold input stage, including Electrostatic
Discharge (ESD) protection and circuit and package parasitics, is shown in Figure 8.
Package
ESD
Parasitics
Switch
R
= 15 Ω
on
4 pF
8
7
INP
INM
Sampling
capacitor
Internal
clock
Switch
R
= 15 Ω
on
4 pF
Sampling
capacitor
Internal
clock
005aaa043
Fig 8. Input sampling circuit
The sample phase occurs when the internal clock (derived from the clock signal on pin
CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the
clock signal goes LOW, the stage enters the hold phase and the voltage information is
transmitted to the ADC core.
ADC1610S_SER_2
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ADC1610S series
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ADC1610S series; CMOS or LVDS DDR digital output
11.2.2 Anti-kickback circuitry
Anti-kickback circuitry (R-C filter in Figure 9) is needed to counteract the effects of a
charge injection generated by the sampling capacitance.
The RC filter is also used to filter noise from the signal before it reaches the sampling
stage. The value of the capacitor should be chosen to maximize noise attenuation without
degrading the settling time excessively.
R
INP
C
R
INM
005aaa073
Fig 9. Anti-kickback circuit
The component values are determined by the input frequency and should be selected so
as not to affect the input bandwidth.
Table 11. RC coupling versus input frequency, typical values
Input frequency
3 MHz
Resistance
25 Ω
Capacitance
12 pF
70 MHz
12 Ω
8 pF
170 MHz
12 Ω
8 pF
11.2.3 Transformer
The configuration of the transformer circuit is determined by the input frequency. The
configuration shown in Figure 10 would be suitable for a baseband application.
ADT1-1WT
100 nF
25 Ω
INP
100 nF
Analog
input
25 Ω
12 pF
25 Ω
100 nF
25 Ω
100 nF
INM
VCM
100 nF
100 nF
005aaa044
Fig 10. Single transformer configuration suitable for baseband applications
ADC1610S_SER_2
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ADC1610S series
NXP Semiconductors
ADC1610S series; CMOS or LVDS DDR digital output
The configuration shown in Figure 11 is recommended for high frequency applications. In
both cases, the choice of transformer will be a compromise between cost and
performance.
ADT1-1WT
ADT1-1WT
12 Ω
12 Ω
INP
100 nF
50 Ω
50 Ω
50 Ω
50 Ω
Analog
input
8.2 pF
INM
100 nF
VCM
100 nF
100 nF
005aaa045
Fig 11. Dual transformer configuration suitable for high intermediate frequency
application
11.3 System reference and power management
11.3.1 Internal/external references
The ADC1610S has a stable and accurate built-in internal reference voltage to adjust the
ADC full-scale. This reference voltage can be set internally via SPI or with pins VREF and
SENSE (programmable in 1 dB steps between 0 dB and −6 dB via control bits
INTREF[2:0] when bit INTREF_EN = 1; see Table 22). See Figure 13, Figure 14,
Figure 15, Figure 16. The equivalent reference circuit is shown in Figure 12. External
reference is also possible by providing a voltage on pin VREF as described in Figure 15.
ADC1610S_SER_2
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ADC1610S series
NXP Semiconductors
ADC1610S series; CMOS or LVDS DDR digital output
REFT
REFERENCE
REFB
AMP
VREF
EXT_ref
EXT_ref
BANDGAP
REFERENCE
BUFFER
ADC CORE
SENSE
SELECTION
LOGIC
005aaa164
Fig 12. Reference equivalent schematic
If bit INTREF_EN is set to 0, the reference voltage will be determined either internally or
externally as detailed in Table 12.
Table 12. Reference selection
Selection
SPI bit
SENSE pin
VREF pin
full-scale (p-p)
INTREF_EN
internal
(Figure 13)
0
0
0
1
AGND
330 pF capacitor to AGND 2 V
internal
(Figure 14)
pin VREF connected to pin SENSE and via 1 V
a 330 pF capacitor to AGND
external
(Figure 15)
VDDA
external voltage between
0.5 V and 1 V[1]
1 V to 2 V
internal via SPI
(Figure 16)
pin VREF connected to pin SENSE and via 1 V to 2 V
330 pF capacitor to AGND
[1] The voltage on pin VREF is doubled internally to generate the internal reference voltage.
ADC1610S_SER_2
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ADC1610S series
NXP Semiconductors
ADC1610S series; CMOS or LVDS DDR digital output
VREF
VREF
330 pF
330
pF
REFERENCE
EQUIVALENT
SCHEMATIC
REFERENCE
EQUIVALENT
SCHEMATIC
SENSE
SENSE
005aaa116
005aaa117
Fig 13. Internal reference, 2 V (p-p) full scale
Fig 14. Internal reference, 1 V (p-p) full scale
VREF
VREF
0.1 μF
V
330 pF
REFERENCE
EQUIVALENT
SCHEMATIC
REFERENCE
EQUIVALENT
SCHEMATIC
SENSE
SENSE
VDDA
005aaa119
005aaa118
Fig 15. External reference, 1 V (p-p) to 2 V (p-p)
full-scale
Fig 16. Internal reference via SPI, 1 V (p-p) to 2 V (p-p)
full-scale
Figure 13 to Figure 16 illustrate how to connect the SENSE and VREF pins to select the
required reference voltage source.
11.3.2 Reference gain control
The reference gain is programmable between 0 dB to −6 dB in 1 dB steps via the SPI
(see Table 22). The corresponding full-scale input voltage range varies between 2 V (p-p)
and 1 V (p-p), as shown in Table 13:
Table 13. Reference SPI gain control
INTREF[2:0]
000
Gain (dB)
0 dB
Full-scale (V (p-p))
2 V
001
−1 dB
1.78 V
1.59 V
1.42 V
1.26 V
1.12 V
1 V
010
−2 dB
011
−3 dB
100
−4 dB
101
−5 dB
110
−6 dB
111
reserved
x
ADC1610S_SER_2
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ADC1610S series
NXP Semiconductors
ADC1610S series; CMOS or LVDS DDR digital output
11.3.3 Common-mode output voltage (VO(cm)
)
A 0.1 μF filter capacitor should be connected between pin VCM and ground to ensure a
low-noise common-mode output voltage. When AC-coupled, pin VCM can be used to set
the common-mode reference for the analog inputs, for instance via a transformer middle
point.
PACKAGE
ESD
PARASITICS
COMMON MODE
REFERENCE
1.5 V
VCM
0.1 μF
ADC CORE
005aaa051
Fig 17. Equivalent schematic of the common-mode reference circuit
11.3.4 Biasing
The common-mode input voltage (VI(cm)) on pins INP and INM should be set externally to
0.5VDDA for optimal performance and should always be between 0.9 V and 2 V.
11.4 Clock input
11.4.1 Drive modes
The ADC1610S can be driven differentially (SINE, LVPECL or LVDS) with little or no
degradation on dynamic performances. It can also be driven by a single-ended LVCMOS
signal connected to pin CLKP (CLKM should be connected to ground via a capacitor) or
CLKM (CLKP should be connected to ground via a capacitor).
CLKP
CLKM
LVCMOS
clock input
CLKP
CLKM
LVCMOS
clock input
005aaa174
005aaa053
a. Rising edge LVCMOS
b. Falling edge LVCMOS
Fig 18. LVCMOS single-ended clock input
ADC1610S_SER_2
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ADC1610S series
NXP Semiconductors
ADC1610S series; CMOS or LVDS DDR digital output
CLKP
CLKM
Sine
clock input
CLKP
CLKM
Sine
clock input
005aaa173
005aaa054
a. Sine clock input
b. Sine clock input (with transformer)
CLKP
CLKP
LVPECL
clock input
LVDS
clock input
CLKM
CLKM
005aaa055
005aaa172
c. LVDS clock input
d. LVPECL clock input
Fig 19. Differential clock input
11.4.2 Equivalent input circuit
The equivalent circuit of the input clock buffer is shown in Figure 21. The common-mode
voltage of the differential input stage is set via internal 5 kΩ resistors.
PACKAGE
ESD
PARASITICS
CLKP
CLKM
V
cm(clk)
SE_SEL SE_SEL
5 kΩ
5 kΩ
005aaa056
Fig 20. Equivalent input circuit
ADC1610S_SER_2
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ADC1610S series
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ADC1610S series; CMOS or LVDS DDR digital output
Single-ended or differential clock inputs can be selected via the SPI interface (see
Table 21). If single-ended is enabled, the input pin (CLKM or CLKP) is selected via control
bit SE_SEL.
If single-ended is implemented without setting SE_SEL to the appropriate value, the
unused pin should be connected to ground via a capacitor.
11.4.3 Duty cycle stabilizer
The duty cycle stabilizer can improve the overall performances of the ADC by
compensating the duty cycle of the input clock signal. When the duty cycle stabilizer is
active (bit DCS_EN = 1; see Table 21), the circuit can handle signals with duty cycles of
between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled
(DCS_EN = 0), the input clock signal should have a duty cycle of between 45 % and
55 %.
11.4.4 Clock input divider
The ADC1610S contains an input clock divider that divides the incoming clock by a factor
of 2 (when bit CLKDIV = 1; see Table 21). This feature allows the user to deliver a higher
clock frequency with better jitter performance, leading to a better SNR result once
acquisition has been performed.
11.5 Digital outputs
11.5.1 Digital output buffers: CMOS mode
The digital output buffers can be configured as CMOS by setting bit LVDS/CMOS to 0
(see Table 23).
Each digital output has a dedicated output buffer. The equivalent circuit of the CMOS
digital output buffer is shown in Figure 22. The buffer is powered by a separate power
supply, pins OGND and VDDO, to ensure 1.8 V to 3.3 V compatibility and is isolated from
the ADC core. Each buffer can be loaded by a maximum of 10 pF.
VDDO
PARASITICS
ESD
PACKAGE
50 Ω
Dx
LOGIC
DRIVER
AGND
005aaa122
Fig 21. CMOS digital output buffer
ADC1610S_SER_2
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ADC1610S series
NXP Semiconductors
ADC1610S series; CMOS or LVDS DDR digital output
The output resistance is 50 Ω and is the combination of the an internal resistor and the
equivalent output resistance of the buffer. There is no need for an external damping
resistor. The drive strength of both data and DAV buffers can be programmed via the SPI
in order to adjust the rise and fall times of the output digital signals (see Table 30):
11.5.2 Digital output buffers: LVDS DDR mode
The digital output buffers can be configured as LVDS DDR by setting bit LVDS/CMOS to 1
(see Table 23).
VCCO
3.5 mA
typ
−
+
D P/D
P
n
n + 1
RECEIVER
100 Ω
D M/D
n
M
n + 1
+
−
AGND
005aaa123
Fig 22. LVDS DDR digital output buffer - externally terminated
Each output should be terminated externally with a 100 Ω resistor (typical) at the receiver
side (Figure 23) or internally via SPI control bits LVDS_INT_TER[2:0] (see Figure 24 and
Table 32).
VCCO
3.5 mA
typ
−
+
D P/D
P
x
x + 1
RECEIVER
100 Ω
D M/D
x
M
x + 1
+
−
AGND
005aaa124
Fig 23. LVDS DDR digital output buffer - internally terminated
The default LVDS DDR output buffer current is set to 3.5 mA. It can be programmed via
the SPI (bits DAVI[1:0] and DATAI[1:0]; see Table 31) in order to adjust the output logic
voltage levels.
ADC1610S_SER_2
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ADC1610S series
NXP Semiconductors
ADC1610S series; CMOS or LVDS DDR digital output
Table 14. LVDS DDR output register 2
LVDS_INT_TER[1:0]
Resistor value (Ω)
000
001
010
011
100
101
110
111
no internal termination
300
180
110
150
100
81
60
11.5.3 Data valid (DAV) output clock
A data valid output clock signal (DAV) can be used to capture the data delivered by the
ADC1610S. Detailed timing diagrams for CMOS and LVDS DDR modes are shown in
Figure 4 and Figure 5 respectively.
11.5.4 Out-of-Range (OTR)
An out-of-range signal is provided on pin OTR. The latency of OTR is fourteen clock
cycles. The OTR response can be speeded up by enabling Fast OTR (bit FASTOTR = 1;
see Table 29). In this mode, the latency of OTR is reduced to only four clock cycles. The
Fast OTR detection threshold (below full-scale) can be programmed via bits
FASTOTR_DET[2:0].
Table 15. Fast OTR register
FASTOTR_DET[2:0]
Detection level (dB)
−20.56
000
001
010
011
100
101
110
111
−16.12
−11.02
−7.82
−5.49
−3.66
−2.14
−0.86
11.5.5 Digital offset
By default, the ADC1610S delivers output code that corresponds to the analog input.
However it is possible to add a digital offset to the output code via the SPI (bits
DIG_OFFSET[5:0]; see Table 25).
11.5.6 Test patterns
For test purposes, the ADC1610S can be configured to transmit one of a number of
predefined test patterns (via bits TESTPAT_SEL[2:0]; see Table 26). A custom test pattern
can be defined by the user (TESTPAT_USER; see Table 27 and Table 28) and is selected
when TESTPAT_SEL[2:0] = 101. The selected test pattern will be transmitted regardless
of the analog input.
ADC1610S_SER_2
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ADC1610S series
NXP Semiconductors
ADC1610S series; CMOS or LVDS DDR digital output
11.5.7 Output codes versus input voltage
Table 16. Output codes
VINP − VINM
< −1
Offset binary
Two’s complement
1000 0000 0000 0000
1000 0000 0000 0000
1000 0000 0000 0001
1000 0000 0000 0010
1000 0000 0000 0011
1000 0000 0000 0100
....
OTR pin
0000 0000 0000 0000
0000 0000 0000 0000
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
−1
−0.99996948 0000 0000 0000 0001
−0.99993896 0000 0000 0000 0010
−0.99990845 0000 0000 0000 0011
−0.99987793 0000 0000 0000 0100
....
....
−0.00006104 0111 1111 1111 1110
−0.00003052 0111 1111 1111 1111
1111 1111 1111 1110
1111 1111 1111 1111
0000 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0010
....
0
1000 0000 0000 0000
+0.00003052 1000 0000 0000 0001
+0.00006104 1000 0000 0000 0010
....
....
+0.99987793 1111 1111 1111 1011
+0.99990845 1111 1111 1111 1100
+0.99993896 1111 1111 1111 1101
+0.99996948 1111 1111 1111 1110
0111 1111 1111 1011
0111 1111 1111 1100
0111 1111 1111 1101
0111 1111 1111 1110
0111 1111 1111 1111
0111 1111 1111 1111
+1
1111 1111 1111 1111
1111 1111 1111 1111
> +1
11.6 Serial peripheral interface
11.6.1 Register description
The ADC1610S serial interface is a synchronous serial communications port that allows
for easy interfacing with many commonly-used microprocessors. It provides access to the
registers that control the operation of the chip.
This interface is configured as a 3-wire type (SDIO as bidirectional pin)
Pin SCLK is the serial clock input and CS is the chip select pin.
Each read/write operation is initiated by a LOW level on CS. A minimum of three bytes will
be transmitted (two instruction bytes and at least one data byte). The number of data
bytes is determined by the value of bits W1 and W2 (see Table 18).
Table 17. Instruction bytes for the SPI
MSB
LSB
0
Bit
7
6
5
4
3
2
1
Description
R/W[1]
A7
W1[2]
W0[2]
A12
A4
A11
A3
A10
A2
A9
A1
A8
A0
A6
A5
[1] Bit R/W indicates whether it is a read (1) or a write (0) operation.
[2] Bits W1 and W0 indicate the number of bytes to be transferred after the instruction byte (see Table 18).
ADC1610S_SER_2
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Table 18. Number of data bytes to be transferred after the instruction bytes
W1
0
W0
0
Number of bytes transmitted
1 byte
0
1
2 bytes
1
0
3 bytes
1
1
4 bytes or more
Bits A12 to A0 indicate the address of the register being accessed. In the case of a
multiple byte transfer, this address is the first register to be accessed. An address counter
is increased to access subsequent addresses.
The steps involved in a data transfer are as follows:
1. A falling edge on CS in combination with a rising edge on SCLK determine the start of
communications.
2. The first phase is the transfer of the 2-byte instruction.
3. The second phase is the transfer of the data which can vary in length but will always
be a multiple of 8 bits. The MSB is always sent first (for instruction and data bytes).
4. A rising edge on CS indicates the end on data transmission.
CS
SCLK
SDIO
W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
R/W
Instruction bytes
Register N (data)
Register N + 1 (data)
005aaa062
Fig 24. SPI mode timing
11.6.2 Default modes at start-up
During circuit initialization, it does not matter which output data standard has been
selected. At power-up, the device enters Pin control mode.
A falling edge on CS will trigger a transition to SPI control mode. When the ADC1610S
enters SPI control mode, the output data standard (CMOS/LVDS DDR) is determined by
the level on pin SDIO (see Figure 25). Once in SPI control mode, the output data standard
can be changed via bit LVDS/CMOS in Table 23.
When the ADC1610S enters SPI control mode, the output data format (two’s complement
or offset binary) is determined by the level on pin SCLK (gray code can only be selected
via the SPI). Once in SPI control mode, the output data format can be changed via bit
DATA_FORMAT[1:0] in Table 23.
ADC1610S_SER_2
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ADC1610S series
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ADC1610S series; CMOS or LVDS DDR digital output
CS
SCLK
(Data fo
rmat)
SDIO
(CMOS LVDS DDR)
Offset binary, LVDS DDR
005aaa063
default mode at start-up
Fig 25. Default mode at start-up: SCLK LOW = offset binary; SDIO HIGH = LVDS DDR
CS
SCLK
(Data fo
rmat)
SDIO
(CMOS LVDS DDR)
two's complement, CMOS
default mode at start-up
005aaa064
Fig 26. Default mode at start-up: SCLK HIGH = two’s complement; SDIO LOW = CMOS
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
11.6.3 Register allocation map
Table 19. Register allocation map
AddrHex Register name R/W Bit definition
Default
Bin
Bit 7
Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0005
0006
0008
0011
0012
0013
0014
0015
0016
0017
0020
0021
0022
Reset and
operating mode
R/W SW_RST
RESERVED[2:0]
-
-
OP_MODE[1:0]
0000
0000
Clock
R/W
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SE_SEL
DIFF_SE
-
CLKDIV DCS_EN 0000
0001
Internal reference R/W
-
INTREF_EN
OUTBUF
DAVINV
INTREF[2:0]
0000
0000
Output data
standard
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LVDS_CMOS
-
OUTBUS_SWAP DATA_FORMAT[1:0] 0000
0000
Output clock
DAVPHASE[2:0]
0000
1110
Offset
DIG_OFFSET[5:0]
-
0000
0000
Test pattern 1
Test pattern 2
Test pattern 3
Fast OTR
-
-
TESTPAT_SEL[2:0]
0000
0000
TESTPAT_USER[15:8]
0000
0000
TESTPAT_USER[7:0]
FASTOTR
0000
0000
-
-
-
-
-
-
-
-
-
-
-
FASTOTR_DET[2:0]
0000
0000
CMOS output
-
DAV_DRV[1:0]
DATAI_x2_EN
LVDS_INT_TER[2:0]
DATA_DRV[1:0]
0000
1110
LVDS DDR O/P 1 R/W
LVDS DDR O/P 2 R/W
DAVI_x2_EN
-
DAVI[1:0]
BIT_BYTE_WISE
DATAI[1:0]
0000
0000
-
0000
0000
ADC1610S series
NXP Semiconductors
ADC1610S series; CMOS or LVDS DDR digital output
Table 20. Reset and operating mode control register (address 0005h) bit description
Bit
Symbol
Access
Value
Description
7
SW_RST
R/W
reset digital section
no reset
0
1
performs a reset on SPI registers
reserved
6 to 4
3 to 2
1 to 0
RESERVED[2:0]
000
00
-
not used
OP_MODE[1:0]
R/W
operating mode
normal (power-up)
power-down
00
01
10
11
sleep
normal (power-up)
Table 21. Clock control register (address 0006h) bit description
Bit
7 to 5
4
Symbol
-
Access
Value
Description
000
not used
SE_SEL
R/W
single-ended clock input pin select
0
CLKM
1
CLKP
3
DIF_SE
R/W
differential/single ended clock input select
0
1
0
fully differential
single-ended
not used
2
1
-
CLKDIV
R/W
R/W
clock input divide by 2
disabled
0
1
enabled
0
DCS_EN
duty cycle stabilizer
disabled
0
1
enabled
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ADC1610S series; CMOS or LVDS DDR digital output
Table 22. Internal reference control register (address 0008h) bit description
Bit
7 to 4
3
Symbol
Access
Value
Description
-
0
not used
INTREF_EN
R/W
programmable internal reference enable
disable
0
1
active
2 to 0
INTREF[2:0]
R/W
programmable internal reference
0 dB (FS = 2 V)
000
001
010
011
100
101
110
111
−1 dB (FS = 1.78 V)
−2 dB (FS = 1.59 V)
−3 dB (FS = 1.42 V)
−4 dB (FS = 1.26 V)
−5 dB (FS = 1.12 V)
−6 dB (FS = 1 V)
reserved
Table 23. Output data standard control register (address 0011h) bit description
Bit
7 to 5
4
Symbol
Access
Value
Description
-
000
not used
LVDS_CMOS
R/W
output data standard: LVDS DDR or CMOS
CMOS
0
1
LVDS DDR
3
2
OUTBUF
R/W
output buffers enable
output enabled
0
1
0
0
1
output disabled (high Z)
outbus swapping
no swapping
OUTBUS_SWAP
output bus is swapping (MSB becomes LSB and vice
versa)
1 to 0
DATA_FORMAT[1:0]
R/W
output data format
offset binary
00
01
10
11
two’s complement
gray code
offset binary
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ADC1610S series; CMOS or LVDS DDR digital output
Table 24. Output clock register (address 0012h) bit description
Bit
7 to 4
3
Symbol
-
Access
Value
Description
0000
not used
DAVINV
R/W
output clock data valid (DAV) polarity
normal
0
1
inverted
2 to 0
DAVPHASE[2:0]
R/W
DAV phase select
000
001
010
011
100
101
110
111
output clock shifted (ahead) by 3 ns
output clock shifted (ahead) by 2.5 ns
output clock shifted (ahead) by 2 ns
output clock shifted (ahead) by 1.5 ns
output clock shifted (ahead) by 1 ns
output clock shifted (ahead) by 0.5 ns
default value as defined in timing section
output clock shifted (delayed) by 0.5 ns
Table 25. Offset register (address 0013h) bit description
Bit
Symbol
Access
Value
Description
7 to 6
5 to 0
-
00
not used
DIG_OFFSET[5:0]
R/W
digital offset adjustment
011111
...
+31 LSB
...
000000
...
0
...
100000
−32 LSB
Table 26. Test pattern register 1 (address 0014h) bit description
Bit
Symbol
Access
Value
Description
7 to 3
2 to 0
-
00000
not used
TESTPAT_SEL[2:0]
R/W
digital test pattern select
000
001
010
011
100
101
110
111
off
mid scale
−FS
+FS
toggle ‘1111..1111’/’0000..0000’
custom test pattern
‘1010..1010.’
‘010..1010’
Table 27. Test pattern register 2 (address 0015h) bit description
Bit
Symbol
Access
Value
Description
7 to 0
TESTPAT_USER[15:8]
R/W
00000000 custom digital test pattern (bits 13 to 6)
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Table 28. Test pattern register 3 (address 0016h) bit description
Bit
Symbol
Access
Value
Description
7 to 0
TESTPAT_USER[7:0]
R/W
00000000 custom digital test pattern (bits 7 to 0)
Table 29. Fast OTR register (address 0017h) bit description
Bit
7 to 4
3
Symbol
-
Access
Value
Description
not used
0000
FASTOTR
R/W
fast Out-of-Range (OTR) detection
disabled
0
1
enabled
2 to 0
FASTOTR_DET[2:0]
R/W
set fast OTR detect level
−20.56 dB
000
001
010
011
100
101
110
111
−16.12 dB
−11.02 dB
−7.82 dB
−5.49 dB
−3.66 dB
−2.14 dB
−0.86 dB
Table 30. CMOS output register (address 0020h) bit description
Bit
Symbol
Access
Value
Description
7 to 4
3 to 2
-
0000
not used
DAV_DRV[1:0]
R/W
drive strength for DAV CMOS output buffer
00
01
10
11
low
medium
high
very high
1 to 0
DATA_DRV[1:0]
R/W
drive strength for DATA CMOS output buffer
00
01
10
11
low
medium
high
very high
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Table 31. LVDS DDR output register 1 (address 0021h) bit description
Bit
7 to 6
5
Symbol
Access
Value
Description
-
00
not used
DAVI_x2_EN
R/W
double LVDS current for DAV LVDS buffer
0
disabled
1
enabled
4 to 3
DAVI[1:0]
R/W
LVDS current for DAV LVDS buffer
00
01
10
11
3.5 mA
4.5 mA
1.25 mA
2.5 mA
2
DATAI_x2_EN
DATAI[1:0]
R/W
R/W
double LVDS current for DATA LVDS buffer
0
disabled
1
enabled
1 to 0
LVDS current for DATA LVDS buffer
00
01
10
11
3.5 mA
4.5 mA
1.25 mA
2.5 mA
Table 32. LVDS DDR output register 2 (address 0022h) bit description
Bit
7 to 4
3
Symbol
Access
Value
Description
-
0000
not used
BIT_BYTE_WISE
R/W
DDR mode for LVDS output
0
bit wise (even data bits output on DAV rising edge/odd data
bits output on DAV falling edge)
1
byte wise (MSB data bits output on DAV rising edge/LSB data
bits output on DAV falling edge)
2 to 0
LVDS_INT_TER[2:0]
R/W
internal termination for LVDS buffer (DAV and DATA)
000
001
010
011
100
101
110
111
no internal termination
300 Ω
180 Ω
110 Ω
150 Ω
100 Ω
81 Ω
60 Ω
ADC1610S_SER_2
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12. Package outline
HVQFN40: plastic thermal enhanced very thin quad flat package; no leads;
40 terminals; body 6 x 6 x 0.85 mm
SOT618-6
D
B
A
terminal 1
index area
E
A
A
1
c
detail X
e
1
1/2 e
C
v
w
C A
C
B
e
b
y
1
y
C
11
20
L
21
10
e
E
h
e
2
1/2 e
1
30
terminal 1
index area
40
31
X
D
h
0
2.5
scale
5 mm
v
Dimensions
Unit
(1)
(1)
(1)
A
A
1
b
c
D
D
h
E
E
h
e
e
e
2
L
w
y
y
1
1
max 1.00 0.05 0.30
6.1 4.55 6.1 4.55
0.5
mm nom 0.85 0.02 0.21 0.2 6.0 4.40 6.0 4.40 0.5 4.5 4.5 0.4 0.1 0.05 0.05 0.1
min 0.80 0.00 0.18 5.9 4.25 5.9 4.25 0.3
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
sot618-6_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
- - -
09-02-23
09-03-04
SOT618-6
MO-220
Fig 27. Package outline SOT618-6 (HVQFN40)
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13. Revision history
Table 33. Revision history
Document ID
Release date
Data sheet status
Objective data sheet
Change Supersedes
notice
ADC1610S_SER_2
Modifications:
20100412
-
ADC1610S125_1
• Figure 12 “Reference equivalent schematic” has been updated
20090528 Objective data sheet
ADC1610S125_1
-
-
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14. Legal information
14.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
14.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
14.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
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ADC1610S series
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ADC1610S series; CMOS or LVDS DDR digital output
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
15. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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16. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
11.6.3
12
Register allocation map . . . . . . . . . . . . . . . . . 28
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 34
Revision history . . . . . . . . . . . . . . . . . . . . . . . 35
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
13
14
Legal information . . . . . . . . . . . . . . . . . . . . . . 36
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 36
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 37
14.1
14.2
14.3
14.4
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
15
16
Contact information . . . . . . . . . . . . . . . . . . . . 37
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7
8
9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal characteristics . . . . . . . . . . . . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
10
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Clock and digital output timing . . . . . . . . . . . . 11
SPI timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
10.1
10.2
10.3
11
11.1
Application information. . . . . . . . . . . . . . . . . . 14
Device control. . . . . . . . . . . . . . . . . . . . . . . . . 14
SPI and Pin control modes. . . . . . . . . . . . . . . 14
Operating mode selection. . . . . . . . . . . . . . . . 14
Selecting the output data standard. . . . . . . . . 14
Selecting the output data format. . . . . . . . . . . 15
Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 15
Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Anti-kickback circuitry . . . . . . . . . . . . . . . . . . . 16
Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . 16
System reference and power management . . 17
Internal/external references . . . . . . . . . . . . . . 17
Reference gain control . . . . . . . . . . . . . . . . . . 19
Common-mode output voltage (VO(cm)) . . . . . 20
Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Drive modes . . . . . . . . . . . . . . . . . . . . . . . . . 20
Equivalent input circuit . . . . . . . . . . . . . . . . . . 21
Duty cycle stabilizer . . . . . . . . . . . . . . . . . . . . 22
Clock input divider . . . . . . . . . . . . . . . . . . . . . 22
Digital outputs. . . . . . . . . . . . . . . . . . . . . . . . . 22
Digital output buffers: CMOS mode . . . . . . . . 22
Digital output buffers: LVDS DDR mode. . . . . 23
Data valid (DAV) output clock. . . . . . . . . . . . . 24
Out-of-Range (OTR). . . . . . . . . . . . . . . . . . . . 24
Digital offset . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Test patterns . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Output codes versus input voltage . . . . . . . . . 25
Serial peripheral interface. . . . . . . . . . . . . . . . 25
Register description . . . . . . . . . . . . . . . . . . . . 25
Default modes at start-up . . . . . . . . . . . . . . . . 26
11.1.1
11.1.2
11.1.3
11.1.4
11.2
11.2.1
11.2.2
11.2.3
11.3
11.3.1
11.3.2
11.3.3
11.3.4
11.4
11.4.1
11.4.2
11.4.3
11.4.4
11.5
11.5.1
11.5.2
11.5.3
11.5.4
11.5.5
11.5.6
11.5.7
11.6
11.6.1
11.6.2
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 12 April 2010
Document identifier: ADC1610S_SER_2
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