935268498518_技术文档

INTEGRATED CIRCUITS

SA8028

2.5 GHz sigma delta fractional-N /

760 MHz IF integer frequency synthesizers

Product data

2002 Feb 22

Supersedes data of 2002 Jan 09

File under Integrated Circuits — IC17

Philips

Semiconductors

Philips Semiconductors

Product data

2.5 GHz sigma delta fractional-N /

760 MHz IF integer frequency synthesizers

SA8028

GENERAL DESCRIPTION

APPLICATIONS

The SA8028 BICMOS device integrates programmable dividers,

charge pumps and phase comparators to implement phase–locked

loops. The device is designed to operate from 3 NiCd cells, in

pocket phones, with low current and nominal 3 V supplies.

• 500 to 2500 MHz wireless equipment

• Cellular phones, all standards including:

CDMA

3G

GSM

TDMA

GAIT

: IS95-B,C WCDMA

: WCDMA / UMTS

: EDGE / GPRS

: IS136 and EDGE

: GSM and TDMA

The synthesizer operates at VCO input frequencies up to 2.5 GHz.

The synthesizer has fully programmable RF, IF, and reference

dividers. All divider ratios are supplied via a 3-wire serial

programming bus. The RF divider is a fractional-N divider with

programmable integer ratios from 33 to 509 and a fractional

• WLAN

nd

resolution of 22 programmable bits (23 bits internal). A 2 order

• Wireless PDAs

sigma-delta modulator is used to achieve fractional division.

• Satellite tuners and all other high frequency equipment

• Extreme fine frequency resolution applications

Separate power and ground pins are provided to the charge pumps

and digital circuits. V

must be equal to or greater than V

.

DDCP

DD

The ground pins should be externally connected to prevent large

currents from flowing across the die and thus causing damage.

The charge pump current (gain) is fully programmable, while I

is

SET

set by an external resistance at the R

pin (refer to section 1.5,

SET

RF and IF Charge Pumps). The phase/frequency detector charge

pump outputs allow for implementing a passive loop filter.

24 23 22 21 20

1

19

V

DDPre

GND

FEATURES

• Extremely low phase noise:

18

17

16

15

14

2

3

4

5

6

CLOCK

REFin+

REFin–

GND

Pre

L

(f)

= –101 dBc/Hz at 5 kHz offset at 800 MHz

RFin+

RFin–

TOP VIEW

• Low power

R

SET

• Programmable Normal & Integral charge pump outputs:

Maximum output = 10.4 mA

GND

V

DDCP

CP

7

13

• Digital fractional spurious compensation

• Hardware and software power-down

N/C

8

9

10 11 12

• I

< 0.1 µA (typ) at V = 3.0 V

DD

DDsleep

• Seperate supply for V and V

DD

DDCP

SR02176

• Programmable loop filter bandwidth

Figure 1. HBCC24 pin configuration.

ORDERING INFORMATION

PACKAGE

NAME

TYPE NUMBER

DESCRIPTION

Plastic, heatsink bottom chip carrier; 24 terminals; body 4 x 4 x 0.65 mm (CSP package)

VERSION

SA8028W

HBCC24

SOT564-1

2

2002 Feb 22

853-2277 27777

Philips Semiconductors

Product data

2.5 GHz sigma delta fractional-N /

760 MHz IF integer frequency synthesizers

SA8028

QUICK REFERENCE DATA

V

= V = V

= +3.0 V, T

= +25°C; unless otherwise specified.

DDCP

DD

DDpre

amb

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

V

, V

Digital supply voltage

V

= V

DDpre

2.7

–

3.6

–

V

DD

DDpre

DD

Charge pump supply voltage

Total supply current

≥ V , V

DDpre

2.7

–

V

DDCP

DD

I

f

RF and IF. on

7.6

0.1

–

mA

DDtotal

Total supply current in power-down mode

VCO Input frequency range

Input frequency range

–

1

µA

DDsleep

RFin

500

100

5

2500

760

30

MHz

–

IFin

Crystal reference input frequency

Maximum phase comparator frequency

–

REFin

RF phase comparator;

max. limit is indicative

–

30

COMPMAX

T

amb

Operating ambient temperature

–40

–

+85

°C

3

2002 Feb 22

Philips Semiconductors

Product data

2.5 GHz sigma delta fractional-N /

760 MHz IF integer frequency synthesizers

SA8028

V

DDCP

DD

DDpre

24

1

14

18

22–BIT SHIFT

REGISTER

CLOCK

DATA

2–BIT SHIFT

REGISTER

PUMP

CURRENT

SETTING

19

15

PUMP

BIAS

CONTROL

LATCH

R

SET

20

ADDRESS DECODER

LOAD SIGNALS

STROBE

SIGMA-DELTA

RF DIVIDER

LATCH

4

5

RFin+

RFin–

7

8

PHP

PHI

PHASE

DETECTOR

LATCH

17

16

REFin+

REFin–

REF DIVIDER

2

2 2 2

22

10

LOCK

DETECT

SA

LOCK

PHA

LATCH

PHASE

DETECTOR

11

23

IFin

IF DIVIDER

21

PON

TEST

2

3

6, 9

GND

CP

Pre

SR02379

Figure 2. HBCC24 Block Diagram

HBCC24 PIN DESCRIPTION

SYMBOL

DESCRIPTION

SYMBOL

DESCRIPTION

Not connected

N/C

13

14

15

V

DDpre

1

Prescaler supply voltage

V

DDCP

Charge pump supply voltage; analog

GND

2

Ground; digital

R

External resistor from this pin to ground

sets the charge pump current

SET

3

Prescaler ground; analog

Input to RF divider (+)

Input to RF divider (–)

Charge pump ground; analog

RF normal charge pump output

RF integral charge pump output

Charge pump ground; analog

IF charge pump output

Input to IF divider

Pre

RFin+

RFin–

4

REFin–

REFin+

CLOCK

DATA

16

17

18

19

20

21

22

Input to reference (–)

5

Input to reference (+)

Programming bus clock input

Programming bus data input

Programming bus enable input

Power-down control input

Lock detect output

GND

PHP

PHI

6

CP

7

STROBE

PON

8

GND

PHA

IFin

9

CP

LOCK

10

11

12

TEST

23

Test (should be either grounded or

connected to V

)

DD

N/C

Not connected

V

DD

24

Supply; digital

4

2002 Feb 22

Philips Semiconductors

Product data

2.5 GHz sigma delta fractional-N /

760 MHz IF integer frequency synthesizers

SA8028

LIMITING VALUES

In accordance with the Absolute Maximum Rating System

SYMBOL

PARAMETER

MIN.

–0.3

MAX.

+3.6

+0.9

UNIT

V

Digital supply voltage

Charge pump supply voltage

Analog supply voltage

Difference in supply voltages

V

DD

DDCP

DDpre

∆V

DD

V

DDCP

– V

(V

DDCP

≥ V

, V

DD

)

DDpre

V

All input pins

–0.3

V

+ 0.3

V

n

DD

∆V

Difference in voltage between GND , GND and GND (these pins

+0.3

GND

pre

CP

should be connected together)

Storage temperature

T

–55

–40

+125

+85

°C

stg

T

amb

Operating ambient temperature

Maximum junction temperature

T

j

150

Handling

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal

precautions appropriate to handling MOS devices.

THERMAL CHARACTERISTICS

SYMBOL

PARAMETER

VALUE

UNIT

R

HBCC24: Thermal resistance from junction to ambient in still air

30

°C/W

th j–a

5

2002 Feb 22

Philips Semiconductors

Product data

2.5 GHz sigma delta fractional-N /

760 MHz IF integer frequency synthesizers

SA8028

CHARACTERISTICS

V

= V = V

= +3.0 V, T

= +25°C; unless otherwise specified.

DDCP

DD

DDpre

amb

SYMBOL

Supply

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

V

,

Digital supply voltage, prescaler supply voltage

V

= V

DDpre

2.7

–

3.6

V

DD

DDpre

V

DDCP

Charge pump supply voltage

≥ V

V

2.7

–

3.6

–

V

DDCP

DD, DDpre

I

Synthesizer operational total supply current

f

= 20 MHz

7.6

mA

DDTotal

REF

(with RF on, IF on)

(with RF on, IF off)

logic levels 0 or VDD

–

6.4

0.1

–

1

mA

I

Total supply current in power-down mode

µA

DDsleep

RF divider input

f

RF VCO input frequency range

AC-coupled input signal level

500

–15

–

2500

0

MHz

dBm

RFin

V

R (external) = R = 50 Ω;

in s

RFin

single-ended drive;

max. limit is indicative

@ 500 to 2500 MHz

112

–

632

mV

pp

Z

Input impedance Re (Z)

f

= 2.4 GHz

–

300

1

–

Ω

RFin

C

N

Typical pin input capacitance

RF divider ratio ranges

–

pF

RFin

Limited test coverage

RF phase comparator

33

–

509

30

RF

F

Maximum phase comparator frequency

–

MHz

COMPmax

IF divider input

f

Input frequency range

100

–15

–

760

0

MHz

dBm

IFin

V

AC-coupled input signal level

f : 100 MHz to 500 MHz

IFin

R

(external) = R = 50 Ω;

S

in

112

–10

200

–

632

0

mV

pp

max. limit is indicative

f

: 500 MHz to 760 MHz

dBm

IFin

R

(external) = R = 50 Ω;

S

in

632

mV

pp

max. limit is indicative

Z

Input impedance Re (Z)

Typical pin input capacitance

IF division ratio

f

= 500 MHz

–

3.9

0.5

–

kΩ

Fin

RFin

C

N

–

pF

Fin

IF

RFin

128

16383

Reference divider input

f

Input frequency range from TCXO

AC-coupled input signal level

5

–

30

MHz

REFin

V

single-ended drive;

360

1300

mV

REFin

PP

max. limit is indicative

Z

Input impedance Re (Z)

Typical pin input capacitance

Reference division ratio

f

= 20 MHz

–

4

10

1

–

kΩ

REFin

REF

C

R

–

pF

REFin

REF

SA = ”000”, IF loop

–

1023

Charge pump current setting resistor input

R

External resistor from pin to ground

Regulated voltage at pin

6

–

7.5

15

–

kΩ

SET

V

R

= 7.5 kΩ

1.22

V

SET

Charge pump outputs; R

= 7.5 kΩ

SET

1

I

Charge pump current ratio to I

Current gain = I /I

–15

–10

0.6

–

+15

+10

%

nA

V

CP

SET

PH SET

= 1/2 V

DDCP

Sink-to-source current matching

Output current variation versus V

Charge pump off leakage current

V

PH

V

PH

V

PH

MATCH

ZOUT

LPH

2

in compliance range

= 1/2 V

PH

DDCP

V

Charge pump voltage compliance

V

DDCP

–0.7

PH

6

2002 Feb 22

Philips Semiconductors

Product data

2.5 GHz sigma delta fractional-N /

760 MHz IF integer frequency synthesizers

SA8028

SYMBOL

PARAMETER

CONDITIONS

= 7.5 kΩ, CP = 00, non speed-up mode)

MIN.

TYP.

MAX.

UNIT

Phase noise (condition R

SET

Synthesizer’s contribution to close-in phase

noise of 900 MHz RF signal at 5 kHz offset.

f

= 13 MHz, TCXO,

–

–99

–

dBc/Hz

L_(f)

REF

= 13 MHz

COMP

indicative, not tested

Synthesizer’s contribution to close-in phase

noise of 1800 MHz RF signal at 5 kHz offset.

As above

–

–93

–

dBc/Hz

Synthesizer’s contribution to close-in phase

noise of 800 MHz RF signal at 5 kHz offset.

f

= 19.44/19.68 MHz, TCXO,

–101

REF

f

= 19.44/19.68 MHz

COMP

indicative, not tested

Synthesizer’s contribution to close-in phase

noise of 2100 MHz RF signal at 5 kHz offset.

As above

–

–93

–

dBc/Hz

Interface logic input signal levels

V

HIGH level input voltage

LOW level input voltage

Input leakage current

0.7*V

–0.3

–0.5

–

V

+0.3

V

IH

IL

DD

0.3*V

+0.5

V

DD

I

V

= 3 V, V = 3 V,

= 0 V

µA

LEAK

DD

IH

IL

Lock detect output signal (in push/pull mode) and Data output signal (in readout test mode)

V

LOW level output voltage

HIGH level output voltage

I

= 2 mA

–

0.4

–

V

OL

sink

source

= –2 mA

V

–0.4

OH

DD

NOTES:

V_SET

I

SET

1.

=

bias current for charge pumps.

R_SET

2. The relative output current variation is defined as:

∆I_ZOUT

( I

| I

I ₁

)

–

+

2

=

2

×

;

I_ZOUT

|

With I @ V = 0.6 V, I @V = V

– 0.7 V (see Figure 3).

1

2

DDCP

CURRENT

I

ZOUT

2

I

1

VOLTAGE

V

1

V

2

V

PH

I

2

I

1

SR00602

Figure 3. Relative output current variation.

7

2002 Feb 22

Philips Semiconductors

Product data

2.5 GHz sigma delta fractional-N /

760 MHz IF integer frequency synthesizers

SA8028

During each RF divider cycle, one divider output pulse is generated.

The positive edge of this pulse drives the phase comparator, the

negative edge drives the sigma-delta modulator which is of 2

order and has an effective resolution of 22 bits. Internally, the

modulator works with 23 fractional bits K<22:0>, but the LSB (bit K0)

is set to ‘1’ internally to avoid limit cycles (cycles of less than

maximum length). This leaves 22 bits (K<22:1>) available for

external programming.

1.0 FUNCTIONAL DESCRIPTION

Frequency synthesizers, such as Philips Semiconductors’ SA8028,

are a crucial part of Phase Locked Loops (PLL) for both voice and

data devices used in communications. Five components make up

the basic PLL (see Figure 4). A very stable, low frequency, signal

source (typically a temperature controlled crystal oscillator TCXO_)

is used as a reference to the system. A second signal source

(typically a VCO) is used to generate the desired output frequency.

A phase/frequency detector (PFD) is used to compare the

phase/frequency error between the two signals. A loop filter (LPF)

rejects undesired noise while also integrating the PFD output current

to drive the VCO with the necessary tuning voltage, and a divider in

the feedback path is used to down-convert the VCO output

nd

Under these conditions (2 order modulator, 23 fractional bits,

23

K0 = ‘1’), all possible sigma-delta sequences are 2*2 divider

cycles long, which is the maximum length. The noise shaping

characteristic is +20 dB/dec for offset frequencies up to approx.

f

/5, which needs to be cancelled by a closed-loop transfer

COMP

frequency to the reference frequency for comparison. The SA8028

is a dual synthesizer that integrates programmable dividers,

programmable charge pumps and phase comparators to be

implemented as part of RF and IF PLLs. The RF synthesizer

operates at VCO input frequencies up to 2.5 GHz, while the IF

synthesizer operates at VCO input frequencies up to 760 MHz.

function of sufficient high order. The output of the sigma-delta

modulator is 2 bits, which are added to the integer RF division ratio

N, such that the momentary division ratios range from

(N–1) to (N+2) in steps of 1.

1.2 IF divider

The IFin input drives a pre-amplifier to provide the clock to the first

divider stage. The pre-amplifier has a high input impedance,

dominated by pin and pad capacitance. The divider consists of a

fully programmable bipolar prescaler followed by a CMOS counter.

The allowable divide ratios are from 128 to 16383 (C-word bits

<21:8>). Table 14 shows all the possible values that can be

programmed into the C-Word for the IF divider.

LPF

TCXO

VCO

PFD

Φ

INTEGRATOR

1

+ ∆N(τ)

1.3 Reference divider (see Figure 5)

N

DIVIDER

The IF phase detector’s reference input is an integer ratio of the

reference frequency. The reference divider chain consists of a

bipolar input buffer followed by a CMOS divider and a 3-bit binary

counter (SA register). The allowable divide ratios, R, are from 4 to

1023 (B-word bits <21:12>) when the 3-bit binary counter (C-word

bits <2:0>) is set to all zeros, SA = 000. The 3-bit SA register

determines which of the 5 divider outputs (refer to Table 12) is

selected as the IF phase detector input (see Figure 5). For the RF

synthesizer, the output of the reference input buffer is routed directly

(not reference divider) to the input of the RF phase detector.

SR02370

Figure 4. PLL block diagram.

1.1 RF Fractional-N divider

The RFin inputs drive a pre-amplifier to provide the clock to the first

divider stage. For single ended operation, the signal should be fed

(AC-coupled) to one of the inputs while the other one is AC grounded.

The pre-amplifier has a high input impedance, dominated by pin and

pad capacitance. The bipolar divider is fully programmable. For

allowable division ratios, see the “characteristics” table.

TO RF PHASE

DETECTOR

REFERENCE

INPUT BUFFER

REFERENCE

INPUT

DIVIDE BY R

/2

SA=”100”

SA=”011”

SA=”010”

SA=”001”

SA=”000”

TO IF PHASE

DETECTOR

SR02294

Figure 5. Reference divider.

8

2002 Feb 22

Philips Semiconductors

Product data

2.5 GHz sigma delta fractional-N /

760 MHz IF integer frequency synthesizers

SA8028

1.4 Phase detector (see Figure 6)

The reference signal and the RF (IF) divider output are connected to a phase frequency detector that controls the charge pumps. The dead

zone (caused by the finite time taken to switch the charge pump current sources on or off) is cancelled by forcing the pumps ON for a minimum

time (backlash time, τ) at every cycle providing improved linearity.

V

DDCP

P

P–TYPE

CHARGE PUMP

D

Q

“1”

* see note

f

CLK

REF

R

I

τ

PH

“1”

D

IF/RF

DIVIDER

CLK

N–TYPE

CHARGE PUMP

X

N

Q

GND

CP

f

REF

R

X

P

N

τ

I

PH

SR02413

NOTES:

For the RF synthesizer, the output of the reference input buffer is routed directly (not divided) to the input of the RF phase detector. Whereas

for the IF synthesizer, the reference input to the IF phase detector is the output from the reference divider.

τ (backlash time) is the delay that fixes the minimum allowable charge pump activity time.

Figure 6. Phase detector structure with timing.

9

2002 Feb 22

Philips Semiconductors

Product data

2.5 GHz sigma delta fractional-N /

760 MHz IF integer frequency synthesizers

SA8028

1.5 RF and IF Charge Pumps

The RF phase detector drives the charge pumps on the PHP and

PHI pins, while the IF phase detector drives the charge pump on the

PHA pin. Both the RF and IF charge pump current values are

determined by the current generated at the R

1.7 Lock Detect

The output LOCK maintains a logic ‘1’ when the IF phase detector

(AND/ORed) with the RF phase detector indicates a lock condition.

The lock condition for the RF and IF synthesizers is defined as a

phase difference of less than "1 period of the frequency at the input

1

pin . The current

SET

REF

REF . One counter can fulfill the lock condition when the

gain can be further programmed by the CP0, CP1 bits in the C-word,

as seen in Table 1.

in+,

in–

other counter is powered down. Out of lock (logic ‘0’) is indicated

when both counters are powered down.

Table 1. RF and IF charge pump currents

1.8 Power-down mode

2

3

CP1

CP0

I

PHI

With power applied to the chip, power-down mode can be entered

either by hardware (external signal on pin PON) or by software (by

programming the PD = Power Down bits (<B10, B9>) in the B-word).

The PON signal is exclusively ORed with the PD bits. If PON = 0,

then the part is powered up when PD = 1 (<B10, B9>). PON can be

used to invert the polarity of the software bits PD. Table 9 of section

2.4.2 illustrates how power-down mode can be implemented.

PHA

PHP

PHP–SU

0

1

0

1

0

1

1.5xl

0.5xl

1.5xl

0.5xl

3xI

1xl

3xl

1xl

15xl

36xl

12xl

0

SET

5xl

SET

15xl

5xl

SET

0

SET

NOTES

1. I

During power-down mode the 3-wire bus remains active and

programming-words may be pre-loaded before switching to

power-up mode. If the chip is programmed while in power-down

= V

/R

bias current for charge pumps.

SET

SET SET:

2. CP1 = 1 is used to disable the PHI pump.

3. I is the total current at pin PHP during speed up condition.

PHP–SU

mode, the RF divider ratio N is internally presented to the RF

RF

1.6 Charge Pumps Speed-up Mode

divider on the next falling edge of STROBE after STROBE has gone

high at the end of the A-word. Power-down mode does not reset the

sigma-delta modulator., i.e., power-down mode preserves the state

of the sigma-delta modulator (as long as power is applied to the

chip).

The RF charge pumps will enter speed-up mode when STROBE

goes high after A-word has been sent. They will exit speed-up mode

on the next falling edge of STROBE. There is no speed-up mode for

the IF charge pump.

The charge pump, by default, will automatically go into speed-up

To take advantage of the register pre-loading capability while the

device is in power-down mode, the B-word needs to be sent a

second time (i.e., again, after the A-word), with the PD (<B10, B9>)

bits now programmed for power-up.

mode (which can deliver up to 15*I

for PHP_SU, and 36*I

for

SET

PHI), based on the strobe pulse width following the A-word to

reduce switching speed for large tuning voltage steps (i.e., large

frequency steps). Figure 7 shows the recommended passive loop

filter configuration. Note: This charge pump architecture eliminates

the need for added active switches and reduces external component

count. Furthermore, the programmable charge pump gains provide

some programmability to the loop filter bandwidth.

If power-up mode is to be controlled by hardware, the PON signal

must be toggled only after the A-word has been sent and STROBE

has gone high and then low.

When the synthesizer is reactivated after power-down mode, the IF

and reference dividers are synchronized to avoid random phase

errors on power-up. There is no power-up synchronization between

the RF divider and the reference clock. After power-up, there is a

delay of four edges (i.e. 1.5 cycles) of the output clock of the

reference divider before the RF phase detector is activated. That

means the reference divider must be powered up for the RF phase

detector to become active.

The duration of speed-up mode is determined by the strobe pulse

that follows the A-word. Recommended optimal strobe width is equal

to the total loop filter capacitance charge time from VCO control

voltage level 1 to VCO control voltage level 2. The strobe width must

not exceed this charge time. An external data processing unit

controls the width of the strobe pulse (e.g., × number of clock

cycles).

When initially applying or reapplying power to the chip, and internal

power-up reset pulse is generated which sets the programming-words

to their default values and also resets the sigma-delta modulator to

its “all-0” state. It is also recommended that the D-word be manually

reset to all zeros, following initial power-up, to avoid unknown states.

In addition, charge pumps will stay in speed-up mode continuously

while Tspu = 1 (in D-word <D15>). The speed-up mode can also be

disabled by programming T

= 1 (in D-word <D16>).

dis-spu

R2

VCO

PHP[PHP–SU]

R1

C2

C3

PHI

C1

SR02356

Figure 7. Typical passive 3-pole loop filter.

10

2002 Feb 22

Philips Semiconductors

Product data

2.5 GHz sigma delta fractional-N /

760 MHz IF integer frequency synthesizers

SA8028

When loading several words in series, the minimum STROBE high

time between words must be observed (refer to Figure 8).

2.0 SERIAL PROGRAMMING BUS

A simple 3-line bidirectional serial bus is used to program the circuit.

The 3 lines are DATA, CLOCK and STROBE. When the STROBE = 0,

the clock driver is enabled and on the positive edges of the CLOCK

signal, DATA is clocked into temporary shift registers. When the

STROBE = 1, the clock is disabled and the data in the shift register

is latched into different working registers, depending on the address

bits. In order to fully program the circuit, 3 words must be sent in the

following order: C, B, and A. An additional word, the D-word, is for

test purposes only: all bits in this test word should be initialized to 0

for normal operation. The N value of the B-word is stored temporarily

until the A-word is loaded to avoid temporarily false N settings, while

the corresponding fractional ratio Kn is not yet active. When a new

fractional ratio is loaded through the A-word, the fractional sigma

delta modulator is not reset, i.e., it will start the new fractional

sequence from the last state of the previously executed sequence. A

typical programming sequence is illustrated in Figure 10.

Unlike the earlier SA80xx family members, SA8028 has the built-in

feature to output the contents of an addressable internal register.

For the current SA8028, only the momentary division ratio N (RF

divider) can be retrieved through the serial bus. The handshake

protocol requires a “request to read” to be sent prior to each “read”,

i.e., by sending a D-word with the TreadN-bit (<D11>) set to “high”.

Immediately after the transition of “STROBE” from low-to-high,

four (4) clock pulses are needed to prepare the data for output and

another nine (9) clock pulses are needed to accomplish the serial

reading with LSB first. A high-to-low transition of “STROBE” then

resets the serial bus to the input mode. The timing diagram is

presented in Figure 9. In general, a high-to-low transition of the

“STROBE” signal will instantaneously reset the serial bus to the

input mode, even when the chip is in the output mode.

Table 2. Serial bus timing requirements (see Figures 8 and 9)

V

DD

= V

=+3.0 V; T

= +25 °C unless otherwise specified. (Guaranteed by design.)

DDCP

amb

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

Serial programming clock; CLK

t

Input rise time

Input fall time

Clock period

–

10

–

40

–

ns

r

–

f

T

100

cy

Enable programming; STROBE

t

Delay to rising clock edge

40

–

ns

START, START;R

Minimum inactive pulse width

Enable set-up time to next clock edge

Reset data line to input mode

1/f

20

W

COMP

SU;E

RESET

Register serial input data; DATA (I)

t

Input data to clock set-up time

Input data to clock hold time

20

–

ns

SU;DAT

HD;DAT

Register serial output data; DATA (O)

t

Input clock to data set-up time

20

–

ns

SU;DAT;R

t

f

t

r

t

T

HD;DAT

SU;E

CY

t

SU;DAT

CLK

LSB

MSB

ADDRESS

DATA

>=0

STROBE

t

W

t

START

SR02296

Figure 8. Serial bus “Write” timing diagram.

11

2002 Feb 22

Philips Semiconductors

Product data

2.5 GHz sigma delta fractional-N /

760 MHz IF integer frequency synthesizers

SA8028

T

cy

t

r

t

f

t

RESET

SU:DAT;R

CLK

1

2

3

4

5

6

7

8

9

10

11

12

13

LSB

MSB

DATA

I

O

I

DEVICE I/O:

STROBE

t

START;R

SR02372

Figure 9. Serial bus “Read” timing diagram.

12

2002 Feb 22

Philips Semiconductors

Product data

2.5 GHz sigma delta fractional-N /

760 MHz IF integer frequency synthesizers

SA8028

POWER–ON

PROGRAM D WORD

SET DEFAULT

–

PROGRAM C WORD

–

SELECT SA

SET CHARGE PUMP GAIN

SET IF DIVIDER

SELECT LOCK DETECT

PROGRAM B WORD

–

SET RF DIVIDER N

SET POWER-UP OPTION

SET REF DIVIDER

SET RESET-BITS

PROGRAM A WORD

–

SET FRACTIONAL VALUE K

READY TO OPERATE

CHANGE

FRACTIONAL

VALUE K

Y

PROGRAM A WORD

N

Y

CHANGE

RF DIVIDER N

N

CHANGE

IF

FREQUENCY

Y

PROGRAM C WORD

PROGRAM B WORD

N

POWER

DOWN

N

POWER

UP

N

POWER

OFF

SR02380

Figure 10. Typical programming sequence

13

2002 Feb 22

Philips Semiconductors

Product data

2.5 GHz sigma delta fractional-N /

760 MHz IF integer frequency synthesizers

SA8028

2.1 Data format

Each of the 4 word registers contains 24 programmable bits. Data is serially clocked in on the rising edge of each clock pulse with the

LSB first in, and MSB last in.

Table 3. Format of programmed data

LAST IN

MSB

SERIAL PROGRAMMING FORMAT

FIRST IN

LSB

p23

p22

p21

p20

.. / ..

p1

p0

2.2 Register addressing

Table 4. Register addressing

Bit

<23>

<22>

<21>

A-word address

B-word address

C-word address

D-word address

0

1

0

1

0

1

x

0

Notice that the register addresses are the MSB in each word; thus, the last to be clocked into the registers.

2.3 A-word register

Table 5. A-word, length 24 bits

Last IN

<21> <20> <19> <18> <17> <16> <15> <14> <13> <12> <11> <10> <9>

<8>

<7>

<6>

<5>

<4>

<3>

<2>

<1>

<0>

Address Fractional ratio Kn

0

K22 K21 K20 K19 K18 K17 K16 K15 K14 K13 K12 K11 K10 K9

K8

K7

K6

K5

K4

K3

K2

K1

Default :

A word address

Fractional ratio select

0

1

0

1

0

1

0

1

0

1

0

1

Fixed to 00.

Kn sets the fractional part of the total division ratio. To avoid limit cycles the K0 bit is internally set to “1”

2.3.1 The fractional multiplier <A21:A0>

The A-word register is dedicated for programming the RF loop, fractional multiplier (the sigma-delta modulator) which has an effective resolution

of 22 bits. The modulator works with 23 bits, Kn<22:0>. However, this K0 bit is set to ‘1’ internally to avoid limit cycles (cycles of less than

maximum length). This leaves 22 bits (Kn<22:1>) available for external programming. Refer to Table 6.

Calculating the desired VCO output frequency can be easily accomplished by using the following equation, Equation (1).

ǒ

^{2 Kn <22:1> ) 1}Ǔ

f

_VCO+ f_refN )

(1)

2²³

where f is the reference frequency at the REF input pin and N is the integer multiplier. K , once again, is the fractional multiplier.

ref

n

Example:

Determine the Kn value required for generating a VCO frequency of 2100 MHz with a reference frequency of 19.68 MHz.

ǒ^fVCOǓ

23

ƪ

ƫ

–N 2

f

ref

Kn<22:1> +

2

ƪǒ^{2100 MHz}

Ǔ

23

ƫ

_{19.68 MHz}–106 2

+ 2966702

2

14

2002 Feb 22

Philips Semiconductors

Product data

2.5 GHz sigma delta fractional-N /

760 MHz IF integer frequency synthesizers

SA8028

Table 6. Kn values for the fractional divider

A21

A20

A19

A18

A17

A16

A15

A14

A13

A12

0

A11

0

A10

0

A9

0

–

0

–

1

A8

0

–

0

–

1

A7

0

–

1

–

1

A6

0

–

0

–

1

A5

0

–

1

–

1

A4

0

–

0

–

1

A3

0

–

1

–

1

A2

0

1

–

1

–

1

A1

0

1

0

–

1

–

1

A0

1

0

1

0

–

0

–

0

1

Kn

0

1

0

2

0

3

4

0

–

…

1

0

1

0

1

0

1

0

1

2966702

…

–

1

4194302

4194303

1

2.4 B-word register

Table 7. B-word, length 24 bits

Last IN

<21> <20> <19> <18> <17> <16> <15> <14> <13> <12>

<11>

<10>

<9>

<8> <7> <6> <5> <4> <3> <2> <1> <0>

Reset Power Down

bit

Address

Reference divider ratio Rn

RF Divider integer ratio N

0

1

R9

R8

R7

R6

R5

R4

R3

R2

R1

R0

PDref

IF

RF

N8 N7 N6 N5 N4 N3 N2 N1 N0

Default:

0

1

0

1

0

1

0

1

0

1

0

1

0

B-word address

R-Divider

Fixed to 01

R0..R9, Reference divider values, see section “characteristics” for allowed divider ratios.

1 → Pdref : powers down (=resets) the reference divider

See Truth Table 9

Reset bit

Power-down

N-Divider

Nn sets the integer part of the RF divider ratio, see section “characteristics” for allowed ratios.

2.4.1 The RF divider <B8:B0>

Programming the RF divider to obtain the desired VCO output frequency is done by programming the B-word followed by the A-word. The

integer divider bits N<8:0> are in the B-word, whereas the fractional divider bits Kn<22:1> are in the A-word. Allowable integer division ratios are

shown in Table 8. The N value, from Equation (2), is simply the whole number of times the reference frequency goes into the desired VCO

output frequency. Recall that the reference frequency for the RF loop is not reduced prior to the phase detector. In other words, the frequency at

the input of the REFin is the comparison frequency.

f

ǒ Ǔ

VCO

MODULO

f

ref

f_VCO

N +

*

(2)

f_ref

900 MHz

ǒ

_{19.68 MHz}Ǔ

MODULO

900 MHz

19.68 MHz

*

19.68 MHz

14.4

+ 45

19.68

N + 45.7317073170...–

15

2002 Feb 22

Philips Semiconductors

Product data

2.5 GHz sigma delta fractional-N /

760 MHz IF integer frequency synthesizers

SA8028

Table 8. Allowable integer values (N) for the RF divider

<B8>

<B7>

<B6>

<B5>

<B4>

<B3>

0

<B2>

0

<B1>

0

<B0>

1

N

33

…

0

1

0

—

1

—

1

—

1

—

1

—

1

—

1

—

1

—

0

—

1

…

509

2.4.2 Power–down <B10:B9>

If the chip is programmed while in power-up mode, the loading of the A-word and of the N values in the B-word are synchronized to the RF

divider output pulse. The data takes effect internally on the second falling edge of the RF divider output pulse after STROBE has gone high at

the end of the A-word. STROBE does not need to be held high until that second falling edge of the RF divider output pulse has occurred.

If the chip is programmed while in power-down mode, this synchronization scheme is disabled. The fully static CMOS design uses virtually no

current when the bus is inactive. It can always capture new programmed data, even during power-down.

To take advantage of the program register pre-loading capability while the device is in power-down mode, the B-word needs to be sent a second

time (i.e. again, after the A-word), with the PD bits now programmed for power-up. If power-up mode is to be controlled by hardware, the PON

signal must be toggled only after the A-word has been sent and STROBE has gone high and then low.

When the synthesizer is reactivated after power-down mode, the IF and reference dividers are synchronized to avoid random phase errors on

power-up. There is no power-up synchronization between the RF divider and the reference clock. However, after power-up, there is a delay of

four edges (i.e. 1.5 cycles) of the output clock of the reference divider before the RF phase detector is activated. That means the reference

divider must be powered up for the RF phase detector to become active.

When initially applying or re-applying power to the chip, an internal power-up reset pulse is generated which sets the programming-words to

their default values and also resets the sigma-delta modulator to its “all-0” state. It is also recommended that the D-word be manually reset to all

zeros, following initial power-up, to avoid unknown states.

Table 9. Power-down Truth Table

PON

IF

RF

IF

RF

<B10>

<B9>

0

1

0

1

0

1

0

1

0

1

0

1

0

1

OFF

ON

OFF

ON

OFF

ON

OFF

ON

OFF

16

2002 Feb 22

Philips Semiconductors

Product data

2.5 GHz sigma delta fractional-N /

760 MHz IF integer frequency synthesizers

SA8028

2.4.3 Programming the IF Reference Divider <B21:B12>

The IF phase detector’s reference input is an integer multiple of the frequency at the input of the REFin pin. The reference divider has 10

programmable bits, <B21:B12> for allowable divide ratios, R, from 4 to 1023 when the 3 bit binary SA counter (refer to section 2.5.1) is set to all

zeros. Table 10 lists the allowable R values.

Table 10. R Values for the IF Reference Divider

<B21>

<B20>

<B19>

<B18>

<B17>

<B16>

<B15>

<B14>

<B13>

<B12>

R

4

0

1

0

1

5

0

1

0

6

—

1

—

1

—

1

—

1

—

1

—

1

—

1

—

1

—

1

—

0

…

1022

1023

1

2.5 C-word Register

Table 11. C-word, length 24 bits

<21>

<20>

<19> <18> <17> <16> <15> <14> <13> <12> <11> <10>

<9>

<8>

<7>

<6>

<5>

<4>

<3>

<2>

<1>

<0>

Last IN

Address

IF Divider An

CP

Lock detect

Reset

bit

SA

1

0

A13 A12 A11 A10 A9

A8

1

A7

1

A6

1

A5

0

A4

0

A3

1

A2

0

A1

1

A0 CP1 CP0

L1

0

L0

0

Tsigrst SA2 SA1 SA0

Default:

0

1

0

C-word address

A-Divider

Fixed to 10

A0..A13, IF divider values , see section “characteristics for allowed for divider ratios.

CP1, CP0: Charge pump current ratio, see table of charge pump currents.

Charge pump current

Ratio

Lock detect

Reset bit

See Table 13.

1 → Tsigrst : resets the sigma-delta modulator after each loading of an A-word.

( It is held in the reset state between the first and second falling edge of the RF divider output pulse

after STROBE has gone high at the end of the A-word. )

IF comparison select

SA Comparison divider select for IF phase detector

2.5.1 Programming the SA Counter <C2:C0>

The 3 bit SA register determines which of the 5 divider outputs (refer to table 11) is selected as the IF phase detector’s input (see Figure 5).

Table 12. IF phase comparator frequency

<C2> <C1> <C0> Divide Ratio IF Phase Comparator Frequency

1

0

1

0

1

0

1

0

R

f

/ R

ref

R * 2

R * 4

R * 8

R * 16

f

/ (R * 2)

/ (R * 4)

/ (R * 8)

/ (R * 16)

ref

1

f

ref

NOTES:

1. f is the input frequency at the REFin pin.

ref

2.5.2 Programming the Reset Bits <B11>, <C3>

The reset bits offer extra flexibility. The default value for bits <B11>, <C3> are all zeros. Bit <B11> disables the IF reference divider and allows

for extra savings of approximately 200 µA when set to ‘1’. However, this bit must initially be set to ‘0’ during any power-up sequence. The RF

phase detector is activated after a delay of four edges of the reference divider output clock. Bit <C3> resets the sigma-delta modulator after

each loading of an A-word. It is held in the reset state between the first and second falling edge of the RF divider output pulse after STROBE

has gone high at the end of the A-word.

17

2002 Feb 22

Philips Semiconductors

Product data

2.5 GHz sigma delta fractional-N /

760 MHz IF integer frequency synthesizers

SA8028

2.5.3 Programming the Lock Detect <C4:C5>

Lock detection is available only for the RF and IF phase detector. A ‘0’ in bit <C4:C5> is used for TTL, while a ‘1’ in bit <C4:C5> is used for RTL.

Table 13. Lock detect select

L1

0

L0

0

Select

1

RF/IF (push/pull)

0

1

RF/IF (open drain)

RF (push/pull)

IF (push/pull)

1

0

1

NOTE:

1. Combined RF_IF lock detect signal present at the lock pin (push/pull).

2.5.4 Programming the Charge Pump Gain <C7:C6>

The RF phase detector drives the charge pumps on the PHP and PHI pins, while the IF phase detector drives the charge pump on the PHA pin.

The current generated at the R

pin determines both the RF and IF charge pump current values in conjunction with the current gain

SET

programmed by the CP0, CP1 bits in the C–word, as seen in Table 1. For more information on charge pump speed-up mode, refer to section

1.6.

2.5.5 Programming the IF Divider for the IF Loop <C21:C8>

The divider is a fully programmable counter. The allowable divide ratios, A, are from 128 to 16383, bits <C21:C8>. Table 14 shows all the

possible values that can be programmed into the C-word for the IF divider.

Table 14. Allowable Values (A) for the IF Divider

C21

0

C20

0

C19

0

C18

0

C17

0

C16

0

C15

1

C14

0

C13

0

C12

0

C11

0

C10

0

C9

0

C8

0

A

128

0

1

0

1

129

0

1

0

1

0

130

—

1

—

1

—

1

—

1

—

1

—

1

—

1

—

1

—

1

—

1

—

1

—

1

—

1

—

0

…

16382

16383

1

2.6 D-word Register

The D-word is for test purposes only. All bits in this test word should be initialized to 0 for normal operation. When initially applying or

re-applying power to the chip, an internal power-up reset pulse if generated which sets the programming-words to their default values and which

resets the sigma-delta modulator to its “all-0” state. It is also recommended that the D-word be manually reset to all zeros, following initial

power-up, to avoid unknown states.

Table 15. D-word, length 24 bits

<21> <20> <19> <18> <17>

<16>

<15>

<14> <13> <12>

<11>

<10>

<9>

<8>

<7>

<6>

<5>

<4>

<3>

<2>

<1>

<0>

Last IN

Address

1

Synthesizer Test bits

1

0

–

Tdis-spu Tspu

–

TreadN

0

–

Default

0

D word address

Tdis-spu

Fixed to 110.

Speed-up mode disabled.

Speed-up mode always on. NOTE: All other test bits must be set to 0 for normal operation.

NOTE: All other test bits must be set to 0 for normal operation.

Tspu: Speed up

TreadN

Used to “request to read” bit settings from bits <B21:12>. For more information on reading out the N value,

refer to Section 2.0, Serial Programming Bus.

18

2002 Feb 22

Philips Semiconductors

Product data

2.5 GHz sigma delta fractional-N /

760 MHz IF integer frequency synthesizers

SA8028

3.0 Typical Performance Characteristics

2500

2000

1500

1000

500

3000

Iset = 204 µA

2000

Iset = 163 µA

1000

–40C

+25C

+85C

Iset = 81 µA

Icp

(µA)

Icp

0

(µA)

–500

–1000

–1500

–2000

–2500

Iset = 81 µA

–1000

–2000

–3000

Iset = 163 µA

Iset = 204 µA

COMPLIANCE VOLTAGE (V)

SR02389

SR02414

Figure 11. PHI_SU charge pump output vs. Iset

(CP = 01_12x, V = 3.0 V, Temp = 25 °C)

Figure 12. PHI_SU charge pump output vs. temperature

(CP = 01_12x, V = 3.0 V, Iset = 163 µA)

DD

8000

6000

4000

8000

6000

Iset = 204 µA

Iset = 163 µA

Iset = 81 µA

4000

2000

–40C

2000

0

+25C

+85C

Icp

(µA)

0

Icp

(µA)

Iset = 81 µA

–2000

–4000

–6000

–8000

Iset = 163 µA

Iset = 204 µA

–4000

–6000

–8000

COMPLIANCE VOLTAGE (V)

SR02390

SR02391

Figure 13. PHI_SU charge pump output vs. Iset

(CP = 00_36x, V = 3.0 V, Temp = 25 °C)

Figure 14. PHI_SU charge pump output vs. temperature

(CP = 00_36x, V = 3.0 V, Iset = 163 µA)

DD

19

2002 Feb 22

Philips Semiconductors

Product data

2.5 GHz sigma delta fractional-N /

760 MHz IF integer frequency synthesizers

SA8028

800

600

400

200

0

Iset = 204 µA

600

400

Iset = 163 µA

200

Iset = 81 µA

Icp

–40C

(µA)

0

–200

–400

–600

–800

Icp

(µA)

+25C

+85C

Iset = 81 µA

–200

Iset = 163 µA

–400

–600

Iset = 204 µA

COMPLIANCE VOLTAGE (V)

SR02393

SR02392

Figure 15. PHP charge pump output vs. Iset

(CP = 10_3x, V = 3.0 V, Temp = 25 °C)

Figure 16. PHP charge pump output vs. temperature

(CP = 10_3x, V = 3.0 V, Iset = 163 µA)

DD

250

200

150

100

50

Iset = 204 µA

200

150

100

50

Iset = 163 µA

Iset = 81 µA

–40C

Icp

(µA)

0

+25C

+85C

Icp

(µA)

0

–50

–100

–150

–200

–250

Iset = 81 µA

–50

–100

–150

–200

Iset = 163 µA

Iset = 204 µA

COMPLIANCE VOLTAGE (V)

SR02394

SR02395

Figure 17. PHP charge pump output vs. Iset

(CP = 11_1x, V = 3.0 V, Temp = 25 °C)

Figure 18. PHP charge pump output vs. temperature

(CP = 11_1x, V = 3.0 V, Iset = 163 µA)

DD

20

2002 Feb 22

Philips Semiconductors

Product data

2.5 GHz sigma delta fractional-N /

760 MHz IF integer frequency synthesizers

SA8028

1000

800

600

400

200

1200

1000

Iset = 204 µA

800

600

400

200

Iset = 163 µA

Iset = 81 µA

–40C

+25C

+85C

Icp

(µA)

Icp

(µA)

0

–200

–400

–600

–800

–1000

–200

Iset = 81 µA

–400

–600

Iset = 163 µA

–800

–1000

–1200

Iset = 204 µA

COMPLIANCE VOLTAGE (V)

SR02397

SR02396

Figure 19. PHP_SU charge pump output vs. Iset

(CP = 01_5x, V = 3.0 V, Temp = 25 °C)

Figure 20. PHP_SU charge pump output vs. temperature

(CP = 01_5x, V = 3.0 V, Iset = 163 µA)

DD

3000

4000

3000

2000

1000

Iset = 204 µA

2000

1000

Iset = 163 µA

Iset = 81 µA

–40C

+25C

+85C

Icp

(µA)

Icp

(µA)

0

Iset = 81 µA

–1000

–2000

–3000

–4000

–1000

–2000

–3000

Iset = 163 µA

Iset = 204 µA

COMPLIANCE VOLTAGE (V)

SR02398

SR02399

Figure 21. PHP_SU charge pump output vs. Iset

(CP = 00_15x, V = 3.0 V, Temp = 25 °C)

Figure 22. PHP_SU charge pump output vs. temperature

(CP = 00_15x, V = 3.0 V, Iset = 163 µA)

DD

21

2002 Feb 22

Philips Semiconductors

Product data

2.5 GHz sigma delta fractional-N /

760 MHz IF integer frequency synthesizers

SA8028

150

100

80

60

40

Iset = 204 µA

100

Iset = 163 µA

50

–40C

20

+25C

+85C

Iset = 81 µA

Icp

(µA)

Icp

(µA)

0

Iset = 81 µA

–20

–40

–50

–100

–150

Iset = 163 µA

–60

–80

Iset = 204 µA

–100

COMPLIANCE VOLTAGE (V)

SR02401

SR02400

Figure 23. PHA charge pump output vs. Iset

Figure 24. PHA charge pump output vs. temperature

(CP = 11_0.5x, V = 3.0 V, Temp = 25 °C)

(CP = 11_0.5x, V = 3.0 V, Iset = 163 µA)

DD

400

300

200

100

300

200

Iset = 204 µA

Iset = 163 µA

Iset = 81 µA

100

–40C

Icp

(µA)

+25C

+85C

0

Icp

(µA)

0

Iset = 81 µA

–100

–200

–300

–400

–100

Iset = 163 µA

–200

–300

Iset = 204 µA

COMPLIANCE VOLTAGE (V)

SR02403

SR02402

Figure 25. PHA charge pump output vs. Iset

(CP = 10_1.5x, V = 3.0 V, Temp = 25 °C)

Figure 26. PHA charge pump output vs. temperature

(CP = 10_1.5x, V = 3.0 V, Iset = 163 µA)

DD

22

2002 Feb 22

Philips Semiconductors

Product data

2.5 GHz sigma delta fractional-N /

760 MHz IF integer frequency synthesizers

SA8028

0

–3

0

–40C

25C

85C

2.7V

3.0V

3.6V

–3

–6

–9

–12

–15

–18

–21

–24

–27

–30

–33

–12

–15

–18

–21

–24

–27

–30

–33

–36

–39

–42

–45

–48

–36

–39

–42

–45

–48

SR02405

INPUT FREQUENCY (MHz)

SR02404

INPUT FREQUENCY (MHz)

Figure 27. RF (main) divider input sensitivity vs. frequency

and supply voltage (Temp = 25 °C, Iset = 164 µA, N = 509)

Figure 28. RF (main) divider input sensitivity vs. frequency

and temperature (V = 3.0 V, Iset = 164 µA, N = 509)

CC

0

2.7V

0

–3

–40C

25C

–3

–6

–9

3.0V

–6

–9

–12

–15

–18

–21

–24

–27

–30

–33

–36

–39

–42

–45

–48

3.6V

–12

–15

–18

–21

–24

–27

–30

–33

–36

–39

–42

–45

–48

85C

SR02407

SR02406

INPUT FREQUENCY (MHz)

Figure 29. RF (main) fractional divider input sensitivity vs.

frequency and supply voltage (Temp = 25 °C, Iset = 164 µA,

N = 509.5)

Figure 30. RF (main) fractional divider input sensitivity

vs. frequency and temperature (V = 3.0 V, Iset = 164 µA,

CC

N = 509.5)

0

–40C

2.7V

3.0V

3.6V

–3

–6

–3

–6

25C

85C

–9

–12

–15

–18

–21

–24

–27

–30

–33

–36

–39

–42

–45

–12

–15

–18

–21

–24

–27

–30

–33

–36

–39

–42

–45

INPUT FREQUENCY (MHz)

SR02408

INPUT FREQUENCY (MHz)

SR02409

Figure 31. IF (aux) divider input sensitivity vs. frequency and

supply voltage (Temp = 25 °C, Iset = 164 µA,

divider ratio = 16383)

Figure 32. IF (aux) divider input sensitivity vs. frequency and

temperature (V = 3.0 V, Iset = 164 µA, divider ratio = 16383)

CC

23

2002 Feb 22

Philips Semiconductors

Product data

2.5 GHz sigma delta fractional-N /

760 MHz IF integer frequency synthesizers

SA8028

0

–40C

25C

2.7V

3.0V

3.6V

–2

–4

–6

–8

–10

–12

–14

–16

–18

–20

–22

–24

–26

–28

–30

–32

–34

–36

–38

–40

–10

–12

85C

–14

–16

–18

–20

–22

–24

–26

–28

–30

–32

–34

–36

–38

–40

INPUT FREQUENCY (MHz)

SR02411

INPUT FREQUENCY (MHz)

SR02410

Figure 33. Reference divider input sensitivity vs. frequency

and supply voltage (Temp = 25 °C, Iset = 164 µA,

divider ratio = 1023)

Figure 34. Reference divider input sensitivity vs. frequency

and temperature (V = 3.0 V, Iset = 164 µA, divider ratio = 1023)

CC

9.00

8.50

8.00

7.50

–40C

7.00

25C

85C

6.50

6.00

2.6

2.8

3

3.2

3.4

3.6

3.8

SUPPLY VOLTAGE (V)

SR02412

Figure 35. Total supply current vs. temperature

(Iset = 163 µA Fcomp = 20 MHz)

24

2002 Feb 22

Philips Semiconductors

Product data

2.5 GHz sigma delta fractional-N /

760 MHz IF integer frequency synthesizers

SA8028

4.0 Application Schematic

25

2002 Feb 22

Philips Semiconductors

Product data

2.5 GHz sigma delta fractional-N /

760 MHz IF integer frequency synthesizers

SA8028

HBCC24: plastic, heatsink bottom chip carrier; 24 terminals; body 4 x 4 x 0.65 mm

SOT564-1

26

2002 Feb 22

Philips Semiconductors

Product data

2.5 GHz sigma delta fractional-N /

760 MHz IF integer frequency synthesizers

SA8028

NOTES

27

2002 Feb 22

Philips Semiconductors

Product data

2.5 GHz sigma delta fractional-N /

760 MHz IF integer frequency synthesizers

SA8028

Data sheet status

Product

status

Definitions

[1]

Data sheet status

[2]

Objective data

Development

This data sheet contains data from the objective specification for product development.

Philips Semiconductors reserves the right to change the specification in any manner without notice.

Preliminary data

Product data

Qualification

Production

This data sheet contains data from the preliminary specification. Supplementary data will be

published at a later date. Philips Semiconductors reserves the right to change the specification

without notice, in order to improve the design and supply the best possible product.

This data sheet contains data from the product specification. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply.

Changes will be communicated according to the Customer Product/Process Change Notification

(CPCN) procedure SNW-SQ-650A.

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL

http://www.semiconductors.philips.com.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or

at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended

periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips

Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or

modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications

do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard

cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless

otherwise specified.

Koninklijke Philips Electronics N.V. 2002

Contact information

For additional information please visit

http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

Date of release: 02-02

9397 750 09499

For sales offices addresses send e-mail to:

sales.addresses@www.semiconductors.philips.com.

Document order number:

Philips

Semiconductors

28

2002 Feb 22


型号：	935268498518
厂家：	NXP
描述：	IC PLL FREQUENCY SYNTHESIZER, 2500 MHz, PBCC24, 4 X 4 MM, 0.65 MM HEIGHT, PLASTIC, HBCC-24, PLL or Frequency Synthesis Circuit
文件：	总28页 (文件大小：278K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

935268498518 [NXP]

相关型号：

935268565112

935268565118

935268595115

935268595125

935268595165

935268596115

935268596118

935268596125

935268596165

935268625518

935268625551

935268635118