935265482118 [NXP]
IC LVC/LCX/Z SERIES, HEX 1-INPUT NON-INVERT GATE, PDSO14, 4.40 MM, PLASTIC, MO-153, SOT-402-1, TSSOP-14, Gate;
| 型号： | 935265482118 |
| 厂家： | 
NXP |
| 描述： | IC LVC/LCX/Z SERIES, HEX 1-INPUT NON-INVERT GATE, PDSO14, 4.40 MM, PLASTIC, MO-153, SOT-402-1, TSSOP-14, Gate 栅 输入元件 光电二极管 逻辑集成电路 |
| 文件： | 总19页 (文件大小：149K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74LVC07A
Hex buffer with open-drain outputs
Product specification
2003 Feb 25
Supersedes data of 2000 Mar 07
Philips Semiconductors
Product specification
Hex buffer with open-drain outputs
74LVC07A
FEATURES
DESCRIPTION
• 5 V tolerant inputs and outputs (open drain) for
interfacing with 5 V logic
The 74LVC07A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families. Inputs can be
driven from either 3.3 or 5 V devices. This feature allows
the use of these devices as translators in a mixed
3.3 to 5 V environment.
• Wide supply voltage range from 1.65 to 5.5 V
• CMOS low power consumption
• Direct interface with TTL levels
• Inputs accept voltages up to 5 V
The 74LVC07A provides six non-inverting buffers.
• Complies with JEDEC standard no. 8-1A
The outputs of the 74LVC07A are open drain and can be
connected to other open-drain outputs to implement
active-LOW wired-OR or active-HIGH wired-AND
functions.
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns.
SYMBOL
PLZ/tPZL
CI
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
propagation delay nA to nY
input capacitance
CL = 50 pF; VCC = 3.3 V
2.2
5.0
6.0
ns
pF
pF
CPD
power dissipation capacitance per gate VI = GND to VCC; note 1
Note
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
FUNCTION TABLE
See note 1.
INPUT
OUTPUT
nA
L
nY
L
H
Z
Note
1. H = HIGH voltage level;
L = LOW voltage level;
Z = high-impedance OFF-state.
2003 Feb 25
2
Philips Semiconductors
Product specification
Hex buffer with open-drain outputs
74LVC07A
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
TEMPERATURE RANGE
PINS
PACKAGE
MATERIAL
CODE
74LVC07AD
74LVC07APW
74LVC07ABQ
−40 to +85 °C
−40 to +85 °C
−40 to +85 °C
14
14
14
SO14
plastic
plastic
plastic
SOT108-1
SOT402-1
SOT762-1
TSSOP14
DHVQFN14
PINNING
PIN
SYMBOL
DESCRIPTION
1
2
1A
1Y
2A
2Y
3A
3Y
GND
4Y
4A
5Y
5A
6Y
6A
VCC
data input
data output
data input
3
4
data output
data input
5
6
data output
ground (0 V)
data output
data input
7
8
9
10
11
12
13
14
data output
data input
data output
data input
supply voltage
V
1A
1
handbook, halfpage
CC
14
handbook, halfpage
1A
1Y
2A
2Y
3A
3Y
1
2
3
4
5
6
7
14 V
CC
1Y
2A
2
3
13 6A
12 6Y
13 6A
12 6Y
11 5A
10 5Y
(1)
2Y
3A
3Y
4
5
6
GND
11 5A
10 5Y
07
9
8
4A
4Y
9
4A
GND
7
8
MNA531
GND 4Y
Top view
MBL760
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
Fig.1 Pin configuration SO14 and TSSOP14.
Fig.2 Pin configuration DHVQFN14.
2003 Feb 25
3
Philips Semiconductors
Product specification
Hex buffer with open-drain outputs
74LVC07A
handbook, halfpage
handbook, halfpage
1
1
1
1
1
1
1
2
1
3
5
9
1A
2A
3A
4A
1Y
2Y
3Y
4Y
2
4
6
8
1A
2A
3A
4A
5A
6A
1Y
3
4
2Y
5
6
3Y
9
8
4Y
11 5A
13 6A
5Y 10
6Y 12
11
13
10
5Y
12
6Y
MNA535
MNA534
Fig.3 Logic symbol.
Fig.4 IEC logic symbol.
Y
handbook, halfpage
A
GND
MNA533
Fig.5 Logic diagram (one gate).
2003 Feb 25
4
Philips Semiconductors
Product specification
Hex buffer with open-drain outputs
74LVC07A
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
1.65
MAX.
5.5
UNIT
VCC
VI
V
V
V
V
input voltage
0
5.5
5.5
5.5
+85
20
VO
output voltage
active mode
0
high-impedance mode
0
Tamb
tr, tf
operating ambient temperature
input rise and fall ratios
−40
0
°C
VCC = 1.65 to 2.7 V
ns/V
ns/V
V
CC = 2.7 to 5.5 V
0
10
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
−0.5
MAX.
+6.5
UNIT
VCC
IIK
V
input diode current
input voltage
VI < 0
note 1
VO < 0
−
−50
mA
V
VI
−0.5
−
+6.5
−50
IOK
VO
output clamping diode current
output voltage
mA
V
active mode; note 1
−0.5
+6.5
+6.5
50
high-impedance mode; note 1 −0.5
V
IO
output source or sink current
VCC or GND current
storage temperature
power dissipation
VO = 0 to VCC
−
mA
mA
°C
mW
I
CC, IGND
−
±100
+150
500
Tstg
Ptot
−65
−
Tamb = −40 to +125 °C; note 2
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO14 packages: above 70 °C derate linearly with 8 mW/K.
For TSSOP14 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60 °C derate linearly with 4.5 mW/K.
2003 Feb 25
5
Philips Semiconductors
Product specification
Hex buffer with open-drain outputs
74LVC07A
DC CHARACTERISTICS
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.(1)
MAX.
UNIT
OTHER
VCC (V)
Tamb = −40 to +85 °C
VIH HIGH-level input voltage
1.65 to 1.95 VCC
−
−
−
−
−
−
−
−
−
−
−
−
V
2.3 to 2.7
2.7 to 3.6
4.5 to 5.5
1.7
V
V
V
V
V
V
V
2.0
0.7 × VCC
VIL
LOW-level input voltage
LOW-level output voltage
1.65 to 1.95 −
GND
0.7
2.3 to 2.7
2.7 to 3.6
4.5 to 5.5
−
−
−
0.8
0.30 × VCC
VOL
VI = VIH or VIL
IO = 100 µA
IO = 4 mA
1.65 to 5.5
1.65
−
−
−
−
−
−
−
−
−
0.20
0.45
0.3
V
−
V
IO = 8 mA
2.3
−
V
IO = 12 mA
IO = 24 mA
IO = 32 mA
VI = 5.5 V or GND
2.7
−
0.4
V
3.0
−
0.55
0.55
±5
V
4.5
−
V
ILI
input leakage current
output leakage current
1.65 to 5.5
1.65 to 5.5
±0.1
0.1
µA
µA
IOZ
VI = VIH;
±10
VO = 5.5 V or GND
Ioff
power-off leakage current
quiescent supply current
VI or VO = 5.5 V
0.0
5.5
−
−
±0.1
±10
µA
µA
ICC
VI = VCC or GND;
IO = 0
0.1
10
∆ICC
additional quiescent supply VI = VCC − 0.6 V;
current per input pin IO = 0
2.3 to 5.5
−
5
500
µA
Note
1. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
2003 Feb 25
6
Philips Semiconductors
Product specification
Hex buffer with open-drain outputs
74LVC07A
AC CHARACTERISTICS
GND = 0 V; tr = tf ≤ 2 ns for VCC ≤ 2.7 V; and tr = tf ≤ 2.5 ns for VCC ≥ 2.7 V.
TEST CONDITIONS
SYMBOL
PARAMETER
MIN. TYP.(1) MAX.
UNIT
WAVEFORMS
VCC (V)
Tamb = −40 to +85 °C
tPLZ/tPZL
propagation delay nA to nY see Figs 6 and 7
1.65 to 1.95
2.3 to 2.7
2.7
−
2.5
1.6
2.4
2.2
1.6
−
ns
0.5
0.5
0.5
0.5
2.8
3.3
3.6
2.6
ns
ns
ns
ns
3.0 to 3.6
4.5 to 5.5
Note
1. All typical values are measured at Tamb = 25 °C and at VCC = 1.8, 2.5, 2.7, 3.3 and 5.0 V, respectively.
AC WAVEFORMS
V
I
V
nA input
M
GND
t
t
PZL
PLZ
V
CC
nY output
V
M
V
V
X
OL
MNA528
VCC
VM
VX
<2.7 V
0.5 × VCC
1.5 V
VOL + 0.15 V
VOL + 0.3 V
VOL + 0.3 V
≥2.7 to 3.6 V
≥4.5 to 5.5 V
0.5 × VCC
Fig.6 The input nA to output nY propagation delays.
2003 Feb 25
7
Philips Semiconductors
Product specification
Hex buffer with open-drain outputs
74LVC07A
V
ext
V
CC
R
L
V
I
V
O
PULSE
GENERATOR
D.U.T.
R
C
R
L
L
T
MNA530
VCC
Vext
VI
CL
30 pF
RL
1 kΩ
1.65 to 1.95 V
2.3 to 2.7 V
2.7 V
2 × VCC
2 × VCC
6 V
VCC
VCC
30 pF
50 pF
50 pF
50 pF
500 Ω
500 Ω
500 Ω
500 Ω
2.7 V
2.7 V
VCC
3.3 to 3.6 V
4.5 to 5.5 V
6 V
2 × VCC
Definitions for test circuits:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.7 Load circuitry for switching times.
2003 Feb 25
8
Philips Semiconductors
Product specification
Hex buffer with open-drain outputs
74LVC07A
PACKAGE OUTLINES
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
7
e
detail X
w
M
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.75
1.27
0.05
1.05
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches
0.041
0.01 0.004
0.069
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT108-1
076E06
MS-012
2003 Feb 25
9
Philips Semiconductors
Product specification
Hex buffer with open-drain outputs
74LVC07A
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
7
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.72
0.38
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT402-1
MO-153
2003 Feb 25
10
Philips Semiconductors
Product specification
Hex buffer with open-drain outputs
74LVC07A
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
SOT762-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
6
L
1
7
8
E
h
e
14
13
9
D
h
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
1
y
D
D
E
L
v
w
y
1
h
h
1
max.
0.05 0.30
0.00 0.18
3.1
2.9
1.65
1.35
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT762-1
- - -
MO-241
- - -
2003 Feb 25
11
Philips Semiconductors
Product specification
Hex buffer with open-drain outputs
74LVC07A
SOLDERING
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferably be kept:
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
• below 220 °C for all the BGA packages and packages
with a thickness ≥ 2.5mm and packages with a
thickness <2.5 mm and a volume ≥350 mm3 so called
thick/large packages
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
• below 235 °C for packages with a thickness <2.5 mm
and a volume <350 mm3 so called small/thin packages.
Wave soldering
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
2003 Feb 25
12
Philips Semiconductors
Product specification
Hex buffer with open-drain outputs
74LVC07A
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE(1)
WAVE
not suitable
REFLOW(2)
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA
suitable
DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP,
HTSSOP, HVQFN, HVSON, SMS
not suitable(3)
suitable
PLCC(4), SO, SOJ
suitable
suitable
LQFP, QFP, TQFP
not recommended(4)(5) suitable
not recommended(6)
suitable
SSOP, TSSOP, VSO, VSSOP
Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2003 Feb 25
13
Philips Semiconductors
Product specification
Hex buffer with open-drain outputs
74LVC07A
DATA SHEET STATUS
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
LEVEL
DEFINITION
I
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information
Applications that are
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
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described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2003 Feb 25
14
Philips Semiconductors
Product specification
Hex buffer with open-drain outputs
74LVC07A
NOTES
2003 Feb 25
15
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Contact information
For additional information please visit http://www.semiconductors.philips.com.
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© Koninklijke Philips Electronics N.V. 2003
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Printed in The Netherlands
613508/02/pp16
Date of release: 2003 Feb 25
Document order number: 9397 750 10531
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74LVC07A; Hex
buffer with open-
drain outputs
download datasheet
Download datasheet
Products
General description
Features
Datasheet
Applications
Buy online
Parametrics
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General description
The 74LVC07A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced
CMOS compatible TTL families. Inputs can be driven from either 3.3 or 5 V devices. This feature allows the use of
these devices as translators in a mixed 3.3 to 5 V environment.
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System
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The 74LVC07A provides six non-inverting buffers.
End of Life
information
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Here!
•
•
The outputs of the 74LVC07A are open drain and can be connected to other open-drain outputs to implement active-
LOW wired-OR or active-HIGH wired-AND functions.
Models
•
•
SoC solutions
Features
●
●
●
●
●
●
●
5 V tolerant inputs and outputs (open drain) for interfacing with 5 V logic
Wide supply voltage range from 1.65 to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Complies with JEDEC standard no. 8-1A
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
Datasheet
Type number Title
Publication release Datasheet status
date
Page
count
File size Datasheet
(kB)
74LVC07A Hex buffer
with open-
2/25/2003
Product specification 16
86
Download
drain outputs
Parametrics
Type number Package
Description Propagation Voltage No. Power
Logic
Output
Delay(ns)
of Dissipation
Pins Considerations Levels
Switching Drive
Capability
Hex Buffer
with Open-
Drain
Low Power or
14 Battery
SOT108-1
74LVC07AD
4~6
Low
Low
TTL
TTL
Medium
(SO14)
Applications
Outputs
Hex Buffer
with Open-
Drain
Low Power or
14 Battery
Applications
SOT402-1
74LVC07APW
4~6
Medium
(TSSOP14)
Outputs
Products, packages, availability and ordering
Type number North
Ordering code Marking/Packing Package Device
Buy online
IC packing info
American type (12NC)
status
number
SOT108-1
(SO14)
Standard Marking
* Tube
Full production
Full production
74LVC07AD 74LVC07AD 9352 654 81112
Standard Marking
9352 654 81118 * Reel Pack,
SOT108-1
(SO14)
74LVC07AD-
T
SMD, 13"
SOT402-1
Standard Marking
* Tube
Full production
Full production
74LVC07APW 74LVC07APW 9352 654 82112
(TSSOP14)
Standard Marking
SMD, 13"
SOT402-1
74LVC07APW-
9352 654 82118 * Reel Pack,
(TSSOP14)
T
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or related to the type number(s) as listed on this page. The similar products page includes products from the same
catalog tree(s), relevant selection guides and products from the same functional category.
Support & tools
Innovative Low Voltage Logic Solutions(date 01-Aug-00)
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