935264186118 [NXP]

IC AHC SERIES, 8-INPUT NAND GATE, PDSO14, SOT-108-1, SO-14, Gate;
935264186118
型号: 935264186118
厂家: NXP    NXP
描述:

IC AHC SERIES, 8-INPUT NAND GATE, PDSO14, SOT-108-1, SO-14, Gate

栅 输入元件 光电二极管 逻辑集成电路
文件: 总9页 (文件大小:103K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
INTEGRATED CIRCUITS  
DATA SHEET  
For a complete data sheet, please also download:  
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications  
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information  
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines  
74HC/HCT30  
8-input NAND gate  
December 1990  
Product specification  
File under Integrated Circuits, IC06  
Philips Semiconductors  
Product specification  
8-input NAND gate  
74HC/HCT30  
FEATURES  
Output capability: standard  
ICC category: SSI  
GENERAL DESCRIPTION  
The 74HC/HCT30 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).  
They are specified in compliance with JEDEC standard no. 7A.  
The 74HC/HCT30 provide the 8-input NAND function.  
QUICK REFERENEC DATA  
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns  
TYPICAL  
SYMBOL  
PARAMETER  
CONDITIONS  
UNIT  
ns  
HC  
12  
HCT  
12  
tPHL/ tPLH  
CI  
propagation delay A, B, C, D, E, F, G, H to Y  
input capacitance  
CL = 15 pF; VCC = 5 V  
3.5  
15  
3.5  
15  
pF  
pF  
CPD  
power dissipation capacitance per gate  
notes 1 and 2  
Notes  
1. CPD is used to determine the dynamic power dissipation (PD in µW):  
2
2
PD = CPD × VCC × fi + ∑ (CL × VCC × fo) where:  
fi = input frequency in MHz  
fo = output frequency in MHz  
2
(CL × VCC × fo) = sum of outputs  
CL = output load capacitance in pF  
VCC = supply voltage in V  
2. For HC the condition is VI = GND to VCC  
For HCT the condition is VI = GND to VCC 1.5 V  
ORDERING INFORMATION  
See “74HC/HCT/HCU/HCMOS Logic Package Information”.  
December 1990  
2
Philips Semiconductors  
Product specification  
8-input NAND gate  
74HC/HCT30  
PIN DESCRIPTION  
PIN NO.  
SYMBOL  
NAME AND FUNCTION  
1
2
3
4
5
6
7
8
A
data input  
B
data input  
C
data input  
D
data input  
E
data input  
F
data input  
GND  
Y
ground (0 V)  
data output  
not connected  
data input  
9, 10, 13  
n.c.  
G
11  
12  
14  
H
data input  
VCC  
positive supply voltage  
Fig.1 Pin configuration.  
Fig.2 Logic symbol.  
Fig.3 IEC logic symbol.  
December 1990  
3
Philips Semiconductors  
Product specification  
8-input NAND gate  
74HC/HCT30  
Fig.4 Functional diagram;  
Y = ABCDEFGH.  
Fig.5 Logic diagram.  
FUNCTION TABLE  
INPUTS  
OUTPUT  
Y
A
B
C
D
E
F
G
H
L
X
X
X
X
L
X
X
X
X
L
X
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
L
X
X
X
X
L
X
X
X
L
H
H
H
H
X
H
H
H
H
H
H
H
H
L
Notes  
1. H = HIGH voltage level  
L = LOW voltage level  
X = don’t care  
December 1990  
4
Philips Semiconductors  
Product specification  
8-input NAND gate  
74HC/HCT30  
DC CHARACTERISTICS FOR 74 HC  
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.  
Output capability: standard  
ICC category: SSI  
AC CHARACTERISTICS FOR 74HC  
GND = 0 V; tr = tf = 6 ns; CL = 50 pF  
T
amb (°C)  
TEST CONDITIONS  
74HC  
SYMBOL  
PARAMETER  
UNIT  
VCC  
+25  
40 to + 85 40 to +125  
WAVEFORMS  
(V)  
min. typ. max. min. max. min. max.  
tPHL/ tPLH propagation delay  
A, B, C, D, E, F, G, H to Y  
41 130  
15 26  
12 22  
165  
33  
28  
195  
39  
33  
ns  
ns  
2.0 Fig.6  
4.5  
6.0  
t
THL/ tTLH output transition time  
19 75  
95  
19  
16  
110  
22  
19  
2.0 Fig.6  
4.5  
6.0  
7
6
15  
13  
DC CHARACTERISTICS FOR 74HCT  
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.  
Output capability: standard  
ICC category: SSI  
Note to HCT types  
The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications.  
To determine ICC per input, multiply this value by the unit load coefficient shown in the table below.  
INPUT  
UNIT LOAD COEFFICIENT  
A, B, C, D, E, F, G, H 0.60  
AC CHARACTERISTICS FOR 74HCT  
GND = 0 V; tr = tf = 6 ns; CL = 50 pF  
Tamb (°C)  
TEST CONDITIONS  
74HCT  
SYMBOL  
PARAMETER  
UNIT  
40  
to +125  
VCC  
+25  
40 to + 85  
WAVEFORMS  
(V)  
min. typ. max. min. max. min. max.  
tPHL/ tPLH propagation delay  
A, B, C, D, E, F, G, H to Y  
16  
28  
35  
42  
ns  
ns  
4.5 Fig.6  
4.5 Fig.6  
tTHL/ tTLH output transition time  
7
15  
19  
22  
December 1990  
5
Philips Semiconductors  
Product specification  
8-input NAND gate  
74HC/HCT30  
AC WAVEFORMS  
(1) HC : VM = 50%; VI = GND to VCC.  
HCT: VM = 1.3 V; VI = GND to 3 V.  
Fig.6 Waveforms showing the input (A, B, C, D, E, F, G, H) to output (Y) propagation delays and the output  
transition times.  
PACKAGE OUTLINES  
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.  
December 1990  
6
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74AHC30;  
74AHCT30; 8-input  
NAND gate  
download datasheet  
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General description  
The 74AHC/AHCT30 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky  
TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.  
Catalog by  
System  
Cross-reference  
Packages  
The 74AHC/AHCT30 provide the 8-input NAND function.  
End of Life  
information  
Distributors Go  
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to
Features  
ESD protection:  
Models  
HBM EIA/JESD22-A114-A exceeds 2000 V  
MM EIA/JESD22-A115-A exceeds 200 V  
CDM EIA/JESD22-C101 exceeds 1000 V  
Balanced propagation delays  
SoC solutions  
Inputs accept voltages higher than V  
CC  
For AHC only: operates with CMOS input levels  
For AHCT only: operates with TTL input levels  
Output capability: standard  
I
category: SSI  
CC  
Specified from -40 to +85 °C and -40 to +125 °C.  
to
Datasheet  
Type number  
Title  
Publication  
release date  
Datasheet status  
Page  
count  
File  
size  
(kB)  
Datasheet  
74AHC30;  
74AHCT30  
8-input  
NAND  
gate  
11/30/1999  
Product specification 16  
82  
Download  
Down  
 
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Blockdiagram(s)  
Block diagram of  
74AHCT30D  
Block diagram of  
74AHCT30D  
to
Parametrics  
Type number Package  
Description Propagation Voltage No. Power  
Logic  
Output  
Delay(ns)  
of Dissipation  
Switching Drive  
Pins Considerations Levels  
Capability  
Low Power or  
SOT108-1  
74AHC30D  
8-Input  
NAND Gate  
5 Volts  
+
6~10  
14 Battery  
Applications  
Low Power or  
14 Battery  
CMOS  
CMOS  
Low  
(SO14)  
SOT402-1  
74AHC30PW  
8-Input  
NAND Gate  
5 Volts  
+
6~10  
Low  
Low  
(TSSOP14)  
Applications  
8-Input  
NAND  
Gate; TTL  
Enabled  
Low Power or  
14 Battery  
SOT108-1  
74AHCT30D  
5 Volts  
+
6~10  
6~10  
TTL  
TTL  
(SO14)  
Applications  
8-Input  
NAND  
Gate; TTL  
Enabled  
Low Power or  
14 Battery  
Applications  
SOT402-1  
74AHCT30PW  
5 Volts  
+
Low  
(TSSOP14)  
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status  
Down  
number  
SOT108-1  
(SO14)  
Standard Marking  
* Tube  
Full production  
Full production  
74AHC30D  
74AHC30D  
9352 641 86112  
-
-
order this  
order this  
Standard Marking  
74AHC30D-T 9352 641 86118 * Reel Pack,  
SMD, 13"  
SOT108-1  
(SO14)  
SOT402-1  
Standard Marking  
* Tube  
Full production  
74AHC30PW 74AHC30PW 9352 641 87112  
(TSSOP14)  
-
order this  
Standard Marking  
SMD, 13"  
SOT402-1  
74AHC30PW-  
T
Full production  
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9352 641 87118 * Reel Pack,  
(TSSOP14)  
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-
-
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SOT108-1  
(SO14)  
Standard Marking  
* Tube  
74AHCT30D 74AHCT30D 9352 641 84112  
Standard Marking  
9352 641 84118 * Reel Pack,  
SOT108-1  
(SO14)  
74AHCT30D-  
T
SMD, 13"  
SOT402-1  
Standard Marking  
* Tube  
Full production  
Full production  
74AHCT30PW 74AHCT30PW 9352 641 85112  
74AHCT30PW-  
(TSSOP14)  
-
-
order this  
order this  
Standard Marking  
SMD, 13"  
SOT402-1  
9352 641 85118 * Reel Pack,  
(TSSOP14)  
T
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