935263520557 [NXP]
IC SPECIALTY TELECOM CIRCUIT, PQFP100, PLASTIC, SOT-317, QFP-100, Telecom IC:Other;
| 型号： | 935263520557 |
| 厂家： | 
NXP |
| 描述： | IC SPECIALTY TELECOM CIRCUIT, PQFP100, PLASTIC, SOT-317, QFP-100, Telecom IC:Other 电信 电信集成电路 |
| 文件： | 总24页 (文件大小：134K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TDA8044
Satellite demodulator and decoder
Product specification
2000 Feb 21
Supersedes data of 1998 Nov 17
File under Integrated Circuits, IC02
Philips Semiconductors
Product specification
Satellite demodulator and decoder
TDA8044
FEATURES
• General features:
– One-chip Digital Video Broadcasting (DVB)
compliant Quadrature Phase Shift Keying (QPSK)
and Binary Phase Shift Keying (BPSK) demodulator
and concatenated Viterbi/Reed-Solomon decoder
with de-interleaver and de-randomizer
(ETS 300 421)
– Truncation length: 144
– Automatic synchronization
– 3.3 V supply voltage (input pads are 5 V tolerant)
– Standby mode for low power dissipation
– Channel Bit Error Rate (BER) estimation
– External indication of Viterbi sync lock
– Differential decoding optional.
– Internal clock PLL to allow low frequency crystal
application and selectable clock frequencies
• Reed-Solomon (RS) decoder:
– Power-on reset module
– Package: QFP100
– (204, 188, T = 8) Reed-Solomon code
– Automatic (I2C-bus configurable) synchronization of
bytes, transport packets and frames
– Boundary scan test.
• QPSK/BPSK demodulator:
– Internal convolutional de-interleaving (I = 12; using
internal memory)
– Interpolator and anti-alias filter to handle a large
range of symbol rates without additional external
filtering
– De-randomizer based on Pseudo Random Bit
Sequence (PRBS)
– On-chip AGC of the analog input I and Q baseband
signals or tuner AGC control
– External indication of Register Select (RS) decoder
sync lock
– Two on-chip matched Analog-to-Digital Converters
(ADCs; 7 bits)
– External indication of uncorrectable error (transport
error indicator is set)
– Half Nyquist (square root raised-cosine) filter with
selectable roll-off factor
– External indication of corrected byte
– Indication of the number of lost blocks
– Indication of the number of corrected blocks.
• Interface:
– I2C-bus interface to initialize and monitor the
demodulator and Forward Error Correction (FEC)
decoder; when no I2C-bus usage, default mode is
defined
– Large range of symbol frequencies:
0.5 to 45 Msymbols/s for TDA8044 and
0.5 to 30 Msymbols/s for TDA8044A, including
Single Carrier Per Channel (SCPC) function
– Can be used at low channel Signal-to-Noise ratio
(S/N)
– Internal carrier recovery, clock recovery and AGC
loops with programmable loop filters
– Programmable interrupt facility
– 6 bits I/O expander for flexible access to and from the
I2C-bus
– Switchable I2C-bus loop-through to suppress I2C-bus
crosstalk in the tuner
– Two loop carrier recovery enabling phase tracking of
the incoming symbols
– Software carrier sweep for low symbol rate
applications
– DiSEqC level 1.X support for dish control applications
– 3-state mode for transport stream outputs.
– Signal-to-noise ratio estimation
– External indication of demodulator lock.
• Viterbi decoder:
APPLICATIONS
– Rate 1⁄2 convolutional code based
• Digital satellite TV: demodulation and Forward Error
Correction (FEC).
– Constraint length K = 7 with G1 = 171oct and
G2 = 133oct; supported puncturing code rates:
1⁄2, 2⁄3, 3⁄4, 4⁄5, 5⁄6, 6⁄7, 7⁄8 and 8⁄9
– 4 bits input for ‘soft decision’ for both I and Q
2000 Feb 21
2
Philips Semiconductors
Product specification
Satellite demodulator and decoder
TDA8044
GENERAL DESCRIPTION
The TDA8044 also has internal anti-alias filters, which can
cover a large range of symbol frequencies (approximately
one decade) without the need to switch external (SAW)
filters. To cover the whole range of 0.5 to 45 Msymbols/s
switching of clock frequency (internally) and filtering
(externally) is necessary.
This document gives preliminary information about the
TDA8044 and TDA8044A, which are the successors of the
TDA8043. The TDA8044A is only specified where the
product deviates from the TDA8044, all other references
are the same. The TDA8044 is backwards compatible with
the TDA8043, with respect to pinning and the I2C-bus
software. The TDA8044 is a DVB compliant demodulator
and error correction decoder IC for reception of QPSK and
BPSK modulated signals for satellite applications. It can
handle variable symbol rates in the range of
0.5 to 45 Msymbols/s (0.5 to 30 Msymbols/s for
TDA8044A) with a minimum number of low cost and
non-critical external components. Typical applications for
this device are Multi Channel Per Carrier (MCPC), Single
Channel Per Carrier (SCPC) and simulcast. In these
applications one satellite transponder contains
The TDA8044 has a double carrier loop configuration
which has excellent capabilities of tracking phase noise.
Synchronization of the FEC unit is done completely
internally, thereby minimizing I2C-bus communication.
The output of the TDA8044 is highly flexible, allowing
different output modes to interface to a
demultiplexer/descrambler/MPEG-2 decoder including a
3-state mode. For evaluation of the TDA8044,
demodulator and Viterbi outputs can be made available
externally.
Interfacing to the TDA8044 has been extended compared
to the TDA8043. Separate resets are available for logic
only, logic plus I2C-bus and carrier loops. A Power-on
reset module has been implemented which gives a reset
signal at power-up. This signal can be used to reset the
TDA8044 in order to guarantee correct starting of the IC.
Two extra general purpose I/O pins (I/O expanders) have
been added. A switchable I2C-bus loop-through to the
tuner is implemented to switch-off the I2C-bus connection
to the tuner. This reduces phase noise in the tuner in the
event of I2C-bus crosstalk. The transport stream outputs
can be put in 3-state mode. DiSEqC level 1.X support is
integrated for dish control applications. The power
consumption in standby mode has been decreased
considerably.
respectively one broad QPSK carrier, several small QPSK
carriers and one small QPSK carrier together with one or
two FM carriers.
The TDA8044 has minimum interface with the tuner, it only
requires the demodulated analog I and Q baseband input
signals. Analog-to-digital conversion is performed
internally by two matched 7-bit ADCs. Since all the loops
(AGC, clock and carrier recovery) are internal, no
feedback to the tuner is needed. However, for maximum
tuner flexibility, there is the possibility to close the AGC
and carrier recovery loop externally via the tuner.
The number of external components required for operation
of the TDA8044 is very low. Moreover the external
components are low cost and non-critical. This gives an
easy and low cost application. The TDA8044 operates on
a low frequency crystal which is upconverted to a clock
frequency by means of an internal PLL. Different clock
frequencies can be selected with the PLL without changing
the crystal. This allows for maximum flexibility concerning
symbol rate range combined with minimum power
consumption.
2000 Feb 21
3
Philips Semiconductors
Product specification
Satellite demodulator and decoder
TDA8044
QUICK REFERENCE DATA
SYMBOL
VDDA
PARAMETER
CONDITIONS
MIN.
TYP. MAX.
UNIT
analog supply voltage
digital supply voltage
total supply current
TDA8044
3.05
3.05
3.3
3.3
3.55
3.55
V
V
VDDD
IDD(tot)
VDDD = 3.3 V
note 1
−
−
320
480
350
mA
mA
TDA8044A
notes 1 and 2
−
fclk
internal clock frequency
CFS = 0 or CFS = 1;
fxtal = 4 MHz
TDA8044
note 1
10.7
10.7
−
−
96
64
MHz
MHz
TDA8044A
notes 1 and 2
note 3
rs
symbol rate
TDA8044
0.5
0.5
−
−
45
30
Msymbols/s
Msymbols/s
TDA8044A
Ptot
total power dissipation
TDA8044
Tamb = 70 °C; note 4
−
−
−
2
1150 1700 mW
TDA8044A
−
1250 mW
IL
implementation loss
note 5
0.3
−
−
−
dB
dB
S/N
signal-to-noise ratio for locking note 5
the TDA8044
Notes
1. Programmable internal frequencies possible:
a) Values 10.7, 16, 32 or 64 MHz for CFS = 0.
b) Values 16, 24, 48 or 96 MHz for CFS = 1.
2. CFS is set to logic 0.
3. Without switching internal clock frequencies, a range of 1 decade can be covered. To cover the full range of symbol
frequencies, internal clock frequencies and external (SAW) filters must be switched. Details can be found in the
application note.
4. Maximum value is specified for a symbol rate of 45 Msymbols/s, a puncturing rate of 7⁄8, a clock frequency of 96 MHz
and a 3.55 V power supply. The typical value is specified for a symbol rate of 27.5 Msymbols/s, a puncture rate of 3⁄4
and a clock frequency of 64 MHz.
5. Implementation loss at the demodulator output and minimum S/N to lock the TDA8044 are measured including tuner
in a laboratory environment at a symbol rate of 27.5 Msymbols/s and a clock frequency of 64 MHz.
ORDERING INFORMATION
PACKAGE
TYPE
NUMBER
NAME
DESCRIPTION
VERSION
TDA8044H
QFP100
plastic quad flat package; 100 leads (lead length 1.95 mm);
SOT317-2
body 14 × 20 × 2.8 mm
TDA8044AH
2000 Feb 21
4
Philips Semiconductors
Product specification
Satellite demodulator and decoder
TDA8044
PINNING
SYMBOL
PIN
I/O
DESCRIPTION
digital I-input bit 2 (ADC bypass)
I2
I3
1
I
I
2
digital I-input bit 3 (ADC bypass)
digital ground 1
VSSD1
CFS
VSSD2
I4
3
−
4
I
clock frequency selection (remains at logic 0 for TDA8044A)
digital ground 2
5
−
6
I
digital I-input bit 4 (ADC bypass)
digital I-input bit 5 (ADC bypass)
digital I-input bit 6 (ADC bypass: MSB)
digital Q-input bit 0 (ADC bypass: LSB)
digital supply voltage 1
I5
7
I
I6
8
I
Q0
9
I
VDDD1
Q1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
−
I
digital Q-input bit 1 (ADC bypass)
digital Q-input bit 2 (ADC bypass)
digital Q-input bit 3 (ADC bypass)
digital Q-input bit 4 (ADC bypass)
digital ground 3
Q2
I
Q3
I
Q4
I
VSSD3
Q5
−
I
digital Q-input bit 5 (ADC bypass)
digital Q-input bit 6 (ADC bypass: MSB)
digital ground 4
Q6
I
VSSD4
VDDD2
PRESET
P3
−
−
digital supply voltage 2
I
set device into default mode
quasi-bidirectional I/O port (bit 3)
quasi-bidirectional I/O port (bit 2)
quasi-bidirectional I/O port (bit 1)
quasi-bidirectional I/O port (bit 0)
digital supply voltage 3
I/O
I/O
I/O
I/O
−
P2
P1
P0
VDDD3
P5
I/O
I/O
O
O
O
O
−
quasi-bidirectional I/O port (bit 5)
quasi-bidirectional I/O port (bit 4)
output clock for transport stream bytes
parallel data output (bit 0)
P4
PDOCLK
PDO0
PDO1
PDO2
VSSD5
PDO3
PDO4
PDO5
VSSD6
VSSD7
PDO6
POR
VDDD4
parallel data output (bit 1)
parallel data output (bit 2)
digital ground 5
O
O
O
−
parallel data output (bit 3)
parallel data output (bit 4)
parallel data output (bit 5)
digital ground 6
−
digital ground 7
O
I
parallel data output (bit 6)
Power-on reset [can be connected to PRESET (pin 20)]
digital supply voltage 4
−
2000 Feb 21
5
Philips Semiconductors
Product specification
Satellite demodulator and decoder
TDA8044
SYMBOL
VDDD5
PIN
I/O
DESCRIPTION
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
−
−
−
−
O
−
−
0
O
0
−
I
digital supply voltage 5
digital ground 8
VSSD8
VDDD6
VDDD7
PDO7
n.c.
digital supply voltage 6
digital supply voltage 7
parallel data output (bit 7)
not connected
VSSD9
PDOERR
PDOVAL
PDOSYNC
VSSD10
SCL
digital ground 9
transport error indicator
data valid indicator
transport packet synchronization signal
digital ground 10
serial clock input of I2C-bus
serial data of I2C-bus
SDA
I/O
O
I
INT
interrupt output (active LOW)
I2C-bus hardware address
Reed-Solomon lock indicator
Viterbi lock indicator
A0
RSLOCK
VLOCK
DLOCK
VDDD8
VDDD9
TEST
TRST
TCK
O
O
O
−
−
I
demodulator lock indicator
digital supply voltage 8
digital supply voltage 9
test pin (normally connected to ground)
I
BST optional asynchronous reset (normally connected to ground)
BST dedicated test clock (normally connected to ground)
serial clock of I2C-bus loop-through
serial data of I2C-bus loop-through
digital supply voltage 10
I
SCLT
I
SDAT
VDDD10
VSSD11
VSSD12
TMS
I/O
−
−
−
I
digital ground 11
digital ground 12
BST input control signal (normally connected to ground)
BST serial test data output
BST serial test data in (normally connected to ground)
digital supply voltage 11
TDO
O
I
TDI
VDDD11
VSSD13
VSSD(AD)
VDDD(AD)
Vref(B)
VSSA1
QA
−
−
−
−
O
−
−
O
I
digital ground 13
digital ground ADC
digital supply ADC
bottom reference voltage for ADC
analog ground 1
analog input Q
Vref(Q)
IA
AGC decoupling - Q path
analog input I
VSSA2
−
analog ground 2
2000 Feb 21
6
Philips Semiconductors
Product specification
Satellite demodulator and decoder
TDA8044
SYMBOL
Vref(I)
PIN
I/O
DESCRIPTION
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
O
−
−
I
AGC decoupling - I path
analog supply voltage
VDDA
VDDXTAL
XTALI
XTALO
VSSXTAL
VDDD12
VDDD13
VSSD14
D22
supply voltage for crystal oscillator
crystal oscillator input
O
−
−
−
−
O
−
−
O
−
−
−
O
I
crystal oscillator output
ground for crystal oscillator
digital supply voltage 12
digital supply voltage 13
digital ground 14
22 kHz output for dish control applications
digital ground 15
VSSD15
VSSD16
VAGC
digital ground 16
AGC output voltage
VSSD(test)
VDDD14
VDDD15
OUSTD
I0
test pin, normally connected to ground
digital supply voltage 14
digital supply voltage 15
general purpose sigma-delta output
digital I-input bit 0 (ADC bypass: LSB)
digital I-input bit 1 (ADC bypass)
I1
I
2000 Feb 21
7
Philips Semiconductors
Product specification
Satellite demodulator and decoder
TDA8044
1
2
I2
I3
80 IA
V
79
ref(Q)
V
V
3
78 QA
V
SSD1
CFS
4
77
76
75
74
73
72
SSA1
V
V
V
V
V
5
ref(B)
SSD2
I4
6
DDD(AD)
SSD(AD)
SSD13
DDD11
7
I5
I6
8
9
Q0
V
10
11
12
13
71 TDI
DDD1
Q1
TDO
TMS
V
70
69
68
67
66
65
Q2
Q3
SSD12
V
V
Q4 14
15
SSD11
DDD10
V
SSD3
TDA8044
TDA8044A
16
Q5
SDAT
Q6 17
64 SCLT
63 TCK
V
V
18
19
20
SSD4
TRST
TEST
V
62
61
60
59
58
57
DDD2
PRESET
P3 21
P2 22
P1 23
P0 24
25
DDD9
V
DDD8
DLOCK
VLOCK
V
56 RSLOCK
55 A0
DDD3
P5 26
P4 27
54
53
52
51
INT
SDA
SCL
V
PDOCLK 28
PDO0
29
PDO1 30
SSD10
MGM606
For compatibility in respect to the TDA8043 see Section “Pin compatibility”.
Fig.1 Pin configuration.
2000 Feb 21
8
Philips Semiconductors
Product specification
Satellite demodulator and decoder
TDA8044
Pin compatibility
The TDA8044 is backwards pin compatible with the TDA8043, this means that the functional pins of the TDA8043 have
been left unchanged on the TDA8044. However due to extra functionality of the TDA8044, some of the not connected
pins of the TDA8043 have become functional pins on the TDA8044. Table 1 lists the modified pins of the TDA8044.
Table 1 Modified pins of the TDA8044
PIN
4
TDA8043 FUNCTION
not connected
TDA8044 SYMBOL
TDA8044 FUNCTION
clock frequency selection
digital ground
CFS
5
not connected
not connected
not connected
not connected
not connected
not connected
not connected
not connected
not connected
not connected
not connected
not connected
not connected
VSSD2
P5
26
27
36
37
39
47
64
65
91
92
93
95
I/O expander bit 5
P4
I/O expander bit 4
VSSD6
VSSD7
POR
VSSD9
SCLT
SDAT
D22
digital ground
digital ground
Power-on reset
digital ground
serial clock of I2C-bus loop-through
serial data of I2C-bus loop-through
22 kHz generation output
digital ground
VSSD15
VSSD16
VSSD(test)
digital ground
test pin, connect to ground
If it is required to replace the TDA8043 with the TDA8044 and the pins with extra functionality are not required, then the
following measures on the PCB layout must be taken to avoid I/O conflicts in the TDA8044:
• Pin numbers 4, 5, 26, 27, 36, 37, 47, 65, 92, 93 and 95 must be put to ground
• Pin numbers 39, 64 and 91 must be left not connected.
With these measures it is possible to use the TDA8043 and the TDA8044 on the same PCB without any problems.
In order to use pins with the extra functionality of the TDA8044, PCB layout changes are necessary.
2000 Feb 21
9
Philips Semiconductors
Product specification
Satellite demodulator and decoder
TDA8044
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VDD
PARAMETER
supply voltage pins
CONDITIONS
MIN. MAX. UNIT
−0.3
+3.55
VDD
V
V
Vmax
Ptot
maximum voltage on all pins
total power dissipation
TDA8044
0
T
amb = 70 °C; note 1
amb = 70 °C; note 2
−
1700 mW
1250 mW
+150 °C
TDA8044A
T
−
Tstg
Tamb
Tj
IC storage temperature
ambient temperature
operating junction temperature
−55
0
Tamb = 70 °C
70
°C
°C
0
125
Notes
1. Maximum power dissipation is specified for 96 MHz clock frequency, 45 Msymbols/s and a puncture rate of 7⁄8.
2. Maximum power dissipation is specified for 64 MHz clock frequency, 30 Msymbols/s and a puncture rate of 7⁄8.
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However it is good practice to take
normal precautions appropriate to handling MOS devices (see “Handling MOS devices”).
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
PARAMETER
CONDITIONS
in free air
VALUE
UNIT
thermal resistance from junction to ambient
TDA8044
34
45
K/W
K/W
TDA8044A
2000 Feb 21
10
Philips Semiconductors
Product specification
Satellite demodulator and decoder
TDA8044
APPLICATION INFORMATION
DRAM
(optional)
FLASH
FRONT
PANEL
CONTROL
RF input
1394
L + PHY
I
IEEE 1394
TDA8044
SAA7214
TMIPS
TDA8060
TSA5056
TDA8044A
Q
IEEE 1284
RS232
SDD
BUFFERS
SCART 1
SCART 2
SCART 3
MGM605
2
RGB
2
I C-bus
I C-bus
CVBS/YC
L/R
SAA7215
SWITCHING
TUNER
AV_DATA
AUDIO
DAC
Vxx
MODEM
telecommunications
operator IF
16-Mbit
SDRAM
(optional)
16-Mbit
SDRAM
smart card(s)
TDA8004
Fig.2 Satellite set-top decoder concept.
2000 Feb 21
11
Philips Semiconductors
Product specification
Satellite demodulator and decoder
TDA8044
tuner AGC (optional)
V
V
10 Ω
10 nF
+3.3 V
DDD1
DDD2
+3.3 V
(1)
(1)
L
15 µF
15 µF
10 kΩ
470 Ω
+ 5 V
V
27 27
pF pF
DDA
L
330 nF
V
DDD2
(3)
C
(3)
C
V
DDD2
100 nF
(3)
C
22 kHz
V
SD
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
100 nF
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I
100 nF
2
100 nF
3
Q
CFS
4
100 nF
5
V
6
DDD2
(3)
C
7
8
V
9
DDD2
(3)
C
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
TDI
DDD
(3)
C
TDO
TMS
V
DDD1
100 nF
V
DDD2
TDA8044
TDA8044A
(3)
C
2
I C-bus
to tuner
470 kΩ
V
DDD1
(3)
C
V
P3
P2
P1
P0
DDD1
(3)
C
lock signals
+5 V
V
DDD1
4.7
4.7
kΩ
1.6
(3)
C
P5
P4
kΩ
kΩ
interrupt
PDOCLK
PDO0
2
I C-bus
packet data
and control
outputs
input
PDO1
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
n.c.
POR
V
+3.3 V
DDA
(1)
L
PDO2 PDO3 PDO5
PDO4
PDO6
PDO7 PDOERR PDOSYNC
PDOVAL
15 µF
(3)
V
C
V
DDD1
DDD1
MGM607
packet data and control outputs
(1) B = SMD bead type C8D8.9/3/3 Grade 4S2.
(2) fxtal = 4 MHz (fundamental).
(3) C = 6.8 nF, SMD.
Fig.3 Application diagram.
12
2000 Feb 21
Philips Semiconductors
Product specification
Satellite demodulator and decoder
TDA8044
PACKAGE OUTLINE
QFP100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SOT317-2
y
X
A
80
51
81
50
Z
E
e
A
2
H
A
E
E
(A )
3
A
1
θ
w M
p
pin 1 index
L
p
b
L
31
100
detail X
1
30
w M
Z
v
M
D
A
b
p
e
D
B
H
v
M
B
D
0
5
scale
10 mm
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.25 2.90
0.05 2.65
0.40 0.25 20.1 14.1
0.25 0.14 19.9 13.9
24.2 18.2
23.6 17.6
1.0
0.6
0.8
0.4
1.0
0.6
mm
3.20
0.25
0.65
1.95
0.2 0.15 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
97-08-01
99-12-27
SOT317-2
MO-112
2000 Feb 21
13
Philips Semiconductors
Product specification
Satellite demodulator and decoder
TDA8044
SOLDERING
If wave soldering is used the following conditions must be
observed for optimum results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Wave soldering
Manual soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
2000 Feb 21
14
Philips Semiconductors
Product specification
Satellite demodulator and decoder
TDA8044
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
REFLOW(1)
BGA, SQFP
not suitable
suitable
suitable
suitable
suitable
suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable(2)
PLCC(3), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
not recommended(3)(4)
not recommended(5)
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2000 Feb 21
15
Philips Semiconductors
Product specification
Satellite demodulator and decoder
TDA8044
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
2000 Feb 21
16
Philips Semiconductors
Product specification
Satellite demodulator and decoder
TDA8044
NOTES
2000 Feb 21
17
Philips Semiconductors
Product specification
Satellite demodulator and decoder
TDA8044
NOTES
2000 Feb 21
18
Philips Semiconductors
Product specification
Satellite demodulator and decoder
TDA8044
NOTES
2000 Feb 21
19
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69
SCA
© Philips Electronics N.V. 2000
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753504/03/pp20
Date of release: 2000 Feb 21
Document order number: 9397 750 05972
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Description
Cross reference
This document gives preliminary information about the TDA8044 and TDA8044A, which are the successors of the TDA8043. The
TDA8044A is only specified where the product deviates from the TDA8044, all other references are the same. The TDA8044 is backwards
compatible with the TDA8043, with respect to pinning and the I²C-bus software. The TDA8044 is a DVB compliant demodulator and error
correction decoder IC for reception of QPSK and BPSK modulated signals for satellite applications. It can handle variable symbol rates in
the range of 0.5 to 45 Msymbols/s (0.5 to 30 Msymbols/s for TDA8044A) with a minimum number of low cost and non-critical external
components. Typical applications for this device are Multi Channel Per Carrier (MCPC), Single Channel Per Carrier (SCPC) and simulcast.
In these applications one satellite transponder contains respectively one broad QPSK carrier, several small QPSK carriers and one small
QPSK carrier together with one or two FM carriers.
Models
Packages
Application notes
Selection guides
Other technical documentation
End of Life information
Datahandbook system
The TDA8044 has minimum interface with the tuner, it only requires the demodulated analog I and Q baseband input signals. Analog-to-
digital conversion is performed internally by two matched 7-bit ADCs. Since all the loops (AGC, clock and carrier recovery) are internal, no
feedback to the tuner is needed. However, for maximum tuner flexibility, there is the possibility to close the AGC and carrier recovery loop
externally via the tuner.
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The number of external components required for operation of the TDA8044 is very low. Moreover the external components are low cost
and non-critical. This gives an easy and low cost application. The TDA8044 operates on a low frequency crystal which is upconverted to a
clock frequency by means of an internal PLL. Different clock frequencies can be selected with the PLL without changing the crystal. This
allows for maximum flexibility concerning symbol rate range combined with minimum power consumption.
TDA8044
TDA8044
The TDA8044 also has internal anti-alias filters, which can cover a large range of symbol frequencies (approximately one decade) without
the need to switch external (SAW) filters. To cover the whole range of 0.5 to 45 Msymbols/s switching of clock frequency (internally) and
filtering (externally) is necessary.
The TDA8044 has a double carrier loop configuration which has excellent capabilities of tracking phase noise. Synchronization of the FEC
unit is done completely internally, thereby minimizing I²C-bus communication. The output of the TDA8044 is highly flexible, allowing
different output modes to interface to a demultiplexer/descrambler/MPEG-2 decoder including a 3-state mode. For evaluation of the
TDA8044, demodulator and Viterbi outputs can be made available externally.
Interfacing to the TDA8044 has been extended compared to the TDA8043. Separate resets are available for logic only, logic plus I²C-bus
and carrier loops. A Power-on reset module has been implemented which gives a reset signal at power-up. This signal can be used to reset
the TDA8044 in order to guarantee correct starting of the IC. Two extra general purpose I/O pins (I/O expanders) have been added. A
switchable I²C-bus loop-through to the tuner is implemented to switch-off the I²C-bus connection to the tuner. This reduces phase noise in
the tuner in the event of I²C-bus crosstalk. The transport stream outputs can be put in 3-state mode. DiSEqC level 1.X support is integrated
for dish control applications. The power consumption in standby mode has been decreased considerably.
Features
l General features:
- One-chip Digital Video Broadcasting (DVB) compliant Quadrature Phase Shift Keying (QPSK) and Binary Phase Shift Keying
(BPSK) demodulator and concatenated Viterbi/Reed-Solomon decoder with de-interleaver and de-randomizer (ETS 300 421)
- 3.3 V supply voltage (input pads are 5 V tolerant)
- Standby mode for low power dissipation
- Internal clock PLL to allow low frequency crystal application and selectable clock frequencies
- Power-on reset module
- Package: QFP100
- Boundary scan test.
l QPSK/BPSK demodulator:
- Interpolator and anti-alias filter to handle a large range of symbol rates without additional external filtering
- On-chip AGC of the analog input I and Q baseband signals or tuner AGC control
- Two on-chip matched Analog-to-Digital Converters (ADCs; 7 bits)
- Half Nyquist (square root raised-cosine) filter with selectable roll-off factor
- Large range of symbol frequencies:
0.5 to 45 Msymbols/s for TDA8044 and
0.5 to 30 Msymbols/s for TDA8044A, including
Single Carrier Per Channel (SCPC) function
- Can be used at low channel Signal-to-Noise ratio (S/N)
- Internal carrier recovery, clock recovery and AGC loops with programmable loop filters
- Two loop carrier recovery enabling phase tracking of the incoming symbols
- Software carrier sweep for low symbol rate applications
- Signal-to-noise ratio estimation
- External indication of demodulator lock.
l Viterbi decoder:
- Rate 1/2 convolutional code based
- Constraint length K = 7 with G1 = 171oct and G2 = 133oct; supported puncturing code rates: 1/2 , 2/3 , 3/4 , 4/5 , 5/6 , 6/7 , 7/8 and
8/9
- 4 bits input for ‘soft decision’ for both I and Q
- Truncation length: 144
- Automatic synchronization
- Channel Bit Error Rate (BER) estimation
- External indication of Viterbi sync lock
- Differential decoding optional.
l Reed-Solomon (RS) decoder:
- (204, 188, T = 8) Reed-Solomon code
- Automatic (I²C-bus configurable) synchronization of bytes, transport packets and frames
- Internal convolutional de-interleaving (I = 12; using internal memory)
- De-randomizer based on Pseudo Random Bit Sequence (PRBS)
- External indication of Register Select (RS) decoder sync lock
- External indication of uncorrectable error (transport error indicator is set)
- External indication of corrected byte
- Indication of the number of lost blocks
- Indication of the number of corrected blocks.
l Interface:
- I²C-bus interface to initialize and monitor the demodulator and Forward Error Correction (FEC) decoder; when no I²C-bus usage,
default mode is defined
- Programmable interrupt facility
- 6 bits I/O expander for flexible access to and from the
- 2 C-bus
- Switchable I 2 C-bus loop-through to suppress I²C-bus crosstalk in the tuner
- DiSEqC level 1.X support for dish control applications
- 3-state mode for transport stream outputs.
Applications
l Digital satellite TV: demodulation and Forward Error Correction (FEC).
Datasheet
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(kB)
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TDA8044 Satellite demodulator and decoder
21-Feb-00
Product
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Specification
Products, packages, availability and ordering
North American
Partnumber
Order code
(12nc)
Partnumber
marking/packing
package device status buy online
Standard Marking * Reel Dry Pack,
SMD, 13"
TDA8044AH/C2
9352 627 94518
SOT317 Full production
SOT317 Full production
SOT317 Full production
-
Standard Marking * Tray Dry Pack,
Bakeable, Multiple
TDA8044AHBA
9352 627 94557
9352 635 20557
Standard Marking * Tray Dry Pack,
Bakeable, Multiple
TDA8044H/C2
-
Find similar products:
TDA8044 links to the similar products page containing an overview of products that are similar in function or related to the part
number(s) as listed on this page. The similar products page includes products from the same catalog tree(s) , relevant selection guides and
products from the same functional category.
Copyright © 2000
Royal Philips Electronics
All rights reserved.
Terms and conditions.
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