935263181026 [NXP]
IC LIQUID CRYSTAL DISPLAY DRIVER, UUC56, DIE, Display Driver;
| 型号： | 935263181026 |
| 厂家： | 
NXP |
| 描述： | IC LIQUID CRYSTAL DISPLAY DRIVER, UUC56, DIE, Display Driver 驱动 |
| 文件： | 总43页 (文件大小：327K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
PCF8579
LCD column driver for dot matrix
graphic displays
1997 Apr 01
Product specification
Supersedes data of 1996 Oct 25
File under Integrated Circuits, IC12
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
CONTENTS
10
11
12
13
14
15
LIMITING VALUES
HANDLING
1
2
3
4
5
6
7
FEATURES
DC CHARACTERISTICS
AC CHARACTERISTICS
APPLICATION INFORMATION
APPLICATIONS
GENERAL DESCRIPTION
ORDERING INFORMATION
BLOCK DIAGRAM
CHIP DIMENSIONS AND BONDING PAD
LOCATIONS
PINNING
16
17
18
CHIP-ON GLASS INFORMATION
PACKAGE OUTLINES
SOLDERING
FUNCTIONAL DESCRIPTION
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
Multiplexed LCD bias generation
Power-on reset
Timing generator
Column drivers
Display RAM
18.1
18.2
18.3
18.3.1
18.3.2
18.3.3
18.4
Introduction
Reflow soldering
Wave soldering
LQFP
Data pointer
VSO
Subaddress counter
I2C-bus controller
Input filters
RAM access
Display control
TEST pin
Method (LQFP and VSO)
Repairing soldered joints
19
20
21
DEFINITIONS
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I2C COMPONENTS
8
I2C-BUS PROTOCOL
8.1
9
Command decoder
CHARACTERISTICS OF THE I2C-BUS
9.1
9.2
9.3
9.4
Bit transfer
Start and stop conditions
System configuration
Acknowledge
1997 Apr 01
2
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
1
FEATURES
2
APPLICATIONS
• LCD column driver
• Automotive information systems
• Telecommunication systems
• Point-of-sale terminals
• Computer terminals
• Used in conjunction with the PCF8578, this device forms
part of a chip set capable of driving up to 40960 dots
• 40 column outputs
• Selectable multiplex rates; 1 : 8, 1 : 16, 1 : 24 or 1 : 32
• Externally selectable bias configuration, 5 or 6 levels
• Instrumentation.
• Easily cascadable for large applications (up to
32 devices)
3
GENERAL DESCRIPTION
The PCF8579 is a low power CMOS LCD column driver,
designed to drive dot matrix graphic displays at multiplex
rates of 1 : 8, 1 : 16, 1 : 24 or 1 : 32. The device has
40 outputs and can drive 32 × 40 dots in a 32 row
multiplexed LCD. Up to 16 PCF8579s can be cascaded
and up to 32 devices may be used on the same I2C-bus
(using the two slave addresses). The device is optimized
for use with the PCF8578 LCD row/column driver.
Together these two devices form a general purpose LCD
dot matrix driver chip set, capable of driving displays of up
to 40960 dots. The PCF8579 is compatible with most
microcontrollers and communicates via a two-line
bidirectional bus (I2C-bus). To allow partial VDD shutdown
the ESD protection system of the SCL and SDA pins does
not use a diode connected to VDD. Communication
overheads are minimized by a display RAM with
• 1280-bit RAM for display data storage
• Display memory bank switching
• Auto-incremented data loading across hardware
subaddress boundaries (with PCF8578)
• Power-on reset blanks display
• Logic voltage supply range 2.5 to 6 V
• Maximum LCD supply voltage 9 V
• Low power consumption
• I2C-bus interface
• TTL/CMOS compatible
• Compatible with most microcontrollers
• Optimized pinning for single plane wiring in multiple
device applications (with PCF8578)
auto-incremented addressing and display bank switching.
• Space saving 56-lead plastic mini-pack and 64-pin
plastic low profile quad flat package
• Compatible with chip-on-glass technology
• I2C-bus address: 011110 SA0.
4
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
PCF8579T
VSO56
−
plastic very small outline package; 56 leads
chip with bumps on tape
SOT190
−
PCF8579U7
PCF8579H
LQFP64
plastic low profile quad flat package; 64 leads; body 10 × 10 × 1.4 mm
SOT314-2
1997 Apr 01
3
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
5
BLOCK DIAGRAM
C39 - C0
17 - 56
(30 to 33, 35 to 64, 1 to 6)
12 (20)
V
DD
14 (22)
(1)
V
V
3
4
COLUMN
15 (23)
16 (24)
PCF8579
DRIVERS
V
LCD
6 (12)
5 (11)
OUTPUT
CONTROLLER
TEST
V
SS
Y DECODER
AND SENSING
AMPLIFIERS
32 x 40 BIT
DISPLAY RAM
DISPLAY
DECODER
POWER-ON
RESET
X DECODER
8 (14)
(9) 3
A3
A2
A1
A0
9 (16)
10 (17)
SYNC
SUBADDRESS
COUNTER
TIMING
GENERATOR
RAM DATA POINTER
(10) 4
CLK
11 (18)
Y
X
2 (8)
1 (7)
2
SCL
SDA
INPUT
FILTERS
I C-BUS
COMMAND
DECODER
CONTROLLER
(15, 19, 21, 25 to 29, 34)
13
7 (13)
SA0
MSA919
n.c.
(1) Operates at LCD voltage levels, all other blocks operate at logic levels.
The pin numbers given in parenthesis refer to the LQFP64 package.
Fig.1 Block diagram.
4
1997 Apr 01
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
6
PINNING
SYMBOL
PINS
DESCRIPTION
VSO56
LQFP64
SDA
1
7
I2C-bus serial data input/output
I2C-bus serial clock input
cascade synchronization input
external clock input
SCL
2
8
SYNC
CLK
3
9
4
10
VSS
5
6
11
ground (logic)
TEST
SA0
12
test pin (connect to VSS)
7
13
I2C-bus slave address input (bit 0)
I2C-bus subaddress inputs
supply voltage
A3 to A0
VDD
8 to 11
12
13(1)
14 and 15
16
14, 16 to 18
20
15, 19, 21,25 to 29, 34
22 and 23
n.c.
not connected
V3, V4
VLCD
LCD bias voltage inputs
LCD supply voltage
24
C39 to C0
17 to 56
30 to 33, 35 to 64 and 1 to 6 LCD column driver outputs
Note
1. Do not connect, this pin is reserved.
1997 Apr 01
5
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
SDA
SCL
1
2
3
4
5
6
7
8
9
56 C0
55
54
C1
C2
SYNC
CLK
53 C3
52 C4
51 C5
V
SS
TEST
SA0
A3
50
C6
49
48 C8
C7
A2
A1 10
47
46
45
44
43
42
C9
11
12
A0
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
V
DD
n.c. 13
V
V
14
15
16
17
3
4
PCF8579
V
LCD
C39
41
40
39
C38 18
19
20
C37
C36
38
37
36
35
C35 21
22
C33 23
24
C31 25
26
C34
34
C32
33 C23
32 C24
C30
31
30
C25
C26
C29 27
C28 28
29 C27
MSA918
Fig.2 Pin configuration (VSO56).
6
1997 Apr 01
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
1
2
3
4
5
6
7
8
9
48 C22
C5
C4
47 C23
46 C24
45 C25
C3
C2
C26
C1
44
43 C27
C0
C28
C29
C30
C31
C32
C33
42
41
40
39
38
37
SDA
SCL
SYNC
PCF8579
CLK 10
V
11
SS
TEST 12
13
14
15
16
36 C34
SA0
A3
35
34
33
C35
n.c.
n.c.
A2
C36
MBH590
Fig.3 Pin configuration (LQFP64).
7
1997 Apr 01
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
7
FUNCTIONAL DESCRIPTION
The PCF8579 column driver is designed for use with the
PCF8578. Together they form a general purpose LCD dot
matrix chip set.
MSA838
1.0
0.8
0.6
0.4
0.2
0
V
bias
V
V
V
op
2
3
Typically up to 16 PCF8579s may be used with one
PCF8578. Each of the PCF8579s is identified by a unique
4-bit hardware subaddress, set by pins A0 to A3.
The PCF8578 can operate with up to 32 PCF8579s when
using two I2C-bus slave addresses. The two slave
addresses are set by the logic level on input SA0.
V
V
4
5
7.1
Multiplexed LCD bias generation
The bias levels required to produce maximum contrast
depend on the multiplex rate and the LCD threshold
voltage (Vth). Vth is typically defined as the RMS voltage at
which the LCD exhibits 10% contrast. Table 1 shows the
optimum voltage bias levels for the PCF8578/PCF8579
chip set as functions of Vop (Vop = VDD − VLCD), together
with the discrimination ratios (D) for the different multiplex
rates. A practical value for Vop is obtained by equating
Voff(rms) with Vth. Figure 4 shows the first 4 rows of Table 1
as graphs.
1:8
1:16
1:24
1:32
multiplex rate
Vbias = V2, V3, V4, V5. See Table 1.
Fig.4 Vbias/Vop as a function of the multiplex rate.
Table 1 Optimum LCD bias voltages
MULTIPLEX RATE
PARAMETER
7.2
Power-on reset
1 : 8
1 : 16
1 : 24
1 : 32
At power-on the PCF8579 resets to a defined starting
condition as follows:
V2
--------
Vop
0.739
0.800
0.830
0.850
1. Display blank (in conjunction with PCF8578)
2. 1 : 32 multiplex rate
V 3
--------
V op
0.522
0.478
0.261
0.297
0.430
1.447
3.370
0.600
0.400
0.200
0.245
0.316
1.291
4.080
0.661
0.339
0.170
0.214
0.263
1.230
4.680
0.700
0.300
0.150
0.193
0.230
1.196
5.190
3. Start bank, 0 selected
4. Data pointer is set to X, Y address 0, 0
5. Character mode
V 4
--------
V op
6. Subaddress counter is set to 0
7. I2C-bus is initialized.
V 5
--------
V op
Data transfers on the I2C-bus should be avoided for 1 ms
following power-on, to allow completion of the reset action.
V off (rms)
-----------------------
Vop
V on (rms)
----------------------
Vop
V on (rms)
D =
-----------------------
Voff (rms)
V op
--------
Vth
1997 Apr 01
8
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
T
frame
ON
OFF
0
1
2
3
4
5
6
7
V
V
V
V
V
V
DD
2
3
ROW 0
4
5
LCD
1:8
V
V
V
V
V
V
DD
2
3
4
COLUMN
5
LCD
SYNC
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
V
DD
V
2
V
3
V
ROW 0
4
V
5
V
LCD
1:16
V
DD
V
2
V
3
V
COLUMN
4
V
5
V
LCD
SYNC
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
V
DD
V
2
V
3
V
ROW 0
4
V
5
V
LCD
1:24
V
DD
V
2
V
3
4
V
COLUMN
V
5
V
LCD
SYNC
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
V
DD
V
2
V
3
V
ROW 0
4
V
5
V
LCD
1:32
V
DD
V
2
V
3
V
COLUMN
4
V
5
V
LCD
SYNC
column
display
MSA841
Fig.5 LCD row/column waveforms.
9
1997 Apr 01
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
T
state 1 (OFF)
state 2 (ON)
frame
V
DD
V
2
V
ROW 1
R1 (t)
3
V
V
V
4
5
LCD
V
V
V
V
V
V
DD
2
ROW 2
R2 (t)
3
dot matrix
1:8 multiplex rate
4
5
LCD
V
V
V
V
V
V
DD
2
COL 1
C1 (t)
3
4
5
LCD
V
V
V
V
V
V
DD
2
COL 2
C2 (t)
3
4
5
LCD
V
op
0.261 V
op
V
(t)
0 V
state 1
0.261 V
op
V
V
op
op
0.478 V
op
op
0.261 V
V
(t)
0 V
state 2
0.261 V
op
0.478 V
op
V
op
MSA840
V
(t) = C1(t) R1(t):
general relationship (n = multiplex rate)
state 1
V
V
on(rms)
on(rms)
1
8
8
1
1
n
n
1
1
=
=
=
=
0.430
(
)
(
)
V
V
8
8
1
n
n
op
op
V
(t) = C2(t) R2(t):
state 2
V
off(rms)
(
)
n 1
n
2
2
V
(
)
1
n
V
op
off(rms)
(
)
1
2
8
=
=
0.297
2
(
)
V
8
8
1
op
Fig.6 LCD drive mode waveforms for 1 : 8 multiplex rate.
10
1997 Apr 01
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
state 1 (OFF)
state 2 (ON)
T
frame
V
V
V
V
V
V
DD
2
ROW 1
R1 (t)
3
4
5
LCD
V
V
V
V
V
V
DD
2
ROW 2
R2 (t)
3
4
5
LCD
V
V
V
V
V
V
DD
2
COL 1
C1 (t)
3
4
5
dot matrix
1:16 multiplex rate
LCD
V
V
V
V
V
V
DD
2
COL 2
C2 (t)
3
4
5
LCD
V
op
0.2 V
op
V
(t)
0 V
0.2 V
state 1
op
V
V
op
op
0.6 V
op
0.2 V
op
V
(t)
0 V
0.2 V
state 2
op
0.6 V
op
V
op
MSA836
V
(t) = C1(t) R1(t):
general relationship (n = multiplex rate)
state 1
V
V
on(rms)
on(rms)
1
16
(
1
1
n
n
1
1
=
=
=
=
0.316
)
(
)
V
V
16 16 16
1
n
n
op
op
V
V
(t) = C2(t) R2(t):
state 2
V
off(rms)
(
)
n 1
n
2
2
V
(
)
1
n
op
off(rms)
(
)
1
2
16
=
=
0.254
2
(
)
V
16 16
1
op
Fig.7 LCD drive mode waveforms for 1 : 16 multiplex rate.sa.
11
1997 Apr 01
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
7.3
Timing generator
7.10 RAM access
The timing generator of the PCF8579 organizes the
internal data flow from the RAM to the display drivers.
An external synchronization pulse SYNC is received from
the PCF8578. This signal maintains the correct timing
relationship between cascaded devices.
There are three RAM ACCESS modes:
• Character
• Half-graphic
• Full-graphic.
These modes are specified by bits G1 and G0 of the RAM
ACCESS command. The RAM ACCESS command
controls the order in which data is written to or read from
the RAM (see Fig.8).
7.4
Column drivers
Outputs C0 to C39 are column drivers which must be
connected to the LCD. Unused outputs should be left
open-circuit.
To store RAM data, the user specifies the location into
which the first byte will be loaded (see Fig.9):
7.5
Display RAM
• Device subaddress (specified by the DEVICE SELECT
The PCF8579 contains a 32 × 40-bit static RAM which
stores the display data. The RAM is divided into 4 banks of
40 bytes (4 × 8 × 40 bits). During RAM access, data is
transferred to/from the RAM via the I2C-bus.
command)
• RAM X-address (specified by the LOAD X-ADDRESS
command)
• RAM bank (specified by bits Y1 and Y0 of the RAM
ACCESS command).
7.6
Data pointer
Subsequent data bytes will be written or read according to
the chosen RAM access mode. Device subaddresses are
automatically incremented between devices until the last
device is reached. If the last device has subaddress 15,
further display data transfers will lead to a wrap-around of
the subaddress to 0.
The addressing mechanism for the display RAM is
realized using the data pointer. This allows an individual
data byte or a series of data bytes to be written into, or read
from, the display RAM, controlled by commands sent on
the I2C-bus.
7.7
Subaddress counter
7.11 Display control
The storage and retrieval of display data is dependent on
the content of the subaddress counter. Storage and
retrieval take place only when the contents of the
subaddress counter agree with the hardware subaddress
at pins A0, A1, A2 and A3.
The display is generated by continuously shifting rows of
RAM data to the dot matrix LCD via the column outputs.
The number of rows scanned depends on the multiplex
rate set by bits M1 and M0 of the SET MODE command.
The display status (all dots on/off and normal/inverse
video) is set by bits E1 and E0 of the SET MODE
command. For bank switching, the RAM bank
corresponding to the top of the display is set by bits
B1 and B0 of the SET START BANK command. This is
shown in Fig.10 This feature is useful when scrolling in
alphanumeric applications.
7.8
I2C-bus controller
The I2C-bus controller detects the I2C-bus protocol, slave
address, commands and display data bytes. It performs
the conversion of the data input (serial-to-parallel) and the
data output (parallel-to-serial). The PCF8579 acts as an
I2C-bus slave transmitter/receiver. Device selection
depends on the I2C-bus slave address, the hardware
subaddress and the commands transmitted.
7.12 TEST pin
The TEST pin must be connected to VSS
.
7.9
Input filters
To enhance noise immunity in electrically adverse
environments, RC low-pass filters are provided on the
SDA and SCL lines.
1997 Apr 01
12
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PCF8579
driver 1
PCF8579
driver 2
PCF8579
driver k
bank 0
bank 1
bank 2
bank 3
RAM
4 bytes
PCF8579 system RAM
LSB
40-bits
1
k
16
1 byte
0
1
2
3
4
5
6
7
8
9 10 11
character mode
MSB
0
1
2
3
4
5
6
7
8
9
10 12 14 16 18 20 22
11 13 15 17 19 21 23
2 bytes
half-graphic mode
0
1
2
3
4
5
6
7
8
9
12 16 20 24 28 32 36 40 44
13 17 21 25 29 33 37 41 45
4 bytes
10 14 18 22 26 30 34 38 42 46
11 15 19 23 27 31 35 39 43 47
MSA921
full-graphic mode
RAM data bytes are
written or read as
indicated above
Fig.8 RAM access mode.
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DEVICE SELECT:
subaddress 12
bank 0
bank 1
bank 2
bank 3
RAM ACCESS:
character mode
bank 1
RAM
LOAD X-ADDRESS: X-address = 8
R / W
slave address
S
A
0
READ
0
1
1
1
1
0
DATA
1
A
A
S
R / W
slave address
DEVICE SELECT
LOAD X-ADDRESS
RAM ACCESS
S
A
0
0
1
1
1
1
0
0
A
1
1
1
0
1
1
0
A
1
0
0
0
1
0
0
A
0
1
1
1
0
0
0
A
1
0
0
S
last command
DATA
A
DATA
A
WRITE
MSA835
Fig.9 Example of commands specifying initial data byte RAM locations.
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
RAM
bank 0
top of LCD
bank 1
LCD
bank 2
bank 3
MSA851
Fig.10 Relationship between display and SET START BANK; 1 : 32 multiplex rate and start bank = 2.
1997 Apr 01
15
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
I2C-BUS PROTOCOL
In READ mode, indicated by setting the read/write bit
HIGH, data bytes may be read from the RAM following the
slave address acknowlegement. After this
8
Two 7-bit slave addresses (0111100 and 0111101) are
reserved for both the PCF8578 and PCF8579. The least
significant bit of the slave address is set by connecting
input SA0 to either logic 0 (VSS) or logic 1 (VDD).
Therefore, two types of PCF8578 or PCF8579 can be
distinguished on the same I2C-bus which allows:
acknowlegement the master transmitter becomes a
master receiver and the PCF8579 becomes a slave
transmitter. The master receiver must acknowledge the
reception of each byte in turn. The master receiver must
signal an end of data to the slave transmitter, by not
generating an acknowledge on the last byte clocked out of
the slave. The slave transmitter then leaves the data line
HIGH, enabling the master to generate a stop
condition (P).
1. One PCF8578 to operate with up to 32 PCF8579s on
the same I2C-bus for very large applications.
2. The use of two types of LCD multiplex schemes on the
same I2C-bus.
Display bytes are written into, or read from, the RAM at the
address specified by the data pointer and subaddress
counter. Both the data pointer and subaddress counter are
automatically incremented, enabling a stream of data to be
transferred either to, or from, the intended devices.
In most applications the PCF8578 will have the same slave
address as the PCF8579.
The I2C-bus protocol is shown in Fig.11.
All communications are initiated with a start condition (S)
from the I2C-bus master, which is followed by the desired
slave address and read/write bit. All devices with this slave
address acknowledge in parallel. All other devices ignore
the bus transfer.
In multiple device applications, the hardware subaddress
pins of the PCF8579s (A0 to A3) are connected to VSS or
VDD to represent the desired hardware subaddress code.
If two or more devices share the same slave address, then
each device must be allocated a unique hardware
subaddress.
In WRITE mode (indicated by setting the read/write bit
LOW) one or more commands follow the slave address
acknowlegement. The commands are also acknowledged
by all addressed devices on the bus.
The last command must clear the continuation bit C. After
the last command a series of data bytes may follow.
The acknowlegement after each byte is made only by the
(A0, A1, A2 and A3) addressed PCF8579 or PCF8578
with its implicit subaddress 0. After the last data byte has
been acknowledged, the I2C-bus master issues a stop
condition (P).
1997 Apr 01
16
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
acknowledge
acknowledge by
all addressed
PCF8578s / PCF8579s
by A0, A1, A2 and A3
selected PCF8578s /
PCF8579s only
R / W
slave address
S
A
0
0
1
1
1
1
0
0
A C
A
DISPLAY DATA
A
P
COMMAND
0 byte(s)
S
1 byte
n
n
0 byte(s)
update data pointers
and if necessary,
subaddress counter
MSA830
(a)
acknowledge by
all addressed
PCF8578s / PCF8579s
acknowledge
from master
no acknowledge
from master
slave address
slave address
S
A
0
S
A
0
0
1
1
1
1
0
0
A
C
A
0
1
1
1
1
0
1
A
DATA
A
DATA
1
COMMAND
P
S
S
n
1 byte
n bytes
last byte
R / W
R / W
at this moment master
transmitter becomes a
master receiver and
PCF8578/PCF8579 slave
receiver becomes a
slave transmitter
update data pointers
and if necessary
subaddress counter
MSA832
(b)
acknowledge by
all addressed
PCF8578s / PCF8579s
acknowledge
from master
no acknowledge
from master
slave address
S
A
0
0
1
1
1
1
0
1
A
A
DATA
1
S
DATA
P
MSA831
n bytes
last byte
R / W
update data pointers
and if necessary,
subaddress counter
(c)
Fig.11 (a) Master transmits to slave receiver (WRITE mode); (b) Master reads after sending command string
(WRITE commands; READ data); (c) Master reads slave immediately after sending slave address (READ
mode).
1997 Apr 01
17
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
8.1
Command decoder
MSB
LSB
The command decoder identifies command bytes that
arrive on the I2C-bus. The most significant bit of a
command is the continuation bit C (see Fig.12). When this
bit is set, it indicates that the next byte to be transferred will
also be a command. If the bit is reset, it indicates the
conclusion of the command transfer. Further bytes will be
regarded as display data. Commands are transferred in
WRITE mode only.
C
REST OF OPCODE
MSA833
C = 0; last command.
C = 1; commands continue.
Fig.12 General format of command byte.
The five commands available to the PCF8579 are defined
in Tables 2 and 3.
Table 2 Summary of commands
COMMAND
SET MODE
OPCODE(1)
DESCRIPTION
C
C
C
C
1
1
1
1
0
1
1
1
D
1
0
1
D
1
D
1
D
D
D
D
D
D
D
D
multiplex rate, display status, system type
defines bank at top of LCD
SET START BANK
DEVICE SELECT
RAM ACCESS
D
D
D
D
defines device subaddress
graphic mode, bank select (D D D D ≥ 12 is not allowed;
see SET START BANK opcode)
LOAD X-ADDRESS
C
0
D
D
D
D
D
D
0 to 39
Note
1. C = command continuation bit. D = may be a logic 1 or 0.
1997 Apr 01
18
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
Table 3 Definition of PCF8578/PCF8579 commands
COMMAND
SET MODE
OPCODE
OPTIONS
DESCRIPTION
C
C
1
1
0
1
T
E1 E0 M1 M0 see Table 4 defines LCD drive mode
see Table 5 defines display status
see Table 6 defines system type
SET START BANK
DEVICE SELECT
RAM ACCESS
1
1
1
B1 B0 see Table 7 defines pointer to RAM bank
corresponding to the top of the LCD;
useful for scrolling, pseudo motion and
background preparation of new display
C
C
1
1
1
1
0
1
A3 A2 A1 A0 see Table 8 four bits of immediate data, bits
A0 to A3, are transferred to the
subaddress counter to define one of
sixteen hardware subaddresses
G1 G0 Y1 Y0 see Table 9 defines the auto-increment behaviour of
the address for RAM access
see Table 10 two bits of immediate data, bits Y0 to Y1,
are transferred to the X-address pointer
to define one of forty display RAM
columns
LOAD X-ADDRESS C
0
X5 X4 X3 X2 X1 X0 see Table 11 six bits of immediate data, bits X0 to X5,
are transferred to the X-address pointer
to define one of forty display RAM
columns
1997 Apr 01
19
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
Table 4 Set mode option 1
Table 8 Device select option 1
BITS
BITS
BIT T
DESCRIPTION
BITS
LCD DRIVE MODE
Decimal value of 0 to 15
A3
A2
A1
A0
M1
M0
1 : 8
MUX ( 8 rows)
MUX (16 rows)
MUX (24 rows)
MUX (32 rows)
0
1
1
0
1
0
1
0
Table 9 RAM access option 1
1 : 16
1 : 24
1 : 32
BITS
RAM ACCESS MODE
G1
G0
Character
0
0
1
1
0
1
0
1
Table 5 Set mode option 2
Half-graphic
Full-graphic
DISPLAY STATUS
Not allowed (note 1)
E1
E0
Blank
0
0
1
1
0
1
0
1
Note
Normal
1. See opcode for SET START BANK in Table 3.
All segments on
Inverse video
Table 10 RAM access option 2
DESCRIPTION
BITS
Table 6 Set mode option 3
Decimal value of 0 to 3
Y1
Y0
SYSTEM TYPE
Table 11 Load X-address option 1
PCF8578 row only
0
1
PCF8578 mixed mode
DESCRIPTION
BITS
Decimal value of 0 to 39
X5 X4 X3 X2 X1 X0
Table 7 Set start bank option 1
BITS
START BANK POINTER
B1
B0
Bank 0
Bank 1
Bank 2
Bank 3
0
0
1
1
0
1
0
1
1997 Apr 01
20
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
CHARACTERISTICS OF THE I2C-BUS
9.4
Acknowledge
9
The I2C-bus is for bidirectional, two-line communication
between different ICs or modules. The two lines are a
serial data line (SDA) and a serial clock line (SCL) which
must be connected to a positive supply via a pull-up
resistor. Data transfer may be initiated only when the bus
is not busy.
The number of data bytes transferred between the start
and stop conditions from transmitter to receiver is
unlimited. Each data byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put
on the bus by the transmitter, whereas the master
generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. Also a
master must generate an acknowledge after the reception
of each byte that has been clocked out of the slave
transmitter. The device that acknowledges must pull down
the SDA line during the acknowledge clock pulse, so that
the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times
must be taken into consideration). A master receiver must
signal the end of a data transmission to the transmitter by
not generating an acknowledge on the last byte that has
been clocked out of the slave. In this event the transmitter
must leave the data line HIGH to enable the master to
generate a stop condition.
9.1
Bit transfer
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this moment will be interpreted as control signals.
9.2
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH, is defined as the start condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH, is defined as the stop condition (P).
9.3
System configuration
A device transmitting a message is a ‘transmitter’, a device
receiving a message is the ‘receiver’. The device that
controls the message flow is the ‘master’ and the devices
which are controlled by the master are the ‘slaves’.
SDA
SCL
data line
stable;
data valid
change
of data
allowed
MBA607
Fig.13 Bit transfer.
1997 Apr 01
21
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
SDA
SDA
SCL
SCL
S
P
STOP condition
START condition
MBA608
Fig.14 Definition of start and stop condition.
SDA
SCL
MASTER
TRANSMITTER /
RECEIVER
SLAVE
TRANSMITTER /
RECEIVER
MASTER
TRANSMITTER /
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER
MBA605
Fig.15 System configuration.
clock pulse for
acknowledgement
START
condition
SCL FROM
MASTER
2
9
1
8
DATA OUTPUT
BY TRANSMITTER
S
DATA OUTPUT
BY RECEIVER
MBA606 - 1
The general characteristics and detailed specification of the I2C-bus are available on request.
Fig.16 Acknowledgement on the I2C-bus.
22
1997 Apr 01
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
10 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VDD
PARAMETER
MIN.
−0.5
MAX.
UNIT
supply voltage
+8.0
V
V
V
VLCD
Vi1
LCD supply voltage
VDD − 11
SS − 0.5
VDD
input voltage pins SDA, SCL, SYNC, CLK, TEST, SA0, A0,
A1, A2 and A3
V
VDD + 0.5
Vi2
Vo1
Vo2
II
input voltage pins V3 and V4
output voltage pin SDA
output voltage pins C0 to C39
DC input current
V
V
V
LCD − 0.5
SS − 0.5
LCD − 0.5
VDD + 0.5
VDD + 0.5
VDD + 0.5
+10
V
V
V
−10
−10
−50
−
mA
mA
mA
IO
DC output current
+10
IDD, ISS, ILCD current at pins VDD, VSS or VLCD
+50
Ptot
Po
Tstg
total power dissipation per package
power dissipation per output
storage temperature
400
mW
mW
°C
−
100
−65
+150
11 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe it is
desirable to take normal precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC12
under “Handling MOS Devices”.
1997 Apr 01
23
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
12 DC CHARACTERISTICS
VDD = 2.5 to 6 V; VSS = 0 V; VLCD = VDD − 3.5 V to VDD − 9 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDD
VLCD
IDD
supply voltage
2.5
−
6.0
DD − 3.5
V
LCD supply voltage
supply current
V
−
−
DD − 9
−
V
V
fCLK = 2 kHz; note 1
note 2
9
20
µA
V
VPOR
power-on reset level
1.3
1.8
Logic
VIL
VIH
ILI1
LOW level input voltage
HIGH level input voltage
VSS
−
−
−
0.3VDD
VDD
V
0.7VDD
−1
V
leakage current at pins SDA, SCL,
SYNC, CLK, TEST, SA0, A0, A1, A2
and A3
Vi = VDD or VSS
+1
µA
IOL
Ci
LOW level output current at pin SDA
input capacitance
VOL = 0.4 V; VDD = 5 V 3
−
−
−
mA
pF
note 3
−
5
LCD outputs
ILI2
leakage current at pins V3 to V4
Vi = VDD or VLCD
−2
−
+2
µA
VDC
DC component of LCD drivers pins
C0 to C39
−
±20
−
mV
RCOL
output resistance at pins C0 to C39
note 4
−
3
6
kΩ
Notes
1. Outputs are open; inputs at VDD or VSS; I2C-bus inactive; clock with 50% duty factor.
2. Resets all logic when VDD < VPOR
3. Periodically sampled; not 100% tested.
.
4. Resistance measured between output terminal (C0 to C39) and bias input (V3, V4, VDD and VLCD) when the specified
current flows through one output under the following conditions (see Table 1):
a) − Vop = VDD − VLCD = 9 V;
b) − V3 − VLCD ≥ 4.70 V; V4 − VLCD ≤ 4.30 V; ILOAD = 100 µA.
1997 Apr 01
24
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
13 AC CHARACTERISTICS
All timing values are referred to VIH and VIL levels with an input voltage swing of VSS to VDD
.
V
DD = 2.5 to 6 V; VSS = 0 V; VLCD = VDD − 3.5 V to VDD − 9 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX.
fclk clock frequency 50% duty factor note 1 10
DD − VLCD = 9 V; with test loads
UNIT
kHz
−
−
tPLCD
driver delays
V
−
100
µs
I2C-bus
fSCL
SCL clock frequency
tolerable spike width on bus
bus free time
−
−
−
−
−
−
−
−
−
−
−
−
−
−
100
100
−
kHz
ns
µs
µs
µs
µs
µs
µs
µs
ns
ns
µs
tSW
tBUF
4.7
4.7
4.0
4.7
4.0
−
tSU;STA
tHD;STA
tLOW
tHIGH
tr
START condition set-up time
START condition hold time
SCL LOW time
repeated start codes only
−
−
−
SCL HIGH time
−
SCL and SDA rise time
SCL and SDA fall time
data set-up time
1.0
0.3
−
tf
−
tSU;DAT
tHD;DAT
tSU;STO
250
0
data hold time
−
STOP condition set-up time
4.0
−
Note
1. Typically 0.9 to 3.3 kHz.
1.5 kΩ
SDA
V
DD
(2%)
1 nF
C0 to C39
MSA916
Fig.17 AC test loads.
1997 Apr 01
25
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
1/ f
CLK
0.7 V
0.3 V
DD
DD
CLK
0.5 V
(V
V
= 9 V)
C0 to C39
DD
LCD
t
0.5 V
PLCD
MSA917
Fig.18 Driver timing waveforms.
k
SDA
SCL
SDA
t
t
t
f
BUF
LOW
t
t
t
SU;DAT
t
HD;STA
r
t
HIGH
HD;DAT
t
SU;STA
MGA728
t
SU;STO
Fig.19 I2C-bus timing waveforms.
26
1997 Apr 01
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V
DD
V
DD
1:32 multiplex rate
32 x 40 x k dots (k 16)
(20480 dots max.)
32
R
C
C
C
C
C
LCD DISPLAY
subaddress 0
V
2
rows
R
(4
R
R
V
3
8
2
3)R
40
columns
40
columns
40
columns
PCF8578
(ROW MODE)
V
unused columns
4
subaddress 1
subaddress k 1
V
5
V
DD
V
V
V
V
V
A0
A1
A2
A3
A0
A1
A2
A3
A0
SA0
V
R
DD
DD
DD
DD
DD
SS
V
A1
A2
A3
LCD
SS
V
V
V
V
V
V
2
k
1
LCD
LCD
LCD
PCF8579
PCF8579
PCF8579
3
3
3
V
LCD
V
OSC
V
V
V
V
4
4
4
V
V
CLK SYNC
SYNC CLK
SYNC CLK
SYNC CLK
V
SDA SCL
SS
SCL SDA SA0
SS
SCL SDA SA0
SS
SCL SDA SA0
V
SS
OSC
SS
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
V
DD
SCL
SDA
MSA845
Fig.20 Typical LCD driver system with 1 : 32 multiplex rate.
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V
V
V
DD
V
V
V
V
V
V
DD
SS
DD
SS
SS
SA0 SDA SCL
A3
SYNC
SA0 SDA SCL
A3
SYNC
SA0 SDA SCL
A3
SYNC
CLK
k
CLK
2
CLK
1
SS
SS
SS
V
3
V
3
V
3
A2
A2
A2
V
4
V
4
V
4
PCF8579
PCF8579
PCF8579
A1
A0
V
A1
A0
V
A1
A0
V
LCD
LCD
LCD
V
V
V
V
V
V
DD
DD
DD
DD
DD
subaddress 0
DD
40
columns
40
columns
40
columns
subaddress k
1
subaddress 1
V
DD
R
16
1:16 multiplex rate
16 x 40 x k dots (k 16)
(10240 dots max.)
V
V
V
LCD DISPLAY
DD
rows
C
C
C
C
C
2
16
1:16 multiplex rate
16 x 40 x k dots (k 16)
(10240 dots max.)
R
R
R
R
rows
3
8
40
columns
40
columns
40
columns
PCF8578
(ROW MODE)
V
4
subaddress 0
subaddress 1
V
subaddress k 1
unused columns
V
5
V
DD
V
A0
A1
A2
V
V
A0
A1
A2
A3
V
A0
SA0
DD
DD
DD
DD
DD
V
V
/
SS DD
V
A1
A2
A3
LCD
SS
V
V
V
V
V
V
2
k
1
LCD
LCD
LCD
PCF8579
PCF8579
PCF8579
3
3
3
V
LCD
V
OSC
V
V
A3
V
V
4
4
4
R
V
V
SCL CLK SYNC
SYNC CLK SCL
SYNC CLK SCL
SYNC CLK SCL
V
SDA
SS
SDA SA0
SS
SDA SA0
V
SS
SDA SA0
V
SS
OSC
SS
V
V
V
V
V
SS
SS
SS
SS
SS
SS
V
DD
SCL
SDA
MSA847
Fig.21 Split screen application with 1 : 16 multiplex rate for improved contrast.
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V
V
V
DD
V
V
V
V
V
V
DD
SS
DD
SS
SS
SA0 SDA SCL
A3
SYNC
SA0 SDA SCL
A3
SYNC
SA0 SDA SCL
A3
SYNC
CLK
k
CLK
2
CLK
1
SS
SS
SS
V
3
V
3
V
3
A2
A2
A2
V
4
V
4
V
4
PCF8579
PCF8579
PCF8579
A1
A0
V
A1
A0
V
A1
A0
V
LCD
LCD
LCD
V
V
V
V
V
V
DD
DD
DD
DD
DD
subaddress 0
DD
40
columns
40
columns
40
columns
subaddress k
1
subaddress 1
V
DD
1:32 multiplex rate
32 x 40 x k dots (k 16)
(20480 dots max.)
V
V
V
LCD DISPLAY
DD
R
R
C
C
C
C
C
32
2
32
1:32 multiplex rate
32 x 40 x k dots (k 16)
(20480 dots max.)
(4
2 3)R
rows
3
8
40
40
columns
40
columns
PCF8578
(ROW MODE)
V
4
columns
subaddress 0
subaddress 1
V
subaddress k 1
unused columns
R
R
V
5
V
DD
V
A0
A1
A2
V
V
A0
A1
A2
A3
V
A0
SA0
DD
DD
DD
DD
DD
V
V
/
SS DD
V
A1
A2
A3
LCD
SS
V
V
V
V
V
V
2
k
1
LCD
LCD
LCD
PCF8579
PCF8579
PCF8579
3
3
3
V
LCD
V
OSC
V
V
A3
V
V
4
4
4
R
V
V
SCL CLK SYNC
SYNC CLK SCL
SYNC CLK SCL
SYNC CLK SCL
V
SDA
SS
SDA SA0
SS
SDA SA0
V
SS
SDA SA0
V
SS
OSC
SS
V
V
V
V
V
SS
SS
SS
SS
SS
SS
V
DD
SCL
SDA
MSA846
Fig.22 Split screen application with 1 : 32 multiplex rate.
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V
SS
V
SCL
SDA
DD
V
LCD
R0
R
R
OSC
R
(4
2 3)R
R
R
n.c.
n.c.
LCD DISPLAY
PCF8578
R31/C31
C0
C27
C28
C39
C0
C27
C28
C39
PCF8579
PCF8579
to other
PCF8579s
MSA852
Fig.23 Example of single plane wiring, single screen with 1 : 32 multiplex rate (PCF8578 in row driver mode).
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
15 CHIP DIMENSIONS AND BONDING PAD LOCATIONS
y
8
9
7
6
5
4
3
2
1
56 55 54 53 52
51
A2
C5
10
11
A1
A0
50
49
48
C6
C7
C8
C9
47
46
C10
C11
V
12
13
DD
45
n.c.
V
3
14
15
44
43
C12
C13
V
4
4.76
mm
0
x
V
0
16
C14
42
LCD
41
40
C15
C16
39
38
37
C17
C18
C19
C20
PCF8579
C39
C38
C37
17
18
19
20
36
35
C21
C22
34
C36
21
22
23
24 25
26
27
28 29
30
31
32 33
MSA920
3.02 mm
Chip area: 14.37 mm2.
Bonding pad dimensions: 120 µm × 120 µm.
Gold bump dimensions (if ordered): 94 × 94 × 25 µm.
The numbers given in the square boxes refer to the pad number.
Fig.24 Bonding pad locations.
31
1997 Apr 01
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
Table 12 Bonding pad locations (dimensions in µm)
All x/y coordinates are referenced to centre of chip, see Fig.24.
PINS
PAD NUMBER
SYMBOL
x
y
VSO56
LQFP64
1
SDA
SCL
SYNC
CLK
VSS
TEST
SA0
A3
252
48
2142
2142
1
7
2
2
8
3
−156
−360
−564
−786
−1032
−1314
−1314
−1314
−1314
−1314
−1314
−1314
−1314
−1314
−1314
−1314
−1314
−1314
−1314
−1032
−786
−564
−360
−156
48
2142
3
9
4
2142
4
10
11
12
13
14
16
17
18
20
21
22
23
24
30
31
32
33
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
5
2142
5
6
2142
6
7
2142
7
8
2142
8
9
A2
1920
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
A1
1716
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
A0
1512
VDD
n.c.
708
504
V3
300
V4
96
VLCD
C39
C38
C37
C36
C35
C34
C33
C32
C31
C30
C29
C28
C27
C26
C25
C24
C23
C22
C21
C20
C19
−108
−1308
−1512
−1716
−1920
−2142
−2142
−2142
−2142
−2142
−2142
−2142
−2142
−2142
−2142
−2142
−2142
−2142
−1830
−1570
−1326
−1122
252
498
702
906
1110
1314
1314
1314
1314
1314
1997 Apr 01
32
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
PINS
PAD NUMBER
SYMBOL
x
y
VSO56
LQFP64
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
−
C18
C17
C16
C15
C14
C13
C12
C11
C10
C9
1314
1314
1314
1314
1314
1314
1314
1314
1314
1314
1314
1314
1314
1314
1314
1110
906
−918
−714
−510
−306
−102
102
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
−
52
53
54
55
56
57
58
59
60
61
62
63
64
1
306
510
714
918
C8
1122
1326
1566
1830
2142
2142
2142
2142
2142
−
C7
C6
C5
C4
2
C3
3
C2
4
C1
702
5
C0
498
6
n.c.
−
15, 19, 21,
25 to 29, 34
1997 Apr 01
33
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V
V
DD
DD
V
3
V
4
V
LCD
V
SS
CLK
SYNC
SCL
SDA
V
3
V
4
V
LCD
V
SS
CLK
SYNC
SCL
SDA
PCF8578
PCF8579
R0 to R31
C0 C1 C2
LCD
DISPLAY
MSA850
If inputs SA0 and A0 to A3 are left unconnected they are internally pulled-up to VDD
.
Fig.25 Typical chip-on glass application (viewed from underside of chip).
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
17 PACKAGE OUTLINES
VSO56: plastic very small outline package; 56 leads
SOT190-1
D
E
A
X
c
y
H
v
M
A
E
Z
56
29
Q
p
A
2
A
(A )
3
A
1
pin 1 index
θ
L
L
detail X
1
28
w
M
b
p
e
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(2)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
0.3
0.1
3.0
2.8
0.42
0.30
0.22 21.65 11.1
0.14 21.35 11.0
15.8
15.2
1.6
1.4
1.45
1.30
0.90
0.55
3.3
0.25
0.01
0.75
2.25
0.2
0.1
0.1
7o
0o
0.012 0.12
0.004 0.11
0.017 0.0087 0.85
0.012 0.0055 0.84
0.44
0.43
0.62
0.60
0.063 0.057
0.055 0.051
0.035
0.022
inches
0.008 0.004 0.004
0.0295
0.089
0.13
Note
1. Plastic or metal protrusions of 0.3 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
96-04-02
97-08-11
SOT190-1
1997 Apr 01
35
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm
SOT314-2
y
X
A
48
33
Z
49
32
E
e
H
A
E
2
E
A
(A )
3
A
1
w M
p
θ
b
L
p
pin 1 index
L
64
17
detail X
1
16
Z
v
M
A
D
e
w M
b
p
D
B
H
v
M
B
D
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.20 1.45
0.05 1.35
0.27 0.18 10.1 10.1
0.17 0.12 9.9 9.9
12.15 12.15
11.85 11.85
0.75
0.45
1.45 1.45
1.05 1.05
1.60
mm
0.25
0.5
1.0
0.2 0.12 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-12-19
97-08-01
SOT314-2
1997 Apr 01
36
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
18 SOLDERING
18.1 Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Even with these conditions, do not consider wave
soldering LQFP packages LQFP48 (SOT313-2),
LQFP64 (SOT314-2) or LQFP80 (SOT315-1).
18.3.2 VSO
Wave soldering techniques can be used for all VSO
packages if the following conditions are observed:
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
18.2 Reflow soldering
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
Reflow soldering techniques are suitable for all LQFP and
VSO packages.
• The package footprint must incorporate solder thieves at
the downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
18.3.3 METHOD (LQFP AND VSO)
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
18.3 Wave soldering
18.3.1 LQFP
18.4 Repairing soldered joints
Wave soldering is not recommended for LQFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
If wave soldering cannot be avoided, the following
conditions must be observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
1997 Apr 01
37
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
19 DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
20 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
21 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1997 Apr 01
38
Philips Semiconductors
Product specification
LCD column driver for dot matrix graphic
displays
PCF8579
NOTES
1997 Apr 01
39
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Internet: http://www.semiconductors.philips.com
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1997
SCA53
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
417067/1200/03/pp40
Date of release: 1997 Apr 01
Document order number: 9397 750 01757
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The PCF8579 is a low power CMOS LCD column driver, designed to drive dot matrix graphic displays at multiplex rates of 1 : 8, 1 : 16, 1 :
24 or 1 : 32. The device has 40 outputs and can drive 32 x 40 dots in a 32 row multiplexed LCD. Up to 16 PCF8579s can be cascaded and
up to 32 devices may be used on the same I2C-bus (using the two slave addresses). The device is optimized for use with the PCF8578
LCD row/column driver. Together these two devices form a general purpose LCD dot matrix driver chip set, capable of driving displays of
up to 40960 dots. The PCF8579 is compatible with most microcontrollers and communicates via a two-line bidirectional bus (I2C-bus). To
allow partial VDD shutdown the ESD protection system of the SCL and SDA pins does not use a diode connected to VDD . Communication
Cross reference
Models
Packages
Application notes
Selection guides
Other technical documentation
End of Life information
Datahandbook system
overheads are minimized by a display RAM with auto-incremented addressing and display bank switching.
Features
l LCD column driver
l Used in conjunction with the PCF8578, this device forms part of a chip set capable of driving up to 40960 dots
l 40 column outputs
l Selectable multiplex rates; 1 : 8, 1 : 16, 1 : 24 or 1 : 32
l Externally selectable bias configuration, 5 or 6 levels
l Easily cascadable for large applications (up to 32 devices)
l 1280-bit RAM for display data storage
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PCF8579
PCF8579
l Display memory bank switching
l Auto-incremented data loading across hardware subaddress boundaries (with PCF8578)
l Power-on reset blanks display
l Logic voltage supply range 2.5 to 6 V
l Maximum LCD supply voltage 9 V
l Low power consumption
l I2C-bus interface
l TTL/CMOS compatible
l Compatible with most microcontrollers
l Optimized pinning for single plane wiring in multiple device applications (with PCF8578)
l Space saving 56-lead plastic mini-pack and 64-pin plastic low profile quad flat package
l Compatible with chip-on-glass technology
l I2C-bus address: 011110 SA0.
Applications
l Automotive information systems
l Telecommunication systems
l Point-of-sale terminals
l Computer terminals
l Instrumentation.
Datasheet
File
size
(kB)
Publication
release date Datasheet status
Page
count
Type nr. Title
Datasheet
Download
PCF8579 LCD column driver for dot matrix
graphic displays
01-Apr-97
Product
Specification
40
287
Blockdiagram
Blockdiagram of PCF8579T
Products, packages, availability and ordering
North American
Partnumber
Order code
(12nc)
Partnumber
marking/packing
package device status buy online
Standard Marking * Tray Dry Pack,
Bakeable, Multiple
PCF8579H/F1 PCF8579HBD
9351 987 80557
SOT314 Full production
SOT190 Full production
SOT190 Full production
PCF8579T
PCF8579TD
9339 646 30112 Standard Marking * Bulk Pack
Standard Marking * Reel Pack,
PCF8579TD-T
9339 646 30118
SMD, 13"
No Marking * Chips on Wafer, Pre-
PCF8579U/10
PCF8579U/12
PCF8579U/2/F1
PCF8579U/F1
9350 141 10005
9350 642 10005
9352 631 81026
9352 633 16026
NONE
NONE
NONE
NONE
Full production
Full production
Full production
Development
-
-
-
-
Sawn, On FFC
No Marking * Chips on Wafer, Pre-
Sawn, On FFC
No Marking * Die In Waffle
Carriers
No Marking * Die In Waffle
Carriers
Please read information about some discontinued variants of this product.
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