935263011112 [NXP]

IC SPECIALTY TELECOM CIRCUIT, PDSO16, PLASTIC, SOT-162, SO-16, Telecom IC:Other;


型号：	935263011112
厂家：	NXP
描述：	IC SPECIALTY TELECOM CIRCUIT, PDSO16, PLASTIC, SOT-162, SO-16, Telecom IC:Other 电信光电二极管电信集成电路
文件：	总33页 (文件大小：574K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PCD3316

Caller-ID on Call Waiting (CIDCW) receiver

11 March 1999

Product speciﬁcation

1. General description

The PCD3316 is a low power mixed signal CMOS integrated circuit for receiving

physical layer signals like Bellcore’s ‘CPE¹Alerting Signal (CAS)’ and the signals

used in similar services. The device is capable of a very high precision detection of

the dual tone (2130 and 2750 Hz) by using a patented digital algorithm. The

PCD3316 can be used for on-hook and off-hook Caller-ID (CID), Caller-ID on Call

Waiting (CIDCW) and Caller-Name (CNAM) applications.

For timing purposes the PCD3316 can be programmed to generate an interrupt

signal to the microcontroller every second or every minute. These timings are derived

from an on-chip 32.768 kHz oscillator.

Also incorporated in the device are a Frequency Shift Keying (FSK)

receiver/demodulator and a ‘Ring or polarity change detector’. The status of the

PCD3316, the received FSK data bytes and the ringer period can be read and many

options can be selected via the I²C-bus serial interface. Two on-chip oscillators are

available. One 3.58 MHz oscillator for all internal functions and a low frequency

32.768 kHz oscillator for the 1 second or 1 minute timing.

In Power-down mode only the polarity comparators and the 32.768 kHz oscillator are

active. The CAS detection, the FSK receiver and the 3.58 MHz oscillator can be

enabled separately. Detection of a polarity change on the inputs POL0 or POL1, the

reception of an FSK data byte, the detection of a CAS tone or a timebase interrupt is

signalled to the microcontroller by an interrupt request signal (IRQ). The

microcontroller can communicate with the PCD3316 device via the serial interface.

The PCD3316 is designed for use in a microcontroller controlled system. The device

is available in a SO16 package.

A demonstration board OM5843 and an application note AN98071 are available.

1. CPE = Customer Premises Equipment.

PCD3316

Philips Semiconductors

CIDCW receiver

2. Features

■ Bellcore’s ‘CPE Alerting Signal (CAS)’ and British Telecom’s (BT) ‘Loop State

Tone Alert Signal’ detection

■ BT’s ‘Idle State Tone Alert Signal’ by means of monitoring the input signal level

■ 1200 baud FSK demodulator conform Bell 202 and CCITT V23 standards

■ Ring or polarity change detector

■ Ring period measurement

■ Low battery comparator

■ Signal level detector

■ On-hook and off-hook applications according to Bellcore TR-NWT-000030 and

SR-TSV-002476 speciﬁcations

■ Receive sensitivity of −37.8 dBm (in 600 Ω) for CAS

■ 2.5 to 3.6 V supply; low power standby mode

■ Selectable 1 second or 1 minute timebase interrupt

■ 3.58 MHz and 32.768 kHz crystal oscillators

■ SO16 package.

3. Applications

■ Analog Display Services Interface (ADSI) phones

■ Feature phones and adjunct boxes with Bellcore CID, CIDCW and CNAM systems

■ Computer Telephony Integrated (CTI) systems.

4. Ordering information

Table 1: Ordering information

Type number

Package

Name

Description

Version

PCD3316T

SO16

plastic small outline package; 16 leads; body width 7.5 mm

SOT162-1

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CIDCW receiver

5. Block diagram

handbook, full pagewidth

FSKIN+

FSKIN−

PREPROCESSOR

CASIN

HXIN

3.58 MHz

OSCILLATOR

LEVEL

DETECT

TIMING

CAS

FSK

HXOUT

IRQ

CONTROL

POR

SCL

SDA

I C-BUS

INTERFACE

LOWBAT

POL0

POL1

PCD3316

LXIN

VOLTAGE

REFERENCE

TIME

BASE

32.768 kHz

OSCILLATOR

LXOUT

MBH983

DGND

AGND

Fig 1. Block diagram.

6. Pinning information

6.1 Pinning

handbook, halfpage

HXIN

HXOUT

IRQ

15 FSKIN+

FSKIN−

SCL

CASIN

PCD3316

SDA

12 LOWBAT

11 POL0

LXIN

LXOUT

DGND

10 POL1

AGND

MBH980

Fig 2. Pin conﬁguration.

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6.2 Pin description

Table 2: Pin description

Symbol

HXIN

I/O

Description

3.58 MHz crystal oscillator input

3.58 MHz crystal oscillator output

HXOUT

IRQ

interrupt output; programmable active HIGH or active LOW

serial clock line of I²C-bus

serial data line of I²C-bus

32.768 kHz crystal oscillator input

32.768 kHz crystal oscillator output

digital ground

SCL

SDA

I/O

LXIN

LXOUT

DGND

AGND

POL1

POL0

LOWBAT

CASIN

FSKIN−

FSKIN+

V_DD

−

analog ground

polarity detector input 1

polarity detector input 0

low battery detector input

input pin for CAS signal

negative input for FSK signal

positive input for FSK signal

supply

−

7. Functional description

7.1 Preprocessor and analog inputs

The preprocessor for the CAS detection and the FSK receiver incorporates an

Analog-to-Digital Converter (ADC) and a digital bandpass ﬁlter.

The LOWBAT input of the PCD3316 can be used for low battery detection. The

voltage on the LOWBAT pin is compared with an internal voltage reference circuit.

When the LOWBAT voltage drops below the reference voltage, the Status register,

bit 5 is set to logic 1.

The PCD3316 can be forced in a Power-down state by switching off the 3.58 MHz

system clock and the ADC. This is done by setting Mode register 2, bit 7 (CIDMD2.7)

to logic 0. To guarantee correct operation the following order of actions must be

performed (see also Section 7.8 about interrupts):

1. Switch off CAS and FSK detection (if turned on)

2. Read the interrupt register (thus clearing pending interrupts generated by the

CAS and FSK detector)

3. Switch off the 3.58 MHz oscillator by clearing bit 7 of Mode register 2.

The two low power comparators (inputs POL0 and POL1) and the 32.768 kHz clock

are always active.

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They can be used for ring or line polarity reversal detection. The POL on/off bit (Mode

change occurs. The result of the two comparators can be read in bits 7 and 6 (POL0

and POL1) of the Status register (see Section 7.4). The 3.58 MHz clock is not needed

for the generation of a polarity interrupt.

7.2 CAS detection

After a power-on reset or after enabling the CAS detector the internal registers of the

CAS detection function are initialized. The initialization takes a maximum of

100 periods of the 3.58 MHz clock.

If the CAS detection is enabled the PCD3316 will generate an interrupt (Interrupt

Interrupts will be blocked when the signal level on the CAS input is below the

threshold in the level detector.

7.3 FSK reception

The FSK receiver function can be enabled by setting the FSK on/off bit (Mode

In the FSK transmission speciﬁcation of BT and Bellcore a channel seizure is

transmitted ﬁrst (sequence of 1010..). After the channel seizure a block of marks and

ﬁnally the data pattern are sent (see Figure 3). These mark bits are detected by the

PCD3316 which sets the FSK-BOM Indication bit (Status register, bit 4). The

FSK-BOM Indication bit is reset when the FSK receiver is disabled.

FSK transmission

mark

width

channel seizure

data

FSK-BOM

MBH979

Fig 3. FSK transmission speciﬁcation.

If the FSK-BOM Indication bit is set, the FSK receiver will generate an interrupt after it

has received a complete data word. An FSK data word consists of one start bit

(space), followed by eight data bits and one stop bit (mark). Interrupts will therefore

not be generated during the channel seizure and during the block of marks. When a

valid data word has been received, FSK data is available in the FSK data register.

By clearing the FSK-BOM-mask on/off bit (Mode register 1, bit 6), the FSK receiver

will not wait with the generation of interrupts until a Begin Of Mark (BOM) has been

detected but will handle the channel seizure as normal data. The block of marks

which is a string of logic 1 will still not generate interrupts because there are no start

bits.

After the generation of an interrupt the IRQ pin will become active (see Figure 4), and

the FSK Interrupt bit is set (Interrupt register, bit 5). The received data is available in

the FSK data register.

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handbook, full pagewidth

START

STOP

IRQ

read by

serial interface

MBH981

Fig 4. IRQ generation after reading a valid data byte.

The FSK-OVR Error bit (Status register, bit 3) indicates that a previous byte is lost

due to an overrun. The FSK-FRM Error bit (Status register, bit 2) indicates an

incorrect start- or stop-bit. These frame errors indicate that there are synchronization

problems. The on-chip level detector can be used to detect a carrier loss during FSK

transmission. FSK data can be rejected when the signal level is below the reference

level, this to avoid that noise is interpreted as data (Interrupt register, bit 4 is logic 1).

7.4 Ring or polarity change detector

For ring and polarity change detection two comparators are available in the

PCD3316. The reference level of the comparators is set internally by the reference

voltage generator. The voltage levels on the two polarity comparator inputs, POL0

and POL1, are compared with the reference voltage V_ref. If POL0 < V_refor

POL1 > V_ref, POL0 and POL1 (Status register, bit 7 and 6) are set respectively and

reset if POL0 > V_refand POL1 < V_ref. Every time the POL0 status bit changes from

logic 1 to logic 0, a POL0 interrupt is generated. Every time the POL1 status bit

changes from logic 0 to logic 1, a POL1 interrupt is generated.

The period time of a POL1-POL0-POL1 sequence is available in the Ringer period

generated. The sequence is:

1. Power-on: Ringer period register = 255

2. First POL1 interrupt: Ringer period register = 255

3. First POL1 interrupt after a POL0 interrupt: Ringer period register = new time

4. First POL1 interrupt after more than ²⁵⁵

⁄₂₀₄₈s: Ringer period register = 255.

The period is given in multiples of ¹⁄₂₀₄₈s. The maximum value is 255.

The POL1-POL0-POL1 sequence is recognized when one or more POL1 interrupts

are generated followed by one or more POL0 interrupts, followed by a POL1 interrupt.

The 32.768 kHz clock is needed for the generation of a polarity interrupt.

7.5 Low battery detection

The low battery voltage detection input (pin LOWBAT) is connected to the positive

input of a comparator. The negative input is connected to the internal reference

voltage. If the voltage on the LOWBAT input pin is less than the reference voltage V_ref,

the LOW-BAT Indication (Status register, bit 5) is set. If the LOWBAT input rises

above V_refagain, the LOW-BAT Indication is cleared.

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The 32.768 kHz clock signal must be available. The LOW-BAT Indication bit does not

generate interrupts, thus the bit should be polled.

7.6 Level detect

When the input signal level on the FSK or the CAS input (the one that is selected) is

below a threshold of typically −40 dBm, the Low Level Status bit will be set (Interrupt

transmission and to detect the ‘Idle State Tone Alert Signal’ for British Telecom. The

signal power on the input can be monitored by polling the register bit since it will not

generate an interrupt. Signal power is measured in a frequency band corresponding

to the selected operation mode, FSK (1000 to 2200 Hz) or CAS (2000 to 2800 Hz).

The Low Level Status bit will be updated every 8 ms. When FSK and CAS are both

disabled the signal level on the FSK input is measured. The 32.768 kHz clock signal

must be available.

7.7 Time base

The 32.768 kHz oscillator is used to generate either a 1 second or a 1 minute

interrupt signal. If the TB on/off bit is set (Mode register 2, bit 6) every second or

minute an interrupt is generated and MIN Interrupt and/or SEC Interrupt bits

(Interrupt register, bit 7 and 6) are set. After reading the Interrupt register the interrupt

is cleared.

The SEC/MIN (Mode register 2, bit 5) selects whether every second (SEC/MIN is set)

or every minute (SEC/MIN is cleared) an interrupt is generated. All possible

selections are shown in Table 3. Resetting bit TB on/off in Mode register 2 (bit 6) will

only disable time base interrupts, and the 32.768 kHz oscillator will continue to run.

7.8 Interrupt

The interrupt request output (IRQ) is active HIGH by default. The polarity of the IRQ

output can be made active LOW by the INT Polarity HIGH/LOW bit (Mode register 1,

bit 3). The IRQ pin is in 3-state when not active, so an external pull-up or pull-down

resistor is required. The interrupt cause is indicated by the ﬂags in the Interrupt

the Interrupt register are reset when the register is read via I²C-bus interface.

The IRQ pin is deactivated at the positive edge of SCL which reads the ﬁrst data bit of

the Interrupt register. The IRQ pin will stay inactive for one SCL cycle. IRQ can

handle a next interrupt after the next positive edge of SCL.

Table 3: Selection of interrupt modes

Mode register 2 (CIDMD2) Interrupt register (CIDINT)

Interrupt

TB on/off

SEC/MIN

MIN Interrupt SEC Interrupt

(CIDMD2.6) (CIDMD2.5) (CIDINT.7)

(CIDINT.6)

X^[1]

no time base interrupt (time base is reset)

every minute an interrupt is generated; no second interrupt

every second an interrupt is generated; every minute an

interrupt is generated

[1] X = don’t care.

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7.9 The internal Power-on reset (POR)

The device contains an on-chip Power-on reset circuitry which activates a reset as

long as V_DDis below a predeﬁned level V_POR(H). If V_DDexceeds V_POR(H), the

3.58 MHz oscillator will start. The PCD3316 is initialized and the internal registers are

set to the default value (see Section 7.13). It takes a maximum of 100 cycles of the

3.58 MHz clock to initialize all internal functions. The POR circuitry also ensures, that

the chip will be switched off as soon as a falling V_DDreaches a predeﬁned level

(V_POR(L)).

7.10 3.58 MHz oscillator circuitry

The 3.58 MHz oscillator is needed for the FSK receiver and the CAS detection. This

on-chip Amplitude Controlled Oscillator (ACO) circuitry is a single-stage inverting

ampliﬁer biased by an internal feedback resistor R_fb. The oscillator circuit is shown in

Figure 5. When using a quartz resonator to drive the oscillator, normally no external

components are needed.

When using ceramic resonators to drive the oscillator, in some cases external

components are needed; refer to the ceramic resonator product speciﬁcations. Two

different conﬁgurations are shown in Figure 6a and Figure 6b.

handbook, halfpage

AMPLITUDE

on/off

CONTROL

PCD3316

HXIN

HXOUT

MGK723

Fig 5. Oscillator.

To drive the device with an external clock source, apply the external clock signal to

HXIN, and leave HXOUT to ﬂoat, as shown in Figure 6c. If the amplitude of the input

signal is less than V_DDto DGND or a sine wave is applied, capacitive decoupling is

needed as shown in Figure 6d.

In the Power-down mode (Mode register 2, bit 7 = 0), the oscillator is stopped and

HXIN and HXOUT are internally pulled LOW. The current of the whole oscillator is

switched off.

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handbook, halfpage

PCD3316

handbook, halfpage

PCD3316

HXIN

HXOUT

HXIN

HXOUT

MGK725

MGK726

a. Standard oscillator: quartz or PXE.

b. Oscillator: quartz or PXE with external capacitors.

handbook, halfpage

PCD3316

handbook, halfpage

PCD3316

HXIN

HXOUT

HXIN

HXOUT

3.58 MHz

square wave

3.58 MHz

sine wave

MGK727

MGK728

c. External clock: square wave.

Fig 6. 3.58 MHz oscillator conﬁgurations.

d. External clock: sine wave.

MBK948

500

handbook, halfpage

(Ω)

400

300

handbook, halfpage

(1)

(2) (3)

200

MBK947

100

C0 (pF)

C1_eand C2_eare the external load capacitances

(see Figure 6b). Normally, they are not needed

due to integrated load capacitances of 10 pF;

see curve (2).

For correct function of the oscillator, the values

of R1 and C0 of the chosen resonator (quartz or

PXE) must be below the related curve lines

shown in Figure 7a. The value of the parallel

resistor R0 must be less than 47 kΩ.

(1) C1_e= C2_e= 22 pF.

(2) C1_e= C2_e= 0 pF.

(3) C1_e= C2_e= 12 pF.

The wiring between chip and resonator should

be kept as short as possible.

a. Resonator requirements for the ACO.

b. Resonator equivalent circuit.

Fig 7. Resonator requirements and equivalent circuit.

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7.11 32 kHz oscillator

The 32.768 kHz oscillator is enabled permanently and is used to generate either a

1 second or 1 minute interrupt. The 32.768 kHz clock is also used for the ‘Ring or

polarity change detector’, the ‘Low battery detection’ and the ‘Level detect’ function.

An external 32.768 kHz signal may be applied to pin LXIN while leaving pin LXOUT

not connected.

The 32 kHz oscillator requires an external 32.768 kHz quartz crystal and an external

feedback resistor (4.7 MΩ) between the LXIN and LXOUT pins (see Figure 8).

handbook, halfpage

PCD3316

32.768 kHz

OSCILLATOR

LXIN

LXOUT

32.768 kHz

MGK724

4.7 MΩ

Fig 8. Connections of the 32 kHz oscillator.

7.12 Serial interface

The serial interface of the PCD3316 is the I²C-bus. A detailed description of the

I²C-bus speciﬁcation, including applications, is given in the brochure: The I²C-bus

and how to use it, order no. 9398 393 40011 or I²C Peripherals Data Handbook IC12.

7.12.1 Characteristics of the I²C-bus

For the I²C-bus conﬁguration see Figure 9. A device generating a message is a

‘transmitter’, a device receiving a message is the ‘receiver’. The device that controls

the message is the ‘master’ and the devices which are controlled by the master are

called the ‘slaves’. The PCD3316 operates in the slave transmitter/receiver mode

only.

The I²C-bus is for bidirectional, two-line communication between different ICs or

modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both

lines must be connected to a positive supply via a pull-up resistor. Data transfer may

be initiated only when the bus is not busy.

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SDA

SCL

MASTER

TRANSMITTER /

RECEIVER

SLAVE

TRANSMITTER /

RECEIVER

MASTER

TRANSMITTER /

RECEIVER

SLAVE

RECEIVER

MASTER

TRANSMITTER

MBA605

Fig 9. I²C-bus conﬁguration.

7.12.2 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line, while the clock is HIGH is deﬁned as the START condition

(S). A LOW-to-HIGH transition of the data line while the clock is HIGH is deﬁned as a

STOP condition (P); see Figure 10.

SDA

SCL

SDA

SCL

STOP condition

START condition

MBA608

Fig 10. START and STOP conditions for the I²C-bus.

7.12.3 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must

remain stable during the HIGH period of the clock pulse as changes in the data line at

this time will be interpreted as a control signal; see Figure 11.

SDA

SCL

data line

stable;

data valid

change

of data

allowed

MBA607

Fig 11. I²C-bus bit transfer.

7.12.4 Acknowledge

The number of data bytes transferred between the START and the STOP conditions

from the transmitter to the receiver is unlimited. Each byte of eight bits is followed by

an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the

transmitter during which time the master generates an extra acknowledge-related

clock pulse.

A slave receiver which is addressed must generate an acknowledge after the

reception of each byte. Also a master receiver must generate an acknowledge after

the reception of each byte that has been clocked out of the slave transmitter.

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The device that acknowledges must pull down the SDA line during the acknowledge

clock period immediately after the 8th SCL pulse, so that the SDA line is stable LOW

during the HIGH period of the acknowledge related clock pulse (set-up and hold

times must be taken into consideration).

A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

dth

DATA OUTPUT

BY TRANSMITTER

not acknowledge

DATA OUTPUT

BY RECEIVER

acknowledge

SCL FROM

MASTER

clock pulse for

acknowledgement

START

condition

MBC602

Fig 12. I²C-bus acknowledge.

7.12.5 I²C-bus protocol

Before any data is transmitted on the I²C-bus, the device which should respond is

addressed ﬁrst. The addressing is always carried out with ﬁrst byte transmitted after

the START procedure. One I²C-bus slave address is reserved for the PCD3316, E0H

(1110 0000 for write and 1110 0001 for read).

The I²C-bus protocol is shown in Figure 13. Two different sequences are considered,

the write sequence and the read sequence. Both sequences are initiated with a

START condition (S) from the I²C-bus master which is followed by the PCD3316 slave

address with the read bit cleared. The ﬁrst byte after the I²C-bus address is

interpreted as the address of a PCD3316 register.During the write sequence the

write sequence is ended with a STOP condition from the master. If the addressed

For the read sequence the bus master issues a repeated START condition followed

by the PCD3316 slave address with the read bit set. Then data is read from

previously set address and sent out. When the master responds with an acknowledge

the address of the register is auto incremented and the slave will put the data from

the next register on the bus. The read sequence is stopped when the master stops

giving an acknowledge and generates a STOP condition.

When a non-existing register is addressed the PCD3316 will return FFH. Existing

reserved for test purposes. This address cannot be reached with the auto-increment

function of the I²C-bus interface.

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acknowledgement

from slave

acknowledgement

from slave

acknowledgement

from slave

handbook, full pagewidth

DATA

SLAVE ADDRESS

R/W

n bytes

auto increment

word address

MBH975

a. I²C-bus write sequence.

no acknowledgement

from master

acknowledgement

from slave

acknowledgement

from slave

acknowledgement

from slave

acknowledgement

from master

DATA

SLAVE ADDRESS

DATA

n bytes

R/W

at this moment master-

transmitter becomes

master - receiver and

PCD3316 slave-receiver

becomes slave-transmitter

auto increment

MBH976

b. I²C-bus read sequence.

Fig 13. I²C-bus write and read sequence.

PCD3316

Philips Semiconductors

CIDCW receiver

7.12.6 I²C-bus bit rate

When a microcontroller is used that implements an I²C-bus in software, the bit rate of

the I²C-bus can be critical during reception of FSK. The collection of the interrupt

data and FSK-data from the PCD3316 takes 48 bits on the I²C-bus. With an FSK

baud rate of 1200 (corresponds to 1200 bits per second) the minimal speed of the

I²C-bus should be 5.76 kbits/s. Additional interrupts generated by the time base of the

PCD3316 will cause the processor to collect extra information from the PCD3316.

As a consequence, the FSK-data can be overrun in the PCD3316 and one data byte

will be lost. In this case, the time base interrupt should be suppressed while FSK is

active. This can be done by setting the ‘INT-SUP on/off’ bit (bit 4 in Mode register 2).

The ‘TB on/off’ bit (bit 6 in Mode register 2) will still be set but the IRQ output will not

be activated by the time base interrupt. Any time base interrupt can be detected by

the microcontroller when an FSK interrupt is processed by reading the Interrupt

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7.13 Registers

Table 4: Register overview

Address

00H

Name

Function

Read/Write

read only

read/write

Default value

CIDINT

CIDFSK

CIDSTA

CIDRNG

CIDMD1

CIDMD2

Interrupt register

FSK data register

Status register

Ringer period register

Mode register 1

Mode register 2

0000 0000

01H

−

02H

−

03H

−

04H

0101 1000

1101 0000

05H

7.13.1 Interrupt register (CIDINT)

Table 5: Interrupt register

Address: 00H; read only.

MIN Interrupt SEC Interrupt FSK Interrupt Low Level Status POL1 Interrupt POL0 Interrupt CAS Interrupt

−

Table 6: Description of CIDINT bits

Bit

Symbol

Description

CIDINT.7 MIN Interrupt

CIDINT.6 SEC Interrupt

CIDINT.5 FSK Interrupt

MIN Interrupt = 0: no interrupt request;

MIN Interrupt = 1: one minute interrupt request

SEC Interrupt = 0: no interrupt request;

SEC Interrupt = 1: one second interrupt request

FSK Interrupt = 0: no FSK interrupt or FSK disabled;

FSK Interrupt = 1: FSK interrupt, one byte received

CIDINT.4 Low Level Status Low Level Status = 0: signal level on selected input above power reference (no interrupt);

Low Level Status = 1: signal level on selected input below power reference (no interrupt)

CIDINT.3 POL1 Interrupt

CIDINT.2 POL0 Interrupt

CIDINT.1 CAS Interrupt

CIDINT.0 −

POL1 Interrupt = 0: no zero to one changes on POL1 input or polarity interrupt disabled;

POL1 Interrupt = 1: a one to zero input change on the POL1 input is detected

POL0 Interrupt = 0: no one to zero changes on POL0 input or polarity interrupt disabled;

POL0 Interrupt = 1: a zero to one input change on the POL0 input is detected

CAS Interrupt = 0: no CAS signal detected or CAS disabled;

CAS Interrupt = 1: CAS signal detected

reserved bit

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7.13.2 FSK data register (CDFSK)

Table 7:

Interrupt register

Address: 01H; read only.

Table 8:

Description of CDFSK bits

Bit

Symbol

Description

CDFSK.7 to

CDFSK.0

D7 to D0

If an FSK interrupt has occurred and no FSK error is detected, the FSK data register

contains valid data.

7.13.3 Status register (CIDSTA)

Table 9: Status register

Address: 02H; read only.

POL1 POL0 LOW-BAT Indication

FSK-BOM Indication

FSK-OVR Error

FSK-FRM Error

−

Table 10: Description of CIDSTA bits

Bit

Symbol

POL1

Description

CIDSTA.7

CIDSTA.6

CIDSTA.5

POL1 = 0: voltage on input POL1 < V_ref; POL1 = 1: voltage on input POL1 > V_ref

POL0 = 0: voltage on input POL0 > V_ref; POL0 = 1: voltage on input POL0 < V_ref

POL0

LOW-BAT Indication LOW-BAT Indication = 0: voltage on input LOWBAT > V_ref

LOW-BAT Indication = 1: voltage on input LOWBAT < V_ref

;

CIDSTA.4

CIDSTA.3

CIDSTA.2

FSK-BOM Indication FSK-BOM Indication = 0: begin of mark period not yet detected;

FSK-BOM Indication = 1: begin of mark period detected

FSK-OVR Error

FSK-FRM Error

−

FSK-OVR Error = 0: no FSK overrun error;

FSK-OVR Error = 1: FSK overrun error, data byte(s) lost

FSK-FRM Error = 0: no FSK frame error;

FSK-FRM Error = 1: FSK frame error, stop bit was wrong

CIDSTA.1 and

CIDSTA.0

reserved bits

7.13.4 Ringer period register (CIDRNG)

Table 11: Register format

Address: 03H; read only.

Table 12: Description of CIDRNG bits

Bit

Symbol

Description

CIDRNG.7 to

CIDRNG.0

D7 to D0

The value held in this byte denotes the time between two positive edges of the POL1

comparator output (between two positive edges of POL1 one positive edge of POL0

must have been detected).

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7.13.5 Mode register 1 (CIDMD1)

Table 13: Mode register 1

Address: 04H; read/write.

FSK on/off FSK-BOM-mask on/off CAS on/off

POL on/off

INT polarity HIGH/LOW

−

Table 14: Description of CIDMD1 bits

Bit

Symbol

Description

FSK on/off = 0: FSK receiver disabled; FSK on/off = 1: FSK receiver enabled

CIDMD1.7

CIDMD1.6

FSK on/off

FSK-BOM-mask on/off FSK-BOM-mask on/off = 0: FSK interrupts will be generated when a data word was

received even before mark period (data from channel seizure);

FSK-BOM-mask on/off = 1: FSK interrupts will only be generated after the mark

period was detected (no interrupts from channel seizure)

CIDMD1.5

CIDMD1.4

CAS on/off

POL on/off

CAS on/off = 0: CAS detector disabled; CAS on/off = 1: CAS detector enabled

POL on/off = 0: disable interrupts due to polarity change;

POL on/off = 1: enable interrupts due to polarity change

CIDMD1.3

INT polarity HIGH/LOW INT polarity HIGH/LOW = 0: interrupt pin active LOW;

INT polarity HIGH/LOW = 1: interrupt pin active HIGH

CIDMD1.2 to

CIDMD1.0

−

reserved bits

7.13.6 Mode register 2 (CIDMD2)

Table 15: Mode register 2

Address: 05H; read/write.

XTAL on/off

TB on/off

SEC/MIN

INT-SUP on/off

−

Table 16: Description of CIDMD2 bits

Bit

Symbol

Description

CIDMD2.7

XTAL on/off

XTAL on/off = 0: disable 3.58 MHz oscillator;

XTAL on/off = 1: enable 3.58 MHz oscillator

CIDMD2.6

CIDMD2.5

CIDMD2.4

TB on/off

SEC/MIN

INT-SUP on/off

−

TB on/off = 0: disable 32.768 kHz timebase;

TB on/off = 1: enable 32.768 kHz timebase

SEC/MIN = 0: every minute a timebase interrupt;

SEC/MIN = 1: every second a timebase interrupt

INT-SUP on/off = 0: enable SEC/MIN interrupts during FSK reception;

INT-SUP on/off = 1: disable SEC/MIN interrupts during FSK reception

CIDMD2.3 to

CIDMD2.0

reserved bits

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8. Limiting values

Table 17: Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DD

I_DD

Parameter

Conditions

Min

−0.5

−

Max

+5.0

Unit

supply voltage

supply current

I_I

DC input current at any input

DC output current at any output

input voltage on all inputs

total power dissipation

power dissipation per output

operating ambient temperature

storage temperature

−10

−0.5

−

+10

I_O

+10

V_I

V_DD+ 0.5^[1]

300

P_tot

P_O

°C

−

T_amb

T_stg

−25

−65

+70

+150

°C

[1] V_I(max)= 5.0 V.

9. Characteristics

Table 18: Characteristics

V_DD= 2.5 to 3.6 V; T_amb= −25 to +70 °C; HXIN = 3.579545 MHz ±0.05%; LXIN = 32.768 kHz ±0.1%; unless otherwise

speciﬁed.

Symbol

V_DD

Parameter

Conditions

Min

2.5

Typ

3.3

Max

3.6

Unit

[1]

[2]

supply voltage

V_POR(H)

V_hys(POR)

I_DD

power-on reset HIGH voltage

power-on reset hysteresis voltage

supply currents

1.85

2.05

100

2.25

150

V_DD= 2.5 V

[3]

Power-down mode

operating

−

µA

[3] [4]

2.0

2.3

Low voltage and polarity comparators (pins LOWBAT, POL0 and POL1)

V_hys

I_LI

hysteresis voltage

−

[5]

[6]

input leakage current

−

µA

Internal reference

V_ref

reference voltage level

1.125 1.25

1.375

P_i(ref)

input signal reference power for Low

Level Status bit

in 600 Ω load

−43.8

−

−37.8 dBm

t_r(level)

t_f(level)

input signal to Low Level Status bit rise

time

input signal power < P_i(ref)

input signal power > P_i(ref)

−

input signal to Low Level Status bit fall

time

Logical output (pin IRQ)^[7]

I_OLLOW-level output current

I_OHHIGH-level output current

V_IRQ= 0.4 V

−

V_IRQ= V_DD− 0.4 V

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Table 18: Characteristics…continued

V_DD= 2.5 to 3.6 V; T_amb= −25 to +70 °C; HXIN = 3.579545 MHz ±0.05%; LXIN = 32.768 kHz ±0.1%; unless otherwise

speciﬁed.

Symbol

FSK receiver (pins FSKIN+ and FSKIN−)

Z_iinput impedance FSKIN+ to FSKIN−

Z_source(max)maximum source impedance

Parameter

Conditions

Min

Typ

Max

Unit

−

1.4

−

MΩ

kΩ

−

200

[8]

P_i(FSKIN)

S/N_FSK

input signal power

signal-to-noise ratio

in 600 Ω load

−50

−

dBm

200 to 3400 Hz

−

|V_dif

differential voltage between mark and

space (twist)

−

f_(D)

f_s

data transmission rate frequency

space frequency

1180

2068

1188

1200 1212

bits/s

−

2222

1320

f_m

mark frequency

CAS detector (pin CASIN)

Z_i

input impedance CASIN to V_ref

−

1.4

−

MΩ

kΩ

Z_source(max)maximum source impedance

−

200

[8]

P_i

input signal power

in 600 Ω load

−37.8

−43.8

−

dBm

TH_ns(CAS)no signal threshold (CAS)

−

−37.8 dBm

f_l

low tone frequency

2130

−

f_h

high tone frequency

−

2750

−

[9]

∆f_max

V_dif

t_dt

maximum frequency deviation

differential voltage level (twist)

dual tone detection time

−0.5

−

+0.5

−

I²C-bus interface (pins SCL and SDA)^[10]; see Figure 14

[11]

V_IL

LOW-level input voltage

HIGH-level input voltage

LOW-level output current for pin SDA

input capacitance for each I/O pin

SCL clock frequency

−

0.3V_DD

V_IH

0.7V_DD

V_DD

−

I_OL1

V_O(SDA)= 0.4 V

kHz

µs

C_i

−

100

−

f_SCL

−

t_BUF

bus free time

4.7

4.0

4.7

4.0

−

t_SU;STA

t_HD;STA

t_LOW

t_HIGH

t_r

START condition set-up time

START condition hold time

SCL LOW time

−

SCL HIGH time

−

[12]

maximum SCL and SDA rise time

maximum SCL and SDA fall time

data set-up time

1000

300

−

t_f

−

t_SU;DAT

t_HD;DAT

t_VD;DAT

t_SU;STO

250

data hold time

−

SCL LOW to data out valid time

STOP condition set-up time

−

3.4

−

4.0

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Table 18: Characteristics…continued

V_DD= 2.5 to 3.6 V; T_amb= −25 to +70 °C; HXIN = 3.579545 MHz ±0.05%; LXIN = 32.768 kHz ±0.1%; unless otherwise

speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

3.58 MHz oscillator (pins HXIN and HXOUT)

V_HXIN(p-p)external clock signal amplitude

(peak-to-peak value) on pin HXIN

0.5

−

V_DD

Z_i(HXIN)

input impedance on pin HXIN

300

1000

−

kΩ

C1_i; C2_i

input capacitance on pins HXIN and

HXOUT^[13]

−

32 kHz oscillator (pins LXIN and LXOUT)

g_m

transconductance

V_i(p-p)< 50 mV

−

µS

C_i(LXIN)

LXIN input capacitance

C_o(LXOUT)LXOUT output capacitance

−

[1] Except for FSK and CAS detection, all circuitry works already when V_DD> V_POR(H). Since the I²C-bus interface will work (starts to

acknowledge), the application can start reading the LOW-BAT Indication bit (Status register, bit 5) to check whether the supply voltage

has reached the operating voltage level. A voltage divider network can be connected to pins V_DD, LOWBAT and AGND/DGND such that

V_LOWBAT= V_refif V_DD= V_DD(min)

[2] The power-on reset LOW level is deﬁned as V_POR(L)= V_POR(H)− V_hys(POR). By design V_POR(L)is always lower than V_POR(H)

[3] 32 kHz oscillator on (MIN Interrupt, SEC Interrupt, Polarity change, Low battery and Level detect available).

[4] 3.58 MHz oscillator on (device fully operational).

[5] GND < V_I< V_DD. The leakage currents are generally very small, <1 nA. The value given here, 1 µA, is a maximum that can occur after

an Electrostatic Stress on the pin.

[6] When FSK is selected the signal power is measured between 1000 and 2200 Hz. When CAS is selected signal levels are measured

between 2000 and 2800 Hz.

[7] The IRQ pin is implemented as a 3-state pin which is only active (either HIGH or LOW) when an interrupt occurs. A pull-up or pull-down

has to be connected to deﬁne the line when no interrupt is generated.

[8] Veriﬁed on sampling basis.

[9] According to Bellcore speciﬁcation: near end speech level ≤ −7 dBm ASL (ASL = Active Speech Level), referenced to 600 Ω, according

to method B of recommendation P.56.

[10] Pins SCL and SDA are equipped with an open-drain output buffer. The pins have no clamp diode to V_DD

[11] The input threshold voltage of SCL and SDA meet the I²C-bus speciﬁcation. Therefore, an input voltage below 0.3V_DDwill be recognized

as a logic 0 and an input voltage above 0.7V_DDwill be recognized as a logic 1

[12] Maximum capacitive load for each bus line is 400 pF.

[13] C1_iand C2_iare the total internal capacitances (including gate capacitance and leadframe capacitance).

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handbook, full pagewidth

SDA

SU;DAT

HD;DAT

HIGH

BUF

LOW

1/f

SCL

SU;STA

MBH977

HD;STA

a. Timing diagram 1.

handbook, full pagewidth

SDA

SU;STO

VD;DAT

SCL

MBH978

b. Timing diagram 2.

Fig 14. I²C-bus timing.

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a/b

b/a

KEYBOARD

CSI

MICRO CONTROLLER

TONE

IRQ

BAT

RINGER/

INTERRUPTER

BAT

xtal

TRANSMISSION IC

TONE

(1)

ATTENNUATION

(2)

CAS FILTER

POL1/0 FSKIN+/−

CASIN

LXIN

IRQ

32.768 kHz LXOUT

PCD3316

HXIN

I C-bus

CID/CIDCW RECEIVER

3.58 MHz

HXOUT

LOWBAT

LCD

BATTERIES

MGK722

A demo-board (OM5843) of this conﬁguration is available. Please contact your Philips sales ofﬁce.

(1) See Figure 16a.

(2) See Figure 16b.

Fig 15. Application diagram for a telephone with CID/CIDCW functionality.

PCD3316

Philips Semiconductors

CIDCW receiver

2.2 µF

820 kΩ

POL0

POL1

a/b

(250 V)

telephone

line

2.2 µF

ok, halfpage

1.8 nF

b/a

PCD3316

(250 V)

100 kΩ

100 nF

CASIN

PCD3316

120 kΩ

1 nF

100 kΩ

FSKIN+

FSKIN−

MBH996

MGK729

Attenuation networks to connect the polarity and FSK inputs to

the telephone line.

High-pass ﬁlter (cut-off

frequency ≈ 1 kHz) to improve

performance of CAS detection.

a. Attenuation networks.

b. High-pass ﬁlter.

Fig 16. Application diagrams.

11. Test information

11.1 Application note on Customer Premises Equipment (CPE) testing

Under certain circumstances, some external CIDCW test equipment may generate

incorrect pulses after the ringing signal becomes inactive. These pulses may cause

the FSK detector of the PCD3316 to respond. Note that this is by no means an

incorrect behaviour of the PCD3316 chip, but a correct detection of incorrect test

stimuli. However, if not known, it may lead to confusing results during testing of the

CPE.

To avoid the issue described above, following work-around can be used:

1. Disable the FSK detection of PCD3316, before and during the ringing signal

detection.

2. Switch on the FSK detection only after a certain period, e.g. 100 ms after the

ringing signal goes inactive.

3. When the ﬁrst FSK data is detected, e.g ‘55H’ (possible part of channel seizure),

switch off the FSK detection and on again. This will force the FSK detector to

resynchronize and detect the normal FSK data correctly. It may be necessary to

repeat this sequence a number of times to ensure that the data detected really

comes from the channel seizure. Thus, it is recommended to wait for a multiple

number of bytes ‘55H’ to be detected to validate a correct channel seizure.

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12. Package outline

SO16: plastic small outline package; 16 leads; body width 7.5 mm

SOT162-1

(A )

pin 1 index

detail X

10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

max.

(1)

UNIT

0.30

0.10

2.45

2.25

0.49

0.36

0.32

0.23

10.5

10.1

7.6

7.4

10.65

10.00

1.1

0.4

1.1

1.0

0.9

0.4

2.65

0.25

0.01

1.27

0.050

1.4

0.25 0.25

0.1

8^o

0^o

0.012 0.096

0.004 0.089

0.019 0.013 0.41

0.014 0.009 0.40

0.30

0.29

0.419

0.394

0.043 0.043

0.016 0.039

0.035

0.016

inches 0.10

0.055

0.01 0.01 0.004

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

EIAJ

95-01-24

97-05-22

SOT162-1

075E03

MS-013AA

Fig 17. SOT162-1.

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13. Soldering

13.1 Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology. A more in-depth account

of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit

Packages (document order number 9398 652 90011).

There is no soldering method that is ideal for all surface mount IC packages. Wave

soldering is not always suitable for surface mount ICs, or for printed-circuit boards

with high population densities. In these situations reﬂow soldering is often used.

13.2 Reﬂow soldering

Reﬂow soldering requires solder paste (a suspension of ﬁne solder particles, ﬂux and

binding agent) to be applied to the printed-circuit board by screen printing, stencilling

or pressure-syringe dispensing before package placement.

Several methods exist for reﬂowing; for example, infrared/convection heating in a

conveyor type oven. Throughput times (preheating, soldering and cooling) vary

between 100 and 200 seconds depending on heating method.

Typical reﬂow peak temperatures range from 215 to 250 °C. The top-surface

temperature of the packages should preferable be kept below 230 °C.

13.3 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices

(SMDs) or printed-circuit boards with a high component density, as solder bridging

and non-wetting can present major problems.

To overcome these problems the double-wave soldering method was speciﬁcally

developed.

If wave soldering is used the following conditions must be observed for optimal

results:

Use a double-wave soldering method comprising a turbulent wave with high

upward pressure followed by a smooth laminar wave.

•

For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

For packages with leads on four sides, the footprint must be placed at a 45° angle

to the transport direction of the printed-circuit board. The footprint must

incorporate solder thieves downstream and at the side corners.

•

During placement and before soldering, the package must be ﬁxed with a droplet of

adhesive. The adhesive can be applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the adhesive is cured.

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Typical dwell time is 4 seconds at 250 °C. A mildly-activated ﬂux will eliminate the

need for removal of corrosive residues in most applications.

13.4 Manual soldering

Fix the component by ﬁrst soldering two diagonally-opposite end leads. Use a low

voltage (24 V or less) soldering iron applied to the ﬂat part of the lead. Contact time

must be limited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within

2 to 5 seconds between 270 and 320 °C.

13.5 Package related soldering information

Table 19: Suitability of surface mount IC packages for wave and reﬂow soldering

methods

Package

Soldering method

Wave

Reﬂow^[1]

suitable

BGA, SQFP

not suitable

not suitable^[2]

HLQFP, HSQFP, HSOP, HTSSOP, SMS

PLCC, SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended^{[3] [4]}

not recommended^[5]

SSOP, TSSOP, VSO

[1] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the

maximum temperature (with respect to time) and body size of the package, there is a risk that internal

or external package cracks may occur due to vaporization of the moisture in them (the so called

popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated

Circuit Packages; Section: Packing Methods.

[2] These packages are not suitable for wave soldering as a solder joint between the printed-circuit board

and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top

version).

[3] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave

direction. The package footprint must incorporate solder thieves downstream and at the side corners.

[4] Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger

than 0.8 mm; it is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

[5] Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than

0.65 mm; it is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

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14. Revision history

Rev Date

CPCN Description

- This data sheet supersedes the version of 1998 May 14 (9397 750 03525):

01 990311

The format of this speciﬁcation has been redesigned to comply with Philips Semiconductors’ new

presentation and information standard

•

Section 1 “General description” on page 1: reference to application note AN98701 added

•

Section 7.6 “Level detect” on page 7: Added text regarding the frequency band for signal power

measurement

Section 7.10 “3.58 MHz oscillator circuitry” on page 8: recommended resonator indication

removed

•

Section 7.13 “Registers” on page 15: new register presentation in this section

•

Table 14 “ Description of CIDMD1 bits” on page 17: Description of bit CIDMD1.6 and CIDMD1.5

adjusted

Application diagram Figure 16a on page 23: diodes removed

•

Added Section 11.1 “Application note on Customer Premises Equipment (CPE) testing” on

page 23.

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Data sheet status

CIDCW receiver

Datasheet status

Product status Deﬁnition^[1]

Objective speciﬁcation

Development

This data sheet contains the design target or goal speciﬁcations for product development. Speciﬁcation may

change in any manner without notice.

Preliminary speciﬁcation Qualiﬁcation

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips

Semiconductors reserves the right to make changes at any time without notice in order to improve design and

supply the best possible product.

Product speciﬁcation

Production

This data sheet contains ﬁnal speciﬁcations. Philips Semiconductors reserves the right to make changes at any

time without notice in order to improve design and supply the best possible product.

[1]

Please consult the most recently issued data sheet before initiating or completing a design.

Deﬁnitions

Disclaimers

Short-form speciﬁcation — The data in

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

short-form speciﬁcation is

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Right to make changes — Philips Semiconductors reserves the right to

make changes, without notice, in the products, including circuits, standard

cells, and/or software, described or contained herein in order to improve

design and/or performance. Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

licence or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products

are free from patent, copyright, or mask work right infringement, unless

otherwise speciﬁed.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

Licenses

Purchase of Philips I²C components

Purchase of Philips I²C components conveys a license

under the Philips’ I²C patent to use the components in the

I²C system provided the system conforms to the I²C speciﬁ-

cation deﬁned by Philips. This speciﬁcation can be ordered

using the code 9398 393 40011.

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Philips Semiconductors - a worldwide company

Argentina: see South America

Middle East: see Italy

Australia: Tel. +61 29 805 4455, Fax. +61 29 805 4466

Austria: Tel. +43 160 101, Fax. +43 160 101 1210

Belarus: Tel. +375 17 220 0733, Fax. +375 17 220 0773

Belgium: see The Netherlands

Netherlands: Tel. +31 40 278 2785, Fax. +31 40 278 8399

New Zealand: Tel. +64 98 49 4160, Fax. +64 98 49 7811

Norway: Tel. +47 22 74 8000, Fax. +47 22 74 8341

Philippines: Tel. +63 28 16 6380, Fax. +63 28 17 3474

Poland: Tel. +48 22 612 2831, Fax. +48 22 612 2327

Portugal: see Spain

Brazil: see South America

Bulgaria: Tel. +359 268 9211, Fax. +359 268 9102

Canada: Tel. +1 800 234 7381

Romania: see Italy

China/Hong Kong: Tel. +852 2 319 7888, Fax. +852 2 319 7700

Colombia: see South America

Russia: Tel. +7 095 755 6918, Fax. +7 095 755 6919

Singapore: Tel. +65 350 2538, Fax. +65 251 6500

Slovakia: see Austria

Czech Republic: see Austria

Denmark: Tel. +45 3 288 2636, Fax. +45 3 157 0044

Finland: Tel. +358 961 5800, Fax. +358 96 158 0920

France: Tel. +33 14 099 6161, Fax. +33 14 099 6427

Germany: Tel. +49 40 23 5360, Fax. +49 402 353 6300

Greece: Tel. +30 1 489 4339/4239, Fax. +30 1 481 4240

Hungary: see Austria

Slovenia: see Italy

South Africa: Tel. +27 11 470 5911, Fax. +27 11 470 5494

South America: Tel. +55 11 821 2333, Fax. +55 11 829 1849

Spain: Tel. +34 33 01 6312, Fax. +34 33 01 4107

Sweden: Tel. +46 86 32 2000, Fax. +46 86 32 2745

Switzerland: Tel. +41 14 88 2686, Fax. +41 14 81 7730

Taiwan: Tel. +886 22 134 2865, Fax. +886 22 134 2874

Thailand: Tel. +66 27 45 4090, Fax. +66 23 98 0793

Turkey: Tel. +90 212 279 2770, Fax. +90 212 282 6707

Ukraine: Tel. +380 44 264 2776, Fax. +380 44 268 0461

United Kingdom: Tel. +44 181 730 5000, Fax. +44 181 754 8421

United States: Tel. +1 800 234 7381

India: Tel. +91 22 493 8541, Fax. +91 22 493 8722

Indonesia: see Singapore

Ireland: Tel. +353 17 64 0000, Fax. +353 17 64 0200

Israel: Tel. +972 36 45 0444, Fax. +972 36 49 1007

Italy: Tel. +39 26 752 2531, Fax. +39 26 752 2557

Japan: Tel. +81 33 740 5130, Fax. +81 33 740 5077

Korea: Tel. +82 27 09 1412, Fax. +82 27 09 1415

Malaysia: Tel. +60 37 50 5214, Fax. +60 37 57 4880

Mexico: Tel. +9-5 800 234 7381

Uruguay: see South America

Vietnam: see Singapore

Yugoslavia: Tel. +381 11 62 5344, Fax. +381 11 63 5777

For all other countries apply to: Philips Semiconductors,

Marketing & Sales Communications,

Internet:http://www.semiconductors.philips.com

Building BE, P.O. Box 218, 5600 MD EINDHOVEN,

The Netherlands, Fax. +31 40 272 4825

9397 750 04824

Product speciﬁcation

11 March 1999

29 of 30

PCD3316

Philips Semiconductors

CIDCW receiver

Contents

General description. . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Applications. . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . 3

6.1

6.2

Pinning information . . . . . . . . . . . . . . . . . 3

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin description . . . . . . . . . . . . . . . . . . . . . 4

Functional description . . . . . . . . . . . . . . . 4

Preprocessor and analog inputs. . . . . . . . 4

CAS detection . . . . . . . . . . . . . . . . . . . . . 5

FSK reception. . . . . . . . . . . . . . . . . . . . . . 5

Ring or polarity change detector . . . . . . . 6

Low battery detection . . . . . . . . . . . . . . . . 6

Level detect . . . . . . . . . . . . . . . . . . . . . . . 7

Time base. . . . . . . . . . . . . . . . . . . . . . . . . 7

Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . 7

The internal Power-on reset (POR) . . . . . 8

3.58 MHz oscillator circuitry . . . . . . . . . . . 8

32 kHz oscillator. . . . . . . . . . . . . . . . . . . 10

7.1

7.2

7.3

7.4

7.5

7.6

7.7

7.8

7.9

7.10

7.11

7.12

Serial interface . . . . . . . . . . . . . . . . . . . . 10

Characteristics of the I²C-bus . . . . . . . . . 10

START and STOP conditions . . . . . . . . . 11

Bit transfer. . . . . . . . . . . . . . . . . . . . . . . 11

Acknowledge . . . . . . . . . . . . . . . . . . . . . 11

I²C-bus protocol . . . . . . . . . . . . . . . . . . . 12

I²C-bus bit rate. . . . . . . . . . . . . . . . . . . . 14

Registers . . . . . . . . . . . . . . . . . . . . . . . . 15

Interrupt register (CIDINT). . . . . . . . . . . . 15

FSK data register (CDFSK) . . . . . . . . . . . 16

Status register (CIDSTA). . . . . . . . . . . . . 16

Ringer period register (CIDRNG) . . . . . . . 16

Mode register 1 (CIDMD1). . . . . . . . . . . . 17

Mode register 2 (CIDMD2). . . . . . . . . . . . 17

7.12.1

7.12.2

7.12.3

7.12.4

7.12.5

7.12.6

7.13

7.13.1

7.13.2

7.13.3

7.13.4

7.13.5

7.13.6

Limiting values . . . . . . . . . . . . . . . . . . . . 18

Characteristics . . . . . . . . . . . . . . . . . . . . 18

Application information . . . . . . . . . . . . . 22

11.1

Test information . . . . . . . . . . . . . . . . . . . 23

Application note on Customer

Premises Equipment (CPE) testing. . . . 23

Package outline. . . . . . . . . . . . . . . . . . . . 24

13.1

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . 25

Introduction to soldering surface mount

packages. . . . . . . . . . . . . . . . . . . . . . . . 25

Reflow soldering. . . . . . . . . . . . . . . . . . . 25

Wave soldering. . . . . . . . . . . . . . . . . . . . 25

Manual soldering . . . . . . . . . . . . . . . . . . 26

Package related soldering information. . 26

13.2

13.3

13.4

13.5

Revision history . . . . . . . . . . . . . . . . . . . 27

Printed in The Netherlands

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner.

The information presented in this document does not form part of any quotation or

contract, is believed to be accurate and reliable and may be changed without notice. No

liability will be accepted by the publisher for any consequence of its use. Publication

thereof does not convey nor imply any license under patent- or other industrial or

intellectual property rights.

Date of release: 11 March 1999

Document order number: 9397 750 04824

Go to Philips Semiconductors' home page

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PCD3316; Caller-ID on Call Waiting (CIDCW) receiver

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Description

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Systems

Communications

The PCD3316 is a low power mixed signal CMOS integrated circuit for receiving physical layer signals like Bellcore’s ‘CPE 1 Alerting Signal

(CAS)’ and the signals used in similar services. The device is capable of a very high precision detection of the dual tone (2130 and 2750

Hz) by using a patented digital algorithm. The PCD3316 can be used for on-hook and off-hook Caller-ID (CID), Caller-ID on Call Waiting

(CIDCW) and Caller-Name (CNAM) applications.

PC/PC-peripherals

Cross reference

Models

For timing purposes the PCD3316 can be programmed to generate an interrupt signal to the microcontroller every second or every minute.

These timings are derived from an on-chip 32.768 kHz oscillator.

Packages

Application notes

Selection guides

935263011112 [NXP]

相关型号：

935263011118

935263028557

935263038112

935263038118

935263040112

935263122551

935263122557

935263151557

935263159551

935263159557

935263160551

935263160557