935186300118 [NXP]
J-K Flip-Flop, HC/UH Series, 2-Func, Negative Edge Triggered, 1-Bit, Complementary Output, CMOS, PDSO14;型号: | 935186300118 |
厂家: | NXP |
描述: | J-K Flip-Flop, HC/UH Series, 2-Func, Negative Edge Triggered, 1-Bit, Complementary Output, CMOS, PDSO14 光电二极管 逻辑集成电路 触发器 |
文件: | 总7页 (文件大小:51K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT107
Dual JK flip-flop with reset;
negative-edge trigger
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Dual JK flip-flop with reset; negative-edge trigger
74HC/HCT107
The 74HC/HCT107 are dual negative-edge triggered
JK-type flip-flops featuring individual J, K, clock (nCP) and
reset (nR) inputs; also complementary Q and Q outputs.
FEATURES
• Output capability: standard
• ICC category: flip-flops
The J and K inputs must be stable one set-up time prior to
the HIGH-to-LOW clock transition for predictable
operation.
GENERAL DESCRIPTION
The 74HC/HCT107 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The reset (nR) is an asynchronous active LOW input.
When LOW, it overrides the clock and data inputs, forcing
the Q output LOW and the Q output HIGH.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
tPHL/ tPLH
PARAMETER
propagation delay
CONDITIONS
UNIT
HC
HCT
nCP to nQ
16
16
16
78
3.5
16
18
17
73
ns
ns
ns
CL = 15 pF;
VCC = 5 V
nCP to nQ
nR to nQ, nQ
fmax
CI
maximum clock frequency
input capacitance
MHz
pF
3.5
power dissipation
capacitance per flip-flop
CPD
notes 1 and 2
30
30
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V.
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
Dual JK flip-flop with reset; negative-edge trigger
74HC/HCT107
PIN DESCRIPTION
PIN NO.
1, 8, 4, 11
SYMBOL
1J, 2J, 1K, 2K
NAME AND FUNCTION
synchronous inputs; flip-flops 1 and 2
2, 6
3, 5
7
1Q, 2Q
1Q, 2Q
GND
complement flip-flop outputs
true flip-flop outputs
ground (0 V)
12, 9
13, 10
14
1CP, 2CP
1R, 2R
VCC
clock input (HIGH-to-LOW, edge-triggered)
asynchronous reset inputs (active LOW)
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
Dual JK flip-flop with reset; negative-edge trigger
74HC/HCT107
Fig.4 Functional diagram.
Fig.5 Logic diagram (one flip-flop).
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING MODE
nR
nCP
J
K
Q
Q
asynchronous reset
L
X
X
X
L
H
toggle
H
H
H
H
↓
↓
↓
↓
h
I
h
h
I
q
L
H
q
q
H
L
q
load “0” (reset)
load “1” (set)
hold “no change”
h
I
I
Note
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition
q = lower case letters indicate the state of the referenced output one set-up time prior to the HIGH-to-LOW CP
transition
X = don’t care
↓ = HIGH-to-LOW CP transition
December 1990
4
Philips Semiconductors
Product specification
Dual JK flip-flop with reset; negative-edge trigger
74HC/HCT107
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: flip-flops
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85 −40 to +125
min. typ. max. min. max. min. max.
52
19
15
160
32
27
200
40
34
240
48
41
2.0
4.5
6.0
propagation delay
nCP to nQ
tPHL/ tPLH
ns
Fig.6
Fig.6
Fig.7
Fig.6
Fig.6
Fig.7
Fig.7
Fig.6
Fig.6
Fig.6
52
19
15
160
32
27
200
40
34
240
48
41
2.0
4.5
6.0
propagation delay
nCP to nQ
t
t
t
PHL/ tPLH
ns
52
19
15
155
31
26
195
39
33
235
47
40
2.0
4.5
6.0
propagation delay
nR to nQ, nQ
PHL/ tPLH
ns
19
7
6
75
15
13
95
19
16
110
22
19
2.0
4.5
6.0
THL/ tTLH output transition time
ns
80
16
14
22
8
6
100
20
17
120
24
20
2.0
4.5
6.0
clock pulse width
HIGH or LOW
tW
ns
80
16
14
22
8
6
100
20
17
120
24
20
2.0
4.5
6.0
reset pulse width
LOW
tW
ns
60
12
10
19
7
6
75
15
13
90
18
15
2.0
4.5
6.0
removal time
nR to nCP
trem
tsu
th
ns
100 22
125
25
21
150
30
26
2.0
4.5
6.0
set-up time
nJ, nK to nCP
20
17
8
6
ns
3
3
3
−6
−2
−2
3
3
3
3
3
3
2.0
4.5
6.0
hold time
nJ, nK to nCP
ns
6.0
30
35
23
70
85
4.8
24
28
4.0
20
24
2.0
4.5
6.0
maximum clock pulse
frequency
fmax
MHz
December 1990
5
Philips Semiconductors
Product specification
Dual JK flip-flop with reset; negative-edge trigger
74HC/HCT107
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: flip-flops
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
nK
nR
nCP, nJ
0.60
0.65
1.00
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tf = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
VCC
+25
−40 to +85 −40 to +125
WAVEFORMS
(V)
min. typ. max. min. max. min. max.
propagation delay
tPHL/ tPLH
19
21
36
36
45
45
54
54
ns
4.5
4.5
Fig.6
Fig.6
nCP to nQ
propagation delay
nCP to nQ
t
t
PHL/ tPLH
PHL/ tPLH
ns
propagation delay
nR to nQ, nQ
20
7
38
15
48
19
57
22
ns
ns
ns
4.5
4.5
4.5
Fig.7
Fig.6
Fig.6
tTHL/ tTLH output transition time
clock pulse width
HIGH or LOW
tW
16
20
14
20
5
9
20
25
18
25
5
24
30
21
30
5
reset pulse width
LOW
tW
11
8
ns
4.5
4.5
4.5
4.5
4.5
Fig.7
Fig.7
Fig.6
Fig.6
Fig.6
removal time
nR to nCP
trem
ns
set-up time
tsu
7
ns
nJ, nK to nCP
hold time
nJ, nK to nCP
th
−2
66
ns
maximum clock pulse
frequency
fmax
30
24
20
MHz
December 1990
6
Philips Semiconductors
Product specification
Dual JK flip-flop with reset; negative-edge trigger
74HC/HCT107
AC WAVEFORMS
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.6 Waveforms showing the clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the J
and K to nCP set-up and hold times, the output transition times and the maximum clock pulse frequency.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing the reset (nR) input to output (nQ, nQ) propagation delays, the reset pulse width and
the nR to nCP removal time.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
7
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