74LVT543 [NXP]
3.3V Octal latched transceiver with dual enable 3-State; 3.3V八路锁存收发器，双能三态
| 型号： | 74LVT543 |
| 厂家： | 
NXP |
| 描述： | 3.3V Octal latched transceiver with dual enable 3-State |
| 文件： | 总12页 (文件大小：107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74LVT543
3.3V Octal latched transceiver with
dual enable (3-State)
Product specification
1998 Feb 19
Supersedes data of 1994 May 20
IC23 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
3.3V Octal latched transceiver with dual enable
(3-State)
74LVT543
FEATURES
DESCRIPTION
The 74LVT543 is a high-performance BiCMOS product designed for
operation at 3.3V.
• Combines 74LVT245 and 74LVT373 type functions in one device
V
CC
• 8-bit octal transceiver with D-type latch
• Back-to-back registers for storage
This device contains two sets of D-type latches for temporary
storage of data flowing in either direction. Separate Latch Enable
(LEAB, LEBA) and Output Enable (OEAB, OEBA) inputs are
provided for each register to permit independent control of data
transfer in either direction. The outputs are guaranteed to sink
64mA.
• Separate controls for data flow in each direction
• Output capability: +64mA/–32mA
• TTL input and output switching levels
FUNCTIONAL DESCRIPTION
• Input and output interface capability to systems at 5V supply
The 74LVT543 contains two sets of eight D–type latches, with
separate control pins for each set. Using data flow from A to B as an
example, when the A-to-B Enable (EAB) input and the A-to-B Latch
Enable (LEAB) input are Low the A-to-B path is transparent. A
subsequent Low-to-High transition of the LEAB signal puts the A
data into the latches where it is stored and the B outputs no longer
change with the A inputs. With EAB and OEAB both Low, the
3-State B output buffers are active and display the data present at
the outputs of the A latches.
• Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
• Live insertion/extraction permitted
• No bus current loading when output is tied to 5V bus
• Power-up 3-State
• Power-up reset
• Latch-up protection exceeds 500mA per JEDEC Std 17
Control of data flow from B to A is similar, but using the EBA, LEBA,
and OEBA inputs.
• ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
QUICK REFERENCE DATA
CONDITIONS
= 25°C; GND = 0V
SYMBOL
PARAMETER
TYPICAL
UNIT
T
amb
t
t
Propagation delay
C = 50pF;
2.3
3.0
PLH
PHL
L
ns
An to Bn or Bn to An
Input capacitance
I/O capacitance
V
CC
= 3.3V
C
V = 0V or 3.0V
I
4
pF
pF
IN
C
Outputs disabled; V = 0V or 3.0V
10
I/O
I/O
I
Total supply current
Outputs disabled; V = 3.6V
0.13
mA
CCZ
CC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
NORTH AMERICA
74LVT543 D
DWG NUMBER
SOT137-1
24-Pin Plastic SOL
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
74LVT543 D
74LVT543 DB
74LVT543 PW
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
74LVT543 DB
SOT340-1
74LVT543PW DH
SOT355-1
PIN CONFIGURATION
LOGIC SYMBOL
LEBA
OEBA
A0
1
2
3
4
5
24
23
22
21
20
V
CC
3
4
5
6
7
8
9
10
EBA
B0
B1
B2
B3
B4
B5
B6
A0 A1 A2 A3 A4 A5 A6 A7
EAB
A1
11
23
14
1
A2
EBA
OEAB
OEBA
13
2
6
7
8
9
19
18
17
16
A3
LEAB
LEBA
A4
A5
B0 B1 B2 B3 B4 B5 B6 B7
A6
A7 10
15 B7
14
22 21 20 19 18 17 16 15
11
EAB
LEAB
SV00027
GND 12
13 OEAB
SV00026
2
1998 Feb 19
853-1749 18988
Philips Semiconductors
Product specification
3.3V Octal latched transceiver with dual enable
(3-State)
74LVT543
LOGIC SYMBOL (IEEE/IEC)
LOGIC DIAGRAM
DETAIL A
22
B0
D
Q
2
1EN3
23
LE
G1
1
IC5
13
ZEN4 (AB)
11
3
A0
Q
D
GZ.
14
ZC6
LE
3
22
V3
5D
2V
4
5
21
20
19
18
17
16
15
6D
B1
B2
B3
B4
B5
B6
B7
A1
A2
A3
A4
A5
A6
A7
4
21
20
19
18
17
16
15
6
7
5
6
DETAIL A X 7
8
9
10
7
8
2
OEBA
9
13
OEAB
23
1
EBA
10
11
14
EAB
LEBA
SV00028
LEAB
SV00029
PIN DESCRIPTION
PIN NUMBER
14, 1
SYMBOL
LEAB / LEBA
EAB / EBA
OEAB / OEBA
A0 – A7
FUNCTION
A to B / B to A Latch Enable input (active-Low)
A to B / B to A Enable input (active-Low)
A to B / B to A Output Enable input (active-Low)
Port A, 3-State outputs
11, 23
13, 2
3, 4, 5, 6, 7, 8, 9, 10
22, 21, 20, 19, 18, 17, 16, 15
B0 – B7
Port B, 3-State outputs
12
24
GND
Ground (0V)
V
CC
Positive supply voltage
FUNCTION TABLE
INPUTS
OUTPUTS
STATUS
Bn or An
OEXX
EXX
LEXX
An or Bn
H
X
X
H
X
X
X
X
Z
Z
Disabled
Disabled
L
L
↑
↑
L
L
h
l
Z
Z
Disabled + Latch
Latch + Display
L
L
L
L
↑
↑
h
l
H
L
L
L
L
L
L
L
H
L
H
L
Transparent
Hold
L
L
H
X
NC
H
h
=
=
High voltage level
X
↑
=
=
Don’t care
High voltage level one set-up time prior to the Low-to-High
transition of LEXX or EXX (XX = AB or BA)
Low voltage level
Low voltage level one set-up time prior to the Low-to-High
transition of LEXX or EXX (XX = AB or BA)
Low-to-High transition of LEXX or EXX (XX = AB or BA)
NC= No change
Z = High impedance or “off” state
L
l
=
=
3
1998 Feb 19
Philips Semiconductors
Product specification
3.3V Octal latched transceiver with dual enable
(3-State)
74LVT543
1, 2
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
CONDITIONS
RATING
–0.5 to +4.6
–50
UNIT
V
V
CC
I
IK
DC supply voltage
DC input diode current
V < 0
I
mA
V
3
V
I
DC input voltage
–0.5 to +7.0
–50
I
DC output diode current
V
O
< 0
mA
V
OK
3
V
OUT
DC output voltage
Output in Off or High state
Output in Low state
–0.5 to +7.0
128
I
DC output current
mA
OUT
Output in High state
–64
T
stg
Storage temperature range
–65 to 150
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
UNIT
MIN
2.7
0
MAX
3.6
V
CC
DC supply voltage
V
V
V
I
Input voltage
5.5
V
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
2.0
V
IH
V
0.8
–32
32
V
IL
I
mA
OH
I
mA
OL
Low-level output current; current duty cycle ≤ 50%; f ≥ 1kHz
Input transition rise or fall rate; outputs enabled
Operating free-air temperature range
64
∆t/∆v
10
ns/V
T
amb
–40
+85
°C
4
1998 Feb 19
Philips Semiconductors
Product specification
3.3V Octal latched transceiver with dual enable
(3-State)
74LVT543
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
Input clamp voltage
TEST CONDITIONS
Temp = -40°C to +85°C
UNIT
V
1
MIN
TYP
MAX
V
IK
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.7V; I = –18mA
–0.9
–1.2
IK
= 2.7 to 3.6V; I = –100µA
V
-0.2
V
CC
-0.1
OH
CC
V
OH
High-level output voltage
= 2.7V; I = –8mA
2.4
2.5
V
OH
= 3.0V; I = –32mA
2.0
2.2
0.1
OH
= 2.7V; I = 100µA
0.2
0.5
OL
= 2.7V; I = 24mA
0.3
OL
V
OL
Low-level output voltage
= 3.0V; I = 16mA
0.25
0.3
0.4
V
OL
= 3.0V; I = 32mA
0.5
OL
= 3.0V; I = 64mA
0.4
0.55
0.55
OL
5
V
RST
Power-up output low voltage
= 3.6V; I = 1mA; V = GND or V
CC
0.13
V
O
I
V
V
V
= 3.6V; V = V or GND
±0.1
1
±1
10
20
CC
CC
CC
I
CC
Control pins
I/O Data pins
= 0 or 3.6V; V = 5.5V
I
I
Input leakage current
= 3.6V; V = 5.5V
1
µA
I
I
4
V
CC
V
CC
V
CC
= 3.6V; V = V
CC
0.1
–1
1
1
-5
I
= 3.6V; V = 0
I
I
Output off current
= 0V; V or V = 0 to 4.5V
±100
µA
µA
OFF
I
O
V
CC
V
CC
V
CC
= 3V; V = 0.8V
75
150
I
6
= 3V; V = 2.0V
–75
–150
I
Bus Hold current A inputs
I
HOLD
= 0V to 3.6V; V = 3.6V
±500
CC
Current into an output in the
I
V
= 5.5V; V = 3.0V
60
15
125
µA
µA
EX
O
CC
High state when V > V
O
CC
Power up/down 3-State output
V
CC
≤ 1.2V; V = 0.5V to V ; V = GND or V
;
CC
O
CC
I
I
±100
PU/PD
3
current
OE/OE = Don’t care
I
V
V
V
V
= 3.6V; Outputs High, V = GND or V I 0
CC, O =
0.13
3
0.19
12
CCH
CC
CC
CC
CC
I
I
Quiescent supply current
= 3.6V; Outputs Low, V = GND or V I 0
CC, O =
mA
mA
CCL
I
I
= 3.6V; Outputs Disabled; V = GND or V
I 0
CC, O =
0.13
0.19
CCZ
I
Additional supply current per
= 3V to 3.6V; One input at V -0.6V,
CC
∆I
0.1
0.2
CC
2
input pin
Other inputs at V or GND
CC
NOTES:
1. All typical values are at V = 3.3V and T
= 25°C.
amb
CC
2. This is the increase in supply current for each input at the specified voltage level other than V or GND
CC
3. This parameter is valid for any V between 0V and 1.2V with a transition time of up to 10msec. From V = 1.2V to V = 3.3V ± 0.3V a
CC
CC
CC
transition time of 100µsec is permitted. This parameter is valid for T
= 25°C only.
amb
4. Unused pins at V or GND.
CC
5. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
6. This is the bus hold overdrive current required to force the input to the opposite logic state.
5
1998 Feb 19
Philips Semiconductors
Product specification
3.3V Octal latched transceiver with dual enable
(3-State)
74LVT543
AC CHARACTERISTICS
GND = 0V, t = t = 2.5ns, C = 50pF, R = 500Ω; T
= –40°C to +85°C.
R
F
L
L
amb
LIMITS
= 3.3V ±0.3V
SYMBOL
PARAMETER
WAVEFORM
V
CC
V
CC
= 2.7V
UNIT
1
MIN
TYP
MAX
MAX
t
t
Propagation delay
An to Bn, Bn to An
1.0
1.0
2.3
3.0
4.7
4.6
5.5
5.8
PLH
PHL
2
ns
ns
ns
ns
ns
ns
t
t
Propagation delay
LEBA to An, LEAB to Bn
1
2
1.0
1.0
3.6
4.2
5.9
5.7
7.3
7.3
PLH
PHL
t
Output enable time
OEBA to An, OEAB to Bn
4
5
1.0
1.1
3.8
3.8
5.8
6.4
7.6
8.2
PZH
t
PZL
t
Output disable time
OEBA to An, OEAB to Bn
4
5
2.4
2.0
3.7
3.5
6.5
5.8
7.1
5.9
PHZ
t
PLZ
t
Output enable time
EBA to An, EAB to Bn
4
5
1.0
1.4
4.0
4.1
6.0
6.7
7.6
8.3
PZH
t
PZL
t
Output disable time
EBA to An, EAB to Bn
4
5
2.3
2.0
3.7
3.5
6.4
5.4
7.1
5.6
PHZ
t
PLZ
NOTE:
1. All typical values are at V = 3.3V and T
= 25°C.
CC
amb
AC SETUP REQUIREMENTS
GND = 0V, t = t = 2.5ns, C = 50pF, R = 500Ω; T
= –40°C to +85°C.
R
F
L
L
amb
LIMITS
SYMBOL
PARAMETER
WAVEFORM
V
CC
= 3.3V ±0.3V
V
CC
= 2.7V
UNIT
MIN
MAX
MIN
t (H)
t (L)
s
Setup time
An to LEAB, Bn to LEBA
0
0.8
0
1.1
s
3
3
3
ns
ns
ns
t (H)
Hold time
An to LEAB, Bn to LEBA
1.7
1.7
1.7
1.7
h
t (L)
h
t (H)
Setup time
An to EAB, Bn to EBA
0
0.9
0
1.2
s
t (L)
s
t (H)
t (L)
h
Hold time
An to EAB, Bn to EBA
1.8
1.8
1.8
1.8
h
3
3
ns
ns
t (L)
w
Latch enable pulse width, Low
3.3
3.3
AC WAVEFORMS
V
M
= 1.5V, V = GND to 2.7V
IN
2.7V
0V
2.7V
V
IN
V
IN
1.5V
1.5V
1.5V
1.5V
0V
t
t
PLH
PHL
t
t
PHL
PLH
V
OH
V
V
OH
OL
V
OUT
V
OUT
1.5V
1.5V
1.5V
1.5V
V
OL
SV00030
SV00113
Waveform 1. Propagation Delay For Inverting Output
Waveform 2. Propagation Delay For Non-Inverting Output
6
1998 Feb 19
Philips Semiconductors
Product specification
3.3V Octal latched transceiver with dual enable
(3-State)
74LVT543
2.7V
0V
2.7V
An,
Bn
1.5V
t
1.5V
1.5V
1.5V
1.5V
1.5V
1.5V
OEAB, OEBA,
EAB, EBA
0V
t
PZL
PLZ
t (H)
t (L)
s
t
(H)
t (L)
h
s
h
3.0V
2.7V
LEAB, LEBA,
EAB, EBA
t
(L)
1.5V
w
V
+0.3V
An, Bn
OL
1.5V
V
OL
0V
NOTE: The shaded areas indicate when the input is permitted
SV00116
to change for predictable output performance.
Waveform 5. 3-State Output Enable Time to Low Level
and Output Disable Time from Low Level
SV00114
Waveform 3. Data Setup and Hold Times And Latch Enable
Pulse Width
2.7V
OEAB, OEBA,
EAB, EBA
1.5V
t
1.5V
0V
OH
t
PZH
PHZ
V
An, Bn
V
OH
–0.3V
0V
1.5V
SV00115
Waveform 4. 3-State Output Enable Time to High Level
and Output Disable Time from High Level
TEST CIRCUIT AND WAVEFORM
6.0V
V
CC
t
W
AMP (V)
Open
GND
90%
90%
NEGATIVE
PULSE
V
V
M
V
V
OUT
M
10%
R
R
IN
L
10%
90%
PULSE
GENERATOR
D.U.T.
0V
(t
t
t
(t
(t
)
t
TLH
)
THL
F
R
R
T
C
L
L
)
t
(t )
TLH
R
THL F
AMP (V)
90%
M
Test Circuit for 3-State Outputs
POSITIVE
PULSE
V
V
M
10%
10%
t
W
0V
SWITCH POSITION
V
= 1.5V
M
TEST
SWITCH
Open
6V
Input Pulse Definition
t
/t
PLH PHL
t
/t
PLZ PZL
t
/t
GND
PHZ PZH
INPUT PULSE REQUIREMENTS
DEFINITIONS
FAMILY
R = Load resistor; see AC CHARACTERISTICS for value.
L
Amplitude
Rep. Rate
t
t
R
t
F
W
C = Load capacitance includes jig and probe capacitance;
L
see AC CHARACTERISTICS for value.
74LVT
2.7V
v10MHz
500ns v2.5ns v2.5ns
R = Termination resistance should be equal to Z
T
of
OUT
pulse generators.
SV00092
7
1998 Feb 19
Philips Semiconductors
Product specification
3.3V Octal latched transceiver with dual enable
(3-State)
74LVT543
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
8
1998 Feb 19
Philips Semiconductors
Product specification
3.3V Octal latched transceiver with dual enable
(3-State)
74LVT543
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
SOT340-1
9
1998 Feb 19
Philips Semiconductors
Product specification
3.3V Octal latched transceiver with dual enable
(3-State)
74LVT543
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
10
1998 Feb 19
Philips Semiconductors
Product specification
3.3V Octal latched transceiver with dual enable
(3-State)
74LVT543
NOTES
11
1998 Feb 19
Philips Semiconductors
Product specification
3.3V Octal latched transceiver with dual enable
(3-State)
74LVT543
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 05-96
9397-750-03537
Document order number:
Philips
Semiconductors
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