74LVC240AD-T [NXP]
IC LVC/LCX/Z SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, PDSO20, 7.50 MM, PLASTIC, MS-013, SOT-163-1, SO-20, Bus Driver/Transceiver;![74LVC240AD-T](http://pdffile.icpdf.com/pdf2/p00223/img/icpdf/74LVC240APW-_1303770_icpdf.jpg)
型号: | 74LVC240AD-T |
厂家: | ![]() |
描述: | IC LVC/LCX/Z SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, PDSO20, 7.50 MM, PLASTIC, MS-013, SOT-163-1, SO-20, Bus Driver/Transceiver 驱动 光电二极管 输出元件 逻辑集成电路 |
文件: | 总17页 (文件大小:210K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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74LVC240A
Octal buffer/line driver with 5 V tolerant inputs/outputs;
inverting; 3-state
Rev. 8 — 29 November 2011
Product data sheet
1. General description
The 74LVC240A is an octal inverting buffer/line driver with 3-state outputs. The 3-state
outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH on nOE causes
the outputs to assume a high-impedance OFF-state. Schmitt trigger action at all inputs
makes the circuit highly tolerant of slower input rise and fall times.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices as translators in
mixed 3.3 V or 5 V applications.
The 74LVC240A is functionally identical to the 74LVC244A except that the 244 has
non-inverting outputs.
2. Features and benefits
5 V tolerant inputs for interlacing with 5 V logic
Supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
High-impedance when VCC = 0 V
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from 40 C to +85 C and 40 C to +125 C
74LVC240A
NXP Semiconductors
Octal buffer/line driver with 5 V tolerant inputs/outputs; inverting;
3-state
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVC240AD
40 C to +125 C
SO20
plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
74LVC240ADB 40 C to +125 C
74LVC240APW 40 C to +125 C
74LVC240ABQ 40 C to +125 C
SSOP20
TSSOP20
plastic shrink small outline package; 20 leads;
body width 5.3 mm
SOT339-1
SOT360-1
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
DHVQFN20 plastic dual in-line compatible thermal enhanced very SOT764-1
thin quad flat package; no leads; 20 terminals;
body 2.5 4.5 0.85 mm
4. Functional diagram
1A0
1A1
1A2
1Y0
1Y1
1Y2
2
4
6
18
16
14
1A3
8
1
1Y3 12
1
2
EN
1OE
18
16
14
12
4
6
8
2
1Y0 18
2Y0
1A0
2A0
2Y0
2Y1
2Y2
2Y3
17
3
5
7
9
3
17 2A0
15 2A1
4
1A1
2A1
1Y1 16
15
5
2Y1
19
11
EN
2A2
13
6
14
7
1Y2
2Y2
1A2
2A2
13
9
2A3
11
19
8
12
9
1Y3
2Y3
1A3
2A3
13
15
17
7
5
3
11
2OE
1OE
2OE
1
19
mgu779
mgu780
mgu778
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Functional diagram
74LVC240A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 29 November 2011
2 of 17
74LVC240A
NXP Semiconductors
Octal buffer/line driver with 5 V tolerant inputs/outputs; inverting;
3-state
5. Pinning information
5.1 Pinning
terminal 1
index area
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
1A0
2Y0
1A1
2Y1
1A2
2Y2
1A3
2Y3
2OE
1Y0
2A0
1Y1
2A1
1Y2
2A2
1Y3
1
2
20
19
18
17
16
15
14
13
12
11
1OE
1A0
2Y0
1A1
2Y1
1A2
2Y2
1A3
2Y3
GND
V
CC
2OE
1Y0
2A0
1Y1
2A1
1Y2
2A2
1Y3
2A3
3
240
4
5
240
6
(1)
GND
7
8
9
001aad037
10
001aad036
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4. Pin configuration for SO20 and (T)SSOP20
Fig 5. Pin configuration for DHVQFN20
5.2 Pin description
Table 2.
Symbol
1OE
Pin description
Pin
1
Description
output enable input (active LOW)
output enable input (active LOW)
data input
2OE
19
1A[0:3]
2A[0:3]
1Y[0:3]
2Y[0:3]
GND
2, 4, 6, 8
17, 15, 13, 11
18, 16, 14, 12
3, 5, 7, 9
10
data input
data output
data output
ground (0 V)
VCC
20
power supply
74LVC240A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 29 November 2011
3 of 17
74LVC240A
NXP Semiconductors
Octal buffer/line driver with 5 V tolerant inputs/outputs; inverting;
3-state
6. Functional description
Table 3.
Function selection[1]
Inputs
Output
nOE
L
nAn
L
nYn
H
L
H
L
H
X
Z
[1] H = HIGH voltage level
L = LOW voltage level
X = don’t care
Z = high-impedance OFF-state
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
0.5
50
0.5
-
Max
+6.5
-
Unit
V
supply voltage
input clamping current
input voltage
VI < 0
mA
V
[1]
VI
+6.5
50
VCC + 0.5
+6.5
50
100
-
IOK
output clamping current
output voltage
VO > VCC or VO < 0
output HIGH or LOW state
output 3-state
mA
V
[2]
[2]
VO
0.5
0.5
-
V
IO
output current
VO = 0 V to VCC
mA
mA
mA
C
ICC
IGND
Tstg
Ptot
supply current
-
ground current
100
65
-
storage temperature
total power dissipation
+150
500
[3]
Tamb = 40 C to +125 C
mW
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] For SO20 packages: above 70 C derate linearly with 8 mW/K.
For (T)SSOP20 packages: above 60 C derate linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60 C derate linearly with 4.5 mW/K.
74LVC240A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 29 November 2011
4 of 17
74LVC240A
NXP Semiconductors
Octal buffer/line driver with 5 V tolerant inputs/outputs; inverting;
3-state
8. Recommended operating conditions
Table 5.
Symbol
VCC
Recommended operating conditions
Parameter
Conditions
Min
1.65
1.2
0
Typ
Max
3.6
-
Unit
V
supply voltage
-
-
-
-
-
-
-
-
functional
V
VI
input voltage
5.5
VCC
5.5
+125
20
V
VO
output voltage
output HIGH or LOW state
output 3-state
0
V
0
V
Tamb
ambient temperature
in free air
40
0
C
ns/V
ns/V
t/V
input transition rise and fall VCC = 1.65 V to 2.7 V
rate
VCC = 2.7 V to 3.6 V
0
10
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C
Unit
Min
Typ[1]
Max
Min
Max
VIH
HIGH-level
input voltage
VCC = 1.2 V
1.08
-
-
-
-
-
-
-
-
-
1.08
-
V
V
V
V
V
V
V
V
VCC = 1.65 V to 1.95 V
0.65 VCC
-
0.65 VCC
-
VCC = 2.3 V to 2.7 V
1.7
-
1.7
-
VCC = 2.7 V to 3.6 V
VCC = 1.2 V
2.0
-
0.12
2.0
-
0.12
VIL
LOW-level
input voltage
-
-
-
-
-
-
-
-
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VI = VIH or VIL
0.35 VCC
0.7
0.35 VCC
0.7
0.8
0.8
VOH
HIGH-level
output
voltage
IO = 100 A;
VCC = 1.65 V to 3.6 V
VCC 0.2
-
-
VCC 0.3
-
V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 18 mA; VCC = 3.0 V
IO = 24 mA; VCC = 3.0 V
VI = VIH or VIL
1.2
1.8
2.2
2.4
2.2
-
-
-
-
-
-
-
-
-
-
1.05
1.65
2.05
2.25
2.0
-
-
-
-
-
V
V
V
V
V
VOL
LOW-level
output
voltage
IO = 100 A;
-
-
0.2
-
0.3
V
VCC = 1.65 V to 3.6 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
-
-
-
-
-
-
0.45
0.6
-
-
-
-
-
0.65
0.8
V
-
V
-
-
0.4
0.6
V
0.55
5
0.8
V
II
input leakage VCC = 3.6 V; VI = 5.5 V or GND
current
0.1
20
A
74LVC240A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 29 November 2011
5 of 17
74LVC240A
NXP Semiconductors
Octal buffer/line driver with 5 V tolerant inputs/outputs; inverting;
3-state
Table 6.
Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C
Unit
Min
Typ[1]
Max
Min
Max
IOZ
OFF-state
output
VI = VIH or VIL; VCC = 3.6 V;
VO = 5.5 V or GND;
-
0.1
10
-
20
A
current
IOFF
power-off
leakage
current
VCC = 0 V; VI or VO = 5.5 V
-
0.1
10
-
20
A
ICC
supply
current
VCC = 3.6 V; VI = VCC or GND;
IO = 0 A
-
-
0.1
5
10
-
-
40
A
A
ICC
additional
supply
current
per input pin;
VCC = 2.7 V to 3.6 V;
VI = VCC 0.6 V; IO = 0 A
500
5000
CI
input
VCC = 0 V to 3.6 V;
-
5.0
-
-
-
pF
capacitance VI = GND to VCC
[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 C.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 8.
Symbol Parameter Conditions 40 C to +85 C
40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
[2]
[2]
[2]
[3]
tpd
propagation 1An to 1Yn; 2An to 2Yn; see Figure 6
delay
VCC = 1.2 V
-
16
5.7
3.0
3.1
2.6
-
-
-
ns
ns
ns
ns
ns
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.0
0.5
1.5
1.3
12.7
6.6
7.0
5.5
1.0
0.5
1.5
1.3
14.6
7.6
9.0
7.0
VCC = 3.0 V to 3.6 V
ten
enable time
1OE to 1Yn; 2OE to 2Yn; see Figure 7
VCC = 1.2 V
-
19
6.3
3.6
3.7
2.9
-
-
-
ns
ns
ns
ns
ns
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.5
1.5
1.0
1.1
15.9
8.8
8.5
7.0
1.5
1.5
1.0
1.1
18.3
10.1
11.0
9.0
VCC = 3.0 V to 3.6 V
tdis
disable time 1OE to 1Yn; 2OE to 2Yn; see Figure 7
VCC = 1.2 V
-
17
4.1
3.4
3.1
2.9
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
2.3
1.0
1.5
1.4
-
9.9
5.6
7.5
6.0
1.0
2.3
1.0
1.5
1.4
-
11.4
6.5
9.5
7.5
1.5
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
tsk(o)
output skew VCC = 3.0 V to 3.6 V
time
74LVC240A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 29 November 2011
6 of 17
74LVC240A
NXP Semiconductors
Octal buffer/line driver with 5 V tolerant inputs/outputs; inverting;
3-state
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 8.
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
[4]
CPD
power
dissipation
capacitance
per buffer; VI = GND to VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
-
-
-
2.0
5.2
8.1
-
-
-
-
-
-
pF
pF
pF
VCC = 3.0 V to 3.6 V
[1] Typical values are measured at Tamb = 25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.
[2] tpd is the same as tPLH and tPHL
ten is the same as tPZL and tPZH
tdis is the same as tPLZ and tPHZ
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] PD is used to determine the dynamic power dissipation (PD in W).
.
.
.
C
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz; fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
(CL VCC2 fo) = sum of the outputs
11. AC waveforms
V
I
nAn input
GND
V
V
M
t
M
t
PHL
PLH
V
OH
V
V
M
nYn output
M
V
OL
mgu781
VM = 1.5 V at VCC 2.7 V;
VM = 0.5 VCC at VCC < 2.7 V;
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 6. Inputs (1An, 2An) to outputs (1Yn, 2Yn) propagation delays
74LVC240A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 29 November 2011
7 of 17
74LVC240A
NXP Semiconductors
Octal buffer/line driver with 5 V tolerant inputs/outputs; inverting;
3-state
V
I
nOE input
nYn output
V
M
GND
t
t
PZL
PLZ
V
CC
V
LOW-to-OFF
OFF-to-LOW
M
V
X
V
OL
t
t
PHZ
PZH
V
OH
V
Y
nYn output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
mgu782
VM = 1.5 V at VCC 2.7 V.
VM = 0.5 VCC at VCC < 2.7 V.
VOL and VOH are typical output voltage levels that occur with the output load.
X =VOL + 0.3 V at VCC 2.7 V;
V
VX =VOL + 0.15 V at VCC 2.7 V;
VY =VOH 0.3 V at VCC 2.7 V;
V
Y =VOH 0.15 V at VCC 2.7 V.
Fig 7. 3-state enable and disable times
74LVC240A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 29 November 2011
8 of 17
74LVC240A
NXP Semiconductors
Octal buffer/line driver with 5 V tolerant inputs/outputs; inverting;
3-state
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
R
V
CC
L
V
V
O
I
G
DUT
R
T
C
L
R
L
001aae331
Test data is given in Table 8.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 8. Test circuit for measuring switching times
Table 8.
Test data
Supply voltage
Input
VI
Load
CL
VEXT
tr, tf
RL
tPLH, tPHL
open
tPLZ, tPZL
2 VCC
2 VCC
2 VCC
2 VCC
2 VCC
tPHZ, tPZH
GND
1.2 V
VCC
VCC
VCC
2.7 V
2.7 V
2 ns
2 ns
2 ns
2.5 ns
2.5 ns
30 pF
30 pF
30 pF
50 pF
50 pF
1 k
1 k
500
500
500
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
open
GND
open
GND
open
GND
3.0 V to 3.6 V
open
GND
74LVC240A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 29 November 2011
9 of 17
74LVC240A
NXP Semiconductors
Octal buffer/line driver with 5 V tolerant inputs/outputs; inverting;
3-state
12. Package outline
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
y
H
E
v
M
A
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
2.65
0.1
0.25
0.01
1.27
0.05
1.4
0.25 0.25
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.51
0.014 0.009 0.49
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches
0.055
0.01 0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT163-1
075E04
MS-013
Fig 9. Package outline SOT163-1 (SO20)
74LVC240A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 29 November 2011
10 of 17
74LVC240A
NXP Semiconductors
Octal buffer/line driver with 5 V tolerant inputs/outputs; inverting;
3-state
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
D
E
A
X
v
c
H
M
A
y
E
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
7.4
7.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
0.9
0.5
mm
2
0.65
0.25
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT339-1
MO-150
Fig 10. Package outline SOT339-1 (SSOP20)
74LVC240A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 29 November 2011
11 of 17
74LVC240A
NXP Semiconductors
Octal buffer/line driver with 5 V tolerant inputs/outputs; inverting;
3-state
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
D
E
A
X
c
H
v
M
A
y
E
Z
11
20
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT360-1
MO-153
Fig 11. Package outline SOT360-1 (TSSOP20)
74LVC240A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 29 November 2011
12 of 17
74LVC240A
NXP Semiconductors
Octal buffer/line driver with 5 V tolerant inputs/outputs; inverting;
3-state
DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
20 terminals; body 2.5 x 4.5 x 0.85 mm
SOT764-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
9
L
1
10
E
h
e
20
11
19
12
D
h
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
1
y
D
D
E
L
v
w
y
1
1
h
h
max.
0.05 0.30
0.00 0.18
4.6
4.4
3.15
2.85
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
3.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT764-1
- - -
MO-241
- - -
Fig 12. Package outline SOT764-1 (DHVQFN20)
74LVC240A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 29 November 2011
13 of 17
74LVC240A
NXP Semiconductors
Octal buffer/line driver with 5 V tolerant inputs/outputs; inverting;
3-state
13. Abbreviations
Table 9.
Acronym
CDM
DUT
Abbreviations
Description
Charged Device Model
Device Under Test
ElectroStatic Discharge
Human Body Model
Machine Model
ESD
HBM
MM
TTL
Transistor-Transistor Logic
14. Revision history
Table 10. Revision history
Document ID
74LVC240 v.8
Modifications:
74LVC240A v.7
Modifications:
Release date
20111129
Data sheet status
Change notice Supersedes
Product data sheet
-
74LVC240A v.7
• Table 7: maximum values for lower voltage ranges changed (errata).
20111027 Product data sheet
-
74LVC240A v.6
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Table 4, Table 5, Table 6, Table 7 and Table 8: values added for lower voltage ranges.
74LVC240A v.6
74LVC240A v.5
74LVC240A v.4
74LVC240A v.3
74LVC240A v.2
74LVC240A v.1
20031202
20030514
20021220
20021002
19980520
-
Product specification
Product specification
Product specification
Product specification
Product specification
Product specification
-
-
-
-
-
-
74LVC240A v.5
74LVC240A v.4
74LVC240A v.3
74LVC240A v.2
74LVC240A v.1
-
74LVC240A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 29 November 2011
14 of 17
74LVC240A
NXP Semiconductors
Octal buffer/line driver with 5 V tolerant inputs/outputs; inverting;
3-state
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
15.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
15.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
74LVC240A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 29 November 2011
15 of 17
74LVC240A
NXP Semiconductors
Octal buffer/line driver with 5 V tolerant inputs/outputs; inverting;
3-state
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74LVC240A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 29 November 2011
16 of 17
74LVC240A
NXP Semiconductors
Octal buffer/line driver with 5 V tolerant inputs/outputs; inverting;
3-state
17. Contents
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 16
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 29 November 2011
Document identifier: 74LVC240A
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