74LVC1G18GV,125 [NXP]
74LVC1G18 - 1-of-2 non-inverting demultiplexer with 3-state deselected output TSOP 6-Pin;
| 型号： | 74LVC1G18GV,125 |
| 厂家： | 
NXP |
| 描述： | 74LVC1G18 - 1-of-2 non-inverting demultiplexer with 3-state deselected output TSOP 6-Pin |
| 文件： | 总13页 (文件大小：67K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVC1G18
1-of-2 non-inverting demultiplexer with 3-state deselected
output
Rev. 02 — 30 August 2007
Product data sheet
1. General description
The 74LVC1G18 is a 1-of-2 non-inverting demultiplexer with a 3-state output. The device
buffers the data on input pin A and passes it either to output 1Y or 2Y, depending on
whether the state of the select input (pin S) is LOW or HIGH. Input can be driven from
either 3.3 or 5 V devices. These features allow the use of these devices in a mixed
3.3 and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
2. Features
I Wide supply voltage range from 1.65 to 5.5 V
I 5 V tolerant input/output for interfacing with 5 V logic
I High noise immunity
I Complies with JEDEC standard:
N JESD8-7 (1.65 V to 1.95 V)
N JESD8-5 (2.3 V to 2.7 V)
N JESD8B/JESD36 (2.7 V to 3.6 V)
I ESD protection:
N HBM EIA/JESD22-A114E exceeds 2000 V
N MM EIA/JESD22-A115-A exceeds 200 V.
I ±24 mA output drive (VCC = 3.0 V)
I CMOS low power consumption
I Latch-up performance exceeds 250 mA
I Direct interface with TTL levels
I SOT363 and SOT457 package
I Specified from −40 to +85 °C and −40 to +125 °C.
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
SOT363
SOT457
74LVC1G18GW
74LVC1G18GV
−40 °C to +125 °C
−40 °C to +125 °C
SC-88
SC-74
plastic surface-mounted package; 6 leads
plastic surface-mounted package (TSOP6); 5 leads
74LVC1G18
NXP Semiconductors
1-of-2 non-inverting demultiplexer with 3-state deselected output
4. Marking
Table 2.
Marking
Type number
74LVC1G18GW
74LVC1G18GV
Marking code
VW
V18
5. Functional diagram
1Y
6
S
1
2Y
A
3
4
mnb088
Fig 1. Logic symbol
6. Pinning information
6.1 Pinning
74LVC1G18
1
2
3
6
5
4
S
GND
A
1Y
V
CC
2Y
001aag921
Fig 2. Pin configuration
6.2 Pin description
Table 3.
Symbol
S
Pin description
Pin
1
Description
data select
ground (0 V)
data input
GND
A
2
3
2Y
4
data output
supply voltage
data output
VCC
1Y
5
6
74LVC1G18_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 30 August 2007
2 of 13
74LVC1G18
NXP Semiconductors
1-of-2 non-inverting demultiplexer with 3-state deselected output
7. Functional description
Table 4.
Function table[1]
Input
Output
S
L
A
L
1Y
L
2Y
Z
L
H
L
H
Z
Z
H
H
L
H
Z
H
[1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
−0.5
−50
−0.5
-
Max
+6.5
-
Unit
V
supply voltage
input clamping current
input voltage
VI < 0 V
mA
V
[1]
VI
+6.5
±50
VCC + 0.5
+6.5
±50
100
-
IOK
output clamping current
output voltage
VO > VCC or VO < 0 V
Active mode
mA
V
[1][2]
[1][2]
VO
−0.5
−0.5
-
Power-down mode
VO = 0 V to VCC
V
IO
output current
mA
mA
mA
°C
ICC
IGND
Tstg
Ptot
supply current
-
ground current
−100
−65
-
storage temperature
total power dissipation
+150
300
[3]
Tamb = −40 °C to +125 °C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3] For SC-74 and SC-88 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
VCC
Recommended operating conditions
Parameter
Conditions
Min
Typ
Max
5.5
Unit
V
supply voltage
input voltage
output voltage
1.65
-
-
-
-
-
-
-
VI
0
5.5
V
VO
Active mode
0
VCC
5.5
VO
VO
°C
VCC = 0 V; Power-down mode
0
Tamb
ambient temperature
−40
+125
20
∆t/∆V
input transition rise and fall rate VCC = 1.65 V to 2.7 V
VCC = 2.7 V to 5.5 V
-
-
ns/V
ns/V
10
74LVC1G18_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 30 August 2007
3 of 13
74LVC1G18
NXP Semiconductors
1-of-2 non-inverting demultiplexer with 3-state deselected output
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ[1] Max
Unit
Tamb = −40 °C to +85 °C
VIH
HIGH-level input voltage
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
0.65 × VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
1.7
-
2.0
-
0.7 × VCC
-
VIL
LOW-level input voltage
-
-
-
-
0.35 × VCC
0.7
0.8
0.3 × VCC
VOH
HIGH-level output voltage VI = VIH or VIL
IO = −100 µA; VCC = 1.65 V to 5.5 V
V
CC − 0.1
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
IO = −4 mA; VCC = 1.65 V
IO = −8 mA; VCC = 2.3 V
IO = −12 mA; VCC = 2.7 V
IO = −24 mA; VCC = 3.0 V
IO = −32 mA; VCC = 4.5 V
VI = VIH or VIL
1.2
1.9
2.2
2.3
3.8
VOL
LOW-level output voltage
IO = 100 µA; VCC = 1.65 V to 5.5 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
-
-
-
-
-
-
-
-
-
0.1
V
-
0.45
0.3
V
-
V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
VCC = 0 V to 5.5 V; VI = 5.5 V or GND
-
0.4
V
-
0.55
0.55
±5
V
-
V
II
input leakage current
±0.1
±0.1
µA
µA
IOZ
OFF-state output current
VCC = 3.6 V; VI = VIH or VIL;
VO = 5.5 V or GND
±10
IOFF
ICC
power-off leakage current VCC = 0 V; VI or VO = 5.5 V
-
-
±0.1
±10
µA
µA
supply current
VI = 5.5 V or GND;
CC = 1.65 V to 5.5 V; IO = 0 A
0.1
10
V
∆ICC
additional supply current
input capacitance
per pin; VCC = 2.3 V to 5.5 V;
VI = VCC − 0.6 V; IO = 0 A
-
-
5
500
-
µA
CI
VCC = 3.3 V; VI = GND to VCC
2.5
pF
Tamb = −40 °C to +125 °C
VIH
HIGH-level input voltage
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
0.65 × VCC
1.7
-
-
-
-
-
-
-
-
V
V
V
V
2.0
0.7 × VCC
74LVC1G18_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 30 August 2007
4 of 13
74LVC1G18
NXP Semiconductors
1-of-2 non-inverting demultiplexer with 3-state deselected output
Table 7.
Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ[1] Max
Unit
V
VIL
LOW-level input voltage
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
-
-
-
-
-
-
-
-
0.35 × VCC
0.7
V
0.8
V
0.3 × VCC
V
VOH
HIGH-level output voltage VI = VIH or VIL
IO = −100 µA; VCC = 1.65 V to 5.5 V
IO = −4 mA; VCC = 1.65 V
IO = −8 mA; VCC = 2.3 V
IO = −12 mA; VCC = 2.7 V
IO = −24 mA; VCC = 3.0 V
IO = −32 mA; VCC = 4.5 V
VI = VIH or VIL
V
CC − 0.1
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
0.95
1.7
1.9
2.0
3.4
VOL
LOW-level output voltage
IO = 100 µA; VCC = 1.65 V to 5.5 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
0.70
0.45
0.60
0.80
0.80
±20
±20
V
V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
VCC = 0 V to 5.5 V; VI = 5.5 V or GND
V
V
V
II
input leakage current
µA
µA
IOZ
OFF-state output current
VCC = 3.6 V; VI = VIH or VIL;
VO = 5.5 V or GND
IOFF
ICC
power-off leakage current VCC = 0 V; VI or VO = 5.5 V
-
-
-
-
±20
µA
µA
supply current
VI = 5.5 V or GND;
CC = 1.65 V to 5.5 V; IO = 0 A
40
V
∆ICC
additional supply current
per pin; VCC = 2.3 V to 5.5 V;
-
-
5000
µA
VI = VCC − 0.6 V; IO = 0 A
[1] All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
74LVC1G18_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 30 August 2007
5 of 13
74LVC1G18
NXP Semiconductors
1-of-2 non-inverting demultiplexer with 3-state deselected output
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 5.
Symbol Parameter Conditions −40 °C to +85 °C
−40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
[2]
[3]
[4]
[5]
tpd
propagation delay A to nY; see Figure 3
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
1.0
1.0
1.0
1.0
1.0
5.1
3.2
3.2
3.0
2.3
10.0
5.5
5.4
5.0
3.8
1.0
0.5
0.5
0.5
0.5
12.5
6.9
6.8
6.3
4.8
ns
ns
ns
ns
ns
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
ten
enable time
S to nY; see Figure 3
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.0
1.0
1.0
1.0
1.0
5.8
3.6
3.6
3.1
2.4
11.0
6.2
6.0
5.2
3.6
1.0
0.5
0.5
0.5
0.5
13.8
7.8
7.5
6.5
4.5
ns
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
S to nY; see Figure 3
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
tdis
disable time
1.0
1.0
1.0
1.0
0.5
-
4.8
2.7
3.5
3.3
2.2
28.8
9.0
5.3
5.2
4.9
3.3
-
1.0
0.5
0.5
0.5
0.5
-
11.3
6.6
6.5
6.1
4.1
-
ns
ns
ns
ns
ns
pF
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
CPD
power dissipation VI = GND to VCC; VCC = 3.3 V
capacitance
[1] Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2] tpd is the same as tPLH and tPHL
[3] ten is the same as tPZH and tPZL
[4] tdis is the same as tPLZ and tPHZ
[5] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL × VCC2 × fo) = sum of outputs.
74LVC1G18_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 30 August 2007
6 of 13
74LVC1G18
NXP Semiconductors
1-of-2 non-inverting demultiplexer with 3-state deselected output
12. AC waveforms
V
I
V
V
M
A input
M
GND
t
t
PLH
PHL
V
OH
V
V
M
nY output
M
V
OL
mnb089
Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output load.
Fig 3. Input A to output Y propagation delays
Table 9.
VCC
Measurement points
VM
Input
VI
tr = tf
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
0.5 × VCC
0.5 × VCC
1.5 V
VCC
VCC
2.7 V
2.7 V
VCC
≤ 2.0 ns
≤ 2.0 ns
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
3.0 V to 3.6 V
4.5 V to 5.5 V
1.5 V
0.5 × VCC
V
I
S input
V
M
t
GND
t
PLZ
PZL
V
CC
nY output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
nY output
V
HIGH-to-OFF
OFF-to-HIGH
M
GND
output
enabled
output
enabled
output
disabled
mnb090
Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output load.
VX = VOL + 0.3 V at VCC ≥ 2.7 V.
VX = VOL + 0.15 V at VCC < 2.7 V.
VY = VOH − 0.3 V at VCC ≥ 2.7 V.
VY = VOH − 0.15 V at VCC < 2.7 V.
Fig 4. 3-state enable and disable times
74LVC1G18_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 30 August 2007
7 of 13
74LVC1G18
NXP Semiconductors
1-of-2 non-inverting demultiplexer with 3-state deselected output
V
EXT
V
CC
R
L
V
V
O
I
G
DUT
R
T
C
L
R
L
mna616
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 5. Load circuitry for switching times
Table 10. Test data
VCC
Input
VI
Load
CL
VEXT
tr = tf
RL
tPLH, tPHL
open
tPZH, tPHZ
GND
tPZL, tPLZ
2 × VCC
2 × VCC
6 V
1.65 V to 1.95 V VCC
≤ 2.0 ns
≤ 2.0 ns
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
30 pF
30 pF
50 pF
50 pF
50 pF
1 kΩ
2.3 V to 2.7 V
2.7 V
VCC
500 Ω
500 Ω
500 Ω
500 Ω
open
GND
2.7 V
2.7 V
VCC
open
GND
3.0 V to 3.6 V
4.5 V to 5.5 V
open
GND
6 V
open
GND
2 × VCC
74LVC1G18_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 30 August 2007
8 of 13
74LVC1G18
NXP Semiconductors
1-of-2 non-inverting demultiplexer with 3-state deselected output
13. Package outline
Plastic surface-mounted package; 6 leads
SOT363
D
B
E
A
X
y
H
v
M
A
E
6
5
4
Q
pin 1
index
A
A
1
1
2
3
c
e
1
b
p
L
p
w
M B
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
UNIT
A
b
c
D
E
e
e
H
L
Q
v
w
y
p
p
1
E
max
0.30
0.20
1.1
0.8
0.25
0.10
2.2
1.8
1.35
1.15
2.2
2.0
0.45
0.15
0.25
0.15
mm
0.1
1.3
0.65
0.2
0.2
0.1
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
04-11-08
06-03-16
SOT363
SC-88
Fig 6. Package outline SOT363 (SC-88)
74LVC1G18_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 30 August 2007
9 of 13
74LVC1G18
NXP Semiconductors
1-of-2 non-inverting demultiplexer with 3-state deselected output
Plastic surface-mounted package (TSOP6); 6 leads
SOT457
D
B
E
A
X
y
H
v
M
A
E
6
5
4
Q
pin 1
index
A
A
1
c
1
2
3
L
p
e
b
p
w
M B
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A
b
c
D
E
e
H
L
Q
v
w
y
p
1
p
E
0.1
0.013
0.40
0.25
1.1
0.9
0.26
0.10
3.1
2.7
1.7
1.3
3.0
2.5
0.6
0.2
0.33
0.23
mm
0.95
0.2
0.2
0.1
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
05-11-07
06-03-16
SOT457
SC-74
Fig 7. Package outline SOT457 (SC-74)
74LVC1G18_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 30 August 2007
10 of 13
74LVC1G18
NXP Semiconductors
1-of-2 non-inverting demultiplexer with 3-state deselected output
14. Abbreviations
Table 11. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
Machine Model
HBM
MM
TTL
Transistor-Transistor Logic
15. Revision history
Table 12. Revision history
Document ID
74LVC1G18_2
Modifications:
Release date
20070830
Data sheet status
Change notice
Supersedes
Product data sheet
-
74LVC1G18_1
• The format of this data sheet has been redesigned to comply with the
new identity guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where
appropriate.
• In Section 10 “Static characteristics”, changed conditions for input
leakage and supply current.
74LVC1G18_1
20030725
Product specification
-
-
74LVC1G18_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 30 August 2007
11 of 13
74LVC1G18
NXP Semiconductors
1-of-2 non-inverting demultiplexer with 3-state deselected output
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of a NXP Semiconductors product can reasonably be expected to
16.2 Definitions
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
17. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
74LVC1G18_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 30 August 2007
12 of 13
74LVC1G18
NXP Semiconductors
1-of-2 non-inverting demultiplexer with 3-state deselected output
18. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2
7
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions. . . . . . . . 3
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 11
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11
8
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 12
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 12
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 30 August 2007
Document identifier: 74LVC1G18_2
相关型号：
74LVC1G18GW-Q100H
74LVC1G18-Q100 - 1-of-2 non-inverting demultiplexer with 3-state deselected output TSSOP 6-Pin
NXP
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