74LVC1G125GS [NXP]
Bus buffer/line driver; 3-state; 总线缓冲器/线路驱动器;三态型号: | 74LVC1G125GS |
厂家: | NXP |
描述: | Bus buffer/line driver; 3-state |
文件: | 总19页 (文件大小:148K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
74LVC1G125
Bus buffer/line driver; 3-state
Rev. 9 — 29 December 2010
Product data sheet
1. General description
The 74LVC1G125 provides one non-inverting buffer/line driver with 3-state output.
The 3-state output is controlled by the output enable input (OE). A HIGH-level at pin OE
causes the output to assume a high-impedance OFF-state.
The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of
this device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
2. Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
24 mA output drive (VCC = 3.0 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CMOS low power consumption
Inputs accept voltages up to 5 V
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
74LVC1G125
NXP Semiconductors
Bus buffer/line driver; 3-state
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVC1G125GW
40 C to +125 C
TSSOP5 plastic thin shrink small outline package; 5 leads; SOT353-1
body width 1.25 mm
74LVC1G125GV
74LVC1G125GM
40 C to +125 C
40 C to +125 C
SC-74A
XSON6
plastic surface-mounted package; 5 leads
SOT753
SOT886
plastic extremely thin small outline package;
no leads; 6 terminals; body 1 1.45 0.5 mm
74LVC1G125GF
74LVC1G125GN
74LVC1G125GS
40 C to +125 C
40 C to +125 C
40 C to +125 C
XSON6
XSON6
XSON6
plastic extremely thin small outline package;
no leads; 6 terminals; body 1 1 0.5 mm
SOT891
SOT1115
SOT1202
extremely thin small outline package; no leads;
6 terminals; body 0.9 1.0 0.35 mm
extremely thin small outline package; no leads;
6 terminals; body 1.0 1.0 0.35 mm
4. Marking
Table 2.
Marking
Type number
Marking code[1]
74LVC1G125GW
74LVC1G125GV
74LVC1G125GM
74LVC1G125GF
74LVC1G125GN
74LVC1G125GS
VM
V25
VM
VM
VM
VM
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
A
Y
4
2
1
Y
A
2
1
4
OE
EN
OE
mna118
mna119
mna120
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Logic diagram
74LVC1G125
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 9 — 29 December 2010
2 of 19
74LVC1G125
NXP Semiconductors
Bus buffer/line driver; 3-state
6. Pinning information
6.1 Pinning
74LVC1G125
74LVC1G125
OE
A
1
2
3
6
5
4
V
CC
74LVC1G125
1
2
3
5
4
OE
A
V
Y
OE
A
1
2
3
6
5
4
V
CC
CC
n.c.
Y
n.c.
Y
GND
GND
GND
001aaf199
001aaf400
Transparent top view
Transparent top view
001aaf198
Fig 4. Pin configuration
SOT353-1 and SOT753
Fig 5. Pin configuration SOT886
Fig 6. Pin configuration SOT891,
SOT1115 and SOT1202
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
Description
SOT353-1, SOT753
SOT886, SOT891, SOT1115, SOT1202
OE
A
1
2
3
4
-
1
2
3
4
5
6
output enable input
data input
GND
Y
ground (0 V)
data output
n.c.
VCC
not connected
supply voltage
5
7. Functional description
Table 4.
Function table[1]
Input
OE
L
Output
A
Y
L
L
L
H
X
H
Z
H
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF-state.
74LVC1G125
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 9 — 29 December 2010
3 of 19
74LVC1G125
NXP Semiconductors
Bus buffer/line driver; 3-state
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
0.5
50
0.5
-
Max
+6.5
-
Unit
V
supply voltage
input clamping current
input voltage
VI < 0 V
mA
V
[1]
VI
+6.5
50
VCC + 0.5
+6.5
50
100
-
IOK
output clamping current
output voltage
VO > VCC or VO < 0 V
Active mode
mA
V
[1][2]
[1][2]
VO
0.5
0.5
-
Power-down mode
VO = 0 V to VCC
V
IO
output current
mA
mA
mA
mW
C
ICC
IGND
Ptot
Tstg
supply current
-
ground current
100
-
[3]
total power dissipation
storage temperature
Tamb = 40 C to +125 C
250
+150
65
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3] For TSSOP5 and SC-74A packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 package: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
VCC
Recommended operating conditions
Parameter
Conditions
Min
Typ
Max
5.5
Unit
V
supply voltage
input voltage
output voltage
1.65
-
-
-
-
-
-
-
VI
0
5.5
V
VO
Active mode
0
VCC
5.5
V
VCC = 0 V; Power-down mode
0
V
Tamb
ambient temperature
40
+125
20
C
ns/V
ns/V
t/V
input transition rise and fall rate VCC = 1.65 V to 2.7 V
VCC = 2.7 V to 5.5 V
-
-
10
74LVC1G125
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 9 — 29 December 2010
4 of 19
74LVC1G125
NXP Semiconductors
Bus buffer/line driver; 3-state
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ[1]
Max
Unit
Tamb = 40 C to +85 C
VIH
HIGH-level input voltage VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
0.65 VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
1.7
-
VCC = 2.7 V to 3.6 V
2.0
-
VCC = 4.5 V to 5.5 V
0.7 VCC
-
VIL
LOW-level input voltage
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
-
-
-
-
0.35 VCC
0.7
0.8
0.3 VCC
VOL
LOW-level output voltage VI = VIH or VIL
VCC = 1.65 V to 5.5 V; IO = 100 A
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
V
V
V
V
V
VCC = 1.65 V; IO = 4 mA
VCC = 2.3 V; IO = 8 mA
VCC = 2.7 V; IO = 12 mA
VCC = 3.0 V; IO = 24 mA
VCC = 4.5 V; IO = 32 mA
0.45
0.3
0.4
0.55
0.55
VOH
HIGH-level output voltage VI = VIH or VIL
VCC = 1.65 V to 5.5 V; IO = 100 A
VCC = 1.65 V; IO = 4 mA
VCC 0.1
-
-
V
1.2
1.9
2.2
2.3
3.8
-
-
-
V
VCC = 2.3 V; IO = 8 mA
-
-
V
VCC = 2.7 V; IO = 12 mA
-
-
V
VCC = 3.0 V; IO = 24 mA
-
-
V
VCC = 4.5 V; IO = 32 mA
-
-
V
II
input leakage current
VCC = 0 V to 5.5 V; VI = 5.5 V or GND
0.1
0.1
5
10
A
A
IOZ
OFF-state output current VCC = 3.6 V; VI = VIH or VIL;
VO = 5.5 V or GND
-
IOFF
ICC
power-off leakage current VCC = 0 V; VI or VO = 5.5 V
-
-
0.1
10
A
A
supply current
VI = 5.5 V or GND;
CC = 1.65 V to 5.5 V; IO = 0 A
0.1
10
V
ICC
additional supply current per pin; VCC = 2.3 V to 5.5 V;
-
-
5
5
500
-
A
VI = VCC 0.6 V; IO = 0 A
CI
input capacitance
pF
74LVC1G125
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 9 — 29 December 2010
5 of 19
74LVC1G125
NXP Semiconductors
Bus buffer/line driver; 3-state
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ[1]
Max
Unit
Tamb = 40 C to +125 C
VIH
HIGH-level input voltage VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
0.65 VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
1.7
-
VCC = 2.7 V to 3.6 V
2.0
-
VCC = 4.5 V to 5.5 V
0.7 VCC
-
VIL
LOW-level input voltage
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
-
-
-
-
0.35 VCC
0.7
0.8
0.3 VCC
VOL
LOW-level output voltage VI = VIH or VIL
VCC = 1.65 V to 5.5 V; IO = 100 A
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
V
V
V
V
V
VCC = 1.65 V; IO = 4 mA
VCC = 2.3 V; IO = 8 mA
VCC = 2.7 V; IO = 12 mA
VCC = 3.0 V; IO = 24 mA
VCC = 4.5 V; IO = 32 mA
0.70
0.45
0.60
0.80
0.80
VOH
HIGH-level output voltage VI = VIH or VIL
VCC = 1.65 V to 5.5 V; IO = 100 A
VCC = 1.65 V; IO = 4 mA
VCC 0.1
-
-
-
-
-
-
-
-
-
V
0.95
1.7
1.9
2.0
3.4
-
-
V
VCC = 2.3 V; IO = 8 mA
-
V
VCC = 2.7 V; IO = 12 mA
-
V
VCC = 3.0 V; IO = 24 mA
-
V
VCC = 4.5 V; IO = 32 mA
-
V
II
input leakage current
VCC = 0 V to 5.5 V; VI = 5.5 V or GND
100
200
A
A
IOZ
OFF-state output current VCC = 3.6 V; VI = VIH or VIL;
VO = 5.5 V or GND
-
IOFF
ICC
power-off leakage current VCC = 0 V; VI or VO = 5.5 V
-
-
-
-
200
A
A
supply current
VI = 5.5 V or GND;
200
VCC = 1.65 V to 5.5 V; IO = 0 A
ICC
additional supply current per pin; VCC = 2.3 V to 5.5 V;
-
-
5000
A
VI = VCC 0.6 V; IO = 0 A
[1] All typical values are measured at VCC = 3.3 V and Tamb = 25 C.
74LVC1G125
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 9 — 29 December 2010
6 of 19
74LVC1G125
NXP Semiconductors
Bus buffer/line driver; 3-state
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9.
Symbol Parameter Conditions 40 C to +85 C
40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
[2]
[3]
[4]
[5]
tpd
propagation delay A to Y; see Figure 7
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
1.0
0.5
0.5
0.5
0.5
3.3
2.2
2.5
2.1
1.7
8.0
5.5
5.5
4.5
4.0
1.0
0.5
0.5
0.5
0.5
10.5
7
ns
ns
ns
ns
ns
VCC = 2.7 V
7
VCC = 3.0 V to 3.6 V
6
VCC = 4.5 V to 5.5 V
5.5
ten
enable time
OE to Y; see Figure 8
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.0
0.5
0.5
0.5
0.5
4.1
2.8
3.3
2.4
2.1
9.4
6.6
6.6
5.3
5.0
1.0
0.5
0.5
0.5
0.5
12
8.5
8.5
7
ns
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
OE to Y; see Figure 8
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
6.5
tdis
disable time
1.0
0.5
0.5
0.5
0.5
4.3
2.7
3.0
3.1
2.2
9.2
5.0
5.0
5.0
4.2
1.0
0.5
0.5
0.5
0.5
12
6.5
6.5
6.5
5.5
ns
ns
ns
ns
ns
V
CC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
CPD
power dissipation per buffer; VI = GND to VCC
capacitance
output enabled
-
-
25
6
-
-
-
-
-
-
pF
pF
output disabled
[1] Typical values are measured at Tamb = 25 C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2] pd is the same as tPLH and tPHL
t
[3] ten is the same as tPZH and tPZL
[4] tdis is the same as tPLZ and tPHZ
[5] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
74LVC1G125
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 9 — 29 December 2010
7 of 19
74LVC1G125
NXP Semiconductors
Bus buffer/line driver; 3-state
12. Waveforms
V
I
V
A input
M
GND
t
t
PHL
PLH
V
OH
V
Y output
M
V
mnb153
OL
Measurement points are given in Table 9.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7. Input A to output Y propagation delay times
V
I
OE input
V
M
GND
t
t
PZL
PLZ
V
CC
output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PHZ
PZH
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
mna644
Measurement points are given in Table 9.
OL and VOH are typical output voltage levels that occur with the output load.
V
Fig 8. 3-state enable and disable times
Table 9. Measurement points
Supply voltage
VCC
Input
VM
Output
VM
VX
VY
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
0.5VCC
0.5VCC
1.5 V
1.5 V
0.5VCC
0.5VCC
0.5VCC
1.5 V
VOL + 0.15 V
VOL + 0.15 V
VOL + 0.3 V
VOL + 0.3 V
VOL + 0.3 V
VOH 0.15 V
VOH 0.15 V
VOH 0.3 V
VOH 0.3 V
VOH 0.3 V
3.0 V to 3.6 V
4.5 V to 5.5 V
1.5 V
0.5VCC
74LVC1G125
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 9 — 29 December 2010
8 of 19
74LVC1G125
NXP Semiconductors
Bus buffer/line driver; 3-state
V
EXT
V
CC
R
L
V
V
O
I
G
DUT
R
T
C
L
R
L
mna616
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 9. Test circuit for measuring switching times
Table 10. Test data
Supply voltage
VCC
Input
VI
Load
CL
VEXT
tr, tf
RL
tPLH, tPHL
open
tPZH, tPHZ
GND
tPZL, tPLZ
2VCC
2VCC
6 V
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
VCC
VCC
2.7 V
2.7 V
VCC
2.0 ns
2.0 ns
2.5 ns
2.5 ns
2.5 ns
30 pF
30 pF
50 pF
50 pF
50 pF
1 k
500
500
500
500
open
GND
open
GND
3.0 V to 3.6 V
4.5 V to 5.5 V
open
GND
6 V
open
GND
2VCC
74LVC1G125
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 9 — 29 December 2010
9 of 19
74LVC1G125
NXP Semiconductors
Bus buffer/line driver; 3-state
13. Package outline
TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm
SOT353-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
4
A
2
A
(A )
3
A
1
θ
L
L
p
1
3
e
w M
b
p
detail X
e
1
0
1.5
3 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
A
A
A
b
c
D
E
e
e
1
H
L
L
p
UNIT
v
w
y
Z
θ
1
2
3
p
E
max.
0.1
0
1.0
0.8
0.30
0.15
0.25
0.08
2.25
1.85
1.35
1.15
2.25
2.0
0.46
0.21
0.60
0.15
7°
0°
mm
1.1
0.65
1.3
0.15
0.425
0.3
0.1
0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-09-01
03-02-19
SOT353-1
MO-203
SC-88A
Fig 10. Package outline SOT353-1 (TSSOP5)
74LVC1G125
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 9 — 29 December 2010
10 of 19
74LVC1G125
NXP Semiconductors
Bus buffer/line driver; 3-state
Plastic surface-mounted package; 5 leads
SOT753
D
B
E
A
X
y
H
v
M
A
E
5
4
Q
A
A
1
c
L
1
2
3
p
detail X
e
b
p
w
M B
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A
1
b
c
D
E
e
H
L
Q
v
w
y
p
p
E
0.100
0.013
0.40
0.25
1.1
0.9
0.26
0.10
3.1
2.7
1.7
1.3
3.0
2.5
0.6
0.2
0.33
0.23
mm
0.95
0.2
0.2
0.1
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
02-04-16
06-03-16
SOT753
SC-74A
Fig 11. Package outline SOT753
74LVC1G125
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 9 — 29 December 2010
11 of 19
74LVC1G125
NXP Semiconductors
Bus buffer/line driver; 3-state
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
SOT886
b
1
2
3
4×
(2)
L
L
1
e
6
5
4
e
1
e
1
6×
A
(2)
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
A
1
UNIT
b
D
E
e
e
L
L
1
1
max max
0.25
0.17
1.5
1.4
1.05
0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.6
0.5
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
04-07-15
04-07-22
SOT886
MO-252
Fig 12. Package outline SOT886 (XSON6)
74LVC1G125
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 9 — 29 December 2010
12 of 19
74LVC1G125
NXP Semiconductors
Bus buffer/line driver; 3-state
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm
SOT891
b
1
2
3
4×
(1)
L
L
1
e
6
5
4
e
1
e
1
6×
A
(1)
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
A
1
UNIT
b
D
E
e
e
L
L
1
1
max max
0.20 1.05 1.05
0.12 0.95 0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.55 0.35
Note
1. Can be visible in some manufacturing processes.
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
05-04-06
07-05-15
SOT891
Fig 13. Package outline SOT891 (XSON6)
74LVC1G125
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 9 — 29 December 2010
13 of 19
74LVC1G125
NXP Semiconductors
Bus buffer/line driver; 3-state
XSON6: extremely thin small outline package; no leads;
6 terminals; body 0.9 x 1.0 x 0.35 mm
SOT1115
b
3
(2)
(4×)
1
2
L
L
1
e
6
5
4
e
1
e
1
(2)
(6×)
A
1
A
D
E
terminal 1
index area
0
L
0.5
scale
1 mm
Dimensions
Unit
(1)
A
A
1
b
D
E
e
e
1
L
1
max 0.35 0.04 0.20 0.95 1.05
0.35 0.40
0.15 0.90 1.00 0.55 0.3 0.30 0.35
0.12 0.85 0.95 0.27 0.32
mm nom
min
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
sot1115_po
References
Outline
version
European
Issue date
projection
IEC
JEDEC
JEITA
10-04-02
10-04-07
SOT1115
Fig 14. Package outline SOT1115 (XSON6)
74LVC1G125
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 9 — 29 December 2010
14 of 19
74LVC1G125
NXP Semiconductors
Bus buffer/line driver; 3-state
XSON6: extremely thin small outline package; no leads;
6 terminals; body 1.0 x 1.0 x 0.35 mm
SOT1202
b
3
(2)
1
2
(4×)
L
L
1
e
6
5
4
e
1
e
1
(2)
(6×)
A
1
A
D
E
terminal 1
index area
0
L
0.5
1 mm
scale
Dimensions
Unit
(1)
A
A
1
b
D
E
e
e
1
L
1
max 0.35 0.04 0.20 1.05 1.05
0.35 0.40
0.15 1.00 1.00 0.55 0.35 0.30 0.35
0.12 0.95 0.95 0.27 0.32
mm nom
min
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
sot1202_po
References
Outline
version
European
Issue date
projection
IEC
JEDEC
JEITA
10-04-02
10-04-06
SOT1202
Fig 15. Package outline SOT1202 (XSON6)
74LVC1G125
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 9 — 29 December 2010
15 of 19
74LVC1G125
NXP Semiconductors
Bus buffer/line driver; 3-state
14. Abbreviations
Table 11. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
TTL
Transistor-Transistor Logic
15. Revision history
Table 12. Revision history
Document ID
74LVC1G125 v.9
Modifications:
74LVC1G125 v.8
Modifications:
Release date
20101229
Data sheet status
Change notice
Supersedes
Product data sheet
-
74LVC1G125 v.8
• Minimum limit VOH at a supply voltage of 3.0 V changed from 2.7 V to 2.3 V.
20100824 Product data sheet 74LVC1G125 v.7
-
• Added type number 74LVC1G125GN (SOT1115/XSON6 package).
• Added type number 74LVC1G125GS (SOT1202/XSON6 package).
74LVC1G125 v.7
74LVC1G125 v.6
74LVC1G125 v.5
74LVC1G125 v.4
74LVC1G125 v.3
74LVC1G125 v.2
74LVC1G125 v.1
20070830
20060912
20040915
20021118
20020528
20010406
20001222
Product data sheet
Product data sheet
Product specification
Product specification
Product specification
Product specification
Product specification
-
-
-
-
-
-
-
74LVC1G125 v.6
74LVC1G125 v.5
74LVC1G125 v.4
74LVC1G125 v.3
74LVC1G125 v.2
74LVC1G125 v.1
-
74LVC1G125
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 9 — 29 December 2010
16 of 19
74LVC1G125
NXP Semiconductors
Bus buffer/line driver; 3-state
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
suitable for use in medical, military, aircraft, space or life support equipment,
16.2 Definitions
nor in applications where failure or malfunction of an NXP Semiconductors
product can reasonably be expected to result in personal injury, death or
severe property or environmental damage. NXP Semiconductors accepts no
liability for inclusion and/or use of NXP Semiconductors products in such
equipment or applications and therefore such inclusion and/or use is at the
customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. The product is not designed, authorized or warranted to be
74LVC1G125
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 9 — 29 December 2010
17 of 19
74LVC1G125
NXP Semiconductors
Bus buffer/line driver; 3-state
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74LVC1G125
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 9 — 29 December 2010
18 of 19
74LVC1G125
NXP Semiconductors
Bus buffer/line driver; 3-state
18. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16
8
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 18
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 29 December 2010
Document identifier: 74LVC1G125
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