74LV4040PW [NXP]
12-stage binary ripple counter; 12级二进制纹波计数器
| 型号： | 74LV4040PW |
| 厂家： | 
NXP |
| 描述： | 12-stage binary ripple counter |
| 文件： | 总14页 (文件大小：134K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74LV4040
12-stage binary ripple counter
Product specification
IC24 Data Handbook
1998 Jun 23
Philips
Semiconductors
Philips Semiconductors
Product specification
12-stage binary ripple counter
74LV4040
FEATURES
DESCRIPTION
The 74LV4040 is a low–voltage Si–gate CMOS device and is pin
and function compatible with 74HC/HCT4040.
• Optimized for Low Voltage applications: 1.0 to 5.5V
• Accepts TTL input levels between V = 2.7V and V = 3.6V
CC
CC
The 74LV4040 is a 12-stage binary ripple counter with a click input
(CP), an overriding asynchronous master reset input (MR) and
twelve fully buffered parallel outputs (Q to Q ). The counter is
• Typical V
(output ground bounce) t 0.8V @ V = 3.3V,
OLP
CC
T
amb
= 25°C
0
11
advanced on the HIGH-to-LOW transition of CP. A HIGH on MR
clears all counter stages and forces all outputs LOW, independent of
the state of CP.
• Typical V
(output V undershoot) u 2V @ V = 3.3V,
OHV
OH
CC
T
= 25°C
amb
• Frequency dividing circuits
• Time delay circuits
Each counter stage is a static toggle flip-flop.
• Control counters
• Output capability: standard
• I category: MSI
CC
QUICK REFERENCE DATA
GND = 0V; T
= 25°C; t =t v2.5 ns
amb
r f
SYMBOL
PARAMETER
Propagation delay
CONDITIONS
TYPICAL
UNIT
C = 15pF
12
7
16
L
CC
CP to Q
0
V
= 3.3V
t
f
/t
ns
PHL PLH
Q to Q
n
n+1
MR to Q
n
Maximum clock frequency
Input capacitance
100
3.5
30
MHz
pF
max
C
C
I
Notes 1 and 2
Power dissipation capacitance per gate
pF
PD
NOTES:
1. C is used to determine the dynamic power dissipation (P in µW)
PD
D
2
2
P
= C V
x f )S (C V
f ) where:
D
PD
CC
i
L
CC o
f = input frequency in MHz; C = output load capacity in pF;
i
L
f = output frequency in MHz; V = supply voltage in V;
o
CC
2
S (C V
f ) = sum of the outputs.
L
CC
o
2. The condition is V = GND to V
I
CC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
NORTH AMERICA
74LV4040 N
PKG. DWG. #
SOT38-4
16-Pin Plastic DIL
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
74LV4040 N
74LV4040 D
74LV4040 DB
74LV4040 PW
16-Pin Plastic SO
74LV4040 D
SOT109-1
SOT338-1
SOT403-1
16-Pin Plastic SSOP Type II
16-Pin Plastic TSSOP Type I
74LV4040 DB
74LV4040PW DH
2
1998 Jun 23
853-2075 19619
Philips Semiconductors
Product specification
12-stage binary ripple counter
74LV4040
PIN CONFIGURATION
LOGIC SYMBOL
9
7
6
5
Q
Q
Q
Q
Q
0
1
2
3
4
16
15
14
13
12
11
Q
1
2
3
4
5
6
7
8
V
CC
11
Q
10
Q
5
4
6
Q
Q
9
7
8
3
Q
Q
Q
10
11
CP
2
Q
5
Q
6
Q
7
Q
Q
Q
3
2
1
4
MR
MR
13
10 CP
12
14
15
1
Q
8
9
Q
0
GND
Q
9
Q
10
11
Q
SV00317
SV00316
Figure 1. Pin configuration
Figure 3. Logic symbol
PIN DESCRIPTION
FUNCTIONAL DIAGRAM
PIN
NUMBER
SYMBOL
FUNCTION
9, 7, 6, 5, 3,
2, 4, 13, 12,
14, 15, 1
Q to Q
0
Parallel outputs
11
8
GND
CP
Ground (0V)
10 CP
T
Clock input (HIGH-to-LOW, edge-
triggered)
12-STAGE COUNTER
10
11
MR
C
D
11
16
MR
Master reset input (active HIGH)
Positive supply voltage
Q
Q
7
Q
5
Q
5
Q
Q
2
Q
4
Q
Q
Q
Q
Q
1
0
1
2
3
4
5
6
7
8
9
10
11
V
CC
9
3
13 12 14 15
LOGIC SYMBOL (IEEE/IEC)
SV00319
Figure 4. Functional diagram
9
7
5
5
CTR12
0
10
11
+
LOGIC DIAGRAM
CT=0
3
2
CT
4
FF0
FF3
FF11
Q
Q
Q
13
T
T
T
CP
12
14
15
1
Q
Q
D
Q
R
D
R
R
D
11
MR
SV00318
Figure 2. IEC Logic symbol
Q0
Q1
Q11
SV00320
Figure 5. Logic diagram
3
1998 Jun 23
Philips Semiconductors
Product specification
12-stage binary ripple counter
74LV4040
1
2
4
8
16
32
64
128
256
512
1.024 2.048 4.096
CP INPUT
MR INPUT
Q
0
Q
1
OUTPUT
OUTPUT
Q
2
Q
3
Q
4
Q
5
Q
6
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
Q
7
OUTPUT
Q
Q
OUTPUT
OUTPUT
8
9
Q
Q
OUTPUT
OUTPUT
10
11
SV00310
Figure 6. Timing diagram
FUNCTION TABLE
INPUTS
OUTPUTS
Q , Q to Q
13
CP
°
MR
L
0
3
no change
±
L
count
L
X
H
NOTES:
H = HIGH voltage level
L = LOW voltage level
X = Don’t care
° = LOW -to-HIGH clock transition
± = HIGH-to-LOW clock transition
4
1998 Jun 23
Philips Semiconductors
Product specification
12-stage binary ripple counter
74LV4040
1, 2
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
UNIT
V
V
CC
–0.5 to +7.0
±I
DC input diode current
DC output diode current
V < –0.5 or V > V + 0.5V
20
50
mA
mA
IK
I
I
CC
±I
OK
V
O
< –0.5 or V > V + 0.5V
O
CC
DC output source or sink current
– standard outputs
±I
O
–0.5V < V < V + 0.5V
mA
O
CC
25
DC V or GND current for types with
–standard outputs
CC
±I
±I
,
mA
GND
50
CC
T
stg
Storage temperature range
–65 to +150
°C
Power dissipation per package
–plastic DIL
–plastic mini-pack (SO)
for temperature range: –40 to +125°C
above +70°C derate linearly with 12mW/K
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
750
500
400
P
TOT
mW
–plastic shrink mini-pack (SSOP and TSSOP)
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
MIN
1.0
0
TYP.
3.3
–
MAX
UNIT
1
V
CC
DC supply voltage
See Note
5.5
V
V
V
V
I
Input voltage
V
CC
V
CC
V
O
Output voltage
0
–
Operating ambient temperature range in free
air
See DC and AC
characteristics
–40
–40
+85
+125
T
amb
°C
V
CC
V
CC
V
CC
V
CC
= 1.0V to 2.0V
= 2.0V to 2.7V
= 2.7V to 3.6V
= 3.6V to 5.5V
–
–
–
–
–
–
–
–
500
200
100
50
t , t
r
Input rise and fall times
ns/V
f
NOTE:
1. The LV is guaranteed to function down to V = 1.0V (input levels GND or V ); DC characteristics are guaranteed from V = 1.2V to V = 5.5V.
CC
CC
CC
CC
5
1998 Jun 23
Philips Semiconductors
Product specification
12-stage binary ripple counter
74LV4040
DC CHARACTERISTICS FOR THE LV FAMILY
Over recommended operating conditions voltages are referenced to GND (ground = 0V)
LIMITS
MAX
-40°C to +85°C
-40°C to +125°C
SYMBOL
PARAMETER
TEST CONDITIONS
= 1.2V
UNIT
1
MIN
0.9
1.4
2.0
TYP
MIN
0.9
1.4
2.0
MAX
V
V
V
V
V
V
V
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
= 2.0V
HIGH level Input
voltage
V
IH
V
= 2.7 to 3.6V
= 4.5 to 5.5V
= 1.2V
0.7*V
0.7*V
CC
CC
0.3
0.6
0.8
0.3
0.6
0.8
= 2.0V
LOW level Input
voltage
V
IL
V
= 2.7 to 3.6V
= 4.5 to 5.5
0.3*V
0.3*V
CC
CC
= 1.2V; V = V or V –I = 100µA
1.2
2.0
2.7
3.0
4.5
I
IH
IL;
O
= 2.0V; V = V or V –I = 100µA
1.8
2.5
2.8
4.3
1.8
2.5
2.8
4.3
I
IH
IL;
O
HIGH level output
voltage; all outputs
= 2.7V; V = V or V –I = 100µA
V
V
V
V
V
V
I
IH
IL;
O
OH
= 3.0V; V = V or V –I = 100µA
I
IH
IL;
O
= 4.5V; V = V or V –I = 100µA
I
IH
IL;
O
HIGH level output
voltage;
STANDARD
V
V
= 3.0V; V = V or V –I = 6mA
2.40
3.60
2.82
4.20
2.20
3.50
CC
I
IH
IL;
O
OH
= 4.5V; V = V or V –I = 12mA
CC
I
IH
IL;
O
outputs
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.2V; V = V or V I
IL; O
= 100µA
= 100µA
= 100µA
= 100µA
= 100µA
0
0
0
0
0
I
IH
= 2.0V; V = V or V
I
0.2
0.2
0.2
0.2
0.2
I
IH
IL; O
LOW level output
voltage; all outputs
= 2.7V; V = V or V
I
0.2
0.2
0.2
V
V
I
IH
IL; O
OL
= 3.0V; V = V or V I
IL; O
I
IH
= 4.5V; V = V or V I
IL; O
I
IH
LOW level output
voltage;
STANDARD
V
CC
V
CC
V
CC
= 3.0V; V = V or V I = 6mA
IL; O
0.25
0.35
0.40
0.55
1.0
0.50
0.65
1.0
I
IH
OL
= 4.5V; V = V or V I = 12mA
IL; O
I
IH
outputs
Input leakage
current
I
I
= 5.5V; V = V or GND
µA
µA
I
CC
Quiescent supply
current; MSI
I
V
= 5.5V; V = V or GND; I = 0
20.0
500
160
850
CC
CC
CC
I
CC
O
Additional
quiescent supply
current per input
∆I
CC
V
= 2.7V to 3.6V; V = V –0.6V
µA
I
CC
NOTE:
1. All typical values are measured at T
= 25°C.
amb
6
1998 Jun 23
Philips Semiconductors
Product specification
12-stage binary ripple counter
74LV4040
AC CHARACTERISTICS
GND = 0V; t = t ≤ 2.5ns; C = 50pF; R = 500W
r
f
L
L
LIMITS
–40 to +85 °C
LIMITS
–40 to +125 °C
CONDITION
(V)
SYMBOL
PARAMETER
WAVEFORM
UNIT
1
V
CC
MIN
–
TYP
MAX
–
MIN
–
MAX
–
1.2
2.0
2.7
60
27
19
–
43
31
26
17
–
–
54
38
32
22
–
Propagation delay
CP to Q
–
–
t
t
Figure 7, 9
Figure 7, 9
Figure 8, 9
ns
PHL/ PLH
0
2
3.0 to 3.6
4.5 to 5.5
1.2
–
16
–
3
–
1
–
–
40
18
13
–
2.0
–
29
21
18
12
–
–
54
38
32
22
–
Propagation delay
Q to Q
2.7
–
–
t
t
ns
ns
PHL/ PLH
n
n+1
2
3.0 to 3.6
4.5 to 5.5
1.2
–
11
–
3
–
7
–
–
55
27
19
–
2.0
–
44
31
26
17
–
–
54
38
32
22
54
–
Propagation delay
MR to Q
2.7
–
–
t
PHL
n
2
3.0 to 3.6
4.5 to 5.5
2.0
–
16
–
3
–
11
–
35
25
20
15
35
25
20
15
–
7
5
41
30
24
18
41
30
24
18
–
2.7
–
Clock pulse width
HIGH to LOW
t
t
Figure 7
Figure 8
ns
ns
W
2
3.0 to 3.6
4.5 to 5.5
2.0
4
–
–
3
3
–
–
11
9
–
–
2.7
–
–
Master reset pulse
width HIGH
W
2
3.0 to 3.6
4.5 to 5.5
1.2
8
–
–
3
7
–
–
10
5
–
–
2.0
22
16
13
10
14
19
24
36
–
26
19
15
12
12
16
20
30
–
Removal time
MR to CP
2.7
4
–
–
t
Figure 8
Figure 7
ns
rem
2
3.0 to 3.6
4.5 to 5.5
2.0
3
–
–
3
2
–
–
60
76
–
–
2.7
–
–
Maximum clock
pulse frequency
f
MHz
max
2
3.0 to 3.6
4.5 to 5.5
94
–
–
3
112
–
–
NOTES:
1. Unless otherwise stated, all typical values are at T
= 25°C.
amb
2. Typical value measured at V = 3.3V.
CC
3. Typical value measured at V = 5.0V.
CC
7
1998 Jun 23
Philips Semiconductors
Product specification
12-stage binary ripple counter
74LV4040
AC WAVEFORMS
V
V
V
= 1.5V at V w 2.7V v 3.6V
TEST CIRCUIT
M
CC
= 0.5V * V at V t 2.7V and w 4.5V
M
CC
CC
and V are the typical output voltage drop that occur with the
OL
OH
V
CC
output load.
V
V
O
I
PULSE
GENERATOR
f
D.U.T.
1/
max
V
I
50pF
R
= 1k
L
R
T
C
L
V
CP INPUT
GND
M
tW
Test Circuit for switching times
DEFINITIONS
t
PLH
t
PHL
V
OH
R
L
C
L
R
T
= Load resistor
Q
n
OUTPUT
V
M
= Load capacitance includes jig and probe capacitance
= Termination resistance should be equal to Z of pulse generators.
OUT
V
OL
TEST
V
V
I
CC
SV00322
t
t
< 2.7V
V
CC
PLH/ PHL
Figure 7. Clock (CP) to output (Q ) propagation delays, the
clock pulse width and the maximum clock pulse frequency
n
2.7–3.6V
2.7V
SV00901
Figure 9.Load circuitry for switching times
V
I
MR INPUT
GND
t
W
t
rem
V
I
CP INPUT
GND
t
PHL
V
OH
Qn OUTPUT
GND
SV00908
Figure 8. Master reset (MR) pulse width, the master reset to
output (Q ) propagation delays and the master reset to clock
n
(CP) removal time
8
1998 Jun 23
Philips Semiconductors
Product specification
12-stage binary ripple counter
74LV4040
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
9
1998 Jun 23
Philips Semiconductors
Product specification
12-stage binary ripple counter
74LV4040
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
10
1998 Jun 23
Philips Semiconductors
Product specification
12-stage binary ripple counter
74LV4040
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
11
1998 Jun 23
Philips Semiconductors
Product specification
12-stage binary ripple counter
74LV4040
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
12
1998 Jun 23
Philips Semiconductors
Product specification
12-stage binary ripple counter
74LV4040
NOTES
13
1998 Jun 23
Philips Semiconductors
Product specification
12-stage binary ripple counter
74LV4040
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 05-96
9397-750-04458
Document order number:
Philips
Semiconductors
相关型号：
74LV4051D-T
IC 8-CHANNEL, SGL ENDED MULTIPLEXER, PDSO16, 3.90 MM, PLASTIC, MS-012, SOT109-1, SOP-16, Multiplexer or Switch
NXP
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