74LV123_15 [NXP]
74LV123_15;型号: | 74LV123_15 |
厂家: | NXP |
描述: | 74LV123_15 |
文件: | 总24页 (文件大小:278K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
74LV123
Dual retriggerable monostable multivibrator with reset
Rev. 7 — 12 December 2011
Product data sheet
1. General description
The 74LV123 is a low-voltage Si-gate CMOS device and is pin and function compatible
with the 74HC123; 74HCT123. It is a dual retriggerable monostable multivibrator which
uses three methods to control the output pulse width:
1. The basic pulse time is programmed by the selection of an external resistor (REXT
)
and capacitor (CEXT). These are normally connected as shown in Figure 9.
2. Once triggered, the basic output pulse width may be extended by retriggering the
gated active LOW-going edge input (nA) or the active HIGH-going edge input (nB). By
repeating this process, the output pulse period (nQ = HIGH, nQ = LOW) can be made
as long as desired (see Figure 12).
3. Alternatively, an output delay can be terminated at any time by a LOW-going edge on
input nRD, which also inhibits the triggering (see Figure 13).
Schmitt-trigger action in the nA and nB inputs makes the circuit highly tolerant of slower
input rise and fall times.
2. Features and benefits
Optimized for low-voltage applications: 1.0 V to 5.5 V
Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
Typical output ground bounce: < 0.8 V at VCC = 3.3 V and Tamb = 25 C
Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and
Tamb = 25 C
DC triggered from active HIGH or active LOW inputs
Retriggerable for very long pulses up to 100 % duty factor
Direct reset terminates output pulses
Schmitt-trigger action on all inputs except for the reset input
74LV123
NXP Semiconductors
Dual retriggerable monostable multivibrator with reset
3. Ordering information
Table 1.
Type number Package
Temperature range Name
Ordering information
Description
Version
74LV123N
74LV123D
40 C to +125 C
40 C to +125 C
DIP16
SO16
plastic dual in-line package; 16 leads (300 mil)
SOT38-4
SOT109-1
plastic small outline package; 16 leads; body width
3.9 mm
74LV123DB
74LV123PW
74LV123BQ
40 C to +125 C
40 C to +125 C
40 C to +125 C
SSOP16
plastic shrink small outline package; 16 leads; body width SOT338-1
5.3 mm
TSSOP16
plastic thin shrink small outline package; 16 leads; body
width 4.4 mm
SOT403-1
DHVQFN16 plastic dual in-line compatible thermal enhanced very thin SOT763-1
quad flat package; no leads; 16 terminals;
body 2.5 3.5 0.85 mm
4. Functional diagram
14
CX
15
RCX
13
1
&
14 1CEXT
2CEXT
15 1REXT/CEXT
2REXT/CEXT
2
3
6
4
7
R
S
13 1Q
Q
Q
6
5
2Q
CX
RCX
&
1A
2A
1
9
T
7
5
4
1Q
9
1B
2
12 2Q
2B 10
10
RD
1RD
3
12
2RD 11
11
R
001aae521
001aae522
Fig 1. Logic symbol
Fig 2. IEC logic symbol
74LV123
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 12 December 2011
2 of 24
74LV123
NXP Semiconductors
Dual retriggerable monostable multivibrator with reset
14
1CEXT
15
1REXT/CEXT
S
13
1Q
1Q
Q
Q
1
1A
T
4
2
3
1B
RD
1RD
6
7
2CEXT
2REXT/CEXT
S
5
2Q
2Q
Q
Q
9
2A
T
12
10
11
2B
RD
2RD
001aaa610
Fig 3. Functional diagram
74LV123
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 12 December 2011
3 of 24
74LV123
NXP Semiconductors
Dual retriggerable monostable multivibrator with reset
nREXT/CEXT
V
CC
Q
Q
RD
R
R
V
CL
CL
CL
CC
V
CC
R
A
B
CL
CL
001aae524
R
Fig 4. Logic diagram
74LV123
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 12 December 2011
4 of 24
74LV123
NXP Semiconductors
Dual retriggerable monostable multivibrator with reset
5. Pinning information
5.1 Pinning
74LV123
terminal 1
index area
74LV123
2
3
4
5
6
7
15
14
13
12
11
10
1B
1RD
1REXT/CEXT
1CEXT
1Q
1A
1
2
3
4
5
6
7
8
16 V
CC
1B
1RD
15 1REXT/CEXT
14 1CEXT
13 1Q
1Q
2Q
2Q
1Q
2CEXT
2REXT/CEXT
(1)
CC
2RD
2B
V
2Q
12 2Q
2CEXT
2REXT/CEXT
GND
11 2RD
10 2B
001aag650
9
2A
001aag678
Transparent top view
(1) The die substrate is attached to this
pad using conductive die attach
material. It cannot be used as a supply
pin or input.
Fig 5. Pin configuration for DIP16, SO16,
SSOP16 and TSSOP16
Fig 6. Pin configuration for DHVQFN16
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
1
Description
1A
negative-edge triggered input 1
positive-edge triggered input 1
direct reset LOW and positive-edge triggered input 1
active LOW output 1
1B
2
1RD
3
1Q
4
2Q
5
active HIGH output 2
2CEXT
6
external capacitor connection 2
external resistor and capacitor connection 2
ground (0 V)
2REXT/CEXT
7
GND
8
2A
9
negative-edge triggered input 2
positive-edge triggered input 2
direct reset LOW and positive-edge triggered input 2
active LOW output 2
2B
10
11
12
13
14
15
16
2RD
2Q
1Q
active HIGH output 1
1CEXT
1REXT/CEXT
VCC
external capacitor connection 1
external resistor and capacitor connection 1
supply voltage
74LV123
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 12 December 2011
5 of 24
74LV123
NXP Semiconductors
Dual retriggerable monostable multivibrator with reset
6. Functional description
Table 3.
Function table[1]
Input
nRD
L
Output
nA
X
nB
X
nQ
nQ
H
L
X
H
X
X
L[2]
L[2]
H[2]
H[2]
X
L
H
L
H
H
H
L
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
= LOW-to-HIGH transition;
= HIGH-to-LOW transition;
= one HIGH level output pulse
= one LOW level output pulse
[2] If the monostable multivibrator was triggered before this condition was established, the pulse will continue as programmed.
74LV123
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 12 December 2011
6 of 24
74LV123
NXP Semiconductors
Dual retriggerable monostable multivibrator with reset
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7
Unit
V
supply voltage
0.5
[1]
[1]
[1]
input clamping current
output clamping current
output current
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
-
-
-
20
50
25
mA
mA
mA
IOK
IO
except for pins nREXT/CEXT;
VO = 0.5 V to (VCC + 0.5 V)
ICC
supply current
-
+50
mA
mA
C
IGND
Tstg
Ptot
ground current
-
50
storage temperature
total power dissipation
65
+150
Tamb = 40 C to +125 C
DIP16 package
[2]
[3]
[4]
[4]
[5]
-
-
-
-
-
750
500
500
500
500
mW
mW
mW
mW
mW
SO16 package
SSOP16 package
TSSOP16 package
DHVQFN16 package
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.
[3] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
[4] For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
[5] For DHVQFN16 package: Ptot derates linearly with 4.5 mW/K above 60 C.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol Parameter
Conditions
Min
Typ
Max
Unit
[1]
[2]
VCC
VI
supply voltage
1.0
3.3
5.5
V
input voltage
0
-
VCC
VCC
+125
500
200
100
50
V
VO
output voltage
0
-
V
Tamb
t/V
ambient temperature
input transition rise and fall rate
in free air
40
+25
C
VCC = 1.0 V to 2.0 V
VCC = 2.0 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 3.6 V to 5.5 V
-
-
-
-
-
-
-
-
ns/V
ns/V
ns/V
ns/V
[1] The 74LV123 is guaranteed to function down to VCC = 1.0 V (input levels GND or VCC); Section 9 “Static characteristics” are guaranteed
from VCC = 1.2 V to VCC = 5.5 V.
[2] Except for Schmitt-trigger inputs nA and nB.
74LV123
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 12 December 2011
7 of 24
74LV123
NXP Semiconductors
Dual retriggerable monostable multivibrator with reset
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ[1] Max
Unit
Tamb = 40 C to +85 C
VIH
HIGH-level input voltage
VCC = 1.2 V
0.9
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
VCC = 2.0 V
1.4
-
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 1.2 V
2.0
-
0.7 VCC
-
VIL
LOW-level input voltage
-
-
-
-
0.3
VCC = 2.0 V
0.6
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
0.8
0.3 VCC
VOH
HIGH-level output voltage VI = VIH or VIL
lO = 100 A; VCC = 1.2 V
-
1.2
-
-
-
-
-
-
-
V
V
V
V
V
V
V
lO = 100 A; VCC = 2.0 V
lO = 100 A; VCC = 2.7 V
lO = 100 A; VCC = 3.0 V
lO = 100 A; VCC = 4.5 V
lO = 6 mA; VCC = 3.0 V
lO = 12 mA; VCC = 4.5 V
VI = VIH or VIL
1.8
2.5
2.8
4.3
2.40
3.60
2.0
2.7
3.0
4.5
2.82
4.20
VOL
LOW-level output voltage
IO = 100 A; VCC = 1.2 V
IO = 100 A; VCC = 2.0 V
IO = 100 A; VCC = 2.7 V
IO = 100 A; VCC = 3.0 V
IO = 100 A; VCC = 4.5 V
IO = 6 mA; VCC = 3.0 V
-
-
-
-
-
-
-
-
-
-
-
0
-
V
0
0.2
0.2
0.2
0.2
0.40
0.55
1.0
20.0
500
-
V
0
V
0
V
0
V
0.25
V
IO = 12 mA; VCC = 4.5 V
VI = VCC or GND; VCC = 5.5 V
VI = VCC or GND; IO = 0 A; VCC = 5.5 V
VI = VCC 0.6 V; VCC = 2.7 V to 3.6 V
0.35
V
II
input leakage current
supply current
-
A
A
A
pF
ICC
ICC
CI
-
additional supply current
input capacitance
-
3.5
Tamb = 40 C to +125 C
VIH HIGH-level input voltage
VCC = 1.2 V
0.9
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
VCC = 2.0 V
1.4
-
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 1.2 V
2.0
-
0.7 VCC
-
VIL
LOW-level input voltage
-
-
-
-
0.3
VCC = 2.0 V
0.6
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
0.8
0.3 VCC
74LV123
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 12 December 2011
8 of 24
74LV123
NXP Semiconductors
Dual retriggerable monostable multivibrator with reset
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VOH HIGH-level output voltage VI = VIH or VIL
lO = 100 A; VCC = 1.2 V
Conditions
Min
Typ[1] Max
Unit
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
lO = 100 A; VCC = 2.0 V
lO = 100 A; VCC = 2.7 V
lO = 100 A; VCC = 3.0 V
lO = 100 A; VCC = 4.5 V
lO = 6 mA; VCC = 3.0 V
lO = 12 mA; VCC = 4.5 V
VI = VIH or VIL
1.8
2.5
2.8
4.3
2.2
3.5
VOL
LOW-level output voltage
IO = 100 A; VCC = 1.2 V
IO = 100 A; VCC = 2.0 V
IO = 100 A; VCC = 2.7 V
IO = 100 A; VCC = 3.0 V
IO = 100 A; VCC = 4.5 V
IO = 6 mA; VCC = 3.0 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
0.2
0.2
0.2
0.2
0.5
0.65
1.0
160
850
V
V
V
V
V
IO = 12 mA; VCC = 4.5 V
VI = VCC or GND; VCC = 5.5 V
VI = VCC or GND; IO = 0 A; VCC = 5.5 V
VI = VCC 0.6 V; VCC = 2.7 V to 3.6 V
V
II
input leakage current
supply current
A
A
A
ICC
ICC
additional supply current
[1] All typical values are measured at Tamb = 25 C.
74LV123
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 12 December 2011
9 of 24
74LV123
NXP Semiconductors
Dual retriggerable monostable multivibrator with reset
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; tr = tf 2.5 ns; for test circuit see Figure 8.
Symbol Parameter Conditions
40 C to +85 C 40 C to +125 C Unit
Min Typ[1] Max
Min
Max
Propagation delay; see Figure 7
tpd propagation delay nRD, nA and nB to nQ
[2]
VCC = 1.2 V
-
-
-
-
-
120
40
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
VCC = 2.0 V
76
56
48
40
92
68
57
46
VCC = 2.7 V
30
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
nRD to nQ (reset)
VCC = 1.2 V
25
18
[2]
-
-
-
-
-
100
30
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
VCC = 2.0 V
57
43
38
31
68
51
45
36
VCC = 2.7 V
23
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
20
14
Inputs nA, nB and nRD; see Figure 7
tW
pulse width
nA = LOW
V
CC = 2.0 V
30
25
20
15
5
-
-
-
-
40
30
25
20
-
-
-
-
ns
ns
ns
ns
VCC = 2.7 V
3.5
3.0
2.5
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
nB = HIGH
VCC = 2.0 V
30
25
20
15
13
8
-
-
-
-
40
30
25
20
-
-
-
-
ns
ns
ns
ns
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
nRD = LOW; see Figure 13
VCC = 2.0 V
7
5
35
30
25
20
6
5
4
3
-
-
-
-
45
40
30
25
-
-
-
-
ns
ns
ns
ns
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
nB to nA; see Figure 12
VCC = 2.0 V
trtrig
retrigger time
-
-
-
-
70
55
45
40
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
74LV123
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 12 December 2011
10 of 24
74LV123
NXP Semiconductors
Dual retriggerable monostable multivibrator with reset
Table 7.
Dynamic characteristics …continued
GND = 0 V; tr = tf 2.5 ns; for test circuit see Figure 8.
Symbol Parameter
Conditions
40 C to +85 C 40 C to +125 C Unit
Min Typ[1] Max
Min
Max
Outputs; nQ = LOW and nQ = HIGH, see Figure 7
tW
pulse width
CEXT = 100 nF; REXT = 10 k
VCC = 2.0 V
-
-
-
-
470
460
450
430
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
CEXT = 0 pF; REXT = 5 k
VCC = 2.0 V
-
-
-
-
100
90
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
80
70
External components
[3]
REXT
external
resistance
see Figure 11
VCC = 1.2 V
10
5
-
-
-
-
-
1000
1000
1000
1000
1000
-
-
-
-
-
-
-
-
-
-
k
k
k
k
k
VCC = 2.0 V
VCC = 2.7 V
3
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
see Figure 11
VCC = 1.2 V
2
2
[3][4]
CEXT
external
capacitance
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
pF
pF
pF
pF
pF
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
Dynamic power dissipation
[5]
CPD
power dissipation VCC = 3.3 V; VI = GND to VCC
capacitance
-
60
-
-
-
pF
[1] All typical values are measured at Tamb = 25 C and nominal supply values (VCC = 3.3 V and 5.0 V).
[2] pd is the same as tPLH and tPHL; CEXT = 0 pF; REXT = 5 k.
t
[3] For other REXT and CEXT combinations see Figure 11 and Section 12.1.1 “Basic timing”.
[4] CEXT has no limits.
[5]
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of the outputs.
74LV123
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 12 December 2011
11 of 24
74LV123
NXP Semiconductors
Dual retriggerable monostable multivibrator with reset
11. Waveforms
V
nB input
M
(nA LOW)
t
W
V
M
nA input
(nB HIGH)
t
W
RESET
V
M
nRD input
nQ output
t
t
t
W
PLH
PLH
V
M
t
t
t
PHL
PLH
t
t
W
W
nQ output
V
M
t
t
t
PLH
PHL
PHL
PHL
001aae528
Measurement points are given in Table 8.
Fig 7. Propagation delays from inputs (nA, nB, nRD) to outputs (nQ, nQ)
Table 8.
VCC
Measurement points
VM
2.7 V
< 2.7 V
1.5 V
0.5 VCC
V
CC
V
V
O
I
PULSE
GENERATOR
DUT
C
50 pF
R
L
1 kΩ
L
R
T
001aae533
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to Zo of the pulse generator.
Fig 8. Load circuitry for switching times
74LV123
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 12 December 2011
12 of 24
74LV123
NXP Semiconductors
Dual retriggerable monostable multivibrator with reset
Table 9.
Test data
Supply voltage
VCC
Input
VI
Load
CL
Test
tr, tf
RL
< 2.7 V
VCC
2.7 V
VCC
2.5 ns
2.5 ns
2.5 ns
50 pF
50 pF
50 pF
1 k
1 k
1 k
tPHL, tPLH
tPHL, tPLH
tPHL, tPLH
2.7 V to 3.6 V
4.5 V
12. Application information
12.1 Timing components
12.1.1 Basic timing
The basic output pulse width is essentially determined by the values of the external timing
components REXT and CEXT
.
C
EXT
R
EXT
(1)
V
CC
GND
8
nCEXT
14 (6)
nREXT/CEXT
15 (7)
13 (5)
74LV123
nQ
1 (9)
nA
nB
2 (10)
4 (12)
nQ
3 (11)
nRD
001aae525
(1) For minimum noise generation it is recommended to ground pins 6 (2CEXT) and 14 (1CEXT)
externally to pin 8 (GND).
Fig 9. Timing components connections
If CEXT > 10 nF, the following formula is valid: tW = K REXT CEXT (typ.) where:
tW = output pulse width in ns
REXT = external resistor in k
CEXT = external capacitor in pF
K = constant: this is 0.45 for VCC = 5.0 V and 0.48 for VCC = 2.0 V (see Figure 10)
The inherent test jig and pin capacitance at pin 15 and pin 7 (nREXT/CEXT) is
approximately 7 pF.
74LV123
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 12 December 2011
13 of 24
74LV123
NXP Semiconductors
Dual retriggerable monostable multivibrator with reset
001aae529
001aae530
6
0.8
10
t
W
'K'
factor
(ns)
5
4
3
2
10
R
EXT
= 100 kΩ
50 kΩ
10 kΩ
2 kΩ
0.6
0.4
0.2
0
10
10
10
0
2
3
4
0
2
4
6
1
10
10
10
10
V
(V)
C
(pF)
ext
CC
CEXT = 10 nF; REXT = 10 k to 100 k
VCC = 3.3 V and Tamb = 25 C
Fig 10. Typical ‘K’ factor as a function of VCC
Fig 11. Typical output pulse width as a function of the
external capacitance values
12.1.2 Retrigger timing
The time to retrigger the monostable multivibrator depends on the values of REXT and
EXT. The output pulse width will only be extended when the time between the active
C
going edges of the trigger pulses meets the minimum retrigger time. If CEXT > 10 pF, the
next formula for the set-up time of a retrigger pulse is valid:
at VCC = 5.0 V: trtrig = 30 + 0.19REXT CEXT0.9 + 13 REXT1.05 (typ.)
at VCC = 3.0 V: trtrig = 41 + 0.15REXT CEXT0.9 1 REXT (typ.)
where:
trtrig = retrigger time in ns
CEXT = external capacitor in pF
REXT = external resistor in k
nB input
t
W
nA input
t
rtrig
t
W
nQ output
t
t
W
001aae526
W
nRD = HIGH
Fig 12. Output pulse control using retrigger pulse nA
74LV123
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 12 December 2011
14 of 24
74LV123
NXP Semiconductors
Dual retriggerable monostable multivibrator with reset
12.1.3 Reset timing
nB input
nRD input
nQ output
t
t
W
W
001aae527
nA = LOW
Fig 13. Output pulse control using reset input nRD
12.2 Power considerations
12.2.1 Power-up
When the monostable multivibrator is powered-up, it may produce an output pulse with a
pulse width defined by the values of REXT and CEXT. This output pulse can be eliminated
using the RC circuit on pin nRD shown in Figure 14.
12.2.2 Power-down
A large capacitor (CEXT) may cause problems when powering-down the monostable due
to the energy stored in this capacitor. When a system containing this device is
powered-down or a rapid decrease of VCC to zero occurs, the monostable may sustain
damage, due to the capacitor discharging through the input protection diodes. To avoid
this possibility, connect a damping diode DEXT (preferably a germanium or Schottky type
diode) able to withstand large current surges - see Figure 14.
D
R
EXT
C
EXT
EXT
V
CC
GND
8
nCEXT
14 (6)
nREXT/CEXT
15 (7)
13 (5)
74LV123
nQ
1 (9)
nA
nB
2 (10)
4 (12)
nQ
3 (11)
nRD
V
RESET
CC
001aae532
Fig 14. Power-up and power-down circuit
74LV123
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 12 December 2011
15 of 24
74LV123
NXP Semiconductors
Dual retriggerable monostable multivibrator with reset
13. Package outline
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
b
2
16
9
M
H
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
w
UNIT
mm
b
b
b
c
D
E
e
e
L
M
M
H
1
2
1
E
max.
min.
max.
max.
1.73
1.30
0.53
0.38
1.25
0.85
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
0.76
0.068 0.021 0.049 0.014
0.051 0.015 0.033 0.009
0.77
0.73
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.03
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
95-01-14
03-02-13
SOT38-4
Fig 15. Package outline SOT38-4 (DIP16)
74LV123
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 12 December 2011
16 of 24
74LV123
NXP Semiconductors
Dual retriggerable monostable multivibrator with reset
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig 16. Package outline SOT109-1 (SO16)
74LV123
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 12 December 2011
17 of 24
74LV123
NXP Semiconductors
Dual retriggerable monostable multivibrator with reset
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
8
1
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
1.00
0.55
mm
2
0.25
0.65
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT338-1
MO-150
Fig 17. Package outline SOT338-1 (SSOP16)
74LV123
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 12 December 2011
18 of 24
74LV123
NXP Semiconductors
Dual retriggerable monostable multivibrator with reset
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig 18. Package outline SOT403-1 (TSSOP16)
74LV123
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 12 December 2011
19 of 24
74LV123
NXP Semiconductors
Dual retriggerable monostable multivibrator with reset
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm
SOT763-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
7
L
1
8
9
E
h
e
16
15
10
D
h
X
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
y
D
D
E
L
v
w
y
1
1
h
1
h
max.
0.05 0.30
0.00 0.18
3.6
3.4
2.15
1.85
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT763-1
- - -
MO-241
- - -
Fig 19. Package outline SOT736-1 (DHVQFN16)
74LV123
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 12 December 2011
20 of 24
74LV123
NXP Semiconductors
Dual retriggerable monostable multivibrator with reset
14. Revision history
Table 10. Revision history
Document ID
74LV123 v.7
Modifications:
74LV123 v.6
74LV123 v.5
74LV123 v.4
74LV123 v.3
74LV123 v.2
74LV123 v.1
Release date
20111212
Data sheet status
Change notice
Supersedes
Product data sheet
-
74LV123 v.6
• Legal pages updated.
20110826
20071108
20070919
20030313
19980420
19970204
Product data sheet
-
-
-
-
-
-
74LV123 v.5
74LV123 v.4
74LV123 v.3
74LV123 v.2
74LV123 v.1
-
Product data sheet
Product specification
Product specification
Product specification
Product specification
74LV123
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 12 December 2011
21 of 24
74LV123
NXP Semiconductors
Dual retriggerable monostable multivibrator with reset
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
15.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
15.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
74LV123
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 12 December 2011
22 of 24
74LV123
NXP Semiconductors
Dual retriggerable monostable multivibrator with reset
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74LV123
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 12 December 2011
23 of 24
74LV123
NXP Semiconductors
Dual retriggerable monostable multivibrator with reset
17. Contents
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
6
Functional description . . . . . . . . . . . . . . . . . . . 6
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended operating conditions. . . . . . . . 7
Static characteristics. . . . . . . . . . . . . . . . . . . . . 8
Dynamic characteristics . . . . . . . . . . . . . . . . . 10
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7
8
9
10
11
12
12.1
Application information. . . . . . . . . . . . . . . . . . 13
Timing components . . . . . . . . . . . . . . . . . . . . 13
Basic timing . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Retrigger timing . . . . . . . . . . . . . . . . . . . . . . . 14
Reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power considerations . . . . . . . . . . . . . . . . . . . 15
Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . 15
12.1.1
12.1.2
12.1.3
12.2
12.2.1
12.2.2
13
14
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 21
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 22
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 23
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 23
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 12 December 2011
Document identifier: 74LV123
相关型号:
74LV125D-T
LV/LV-A/LVX/H SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14, 3.90 MM, PLASTIC, MS-012, SOT108-1, SOP-14
NXP
74LV125DB-T
IC LV/LV-A/LVX/H SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14, 5.30 MM, PLASTIC, MO-150, SOT337-1, SSOP-14, Bus Driver/Transceiver
NXP
©2020 ICPDF网 联系我们和版权申明