74HC259BQ-Q100,115 [NXP]
74HC(T)259-Q100 - 8-bit addressable latch QFN 16-Pin;型号: | 74HC259BQ-Q100,115 |
厂家: | NXP |
描述: | 74HC(T)259-Q100 - 8-bit addressable latch QFN 16-Pin |
文件: | 总20页 (文件大小:260K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
74HC259-Q100; 74HCT259-Q100
8-bit addressable latch
Rev. 1 — 30 July 2012
Product data sheet
1. General description
The 74HC259-Q100; 74HCT259-Q100 are high-speed Si-gate CMOS devices and are pin
compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with
JEDEC standard No. 7A.
The 74HC259-Q100; 74HCT259-Q100 are high-speed 8-bit addressable latches
designed for general-purpose storage applications in digital systems. They are
multifunctional devices capable of storing single-line data in eight addressable latches and
providing a 3-to-8 decoder and multiplexer function with active HIGH outputs (Q0 to Q7).
They also incorporate an active LOW common reset (MR) for resetting all latches as well
as an active LOW enable input (LE).
The 74HC259-Q100; 74HCT259-Q100 has four modes of operation:
• Addressable latch mode, in this mode data on the data line (D) is written into the
addressed latch. The addressed latch follows the data input with all non-addressed
latches remaining in their previous states.
• Memory mode, in this mode all latches remain in their previous states and are
unaffected by the data or address inputs.
• Demultiplexing mode (or 3-to-8 decoding), in this mode the addressed output follows
the state of the data input (D) with all other outputs in the LOW state.
• Reset mode, in this mode all outputs are LOW and unaffected by the address inputs
(A0 to A2) and data input (D).
When operating the 74HC259-Q100; 74HCT259-Q100 as an address latch, changing
more than one address bit could impose a transient wrong address. Therefore, this should
only be done while in the Memory mode.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Combined demultiplexer and 8-bit latch
Serial-to-parallel capability
Output from each storage bit available
Random (addressable) data entry
Easily expandable
Common reset input
74HC259-Q100; 74HCT259-Q100
NXP Semiconductors
8-bit addressable latch
Useful as a 3-to-8 active HIGH decoder
Input levels:
For 74HC259-Q100: CMOS level
For 74HCT259-Q100: TTL level
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature
range
Name
Description
Version
74HC259D-Q100
74HCT259D-Q100
40 C to +125 C SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74HC259PW-Q100 40 C to +125 C TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
74HCT259PW-Q100
74HC259BQ-Q100
74HCT259BQ-Q100
40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced very SOT763-1
thin quad flat package; no leads; 16 terminals;
body 2.5 3.5 0.85 mm
4. Functional diagram
13
15
14
Z9
G8
G10
9,10D
1
DX
4
C10
8R
14
LE
0
1
2
3
0
2
5
6
4
5
0
7
1
2
3
4
5
6
7
Q0
G
13
D
Q1
Q2
Q3
Q4
Q5
Q6
Q7
6
7
7
9
1
2
3
9
A0
A1
A2
10
11
12
10
11
12
MR
15 mna573
mna572
Fig 1. Logic symbol
Fig 2. IEC logic symbol
74HC_HCT259_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 30 July 2012
2 of 20
74HC259-Q100; 74HCT259-Q100
NXP Semiconductors
8-bit addressable latch
Q0
Q1
Q2
Q3
Q4
Q5
4
5
A0
A1
A2
1
2
3
6
1-of-8
DECODER
7
8 LATCHES
9
14 LE
10
15
13
MR
D
Q6 11
Q7 12
mna571
Fig 3. Functional diagram
5. Pinning information
5.1 Pinning
74HC259-Q100
74HCT259-Q100
terminal 1
index area
74HC259-Q100
74HCT259-Q100
2
15
14
13
12
11
10
A1
MR
LE
D
3
4
5
6
7
A2
Q0
Q1
Q2
Q3
1
2
3
4
5
6
7
8
16
V
A0
A1
CC
15
14
13
12
11
10
9
MR
LE
D
A2
Q7
Q6
Q5
Q0
(1)
GND
Q1
Q7
Q6
Q5
Q4
Q2
Q3
aaa-003387
GND
Transparent top view
aaa-003386
(1) The die substrate is attached to this pad using
conductive die attach material. It cannot be used as
supply pin or input.
Fig 4. Pin configuration (SO16 and TSSOP16)
Fig 5. Pin configuration (DHVQFN16)
74HC_HCT259_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 30 July 2012
3 of 20
74HC259-Q100; 74HCT259-Q100
NXP Semiconductors
8-bit addressable latch
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
A0, A1, A2
1, 2, 3
address input
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 4, 5, 6, 7, 9, 10, 11, 12 latch output
GND
D
8
ground (0 V)
13
14
15
16
data input
LE
latch enable input (active LOW)
conditional reset input (active LOW)
supply voltage
MR
VCC
6. Functional description
Table 3.
Function table[1]
Operating mode
Input
Output
MR LE
D
X
d
d
d
d
d
d
d
d
X
d
d
d
d
d
d
d
d
A0
X
L
A1
X
L
A2 Q0
Q1
Q2
L
Q3
L
Q4
L
Q5
L
Q6
L
Q7
L
Reset (clear)
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
X
L
L
L
Demultiplexer
(active HIGH 8-channel)
decoder (when D = H)
L
Q = d L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
q0
Q = d L
L
L
L
L
L
L
H
H
L
L
L
Q = d L
L
L
L
L
L
H
L
L
L
L
Q = d L
L
L
L
L
H
H
H
H
X
L
L
L
L
Q = d L
L
L
L
H
L
L
L
L
L
L
Q = d L
L
L
H
H
X
L
L
L
L
L
L
Q = d L
L
H
X
L
L
L
L
L
L
L
Q = d
Memory (no action)
Addressable latch
H
H
H
H
H
H
H
H
H
q1
q2
q2
q3
q3
q3
q4
q4
q4
q4
q5
q5
q5
q5
q5
q6
q6
q6
q6
q6
q6
q7
q7
q7
q7
q7
q7
q7
Q = d q1
H
L
L
L
q0
q0
q0
q0
q0
q0
q0
Q = d q2
H
H
L
L
q1
q1
q1
q1
q1
q1
Q = d q3
H
L
L
q2
q2
q2
q2
q2
Q = d q4
H
H
H
H
q3
q3
q3
q3
Q = d q5
H
L
L
q4
q4
q4
Q = d q6
H
H
q5
q5
Q = d q7
q6 Q = d
H
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
d = HIGH or LOW data one set-up time prior to the LOW-to-HIGH LE transition;
q = lower case letter indicates the state of the referenced input one set-up time prior to the LOW-to-HIGH transition.
74HC_HCT259_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 30 July 2012
4 of 20
74HC259-Q100; 74HCT259-Q100
NXP Semiconductors
8-bit addressable latch
Table 4.
Operating mode select table[1]
LE
L
MR
H
Mode
Addressable latch mode
Memory mode
H
L
H
L
Demultiplexer mode
Reset mode
H
L
[1] H = HIGH voltage level; L = LOW voltage level.
7. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Max
+7.0
20
20
25
+70
-
Unit
V
VCC
IIK
supply voltage
0.5
[1]
[1]
input clamping current
output clamping current
output current
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
VO = 0.5 V to VCC + 0.5 V
-
mA
mA
mA
mA
mA
C
IOK
IO
-
-
ICC
IGND
Tstg
Ptot
supply current
-
ground current
70
65
-
storage temperature
total power dissipation
+150
500
[2]
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
For TSSOP16 package: Ptot derates linearly with 5.5 mW/K above 60 C.
For DHVQFN16 package: Ptot derates linearly with 4.5 mW/K above 60 C.
74HC_HCT259_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 30 July 2012
5 of 20
74HC259-Q100; 74HCT259-Q100
NXP Semiconductors
8-bit addressable latch
8. Recommended operating conditions
Table 6.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions
74HC259-Q100
74HCT259-Q100
Unit
Min
Typ
Max
6.0
Min
Typ
Max
5.5
VCC
VCC
+125
-
VCC
VI
supply voltage
2.0
5.0
4.5
5.0
V
input voltage
0
-
VCC
VCC
+125
625
139
83
0
-
V
VO
output voltage
0
-
0
-
V
Tamb
t/V
ambient temperature
input transition rise and fall rate VCC = 2.0 V
VCC = 4.5 V
40
-
40
-
C
-
-
-
-
-
-
-
-
ns/V
ns/V
ns/V
1.67
-
1.67
-
139
-
VCC = 6.0 V
9. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max
Min
Max
Min
Max
74HC259-Q100
VIH
HIGH-level
input voltage
VCC = 2.0 V
1.5
1.2
2.4
3.2
0.8
-
-
1.5
-
-
1.5
-
-
V
V
V
V
V
V
VCC = 4.5 V
3.15
3.15
3.15
VCC = 6.0 V
4.2
-
4.2
-
4.2
-
VIL
LOW-level
input voltage
VCC = 2.0 V
-
-
-
0.5
-
-
-
0.5
1.35
1.8
-
-
-
0.5
1.35
1.8
VCC = 4.5 V
2.1 1.35
VCC = 6.0 V
2.8
1.8
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = 20 A; VCC = 2.0 V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
1.9
4.4
5.9
2.0
4.5
6.0
-
-
-
-
-
1.9
4.4
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
5.9
IO = 4.0 mA; VCC = 4.5 V 3.98 4.32
IO = 5.2 mA; VCC = 6.0 V 5.48 5.81
VI = VIH or VIL
3.84
5.34
VOL
LOW-level
output voltage
IO = 20 A; VCC = 2.0 V
IO = 20 A; VCC = 4.5 V
IO = 20 A; VCC = 6.0 V
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
-
-
-
-
-
-
0
0
0
0.1
0.1
0.1
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
1
V
V
0.1
V
0.15 0.26
0.16 0.26
0.33
0.33
1
V
V
II
input leakage
current
VI = VCC or GND;
VCC = 6.0 V
-
0.1
A
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
-
8.0
-
80
-
160
A
74HC_HCT259_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 30 July 2012
6 of 20
74HC259-Q100; 74HCT259-Q100
NXP Semiconductors
8-bit addressable latch
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max
Min
Max
Min
Max
CI
input
-
3.5
-
-
-
-
-
pF
capacitance
74HCT259-Q100
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
1.6
1.2
-
2.0
-
-
2.0
-
-
V
V
VIL
LOW-level
0.8
0.8
0.8
input voltage
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
4.4
4.5
-
-
4.4
-
-
4.4
3.7
-
-
V
V
IO = 4.0 mA
3.98 4.32
3.84
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
-
-
-
0
0.1
-
-
-
0.1
0.33
1
-
-
-
0.1
0.4
1
V
0.15 0.26
V
II
input leakage
current
VI = VCC or GND;
VCC = 5.5 V
-
0.1
A
ICC
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
8.0
-
80
-
160
A
additional
VI = VCC 2.1 V; IO = 0 A;
supply current other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
pin An, LE
pin D
-
-
-
-
150
120
75
540
432
270
-
-
-
-
-
675
540
338
-
-
-
-
-
735
588
368
-
A
A
A
pF
pin MR
CI
input
3.5
capacitance
74HC_HCT259_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 30 July 2012
7 of 20
74HC259-Q100; 74HCT259-Q100
NXP Semiconductors
8-bit addressable latch
10. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 12.
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ[1] Max
Min
Max
Min
Max
74HC259-Q100
[2]
[2]
[2]
tpd
propagation
delay
D to Qn; see Figure 6
VCC = 2.0 V
-
-
-
-
58
21
18
17
185
37
-
-
-
-
-
230
46
-
-
-
-
-
280
56
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
31
39
48
An to Qn; see Figure 7
VCC = 2.0 V
-
-
-
-
58
21
17
17
185
37
-
-
-
-
-
230
46
-
-
-
-
-
280
56
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
31
39
48
LE to Qn; see Figure 8
VCC = 2.0 V
-
-
-
-
55
20
17
16
170
34
-
-
-
-
-
215
43
-
-
-
-
-
255
51
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
29
37
43
tPHL
HIGH to LOW MR to Qn; see Figure 9
propagation
delay
VCC = 2.0 V
-
-
-
-
50
18
15
14
155
31
-
-
-
-
-
195
39
-
-
-
-
-
235
47
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
26
33
40
[3]
tt
transition time see Figure 8
VCC = 2.0 V
-
-
-
19
7
75
15
13
-
-
-
95
19
16
-
-
-
119
22
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
6
19
tW
pulse width
LE HIGH or LOW;
see Figure 8
VCC = 2.0 V
VCC = 4.5 V
70
14
12
17
6
-
-
-
90
18
15
-
-
-
105
21
-
-
-
ns
ns
ns
VCC = 6.0 V
5
18
MR LOW; see Figure 9
VCC = 2.0 V
70
14
12
17
6
-
-
-
90
18
15
-
-
-
105
21
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
5
18
74HC_HCT259_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 30 July 2012
8 of 20
74HC259-Q100; 74HCT259-Q100
NXP Semiconductors
8-bit addressable latch
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 12.
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ[1] Max
Min
Max
Min
Max
tsu
set-up time
D, An to LE;
see Figure 10 and
Figure 11
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
80
16
14
19
7
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
6
17
20
th
hold time
D to LE; see Figure 10
and Figure 11
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
0
0
0
19
6
-
-
-
0
0
0
-
-
-
0
0
0
-
-
-
ns
ns
ns
5
An to LE; see Figure 10
and Figure 11
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
2
2
2
-
11
4
-
-
-
-
2
2
2
-
-
-
-
-
2
2
2
-
-
-
-
-
ns
ns
ns
pF
3
[4]
CPD
power
fi = 1 MHz;
19
dissipation
capacitance
VI = GND to VCC
74HCT259-Q100
[2]
[2]
[2]
tpd
propagation
delay
D to Qn; see Figure 6
VCC = 4.5 V
-
-
23
20
39
-
-
-
49
-
-
-
59
-
ns
ns
VCC = 5.0 V; CL = 15 pF
An to Qn; see Figure 7
VCC = 4.5 V
-
-
25
20
41
-
51
-
62
-
ns
ns
VCC = 5.0 V; CL = 15 pF
LE to Qn; see Figure 8
VCC = 4.5 V
-
-
-
-
22
20
38
-
-
-
48
-
-
-
57
-
ns
ns
VCC = 5.0 V; CL = 15 pF
tPHL
HIGH to LOW MR to Qn; see Figure 9
propagation
delay
VCC = 4.5 V
-
-
23
20
39
-
-
-
49
-
-
-
59
-
ns
ns
VCC = 5.0 V; CL = 15 pF
[3]
tt
transition time see Figure 8
VCC = 4.5 V
-
7
15
-
19
-
22
ns
tW
pulse width
LE HIGH or LOW;
see Figure 8
VCC = 4.5 V
19
18
11
10
-
-
24
23
-
-
29
27
-
-
ns
ns
MR LOW; see Figure 9
VCC = 4.5 V
74HC_HCT259_Q100
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Product data sheet
Rev. 1 — 30 July 2012
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74HC259-Q100; 74HCT259-Q100
NXP Semiconductors
8-bit addressable latch
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 12.
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ[1] Max
Min
Max
Min
Max
tsu
set-up time
D, An to LE;
see Figure 10 and
Figure 11
VCC = 4.5 V
17
0
10
-
-
21
0
-
-
26
0
-
-
ns
ns
th
hold time
D to LE; see Figure 10
and Figure 11
VCC = 4.5 V
8
An to LE; see Figure 10
and Figure 11
VCC = 4.5 V
0
-
4
-
-
0
-
-
-
0
-
-
-
ns
[4]
CPD
power
fi = 1 MHz;
19
pF
dissipation
capacitance
VI = GND to VCC 1.5 V
[1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
[2] tpd is the same as tPLH and tPHL
[3] tt is the same as tTHL and tTLH
.
.
[4] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of the outputs.
11. Waveforms
V
CC
D input
V
M
GND
t
t
PLH
PHL
V
OH
V
M
Qn output
V
OL
001aah123
Measurement points are given in Table 9.
OL and VOH are typical voltage output levels that occur with the output load.
V
Fig 6. Data input to output propagation delays
74HC_HCT259_Q100
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Product data sheet
Rev. 1 — 30 July 2012
10 of 20
74HC259-Q100; 74HCT259-Q100
NXP Semiconductors
8-bit addressable latch
V
CC
V
M
An input
GND
t
t
PLH
PHL
V
OH
V
Qn output
M
V
OL
001aah122
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Address input to output propagation delays
V
CC
D input
GND
V
CC
V
M
LE input
GND
t
W
t
t
PLH
PHL
V
OH
V
Y
V
Qn output
M
V
X
V
OL
t
t
THL
TLH
001aaj446
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8. Enable input to output propagation delays and pulse width
V
CC
MR input
V
M
GND
t
W
t
PHL
V
OH
V
Qn output
M
V
OL
001aah124
Measurement points are given in Table 9.
OL and VOH are typical voltage output levels that occur with the output load.
V
Fig 9. Master reset input to output propagation delays
74HC_HCT259_Q100
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Product data sheet
Rev. 1 — 30 July 2012
11 of 20
74HC259-Q100; 74HCT259-Q100
NXP Semiconductors
8-bit addressable latch
V
CC
LE input
V
M
GND
t
t
su
su
t
t
h
h
V
CC
V
D input
M
GND
V
OH
V
Qn output
Q = D
Q = D
M
V
OL
001aah125
Measurement points are given in Table 9.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 10. Data input to latch enable input set-up and hold times
V
CC
An input
LE input
V
ADDRESS STABLE
M
GND
t
t
h
su
V
CC
V
M
GND
001aah126
Measurement points are given in Table 9.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 11. Address input to latch enable input set-up and hold times
Table 9.
Type
Measurement points
Input
VM
Output
VM
VX
VY
74HC259-Q100
74HCT259-Q100
0.5VCC
1.3 V
0.5VCC
1.3 V
0.1VCC
0.1VCC
0.9VCC
0.9VCC
74HC_HCT259_Q100
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Product data sheet
Rev. 1 — 30 July 2012
12 of 20
74HC259-Q100; 74HCT259-Q100
NXP Semiconductors
8-bit addressable latch
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
CC
V
CC
V
V
O
I
R
L
S1
G
open
DUT
R
T
C
L
001aad983
Test data is given in Table 10.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch
Fig 12. Load circuit for measuring switching times
Table 10. Test data
Type
Input
VI
Load
S1 position
tPHL, tPLH
open
tr, tf
6 ns
6 ns
CL
RL
74HC259-Q100
74HCT259-Q100
VCC
3 V
15 pF, 50 pF
15 pF, 50 pF
1 k
1 k
open
74HC_HCT259_Q100
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Product data sheet
Rev. 1 — 30 July 2012
13 of 20
74HC259-Q100; 74HCT259-Q100
NXP Semiconductors
8-bit addressable latch
12. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig 13. Package outline SOT109-1 (SO16)
74HC_HCT259_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 30 July 2012
14 of 20
74HC259-Q100; 74HCT259-Q100
NXP Semiconductors
8-bit addressable latch
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig 14. Package outline SOT403-1 (TSSOP16)
74HC_HCT259_Q100
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Product data sheet
Rev. 1 — 30 July 2012
15 of 20
74HC259-Q100; 74HCT259-Q100
NXP Semiconductors
8-bit addressable latch
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm
SOT763-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
7
L
1
8
9
E
h
e
16
15
10
D
h
X
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
1
y
D
D
E
L
v
w
y
1
1
h
h
max.
0.05 0.30
0.00 0.18
3.6
3.4
2.15
1.85
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT763-1
- - -
MO-241
- - -
Fig 15. Package outline SOT763-1 (DHVQFN16)
74HC_HCT259_Q100
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Product data sheet
Rev. 1 — 30 July 2012
16 of 20
74HC259-Q100; 74HCT259-Q100
NXP Semiconductors
8-bit addressable latch
13. Abbreviations
Table 11. Abbreviations
Acronym
CDM
CMOS
DUT
Description
Charged Device Model
Complementary Metal-Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
LSTTL
MM
Low-power Schottky Transistor-Transistor Logic
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 12. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74HC_HCT259_Q100 v.1 20120730
Product data sheet
-
-
74HC_HCT259_Q100
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Product data sheet
Rev. 1 — 30 July 2012
17 of 20
74HC259-Q100; 74HCT259-Q100
NXP Semiconductors
8-bit addressable latch
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use in automotive applications — This NXP
15.2 Definitions
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74HC_HCT259_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 30 July 2012
18 of 20
74HC259-Q100; 74HCT259-Q100
NXP Semiconductors
8-bit addressable latch
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74HC_HCT259_Q100
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Product data sheet
Rev. 1 — 30 July 2012
19 of 20
74HC259-Q100; 74HCT259-Q100
NXP Semiconductors
8-bit addressable latch
17. Contents
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 17
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 18
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 19
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 30 July 2012
Document identifier: 74HC_HCT259_Q100
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