74HC162 [NXP]
Presettable synchronous BCD decade counter; synchronous reset; 可预置同步BCD十进制计数器;同步复位
| 型号： | 74HC162 |
| 厂家： | 
NXP |
| 描述： | Presettable synchronous BCD decade counter; synchronous reset |
| 文件： | 总11页 (文件大小：85K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT162
Presettable synchronous BCD
decade counter; synchronous reset
December 1990
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
Presettable synchronous BCD decade
counter; synchronous reset
74HC/HCT162
that the set-up and hold time requirements for PE are met).
Preset takes place regardless of the levels at count enable
inputs (CEP and CET).
FEATURES
• Synchronous counting and loading
• Two count enable inputs for n-bit cascading
• Positive-edge triggered clock
• Synchronous reset
For the “162” the clear function is synchronous.
A LOW level at the master reset input (MR) sets all four
outputs of the flip-flops (Q0 to Q3) to LOW level after the
next positive-going transition on the clock (CP) input
(provided that the set-up and hold time requirements for
MR are met). This action occurs regardless of the levels at
PE, CET and CEP inputs.
• Output capability: standard
• ICC category: MSI
This synchronous reset feature enables the designer to
modify the maximum count with only one external NAND
gate.
GENERAL DESCRIPTION
The 74HC/HCT162 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The look-ahead carry simplifies serial cascading of the
counters. Both count enable inputs (CEP and CET) must
be HIGH to count. The CET input is fed forward to enable
the terminal count output (TC). The TC output thus
enabled will produce a HIGH output pulse of a duration
approximately equal to a HIGH level output of Q0. This
pulse can be used to enable the next cascaded stage.
The 74HC/HCT162 are synchronous presettable decade
counters which feature an internal look-ahead carry and
can be used for high-speed counting.
Synchronous operation is provided by having all flip-flops
clocked simultaneously on the positive-going edge of the
clock (CP).
The outputs (Q0 to Q3) of the counters may be preset to a
HIGH or LOW level. A LOW level at the parallel enable
input (PE) disables the counting action and causes the
data at the data inputs (D0 to D3) to be loaded into the
counter on the positive-going edge of the clock (providing
The maximum clock frequency for the cascaded counters
is determined by the CP to TC propagation delay and CEP
to CP set-up time, according to the following formula:
1
--------------------------------------------------------------------------------------------------------
fmax
=
tP (max) (CP to TC) + tSU (CEP to CP)
Notes
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
1. CPD is used to determine the
dynamic power dissipation
TYPICAL
HC HCT
(PD in µW):
SYMBOL
PARAMETER
CONDITIONS
UNIT
PD = CPD × VCC2 × fi +
∑ (CL × VCC2 × fo)
where:
tPHL
propagation delay
CP to Qn
CL = 15 pF;
VCC = 5 V
19
21
11
20
26
15
ns
ns
ns
CP to TC
CET to TC
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of
outputs
tPLH
propagation delay
CP to Qn
19
21
11
20
19
10
ns
ns
ns
CP to TC
CET to TC
CL = output load capacitance in
pF
fmax
maximum clock
frequency
63
32
MHz
VCC = supply voltage in V
2. For HC the condition is
VI = GND to VCC
CI
input capacitance
3.5 3.5 pF
37 37 pF
CPD
power dissipation
capacitance per package
notes 1 and 2
For HCT the condition is
VI = GND to VCC − 1.5 V
December 1990
2
Philips Semiconductors
Product specification
Presettable synchronous BCD decade
counter; synchronous reset
74HC/HCT162
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1
MR
synchronous master reset (active LOW)
clock input (LOW-to-HIGH, edge-triggered)
data inputs
2
CP
3, 4, 5, 6
D0 to D3
CEP
GND
PE
7
count enable input
8
ground (0 V)
9
parallel enable input (active LOW)
count enable carry input
flip-flop outputs
10
CET
14, 13, 12, 11 Q0 to Q3
15
16
TC
terminal count output
VCC
positive supply voltage
Fig.1 Pin configuration.
Fig.3 IEC logic symbol.
Fig.2 Logic symbol.
December 1990
3
Philips Semiconductors
Product specification
Presettable synchronous BCD decade
counter; synchronous reset
74HC/HCT162
Fig.4 Functional diagram.
FUNCTION TABLE
OPERATING MODE
INPUTS
CEP CET
OUTPUTS
MR
CP
PE
Dn
Qn
TC
reset (clear)
parallel load
I
↑
X
X
X
X
L
L
h
h
↑
↑
X
X
X
X
I
I
I
h
L
H
L
(1)
(1)
(1)
L
count
h
↑
h
h
h
X
count
hold
(do nothing)
h
h
X
X
I
X
X
I
h
h
X
X
qn
qn
Notes
1. The TC output is HIGH when CET is HIGH and the counter is at terminal count (HLLH).
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
q = lower case letters indicate the state of the referenced output one set-up time prior to the
LOW-to-HIGH CP transition
X = don’t care
↑ = LOW-to-HIGH CP transition
December 1990
4
Philips Semiconductors
Product specification
Presettable synchronous BCD decade
counter; synchronous reset
74HC/HCT162
Fig.5 State diagram.
Fig.6 Typical timing sequence: reset outputs to zero; preset to BCD seven; count to eight, nine, zero, one, two
and three; inhibit.
December 1990
5
Philips Semiconductors
Product specification
Presettable synchronous BCD decade
counter; synchronous reset
74HC/HCT162
Fig.7 Logic diagram.
December 1990
6
Philips Semiconductors
Product specification
Presettable synchronous BCD decade
counter; synchronous reset
74HC/HCT162
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
WAVEFORMS
VCC
(V)
+25
−40 to +85
−40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to Qn
58
21
17
190
38
32
240
48
41
285
57
48
ns
2.0
4.5
6.0
Fig.8
t
t
t
PHL/ tPLH propagation delay
CP to TC
69
25
20
215
43
37
270
54
46
325
65
55
ns
2.0
4.5
6.0
Fig.8
PHL/ tPLH propagation delay
CET to TC
39
14
11
150
30
26
190
38
33
225
45
38
ns
2.0
4.5
6.0
Fig.9
THL/ tTLH output transition
time
19
7
6
75
15
13
95
19
16
110
22
19
ns
2.0
4.5
6.0
Figs 8 and 9
Fig.8
tW
clock pulse width
HIGH or LOW
80
16
14
22
8
6
100
20
17
120
24
20
ns
2.0
4.5
6.0
tsu
tsu
tsu
th
set-up time
MR, Dn to CP
100 28
125
25
21
150
30
26
ns
2.0
4.5
6.0
Figs 9 and 11
Fig.9
20
17
10
8
set-up time
PE to CP
135 39
170
34
29
205
41
35
ns
2.0
4.5
6.0
27
23
14
11
set-up time
CEP, CET to CP
200 69
250
50
43
300
60
51
ns
2.0
4.5
6.0
Fig.12
40
34
25
20
hold time
Dn, PE, CEP,
CET, MR to CP
0
0
0
−17
−6
−5
0
0
0
0
0
0
ns
2.0
4.5
6.0
Figs 9, 11 and
12
fmax
maximum clock
pulse
frequency
6.0
30
35
19
57
68
4.8
24
28
4.0
20
24
MHz
2.0
4.5
6.0
Fig.8
December 1990
7
Philips Semiconductors
Product specification
Presettable synchronous BCD decade
counter; synchronous reset
74HC/HCT162
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
MR
CP
0.95
0.80
0.25
0.25
1.50
0.30
CEP
Dn
CET
PE
December 1990
8
Philips Semiconductors
Product specification
Presettable synchronous BCD decade
counter; synchronous reset
74HC/HCT162
AC CHARACTERISTICS FOR HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
WAVEFORMS
74HCT
SYMBOL PARAMETER
UNIT
+25
−40 to +85
−40
to +125
VCC
(V)
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to Qn
24
30
22
18
12
7
43
51
45
35
24
15
54
64
56
44
30
19
65
77
68
53
36
22
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5
Fig.8
tPHL
tPLH
tPHL
tPLH
propagation delay
CP to TC
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
Fig.8
propagation delay
CP to TC
Fig.8
propagation delay
CET to TC
Fig.9
propagation delay
CET to TC
Fig.9
tTHL/ tTLH output transition time
Figs 8 and 9
Fig.8
tW
tsu
tsu
tsu
tsu
th
clock pulse width
HIGH or LOW
16
20
35
40
20
0
7
20
25
44
50
25
0
24
30
53
60
30
0
set-up time
Dn to CP
9
Fig.9
set-up time
PE to CP
16
23
12
−10
Fig.9
set-up time
CEP, CET to CP
Fig.12
Fig.11
set-up time
MR to CP
hold time
Figs 9, 11 and 12
Dn, PE, CEP,
CET, MR to CP
fmax
maximum clock
pulse frequency
17
29
14
11
MHz 4.5
Fig.8
December 1990
9
Philips Semiconductors
Product specification
Presettable synchronous BCD decade
counter; synchronous reset
74HC/HCT162
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.8 Waveforms showing the clock (CP) to outputs (Qn, TC) propagation delays, the clock pulse width, the
output transition times and the maximum clock frequency.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.9 Waveforms showing the input (CET) to output (TC) propagation delays and output transition times.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.10 Waveforms showing the set-up and hold times for the input (Dn) and parallel enable input (PE).
December 1990
10
Philips Semiconductors
Product specification
Presettable synchronous BCD decade
counter; synchronous reset
74HC/HCT162
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.11 Waveforms showing the MR set-up and hold times.
The shaded areas indicate when the input is permitted
to change for predictable output performance.
(1) HC : VM = 50%; VI = GND to VCC
.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.12 Waveforms showing the CEP and CET set-up and hold times.
APPLICATION INFORMATION
The HC/HCT162 facilitate designing counters of any modulus with minimal external logic.
The output is glitch-free due to the synchronous reset.
Fig.13 Modulo-5 counter.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
11
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