74F8960 [NXP]
Octal latched bidirectional Futurebus transceivers 3-State open-collector; 八进制锁存双向FUTUREBUS收发器，三态集电极开路
| 型号： | 74F8960 |
| 厂家： | 
NXP |
| 描述： | Octal latched bidirectional Futurebus transceivers 3-State open-collector |
| 文件： | 总11页 (文件大小：198K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors FAST Products
Product specification
Octal latched bidirectional Futurebus transceivers
(3-State + open-collector)
74F8960/74F8961
voltage swing is much less for BTL, so is its
receiver threshold region, therefore noise
margins are excellent.
FEATURES
• Octal latched transceiver
DESCRIPTION
The 74F8960 and 74F8961 are octal
bidirectional latched transceivers and are
intended to provide the electrical interface to
a high performance wired–OR bus. The B
port inverting drivers are low–capacitance
open collector with controlled ramp and are
designed to sink 100mA from 2 volts. The B
port inverting receivers have a 100 mV
threshold region and a 4ns glitch filter.
• Drives heavily loaded backplanes with
equivalent load impedances down to 10Ω
BTL offers low power consumption, low
ground bounce, EMI and crosstalk, low
capacitive loading, superior noise margin and
low propagation delays. This results in a high
bandwidth, reliable backplane.
• High drive (100mA) open collector drivers
on B port
• Reduced voltage swing (1 volt) produces
The 74F8960 and 74F8961 A ports have TTL
3–state drivers and TTL receivers with a latch
function. A separate High–level control input
(VX) is provided to limit the A side output
level to a given voltage level (such as 3.3V).
For 5.0V systems, VX is simply tied to VCC.
less noise and reduces power consumption
• High speed operation enhances
performance of backplane buses and
facilitates incident wave switching
The B port interfaces to ‘Backplane
Transceiver Logic’ (BTL). BTL features a
reduced (1V to 2V) voltage swing for lower
power consumption and a series diode on
the drivers to reduce capacitive loading.
• Compatible with IEEE futurebus standards
The 74F8961 is the non–inverting version of
74F8960.
• Built-in precision band-gap reference
provides accurate receiver thresholds and
improved noise immunity
Incident switching is employed, therefore BTL
propagation delays are short. Although the
• Controlled output ramp and multiple GND
pins minimize ground bounce
• Glitch-free power up/down operation
TYPE
TYPICAL PROPAGATION DELAY
TYPICAL SUPPLY CURRENT( TOTAL)
74F8960
74F8961
6.5ns
6.5ns
80mA
80mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V ±10%, T
= 0°C to +70°C
amb
1
28–pin plastic DIP (300 mil)
N74F8960N, N748961N
N74F8960A, N74F8961A
1
28–pin PLCC
NOTE: Thermal mounting techiques are recommended.
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
PINS
DESCRIPTION
A0 – A8
B0 – B8
OEA
PNP latched inputs
3.5/0.117
5.0/0.167
1.0/0.033
1.0/0.033
1.0/0.033
150/40
70µA/70µA
100µA/100µA
20µA/20µA
20µA/20µA
20µA/20µA
3mA/24mA
OC/100mA
Data inputs with threshold circuitry
A output enable input (active high)
B output enable inputs (active low)
Latch enable input (active low)
3–state outputs
OEB0, OEB1
LE
A0 – A7
B0 – B7
Open collector outputs
OC/166.7
NOTES:
1. One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
2. OC = Open collector.
1
December 19, 1990
853-1120 01322
Philips Semiconductors FAST Products
Product specification
Octal latched bidirectional Futurebus transceivers
(3-State + open-collector)
74F8960/74F8961
PIN CONFIGURATION
PIN CONFIGURATION PLCC
LOGIC SYMBOL
74F8960
74F8960
74F8960
1
2
3
4
5
6
7
8
9
28 LE
27 B0
V
CC
3
5
6
7
9
10
12 13
OEA
A0
V
GND A0 OEA
LE B0 B1
CC
1
26
4
3
2
28 27
26
25
B1
A1
A2
5
6
7
A0 A1 A2 A3 A4 A5
OEB0
A6 A7
25
24
23
22
21
20
19
GND
GND
A1
GND
24 B2
23
B2
15
2
A2
A3
OEA
LE
B3
B3
A3
28
16
22 GND
GND
8
9
PLCC
GND
B4
OEB1
21
GND
A4
A4
B4
20 B5
B0 B1 B2 B3 B4 B5
B6 B7
19 17
A5 10
B5
B6
A5 10
19
18
17
16
15
B6
GND 11
11
12
13
14
GND
A6
GND
B7
12 13 14 15 16 17
A6 A7 OEB2OEB1 B7 GND
18
27 26 24 23 21 20
V
X
OEB1
A7
OEB0
V
X
V
= Pin 1, V = Pin 14
X
GND = Pin 4, 8, 11, 18, 22, 25
CC
PIN CONFIGURATION
PIN CONFIGURATION PLCC
LOGIC SYMBOL
74F8961
74F8961
74F8961
1
2
3
4
5
6
7
8
9
28 LE
27 B0
V
CC
3
5
6
7
9
10
12 13
OEA
A0
V
GND A0 OEA
LE B0 B1
CC
1
26
4
3
2
28 27
26
25
B1
A1
A2
5
6
7
A0 A1 A2 A3 A4 A5
OEB0
A6 A7
25
24
23
22
GND
GND
A1
GND
24 B2
23
B2
15
2
A2
A3
OEA
LE
B3
22 GND
B3
A3
28
16
GND
8
9
PLCC
GND
OEB1
A4
GND
A4
21
B4
21 B4
20 B5
B0 B1 B2 B3 B4 B5 B6 B7
A5 10
20
19
B5
B6
A5 10
19
18
17
16
15
B6
GND 11
11
12
13
14
GND
A6
GND
B7
12 13 14 15 16 17
18
27 26 24 23 21 20 19 17
A6 A7
OEB2OEB1 B7 GND
V
X
OEB1
A7
OEB0
V
X
V
= Pin 1, V = Pin 14
X
GND = Pin 4, 8, 11, 18, 22, 25
CC
2
December 19, 1990
Philips Semiconductors FAST Products
Product specification
Octal latched bidirectional Futurebus transceivers
(3-State + open-collector)
74F8960/74F8961
IEC/IEEE SYMBOL FOR 74F8960
IEC/IEEE SYMBOL FOR 74F8961
74F8960
74F8961
&
&
15
16
28
2
15
EN2
EN2
16
28
C1
C1
2
EN3
EN3
27
27
3
3
2
2
1D
3
1D
3
5
5
26
24
23
21
20
19
17
26
24
23
21
20
19
17
6
6
7
7
9
9
10
11
13
10
11
13
PIN DESCRIPTION
SYMBOL
PINS
TYPE
NAME AND FUNCTION
A0 – A7
B0 – B7
3, 5, 6, 7, 9, 10, 12, 13
I/O
PNP latched input/3–state output (with V control option)
X
Data input with special threshold circuitry to reject noise/ open collector output, high
current drive
27, 26, 24, 23, 21, 20, 19, 17
I/O
OEB0
OEB1
LE
15
16
28
14
Input
Input
Input
Input
Enables the B outputs when both pins are low
Enables the A outputs when high
Latched when high (a special feature is buillt in for proper enabling times)
V
X
Clamping voltage keeping V from rising above V (V = V for normal use)
OH X X cc
3
December 19, 1990
Philips Semiconductors FAST Products
Product specification
Octal latched bidirectional Futurebus transceivers
(3-State + open-collector)
74F8960/74F8961
LOGIC DIAGRAM
74F9861
74F9860
15
16
15
16
OEB0
OEB0
OEB1
OEA
OEB1
OEA
2
2
28
3
28
3
LE
A0
LE
A0
Q
Q
Data
LE
Q
Q
Data
LE
27
27
26
B0
B0
B1
5
5
A1
Data
LE
A1
Data
LE
26
B1
6
6
Q
Q
A2
A3
Data
LE
A2
A3
Data
LE
24
24
23
B2
B2
B3
7
7
Q
Q
Data
LE
Data
LE
23
B3
9
9
Q
Q
Q
Q
A4
A5
Data
LE
A4
A5
Data
LE
21
21
20
B4
B4
B5
10
10
Data
LE
Data
LE
20
B5
12
13
12
13
Q
Q
A6
A7
Data
LE
A6
A7
Data
LE
19
19
17
B6
B6
B7
Q
Q
Data
LE
Data
LE
17
B7
V
= Pin 1, V = Pin 14,
X
CC
GND = Pin 4, 8, 11, 18, 22, 25
4
December 19, 1990
Philips Semiconductors FAST Products
Product specification
Octal latched bidirectional Futurebus transceivers
(3-State + open-collector)
74F8960/74F8961
FUNCTION TABLE FOR 74F8960
INPUTS
LATCH
STATE
H
OUTPUTS
OPERATING MODE
An Bn* LE
OEA
L
OEB
OEB
An
Z
Bn
L
0
1
H
X
X
X
–
L
L
L
L
A 3–state, data from A to B
L
L
L
L
L
L
L
Z
H**
X
H
L
L
Qn
(1)
H (2)
H (2)
Qn
H
Z
Qn A 3–state, latched data to B
(1) Feedback: A to B, B to A
–
H
H
H
H
L
L
L
(1)
H
L
–
H
L
H
H
H
L
L
L
Z(2) Preconditioned latch enabling data transfer from B to A
–
L
L
Z(2)
–
–
L
L
Qn
Z
Qn Latch state to A and B
Z
H
X
X
X
H
L
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
l
L
L
l
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
B and A 3–state
X
H
L
L
Qn
H
Z
–
H
H
H
H
L
H
L
–
L
L
B 3–state, data from B to A
–
H
L
H
H
L
Qn
Qn
H
H
L
–
H
X
X
X
H
L
Z
l
L
L
l
Z
B and A 3–state
X
H
L
L
Qn
H
Z
–
H
H
H
H
H
L
–
L
L
B 3–state, data from B to A
–
H
L
H
H
Qn
Qn
H
L
–
NOTES:
1. H = High–voltage level
2. L
3. X
4. –
5. Z
=
=
=
=
Low–voltage level
Don’t care
Input not externally driven
High impedance (off) state
6. Q = High or low voltage level one setup time prior to the low–to–high LE transition.
n
7. (1) = Condition will cause a feedback loop path: A to B and B to A.
8. (2) = The latch must be preconmditioned such that B inputs may assume a high or low level while OEB0 and OEB1 are low and LE is high.
9. H**= Goes to level of pullup voltage.
10.B* = Precaution should be taken to insure the B inputs do not float. If they do they are equal to low state.
5
December 19, 1990
Philips Semiconductors FAST Products
Product specification
Octal latched bidirectional Futurebus transceivers
(3-State + open-collector)
74F8960/74F8961
FUNCTION TABLE FOR 74F8961
INPUTS
LATCH
STATE
H
OUTPUTS
OPERATING MODE
An Bn* LE
OEA
L
OEB
OEB
An
Z
Bn
0
1
H
X
X
X
–
L
L
L
L
H** A 3–state, data from A to B
L
L
L
L
L
L
L
L
Z
X
H
L
L
Qn
(1)
H (2)
H (2)
Qn
H
Z
Qn A 3–state, latched data to B
(1) Feedback: A to B, B to A
–
H
H
H
H
L
L
L
(1)
H
L
–
H
L
H
H
H
L
L
L
Z(2) Preconditioned latch enabling data transfer from B to A
–
L
L
Z(2)
–
–
L
L
Qn
Z
Qn Latch state to A and B
Z
H
X
X
X
H
L
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
l
L
L
l
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
B and A 3–state
X
H
L
L
Qn
H
Z
–
H
H
H
H
L
H
L
–
L
L
B 3–state, data from B to A
–
H
L
H
H
L
Qn
Qn
H
H
L
–
H
X
X
X
H
L
Z
l
L
L
l
Z
B and A 3–state
X
H
L
L
Qn
H
Z
–
H
H
H
H
H
L
–
L
L
B 3–state, data from B to A
–
H
L
H
H
Qn
Qn
H
L
–
NOTES:
1. H = High–voltage level
2. L
3. X
4. –
5. Z
=
=
=
=
Low–voltage level
Don’t care
Input not externally driven
High impedance (off) state
6. Q = High or low–voltage level one setup time prior to the low–to–high LE transition.
n
7. (1) = Condition will cause a feedback loop path: A to B and B to A.
8. (2) = The latch must be preconmditioned such that B inputs may assume a high or low level while OEB0 and OEB1 are low and LE is high.
9. H**= Goes to level of pullup voltage.
10.B* = Precaution should be taken to insure the B inputs do not float. If they do they are equal to low state.
6
December 19, 1990
Philips Semiconductors FAST Products
Product specification
Octal latched bidirectional Futurebus transceivers
(3-State + open-collector)
74F8960/74F8961
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL
PARAMETER
RATING
UNIT
V
V
V
V
Supply voltage
Threshold control
Input voltage
–0.5 to +7.0
–0.5 to +7.0
–0.5 to +7.0
–0.5 to +5.5
–40 to +5
CC
X
V
OEB, OEA, LE
V
IN
A0 – A7, B0 – B7
V
I
IN
Input current
mA
V
I
Voltage applied to output in high output state
Current applied to output in low output state
–0.5 to V
V
OUT
CC
A0 – A7
B0 – B7
48
mA
mA
°C
°C
OUT
200
T
amb
Operating free air temperature range
Storage temperature range
0 to +70
Tstg
–65 to +150
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
MIN
NOM
MAX
UNIT
V
V
Supply voltage
4.5
5.0
5.5
CC
IH
V
High–level input voltage
Low–level input voltage
Input clamp current
Except B0 – B7
2.0
1.6
V
B0 – B7
Except B0 – B7
B0 – B7
V
V
IL
0.8
1.475
–18
–40
–3
V
V
I
Ik
Except A0 – A7
A0 – A7
mA
mA
mA
mA
mA
I
I
High–level output current
Low–level output current
A0 – A7
OH
A0 – A7
24
OL
B0 – B7
100
+70
T
amb
Operating free air temperature
0
°C
7
December 19, 1990
Philips Semiconductors FAST Products
Product specification
Octal latched bidirectional Futurebus transceivers
(3-State + open-collector)
74F8960/74F8961
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST
LIMITS
UNIT
TYP.
1
2
CONDITIONS
MIN.
MAX.
100
I
I
High–level output current
B0 – B7
B0 – B7
V
V
V
= MAX, V = MAX, V = MIN, V = 2.1V
µA
µA
V
OH
CC
CC
CC
IL
IH
OH
Power–off output current
= 0.0V, V = MAX, V = MIN, V = 2.1V
100
OFF
IL
IH
OH
= MIN,
= MAX, V = MIN
I
= –3mA, V =V
2.5
2.5
V
CC
OH
X
CC
4
V
High-level output voltage
A0 – A7
I
= –4mA,
=3.13V and 3.47V
OH
OH
V
IL
V
IH
V
X
4
A0 – A7
V
V
V
V
V
= MIN,
I
OL
= 20mA, V = V
CC
0.50
1.15
V
V
V
V
CC
X
V
V
Low-level output voltage
Input clamp voltage
B0 – B78
= MAX
= MIN
I
OL
= 100mA
OL
IL
I
OL
= 4mA
0.40
IH
A0 – A7
= MIN, I = I
-0.5
-1.2
IK
CC
CC
I
IK
Except A0 – A7
= MIN, I = I
V
I
IK
I
µA
mA
µA
Input current at
OEBn, OEA, LE
A0–A7, B0 – B7
V
V
= MAX, V = 7.0V
100
1
I
CC
I
maximum input voltage
= MAX, V = 5.5V
I
CC
I
IH
High–level input current
Low–level input current
OEBn, OEA, LE
B0–B7
V
CC
V
CC
V
CC
V
CC
= MAX, V = 2.7V
20
100
–20
–100
I
µA
µA
µA
= MAX, V = 2.1V, Bn – An = 0V
I
I
IL
OEBn, OEA, LE
B0 – B7
= MAX, V = 0.5V
I
= MAX, V = 0.3V
I
Off–state output current,
high–level current applied
I
I
+ I
+ I
A0 – A7
A0 – A7
V
= MAX, V = 2.7V
70
–70
100
10
µA
µA
µA
µA
OZH
IH
CC
O
Off–state output current,
low–level voltage applied
V
V
= MAX, V = 0.5V
OZL
IL
CC
I
= MAX, V = V , LE = OEA = OEBn =
CC
X
CC
–100
–10
2.7V, A0 – A7 = 2.7V, B0 – B7 = 2.0V,
I
X
High–level control current
V
CC
= MAX, V = 3.13 & 3.47V, LE = OEA =
X
OEBn = A0 – A7 = 2.7V, B0 – B7 = 2.0V,
V
2.7V
= MAX, Bn = 1.3V, OEA = 2.0V, OEBn =
= MAX, Bn = 1.8V, OEA = 2.0V, OEBn =
= MAX
CC
74F8960
A0–A7
I
Short circuit output
-60
-150
mA
OS
3
current
V
CC
2.7V
only 74F8961
I
I
V
V
65
100
75
100
145
100
mA
mA
mA
CCH
CC
I
Supply current (total)
I
= MAX, V = 0.5V
IL
CC
CCL
CC
CCZ
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type
and function table for operating mode.
2. All typical values are at V = 5V, T
3. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
= 25°C.
CC
amb
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I tests should be performed last.
OS
4. Due to test equipment limitations, actual test conditions are for V =1.8v and V = 1.3V.
IH
IL
8
December 19, 1990
Philips Semiconductors FAST Products
Product specification
Octal latched bidirectional Futurebus transceivers
(3-State + open-collector)
74F8960/74F8961
AC ELECTRICAL CHARACTERISTICS FOR 74F8960
A PORT LIMITS
T
= +25°C
= +5.0V
T
= 0°C to +70°C
= +5.0V ± 10%
amb
amb
V
SYMBOL
PARAMETER
TEST
V
UNIT
CC
CC
CONDITION
C = 50pF, R = 500Ω
C = 50p, R = 500Ω
L
L
L
L
MIN
TYP
MAX
MIN
MAX
t
t
Propagation delay
Bn to An
4.5
6.0
6.0
10.0
8.5
13.5
3.5
7.5
9.5
14.5
PLH
PHL
Waveform 1, 2
ns
ns
ns
t
t
Output enable time to high or low, OEA
to An
Waveform 4
Waveform 5
8.0
8.5
10.5
11.0
13.5
13.5
7.5
8.5
15.0
16.0
PZH
PZL
t
t
Output enable time from high or low,
OEA to An
Waveform 4
Waveform 5
2.0
2.0
3.5
4.5
6.5
7.0
2.0
2.0
7.0
7.5
PHZ
PLZ
B PORT LIMITS
T
= +25°C
= +5.0V
T
= 0°C to +70°C
= +5.0V ± 10%
amb
amb
V
SYMBOL
PARAMETER
TEST
V
UNIT
CC
CC
CONDITION
C
= 50pF, R = 9Ω
C
= 50pF, R = 9Ω
D
U
D
L
MIN
TYP
MAX
MIN
MAX
t
t
Propagation delay
An to Bn
3.5
3.5
5.5
5.0
8.0
8.0
2.0
3.0
9.5
9.0
PLH
PHL
Waveform 1, 2
Waveform 1, 2
Waveform 1, 2
ns
ns
ns
ns
t
t
Propagation delay
LE to Bn
3.5
4.0
5.5
6.5
8.5
9.0
2.5
3.0
9.5
10.5
PLH
PHL
t
t
Output enable/disable time
OEBn to Bn
2.5
3.5
4.5
5.5
7.5
8.5
1.5
3.5
8.0
9.0
PLH
PHL
t
t
Transition time, Bn port
1.3V to 1.7V, 1.7V to 1.3V
Test circuit and
waveforms
0.5
0.5
2.0
2.0
4.5
4.5
0.5
0.5
5.0
6.0
TLH
THL
AC SETUP REQUIREMENTS FOR 74F8960
LIMITS
T
= +25°C
= +5.0V
T
= 0°C to +70°C
= +5.0V ± 10%
amb
amb
V
SYMBOL
PARAMETER
TEST
V
UNIT
CC
CC
CONDITION
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
t
su
t
su
(H)
(L)
Setup time, high or low
An to LE
5.0
3.0
5.0
5.0
Waveform 3
ns
th(H)
th(L)
Hold time, high or low
An to LE
0.0
0.0
0.0
0.0
Waveform 3
Waveform 3
ns
ns
t (L)
w
LE pulse width, low
4.5
5.0
9
December 19, 1990
Philips Semiconductors FAST Products
Product specification
Octal latched bidirectional Futurebus transceivers
(3-State + open-collector)
74F8960/74F8961
AC ELECTRICAL CHARACTERISTICS FOR 74F8961
A PORT LIMITS
T
= +25°C
= +5.0V
T
= 0°C to +70°C
= +5.0V ± 10%
amb
amb
V
SYMBOL
PARAMETER
TEST
V
UNIT
CC
CC
CONDITION
C = 50pF, R = 500Ω
C = 50p, R = 500Ω
L
L
L
L
MIN
TYP
MAX
MIN
MAX
t
t
Propagation delay
Bn to An
5.5
4.5
8.0
6.0
12.0
9.0
5.5
4.5
12.0
9.0
PLH
PHL
Waveform 1, 2
ns
ns
ns
t
t
Output enable time to high or low, OEA
to An
Waveform 4
Waveform 5
8.0
8.5
10.5
11.0
13.5
13.5
7.5
8.0
15.0
15.5
PZH
PZL
t
t
Output enable time from high or low,
OEA to An
Waveform 4
Waveform 5
2.0
2.0
3.5
4.5
6.0
7.0
1.5
2.0
6.5
7.5
PHZ
PLZ
B PORT LIMITS
T
= +25°C
= +5.0V
T
= 0°C to +70°C
= +5.0V ± 10%
amb
amb
V
SYMBOL
PARAMETER
TEST
V
UNIT
CC
CC
CONDITION
C
= 50pF, R = 9Ω
C
= 50pF, R = 9Ω
D
U
D
U
MIN
TYP
MAX
MIN
MAX
t
t
Propagation delay
An to Bn
3.0
3.0
5.0
4.5
7.0
7.5
2.5
2.5
8.0
8.5
PLH
PHL
Waveform 1, 2
Waveform 1, 2
Waveform 1, 2
ns
ns
ns
ns
t
t
Propagation delay
LE to Bn
3.5
3.5
5.0
5.0
8.0
8.0
3.0
2.5
9.0
9.0
PLH
PHL
t
t
Output enable/disable time
OEBn to Bn
3.0
3.5
4.5
5.5
7.0
9.0
2.5
3.5
8.0
10.0
PLH
PHL
t
t
Transition time, Bn port
1.3V to 1.7V, 1.7V to 1.3V
Test circuit and
waveforms
0.5
0.5
2.0
2.0
4.5
4.5
0.5
0.5
5.0
4.5
TLH
THL
AC SETUP REQUIREMENTS FOR 74F8961
LIMITS
T
= +25°C
= +5.0V
T
= 0°C to +70°C
= +5.0V ± 10%
amb
amb
V
SYMBOL
PARAMETER
TEST
V
UNIT
CC
CC
CONDITION
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
t
su
t
su
(H)
(L)
Setup time, high or low
An to LE
3.5
4.5
4.5
5.0
Waveform 3
ns
th(H)
th(L)
Hold time, high or low
An to LE
0.0
0.0
0.0
0.0
Waveform 3
Waveform 3
ns
ns
t (L)
w
LE pulse width, low
4.0
5.0
10
December 19, 1990
Philips Semiconductors FAST Products
Product specification
Octal latched bidirectional Futurebus transceivers
(3-State + open-collector)
74F8960/74F8961
AC WAVEFORMS
An, Bn, OEBn
An, Bn, OEBn
V
V
M
V
V
M
M
M
t
t
t
t
PHL
PLH
PLH
PHL
An, Bn
V
V
V
V
M
M
M
M
An, Bn
Waveform 1. Propagation delay for data to output
Waveform 2. Propagation delay for data to output
An
V
V
V
V
M
M
M
M
t
(L)
t (H)
h
h
t
(L)
t (H)
s
s
t
(L)
w
V
V
V
M
LE
M
M
Waveform 3. Data setup and hold times and LE pulse width
OEA
OEA
An
V
V
V
V
M
M
M
M
V
-0.3V
0V
OH
t
t
t
t
PLZ
PZH
PHZ
PZL
V
V
M
An
M
V
+0.3V
OL
Waveform 4. 3–state output enable time to high level
and output disable time from high level
Waveform 5. 3-state output enable time to low level
and output disable time from low level
NOTES:
1. For all waveforms, V = 1.5V.
M
2. The shaded areas indicate when the input is permitted to change for predictable output performance.
TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION
t
AMP (V)
Low V
w
90%
90%
TEST
SWITCH
closed
open
NEGATIVE
PULSE
V
CC
V
V
M
M
t
, t
PLZ PZL
10%
10%
7.0V
All other
R
t
t
)
)
t
t )
L
THL ( f
TLH ( r
V
V
OUT
IN
PULSE
GENERATOR
D.U.T.
t
t
t
t )
TLH ( r
THL ( f
AMP (V)
Low V
R
C
R
L
90%
M
90%
T
L
POSITIVE
PULSE
V
V
M
10%
10%
Test circuit for 3–state outputs on A port
t
w
V
7.0V
CC
Input pulse definition
INPUT PULSE REQUIREMENTS
R
U
V
V
OUT
IN
family
PULSE
GENERATOR
D.U.T.
V
Low V
74F amplitude
rep. rate
1MHz
t
t
t
M
w
TLH
THL
A port
B port
3.0V
3.0V
0.0V 1.5V
1.0V 1.5V
500ns 2.5ns 2.5ns
500ns 4.0ns 4.0ns
R
C
D
T
1MHz
Test circuit for outputs on B port
DEFINITIONS:
R
C
R
C
R
=
=
=
=
=
Load resistor; see AC electrical characteristics for value.
Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value.
Pull up resistor; see AC electrical characteristics for value.
L
L
U
D
T
Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value.
Termination resistance should be equal to Z
of pulse generators.
OUT
11
December 19, 1990
相关型号：
74F8960A
Registered Bus Transceiver, F/FAST Series, 1-Func, 8-Bit, Inverted Output, TTL, PDSO28
YAGEO
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