74ALVC373PW,112 [NXP]
74ALVC373 - Octal D-type transparent latch; 3-state TSSOP2 20-Pin;型号: | 74ALVC373PW,112 |
厂家: | NXP |
描述: | 74ALVC373 - Octal D-type transparent latch; 3-state TSSOP2 20-Pin 驱动 光电二极管 逻辑集成电路 |
文件: | 总17页 (文件大小:92K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
74ALVC373
Octal D-type transparent latch; 3-state
Rev. 02 — 18 October 2007
Product data sheet
1. General description
The 74ALVC373 is an octal D-type transparent latch featuring separate D-type inputs for
each latch and 3-state true outputs for bus-oriented applications. A latch enable (LE) input
and an outputs enable (OE) input are common to all latches.
When pin LE is HIGH, data at the D-inputs (pins D0 to D7) enters the latches. In this
condition, the latches are transparent, that is, a latch output will change each time its
corresponding D-input changes. When pin LE is LOW, the latches store the information
that was present at the D-inputs one set-up time preceding the HIGH-to-LOW transition of
pin LE.
When pin OE is LOW, the contents of the eight latches are available at the Q-outputs (pins
Q0 to Q7). When pin OE is HIGH, the outputs go to the high-impedance OFF-state.
Operation of input pin OE does not affect the state of the latches.
The 74ALVC373 is functionally identical to the 74ALVC573, but has a different pin
arrangement.
2. Features
■ Wide supply voltage range from 1.65 V to 3.6 V
■ 3.6 V tolerant inputs/outputs
■ CMOS low power consumption
■ Direct interface with TTL levels (2.7 V to 3.6 V)
■ Power-down mode
■ Latch-up performance exceeds 250 mA
■ Complies with JEDEC standards:
◆ JESD8-7 (1.65 V to 1.95 V)
◆ JESD8-5 (2.3 V to 2.7 V)
◆ JESD8B/JESD36 (2.7 V to 3.6 V)
■ ESD protection:
◆ HBM JESD22-A114E exceeds 2000 V
◆ MM JESD22-A 115-A exceeds 200 V
74ALVC373
NXP Semiconductors
Octal D-type transparent latch; 3-state
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74ALVC373D
−40 °C to +85 °C
SO20
plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
74ALVC373PW −40 °C to +85 °C
74ALVC373BQ −40 °C to +85 °C
TSSOP20
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT360-1
DHVQFN20 plastic dual in-line compatible thermal enhanced very SOT764-1
thin quad flat package; no leads; 20 terminals;
body 2.5 × 4.5 × 0.85 mm
4. Functional diagram
1
EN
11
D7
D6
D5
D4
D3
D2
D1
D0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
18
17
14
13
8
19
16
15
12
9
C1
3
2
1D
4
7
8
5
6
9
7
6
13
14
17
18
12
15
16
19
4
5
3
2
LE OE
mna881
11
1
mna880
Fig 1. Logic symbol
Fig 2. IEC logic symbol
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
3
4
2
5
7
6
8
9
LATCH
1 to 8
3-STATE
OUTPUTS
13
14
17
18
12
15
16
19
LE
11
1
OE
mna882
Fig 3. Functional diagram
74ALVC373_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 18 October 2007
2 of 17
74ALVC373
NXP Semiconductors
Octal D-type transparent latch; 3-state
LE
LE
LE
LE
D
Q
mna189
Fig 4. Logic diagram (one latch)
D0
D1
D2
D3
D4
D5
D6
D7
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
mna883
Fig 5. Logic diagram
74ALVC373_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 18 October 2007
3 of 17
74ALVC373
NXP Semiconductors
Octal D-type transparent latch; 3-state
5. Pinning information
5.1 Pinning
terminal 1
index area
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
Q0
Q7
D7
D6
Q6
Q5
D5
D4
Q4
D0
D1
Q1
Q2
D2
D3
Q3
1
2
20
19
18
17
16
15
14
13
12
11
OE
Q0
V
CC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
LE
3
D0
373A
4
D1
5
Q1
373A
6
Q2
(1)
GND
7
D2
8
D3
9
Q3
001aad089
10
GND
Transparent top view
001aad090
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 6. Pin configuration SO20 and TSSOP20
Fig 7. Pin configuration DHVQFN20
5.2 Pin description
Table 2.
Symbol
D[0:7]
LE
Pin description
Pin
Description
3, 4, 7, 8, 13, 14, 17, 18
data input
11
latch enable input (active HIGH)
output enable input (active LOW)
3-state latch output
OE
1
Q[0:7]
VCC
2, 5, 6, 9, 12, 15, 16, 19
20
10
supply voltage
GND
ground (0 V)
74ALVC373_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 18 October 2007
4 of 17
74ALVC373
NXP Semiconductors
Octal D-type transparent latch; 3-state
6. Functional description
Table 3.
Functional table[1]
Operating modes
Input
Internal latch
Output
OE
L
LE
H
H
L
Dn
L
Qn
L
Enable and read register
(transparent mode)
L
L
H
l
H
L
H
L
Latch and read register
L
L
L
h
H
X
H
H
Z
Latch register and disable
outputs
H
H
X
L
X
h
Z
[1] H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition
X = don’t care
Z = High-impedance OFF-state
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
−0.5
−50
−0.5
-
Max
+4.6
-
Unit
V
supply voltage
input clamping current
input voltage
VI < 0 V
mA
V
VI
+4.6
±50
VCC + 0.5
+4.6
+4.6
±50
100
-
IOK
output clamping current
output voltage
VO > VCC or VO < 0 V
output HIGH or LOW state
output 3-state
mA
V
[1] [2]
[2]
VO
−0.5
−0.5
−0.5
-
V
power-down mode, VCC = 0 V
VO = 0 V to VCC
V
IO
output current
mA
mA
mA
°C
mW
ICC
IGND
Tstg
Ptot
supply current
-
ground current
−100
−65
-
storage temperature
total power dissipation
+150
500
[3]
Tamb = −40 °C to +85 °C
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (power-down mode), the output voltage can be 3.6 V in normal operation.
[3] For SO20 packages: above 70 °C derate linearly with 8 mW/K.
For TSSOP20 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60 °C derate linearly with 4.5 mW/K.
74ALVC373_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 18 October 2007
5 of 17
74ALVC373
NXP Semiconductors
Octal D-type transparent latch; 3-state
8. Recommended operating conditions
Table 5.
Symbol
VCC
Recommended operating conditions
Parameter
Conditions
Min
Max
3.6
3.6
VCC
3.6
3.6
+85
20
Unit
V
supply voltage
input voltage
output voltage
1.65
VI
0
V
VO
output HIGH or LOW state
output 3-state
0
V
0
V
power-down mode; VCC = 0 V
in free air
0
V
Tamb
ambient temperature
−40
°C
ns/V
ns/V
∆t/∆V
input transition rise and fall rate
VCC = 1.65 V to 2.7 V
VCC = 2.7 V to 3.6 V
-
-
10
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
−40 °C to +85 °C
Unit
Min
Typ[1]
Max
VIH
HIGH-level input voltage
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
0.65 × VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
1.7
2.0
VIL
LOW-level input voltage
-
-
-
0.35 × VCC
0.7
0.8
VOH
HIGH-level output voltage VI = VIH or VIL
IO = −100 µA; VCC = 1.65 V to 3.6 V
V
CC − 0.2
1.25
1.8
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
IO = −6 mA; VCC = 1.65 V
IO = −12 mA; VCC = 2.3 V
IO = −18 mA; VCC = 2.3 V
IO = −12 mA; VCC = 2.7 V
IO = −18 mA; VCC = 3.0 V
IO = −24 mA; VCC = 3.0 V
VI = VIH or VIL
1.51
2.10
2.01
2.53
2.76
2.68
1.7
2.2
2.4
2.2
VOL
LOW-level output voltage
IO = 100 µA; VCC = 1.65 V to 3.6 V
IO = 6 mA; VCC = 1.65 V
IO = 12 mA; VCC = 2.3 V
IO = 18 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 18 mA; VCC = 3.0 V
IO = 24 mA; VCC = 3.0 V
VCC = 3.6 V; VI = 3.6 V or GND
-
-
-
-
-
-
-
-
-
0.2
0.3
0.4
0.6
0.4
0.4
0.55
±5
V
0.11
0.17
0.25
0.16
0.23
0.30
±0.1
V
V
V
V
V
V
II
input leakage current
µA
74ALVC373_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 18 October 2007
6 of 17
74ALVC373
NXP Semiconductors
Octal D-type transparent latch; 3-state
Table 6.
Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
−40 °C to +85 °C
Typ[1]
Unit
Min
Max
IOZ
OFF-state output current
VI = VIH or VIL; VCC = 1.65 V to 3.6 V;
VO = 3.6 V or GND;
-
±0.1
±10
µA
IOFF
ICC
power-off leakage supply
supply current
VCC = 0 V; VI or VO = 0 V to 3.6 V
-
-
±0.1
±10
µA
µA
VCC = 3.6 V; VI = VCC or GND;
IO = 0 A
0.2
10
∆ICC
additional supply current
input capacitance
per input pin; VCC = 3.0 V to 3.6 V;
VI = VCC − 0.6 V; IO = 0 A
-
-
5
750
-
µA
CI
3.5
pF
[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 12.
Symbol Parameter
Conditions
−40 °C to +85 °C
Unit
Min
Typ[1]
Max
[2]
tpd
propagation delay
Dn to Qn; see Figure 8
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.0
2.5
2.0
2.3
2.2
5.4
3.5
3.6
3.3
ns
ns
ns
ns
1.0
1.0
1.0
VCC = 3.0 V to 3.6 V
LE to Qn; see Figure 9
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.0
1.0
1.0
1.0
2.8
2.1
2.4
2.3
6.0
3.8
3.7
3.3
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
OE to Qn; see Figure 10
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
[2]
ten
enable time
disable time
1.5
1.0
1.5
1.0
3.0
2.4
3.0
2.3
6.4
4.5
4.6
4.0
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
OE to Qn; see Figure 10
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
[2]
tdis
1.5
1.0
1.5
1.0
3.4
2.2
2.8
2.7
7.0
4.4
4.4
4.4
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
74ALVC373_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 18 October 2007
7 of 17
74ALVC373
NXP Semiconductors
Octal D-type transparent latch; 3-state
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 12.
Symbol Parameter
Conditions
−40 °C to +85 °C
Unit
Min
Typ[1]
Max
tW
pulse width
set-up time
hold time
LE pulse width HIGH; see Figure 9
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
3.8
3.3
3.3
3.3
1.0
0.8
2.0
2.2
-
-
-
-
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
Dn to LE; see Figure 11
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
tsu
0.8
0.8
0.8
0.8
0.1
0.1
0.1
0.1
-
-
-
-
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
Dn to LE; see Figure 11
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
th
0.8
0.8
0.8
0.7
−0.1
−0.2
−0.3
−0.1
-
-
-
-
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
per latch; VI = GND to VCC; VCC = 3.3 V
outputs HIGH or LOW state
outputs 3-state
[3]
CPD
power dissipation
capacitance
-
-
35
14
-
-
pF
pF
[1] Typical values are measured at Tamb = 25 °C
[2] tpd is the same as tPHL and tPLH
ten is the same as tPZH and tPZL
tdis is the same as tPHZ and tPLZ
.
.
.
[3] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz; fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
Σ(CL × VCC2 × fo) = sum of the outputs
74ALVC373_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 18 October 2007
8 of 17
74ALVC373
NXP Semiconductors
Octal D-type transparent latch; 3-state
11. Waveforms
V
I
V
Dn input
M
GND
t
t
PLH
PHL
V
OH
V
M
Qn output
V
OL
mna884
Measurement points are given in Table 8.
VOL and VOH are the typical output voltage levels that occur with the output load.
Fig 8. Input Dn to output Qn propagation delay times
Table 8.
Measurement points
Supply voltage VCC
VM
Output
Vx
Vy
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
0.5VCC
0.5VCC
1.5 V
VOL + 0.15 V
VOL + 0.15 V
VOL + 0.3 V
VOL + 0.3 V
V
V
V
V
OH − 0.15 V
OH − 0.15 V
OH − 0.3 V
OH − 0.3 V
3.0 V to 3.6 V
1.5 V
V
I
LE input
V
M
GND
t
W
t
t
PLH
PHL
V
OH
V
M
Qn output
V
OL
mna885
Measurement points are given in Table 8.
VOL and VOH are the typical output voltage levels that occur with the output load.
Fig 9. Latch enable (LE) pulse width and latch enable input to output (Qn) propagation delays
74ALVC373_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 18 October 2007
9 of 17
74ALVC373
NXP Semiconductors
Octal D-type transparent latch; 3-state
V
I
OE input
V
M
GND
t
t
PZL
PLZ
V
CC
Q
output
n
V
M
LOW-to-OFF
OFF-to-LOW
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
Q
output
n
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
mna395
Measurement points are given in Table 8.
VOL and VOH are the typical output voltage levels that occur with the output load.
Fig 10. Enable and disable times
V
I
V
M
Dn input
GND
t
t
h
h
t
t
su
su
V
I
LE input
V
M
GND
mna887
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predicable output performance.
Fig 11. The data set-up and hold times for Dn input to LE input
74ALVC373_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 18 October 2007
10 of 17
74ALVC373
NXP Semiconductors
Octal D-type transparent latch; 3-state
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
r
f
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
V
CC
R
L
V
V
O
I
G
DUT
R
T
C
L
R
L
001aae331
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 12. Test circuitry for switching times
Table 9.
Test data
Supply voltage
Input
VI
Load
CL
VEXT
tr, tf
RL
tPLH, tPHL
open
tPLZ, tPZL
2 × VCC
2 × VCC
6 V
tPHZ, tPZH
GND
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
VCC
VCC
2.7 V
2.7 V
≤ 2.0 ns
≤ 2.0 ns
≤ 2.5 ns
≤ 2.5 ns
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
open
GND
open
GND
3.0 V to 3.6 V
open
6 V
GND
74ALVC373_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 18 October 2007
11 of 17
74ALVC373
NXP Semiconductors
Octal D-type transparent latch; 3-state
12. Package outline
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
y
H
E
v
M
A
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
2.65
0.1
0.25
0.01
1.27
0.05
1.4
0.25
0.01
0.25
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.51
0.014 0.009 0.49
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches
0.055
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT163-1
075E04
MS-013
Fig 13. Package outline SOT163-1 (SO20)
74ALVC373_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 18 October 2007
12 of 17
74ALVC373
NXP Semiconductors
Octal D-type transparent latch; 3-state
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
D
E
A
X
c
H
v
M
A
y
E
Z
11
20
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT360-1
MO-153
Fig 14. Package outline SOT360-1 (TSSOP20)
74ALVC373_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 18 October 2007
13 of 17
74ALVC373
NXP Semiconductors
Octal D-type transparent latch; 3-state
DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
20 terminals; body 2.5 x 4.5 x 0.85 mm
SOT764-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
9
L
1
10
E
h
e
20
11
19
12
D
h
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
1
y
D
D
E
L
v
w
y
1
1
h
h
max.
0.05 0.30
0.00 0.18
4.6
4.4
3.15
2.85
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
3.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT764-1
- - -
MO-241
- - -
Fig 15. Package outline SOT764-1 (DHVQFN20)
74ALVC373_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 18 October 2007
14 of 17
74ALVC373
NXP Semiconductors
Octal D-type transparent latch; 3-state
13. Abbreviations
Table 10. Abbreviations
Acronym
CDM
DUT
Description
Charged Device Model
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
Machine Model
HBM
MM
TTL
Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
Release date
20071018
Data sheet status
Change notice
Supersedes
74ALVC373_2
Product data sheet
-
74ALVC373_1
Modifications:
• The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Section 3: DHVQFN20 package added.
• Section 7: derating values added for DHVQFN20 package.
• Section 12: outline drawing added for DHVQFN20 package.
74ALVC373_1
20020226
Product specification
-
-
74ALVC373_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 18 October 2007
15 of 17
74ALVC373
NXP Semiconductors
Octal D-type transparent latch; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of a NXP Semiconductors product can reasonably be expected to
15.2 Definitions
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
16. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
74ALVC373_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 18 October 2007
16 of 17
74ALVC373
NXP Semiconductors
Octal D-type transparent latch; 3-state
17. Contents
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 16
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 18 October 2007
Document identifier: 74ALVC373_2
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