74AHCT2G125DP,125 [NXP]
74AHC(T)2G125 - Dual buffer/line driver; 3-state TSSOP 8-Pin;
| 型号： | 74AHCT2G125DP,125 |
| 厂家： | 
NXP |
| 描述： | 74AHC(T)2G125 - Dual buffer/line driver; 3-state TSSOP 8-Pin PC 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总16页 (文件大小：195K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AHC2G125; 74AHCT2G125
Dual buffer/line driver; 3-state
Rev. 3 — 6 May 2013
Product data sheet
1. General description
The 74AHC2G125 and 74AHCT2G125 are high-speed Si-gate CMOS devices. They
provide a dual non-inverting buffer/line driver with 3-state output. The 3-state output is
controlled by the output enable input (nOE). A HIGH at nOE causes the output to assume
a high-impedance OFF-state.
The AHC device has CMOS input switching levels and supply voltage range 2 V to 5.5 V.
The AHCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V.
2. Features and benefits
Symmetrical output impedance
High noise immunity
Low power dissipation
Balanced propagation delays
Multiple package options
ESD protection:
HBM JESD22-A114E: exceeds 2000 V
MM JESD22-A115-A: exceeds 200 V
CDM JESD22-C101C: exceeds 1000 V
Specified from 40 C to +125 C
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74AHC2G125DP
74AHCT2G125DP
74AHC2G125DC
74AHCT2G125DC
74AHC2G125GD
74AHCT2G125GD
40 C to +125 C
40 C to +125 C
40 C to +125 C
TSSOP8 plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
SOT505-2
VSSOP8 plastic very thin shrink small outline package;
8 leads; body width 2.3 mm
SOT765-1
SOT996-2
XSON8
plastic extremely thin small outline package; no
leads; 8 terminals; body 3 2 0.5 mm
74AHC2G125; 74AHCT2G125
NXP Semiconductors
Dual buffer/line driver; 3-state
4. Marking
Table 2.
Marking codes
Type number
Marking
A25
74AHC2G125DP
74AHCT2G125DP
74AHC2G125DC
74AHCT2G125DC
74AHC2G125GD
74AHCT2G125GD
C25
A25
C25
A25
C25
5. Functional diagram
1A
1Y
6
3
2
1
5
7
2
1
1OE
2A
6
1
EN1
2Y
nY
nA
5
7
3
2
2OE
EN2
nOE
mce185
mce186
mna227
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Logic diagram (one buffer)
6. Pinning information
6.1 Pinning
74AHC2G125
74AHCT2G125
1OE
1A
1
2
3
4
8
7
6
5
V
CC
74AHC2G125
74AHCT2G125
2OE
1Y
2Y
1
2
3
4
8
7
6
5
1OE
1A
V
CC
2OE
1Y
GND
2A
2Y
GND
2A
001aaj261
Transparent top view
001aaj260
Fig 4. Pin configuration SOT505-2 (TSSOP8) and
SOT765-1 (VSSOP8)
Fig 5. Pin configuration SOT996-2 (XSON8)
74AHC_AHCT2G125
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 6 May 2013
2 of 16
74AHC2G125; 74AHCT2G125
NXP Semiconductors
Dual buffer/line driver; 3-state
6.2 Pin description
Table 3.
Symbol
1OE, 2OE
1A, 2A
GND
Pin description
Pin
1, 7
2, 5
4
Description
output enable input (active LOW)
data input
ground (0 V)
1Y, 2Y
VCC
6, 3
8
data output
supply voltage
7. Functional description
Table 4.
Function table[1]
Control
Input
nA
L
Output
nOE
L
nY
L
L
H
H
Z
H
X
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
VI
Parameter
Conditions
Min
0.5
0.5
20
-
Max
+7.0
+7.0
-
Unit
V
supply voltage
input voltage
V
[1]
[1]
IIK
input clamping current
output clamping current
output current
VI < 0.5 V
mA
mA
mA
mA
mA
C
IOK
VO < 0.5 V or VO > VCC + 0.5 V
0.5 V < VO < VCC + 0.5 V
20
25
75
IO
-
ICC
supply current
-
IGND
Tstg
Ptot
ground current
75
65
-
-
storage temperature
total power dissipation
+150
250
[2]
Tamb = 40 C to +125 C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP8 package: above 55 C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110 C the value of Ptot derates linearly with 8 mW/K.
For XSON8 package: above 45 C the value of Ptot derates linearly with 2.4 mW/K.
74AHC_AHCT2G125
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 6 May 2013
3 of 16
74AHC2G125; 74AHCT2G125
NXP Semiconductors
Dual buffer/line driver; 3-state
9. Recommended operating conditions
Table 6.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
74AHC2G125
74AHCT2G125
Unit
Min
2.0
0
Typ
Max
5.5
Min
Typ
Max
VCC
VI
supply voltage
input voltage
5.0
4.5
5.0
5.5
5.5
V
V
V
-
-
5.5
0
0
-
VO
output voltage
ambient temperature
0
VCC
-
VCC
Tamb
t/V
40
-
+25
+125
100
20
40
-
+25
+125 C
input transition rise
and fall rate
VCC = 3.3 V 0.3 V
VCC = 5.0 V 0.5 V
-
-
-
-
-
ns/V
ns/V
-
-
20
10. Static characteristics
Table 7.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Max Min Max
Min Typ Max
74AHC2G125
VIH
HIGH-level
input voltage
VCC = 2.0 V
1.5
-
-
-
-
-
-
-
1.5
-
-
-
1.5
-
-
-
V
V
V
V
V
V
VCC = 3.0 V
2.1
-
2.1
2.1
VCC = 5.5 V
3.85
-
3.85
3.85
VIL
LOW-level
input voltage
VCC = 2.0 V
-
-
-
0.5
0.9
1.65
-
-
-
0.5
-
-
-
0.5
VCC = 3.0 V
0.9
0.9
VCC = 5.5 V
1.65
1.65
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = 50 A; VCC = 2.0 V
IO = 50 A; VCC = 3.0 V
IO = 50 A; VCC = 4.5 V
1.9
2.9
4.4
2.0
3.0
4.5
-
-
-
-
-
-
1.9
2.9
4.4
2.48
3.8
-
-
-
-
-
1.9
-
-
-
-
-
V
V
V
V
V
2.9
4.4
IO = 4.0 mA; VCC = 3.0 V 2.58
IO = 8.0 mA; VCC = 4.5 V 3.94
VI = VIH or VIL
2.40
3.70
-
VOL
LOW-level
output voltage
IO = 50 A; VCC = 2.0 V
IO = 50 A; VCC = 3.0 V
IO = 50 A; VCC = 4.5 V
IO = 4.0 mA; VCC = 3.0 V
IO = 8.0 mA; VCC = 4.5 V
VI = VCC or GND;
-
-
-
-
-
-
0
0
0
-
0.1
-
-
-
-
-
-
0.1
-
-
-
-
-
-
0.1
0.1
V
0.1
0.1
V
0.1
0.1
0.1
V
0.36
0.36
0.25
0.44
0.44
2.5
0.55
0.55
10
V
-
V
IOZ
II
OFF-state
-
A
output current VCC = 5.5 V
input leakage VI = 5.5 V or GND;
-
-
-
-
0.1
1.0
-
-
1.0
10
-
-
2.0
40
A
A
current
VCC = 0 V to 5.5 V
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
74AHC_AHCT2G125
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 6 May 2013
4 of 16
74AHC2G125; 74AHCT2G125
NXP Semiconductors
Dual buffer/line driver; 3-state
Table 7.
Static characteristics …continued
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Max Min Max
Min Typ Max
CI
input
-
1.5
10
-
10
-
10
pF
capacitance
74AHCT2G125
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
-
-
-
2.0
-
-
2.0
-
-
V
V
VIL
LOW-level
0.8
0.8
0.8
input voltage
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 50 A
4.4
4.5
-
-
-
4.4
3.8
-
-
4.4
-
-
V
V
IO = 8.0 mA
3.94
3.70
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 50 A
-
-
-
0
-
0.1
-
-
-
0.1
-
-
-
0.1
0.55
10
V
IO = 8.0 mA
0.36
0.25
0.44
2.5
V
IOZ
II
ICC
ICC
OFF-state
VI = VCC or GND;
output current VCC = 5.5 V
-
A
input leakage VI = 5.5 V or GND;
-
-
-
-
-
-
0.1
-
-
-
1.0
10
-
-
-
2.0
40
A
A
mA
current
VCC = 0 V to 5.5 V
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
1.0
additional
per input pin; VI = 3.4 V;
1.35
1.5
1.5
supply current other inputs at VCC or GND;
IO = 0 A; VCC = 5.5 V
CI
input
-
1.5
10
-
10
-
10
pF
capacitance
11. Dynamic characteristics
Table 8.
Dynamic characteristics
GND = 0 V; for test circuit see Figure 8.
Symbol Parameter Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max
Min
Max
Min
Max
74AHC2G125
[1]
[2]
tpd
propagation nA to nY; see Figure 6
delay
VCC = 3.0 V to 3.6 V
CL = 15 pF
CL = 50 pF
-
-
4.7
8.0
1.0
1.0
9.5
1.0
1.0
11.5
14.5
ns
ns
6.6 11.5
13.0
[3]
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
3.4
4.8
5.5
7.5
1.0
1.0
6.5
8.5
1.0
1.0
7.0
9.5
ns
ns
CL = 50 pF
74AHC_AHCT2G125
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 6 May 2013
5 of 16
74AHC2G125; 74AHCT2G125
NXP Semiconductors
Dual buffer/line driver; 3-state
Table 8.
Dynamic characteristics …continued
GND = 0 V; for test circuit see Figure 8.
Symbol Parameter Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max
Min
Max
Min
Max
[1]
[2]
ten
enable time nOE to nY; see Figure 7
VCC = 3.0 V to 3.6 V
CL = 15 pF
-
-
5.0
8.0
1.0
1.0
9.5
1.0
1.0
11.5
14.5
ns
ns
CL = 50 pF
6.9 11.5
13.0
[3]
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
3.6
4.9
5.1
7.5
1.0
1.0
6.0
8.5
1.0
1.0
6.5
9.5
ns
ns
CL = 50 pF
[1]
[2]
tdis
disable time nOE to nY; see Figure 7
VCC = 3.0 V to 3.6 V
CL = 15 pF
-
-
6.0
9.7
1.0
1.0
11.5
15.0
1.0
1.0
12.5
16.5
ns
ns
CL = 50 pF
8.3 13.2
[3]
[4]
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
-
4.1
5.7
9
6.8
8.8
-
1.0
1.0
-
8.0
10.0
-
1.0
1.0
-
8.5
11.0
-
ns
ns
pF
CL = 50 pF
CPD
power
per buffer;
dissipation
CL = 50 pF; fi = 1 MHz;
capacitance VI = GND to VCC
74AHCT2G125
[1]
[3]
tpd
ten
tdis
propagation nA to nY; see Figure 6
delay
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
3.4
4.8
5.5
7.5
1.0
1.0
6.5
8.5
1.0
1.0
6.5
8.5
ns
ns
CL = 50 pF
[1]
[3]
enable time nOE to nY; see Figure 7
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
3.9
5.1
5.1
7.5
1.0
1.0
6.0
8.5
1.0
1.0
6.0
8.5
ns
ns
CL = 50 pF
[1]
[3]
disable time nOE to nY; see Figure 7
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
4.5
6.1
6.8
8.8
1.0
1.0
8.0
1.0
1.0
8.0
ns
ns
CL = 50 pF
10.0
10.0
74AHC_AHCT2G125
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 6 May 2013
6 of 16
74AHC2G125; 74AHCT2G125
NXP Semiconductors
Dual buffer/line driver; 3-state
Table 8.
Dynamic characteristics …continued
GND = 0 V; for test circuit see Figure 8.
Symbol Parameter Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max
Min
Max
Min
Max
[4]
CPD
power
per buffer;
-
11
-
-
-
-
-
pF
dissipation
CL = 50 pF; fi = 1 MHz;
capacitance VI = GND to VCC
[1] tpd is the same as tPLH and tPHL
ten is the same as tPZL and tPZH
tdis is the same as tPLZ and tPHZ
.
.
.
[2] Typical values are measured at VCC = 3.3 V.
[3] Typical values are measured at VCC = 5.0 V.
[4]
CPD is used to determine the dynamic power dissipation PD (W).
PD = CPD VCC2 fi + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
12. Waveforms
V
I
V
nA input
M
GND
t
t
PHL
PLH
V
OH
V
nY output
M
V
OL
mna230
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 6. Input (nA) to output (nY) propagation delays
74AHC_AHCT2G125
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 6 May 2013
7 of 16
74AHC2G125; 74AHCT2G125
NXP Semiconductors
Dual buffer/line driver; 3-state
V
I
nOE input
GND
V
M
t
t
PZL
PLZ
V
CC
output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PHZ
PZH
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
mna362
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7. Enable and disable times
Table 9.
Type
Measurement points
Input
Output
VM
VM
VX
VY
74AHC2G125
74AHCT2G125
0.5VCC
1.5 V
0.5VCC
0.5VCC
VOL 0.3 V
VOL 0.3 V
VOH 0.3 V
VOH 0.3 V
74AHC_AHCT2G125
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 6 May 2013
8 of 16
74AHC2G125; 74AHCT2G125
NXP Semiconductors
Dual buffer/line driver; 3-state
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
CC
V
CC
V
V
O
I
R
L
S1
G
open
DUT
R
T
C
L
001aad983
Test data is given in Table 10.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 8. Test circuit for measuring switching times
Table 10. Test data
Type
Input
VI
Load
S1 position
tPHL, tPLH
open
tr, tf
CL
RL
tPZH, tPHZ
GND
tPZL, tPLZ
VCC
74AHC2G125
74AHCT2G125
VCC
3 V
3 ns
3 ns
15 pF, 50 pF
15 pF, 50 pF
1 k
1 k
open
GND
VCC
74AHC_AHCT2G125
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 6 May 2013
9 of 16
74AHC2G125; 74AHCT2G125
NXP Semiconductors
Dual buffer/line driver; 3-state
13. Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
SOT505-2
D
E
A
X
c
H
v
M
y
A
E
Z
5
8
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
A
A
A
b
c
D
E
e
H
E
L
L
p
UNIT
v
w
y
Z
θ
1
2
3
p
max.
0.15
0.00
0.95
0.75
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9
4.1
3.9
0.47
0.33
0.70
0.35
8°
0°
mm
1.1
0.65
0.25
0.5
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-01-16
SOT505-2
- - -
Fig 9. Package outline SOT505-2 (TSSOP8)
74AHC_AHCT2G125
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 6 May 2013
10 of 16
74AHC2G125; 74AHCT2G125
NXP Semiconductors
Dual buffer/line driver; 3-state
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
Q
A
2
A
A
1
(A )
3
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
A
A
A
b
c
D
E
e
H
L
L
p
Q
UNIT
v
w
y
Z
θ
1
2
3
p
E
max.
0.15
0.00
0.85
0.60
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
3.2
3.0
0.40
0.15
0.21
0.19
0.4
0.1
8°
0°
mm
1
0.5
0.12
0.4
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-06-07
SOT765-1
MO-187
Fig 10. Package outline SOT765-1 (VSSOP8)
74AHC_AHCT2G125
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 6 May 2013
11 of 16
74AHC2G125; 74AHCT2G125
NXP Semiconductors
Dual buffer/line driver; 3-state
XSON8: plastic extremely thin small outline package; no leads;
8 terminals; body 3 x 2 x 0.5 mm
SOT996-2
D
B
A
E
A
A
1
detail X
terminal 1
index area
e
1
C
v
C
C
A
B
b
e
L
1
y
1
y
w
C
1
4
L
2
L
8
5
X
0
1
2 mm
scale
Dimensions (mm are the original dimensions)
(1)
Unit
A
A
1
b
D
E
e
e
1
L
L
1
L
2
v
w
y
y
1
max
mm nom 0.5
min
0.05 0.35 2.1 3.1
0.00 0.15 1.9 2.9
0.5 0.15 0.6
0.3 0.05 0.4
0.5 1.5
0.1 0.05 0.05 0.1
sot996-2_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
07-12-21
12-11-20
SOT996-2
Fig 11. Package outline SOT996-2 (XSON8)
74AHC_AHCT2G125
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 6 May 2013
12 of 16
74AHC2G125; 74AHCT2G125
NXP Semiconductors
Dual buffer/line driver; 3-state
14. Abbreviations
Table 11. Abbreviations
Acronym
CMOS
CDM
DUT
Description
Complementary Metal Oxide Semiconductor
Charged Device Model
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
Machine Model
HBM
MM
TTL
Transistor-Transistor Logic
15. Revision history
Table 12. Revision history
Document ID
Release date
Data sheet status
Change
notice
Supersedes
74AHC_AHCT2G125 v.3
Modifications:
20130506
Product data sheet
-
74AHC_AHCT2G125 v.2
• For type number 74AHC2G125GD and 74AHCT2G125GD XSON8U has changed to
XSON8.
74AHC_AHCT2G125 v.2
Modifications:
20081222
Product data sheet
-
74AHC_AHCT2G125 v.1
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Added type number 74AHC2G125GD and 74AHCT2G125GD (XSON8U package).
74AHC_AHCT2G125 v.1
20040113
Product specification
-
-
74AHC_AHCT2G125
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 6 May 2013
13 of 16
74AHC2G125; 74AHCT2G125
NXP Semiconductors
Dual buffer/line driver; 3-state
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
16.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
74AHC_AHCT2G125
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 6 May 2013
14 of 16
74AHC2G125; 74AHCT2G125
NXP Semiconductors
Dual buffer/line driver; 3-state
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74AHC_AHCT2G125
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 6 May 2013
15 of 16
74AHC2G125; 74AHCT2G125
NXP Semiconductors
Dual buffer/line driver; 3-state
18. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 13
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13
8
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 15
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 6 May 2013
Document identifier: 74AHC_AHCT2G125
相关型号：
74AHCT2G125DP-G
Bus buffer/line driver; 3-state - Description: Dual Buffer/Line Driver with Active LOW Output Enable; TTL Enabled (3-State) ; Logic switching levels: TTL ; Number of pins: 8 ; Output drive capability: +/- 8 mA ; Power dissipation considerations: Low Power ; Propagation delay: 3.4 ns; Voltage: 4.5-5.5 V
NXP
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