74AHC30PW,112 [NXP]
74AHC(T)30 - 8-input NAND gate TSSOP 14-Pin;
| 型号： | 74AHC30PW,112 |
| 厂家： | 
NXP |
| 描述： | 74AHC(T)30 - 8-input NAND gate TSSOP 14-Pin |
| 文件： | 总17页 (文件大小：186K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AHC30; 74AHCT30
8-input NAND gate
Rev. 4 — 22 July 2015
Product data sheet
1. General description
The 74AHC30; 74AHCT30 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7-A.
The 74AHC30; 74AHCT30 provides an 8-input NAND function.
2. Features and benefits
Balanced propagation delays
All inputs have Schmitt-trigger actions
Inputs accept voltages higher than VCC
Input levels:
For 74AHC30: CMOS level
For 74AHCT30: TTL level
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature
range
Name
Description
Version
74AHC30D
40 C to +125 C
40 C to +125 C
40 C to +125 C
SO14
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74AHCT30D
74AHC30PW
74AHCT30PW
74AHC30BQ
74AHCT30BQ
TSSOP14
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
SOT762-1
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 3 0.85 mm
74AHC30GU12 40 C to +125 C
XQFN12
plastic, extremely thin quad flat package; no leads;
12 terminals; body 1.70 2.00 0.50 mm
SOT1174-1
74AHC30; 74AHCT30
NXP Semiconductors
8-input NAND gate
4. Marking
Table 2.
Marking codes
Type number
74AHC30D
Marking
74AHC30D
74AHCT30D
74AHC30PW
74AHCT30PW
74AHC30BQ
74AHCT30BQ
74AHC30GU12
74AHCT30D
AHC30
AHCT30
AHC30
AHT30
A3[1]
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
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Pin numbers are shown for SO14, TSSOP14 and
DHVQFN14 packages only
Pin numbers are shown for SO14, TSSOP14 and
DHVQFN14 packages only
Fig 1. Logic symbol
Fig 2. IEC logic symbol
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Fig 3. Logic diagram
74AHC_AHCT30
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 4 — 22 July 2015
2 of 17
74AHC30; 74AHCT30
NXP Semiconductors
8-input NAND gate
6. Pinning information
6.1 Pinning
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(1) This is not a supply pin, the substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad,
however if it is soldered the solder land should remain
floating or be connected to GND
Fig 4. Pin configuration SO14 and TSSOP14
Fig 5. Pin configuration DHVQFN14
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Fig 6. Pin configuration XQFN12 (SOT1174-1)
74AHC_AHCT30
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 4 — 22 July 2015
3 of 17
74AHC30; 74AHCT30
NXP Semiconductors
8-input NAND gate
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
Description
SO14, TSSOP14 and DHVQFN14
XQFN12
A
1
1
data input
B
2
2
data input
C
3
3
data input
D
4
4
data input
E
5
5
data input
F
6
7
data input
GND
Y
7
6
ground (0 V)
data output
not connected
not connected
data input
8
8
n.c.
n.c.
G
9
-
10
11
12
13
14
-
9
H
10
11
12
data input
n.c.
VCC
not connected
supply voltage
7. Functional description
Table 4.
Function table[1]
Input
A
Output
B
X
L
C
X
X
L
D
X
X
X
L
E
X
X
X
X
L
F
X
X
X
X
X
L
G
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
L
Y
H
H
H
H
H
H
H
H
L
L
X
X
X
X
X
X
X
X
H
X
X
X
X
X
X
H
X
X
X
X
X
H
X
X
X
X
H
X
X
X
H
X
X
H
H
H
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
74AHC_AHCT30
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 4 — 22 July 2015
4 of 17
74AHC30; 74AHCT30
NXP Semiconductors
8-input NAND gate
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
0.5
0.5
20
20
25
-
Max
+7.0
+7.0
-
Unit
V
VCC
VI
supply voltage
input voltage
V
[1]
[1]
IIK
input clamping current
output clamping current
output current
VI < 0.5 V
mA
mA
mA
mA
mA
C
IOK
IO
VO <0.5 V or VO > VCC + 0.5 V
VO =0.5 V to (VCC + 0.5 V)
+20
+25
+75
-
ICC
IGND
Tstg
Ptot
supply current
ground current
75
65
storage temperature
total power dissipation
+150
Tamb = 40 C to +125 C
SO14, TSSOP14 and DHVQFN14
XQFN12
[2]
-
-
500
250
mW
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO14 packages: above 70 C, the value of Ptot derates linearly at 8 mW/K.
For TSSOP14 packages: above 60 C, the value of Ptot derates linearly at 5.5 mW/K.
For DHVQFN14 packages: above 60 C, the value of Ptot derates linearly at 4.5 mW/K.
9. Recommended operating conditions
Table 6.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
74AHC30
74AHCT30
Unit
Min
2.0
0
Typ
Max
5.5
Min
4.5
0
Typ
Max
5.5
VCC
VI
supply voltage
input voltage
5.0
5.0
V
V
V
-
5.5
-
5.5
VO
output voltage
ambient temperature
0
-
VCC
+125
100
20
0
-
VCC
Tamb
t/V
40
-
+25
40
-
+25
+125 C
input transition rise
and fall rate
VCC = 3.3 V 0.3 V
VCC = 5.0 V 0.5 V
-
-
-
-
-
ns/V
ns/V
-
-
20
74AHC_AHCT30
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 4 — 22 July 2015
5 of 17
74AHC30; 74AHCT30
NXP Semiconductors
8-input NAND gate
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 C
Min Typ
40 C to +85 C 40 C to +125 C Unit
Max
Min
Max
Min
Max
74AHC30
VIH
HIGH-level
input voltage
VCC = 2.0 V
1.5
-
-
-
-
-
-
-
-
1.5
-
-
1.5
-
-
V
V
V
V
V
V
VCC = 3.0 V
2.1
2.1
2.1
VCC = 5.5 V
3.85
-
3.85
-
3.85
-
VIL
LOW-level
input voltage
VCC = 2.0 V
-
-
-
0.5
0.9
1.65
-
-
-
0.5
0.9
1.65
-
-
-
0.5
0.9
1.65
VCC = 3.0 V
VCC = 5.5 V
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = 50 A; VCC = 2.0 V
IO = 50 A; VCC = 3.0 V
IO = 50 A; VCC = 4.5 V
1.9
2.9
4.4
2.0
3.0
4.5
-
-
-
-
-
-
1.9
2.9
-
-
-
-
-
1.9
2.9
-
-
-
-
-
V
V
V
V
V
4.4
4.4
IO = 4.0 mA; VCC = 3.0 V 2.58
IO = 8.0 mA; VCC = 4.5 V 3.94
VI = VIH or VIL
2.48
3.80
2.40
3.70
-
VOL
LOW-level
output voltage
IO = 50 A; VCC = 2.0 V
IO = 50 A; VCC = 3.0 V
IO = 50 A; VCC = 4.5 V
IO = 4.0 mA; VCC = 3.0 V
IO = 8.0 mA; VCC = 4.5 V
-
-
-
-
-
-
0
0
0
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
V
V
0.1
0.1
0.1
V
0.36
0.36
0.1
0.44
0.44
1.0
0.55
0.55
2.0
V
-
V
II
input leakage VI = 5.5 V or GND;
current VCC = 0 V to 5.5 V
-
A
ICC
CI
CO
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
-
-
2.0
10
-
-
-
-
20
10
-
-
-
-
40
10
-
A
pF
pF
input
VI = VCC or GND
3
4
capacitance
output
capacitance
74AHC_AHCT30
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 4 — 22 July 2015
6 of 17
74AHC30; 74AHCT30
NXP Semiconductors
8-input NAND gate
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 C
Min Typ
40 C to +85 C 40 C to +125 C Unit
Max
Min
Max
Min
Max
74AHCT30
VIH
VIL
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
-
-
-
2.0
-
-
2.0
-
-
V
V
LOW-level
0.8
0.8
0.8
input voltage
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 50 A
4.4
4.5
-
-
-
4.4
-
-
4.4
-
-
V
V
IO = 8.0 mA
3.94
3.80
3.70
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 50 A
-
-
-
0
-
0.1
0.36
0.1
-
-
-
0.1
0.44
1.0
-
-
-
0.1
0.55
2.0
V
IO = 8.0 mA
V
II
input leakage VI = 5.5 V or GND;
current VCC = 0 V to 5.5 V
-
A
ICC
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
-
-
2.0
-
-
20
-
-
40
A
additional
per input pin;
1.35
1.5
1.5
mA
supply current VI = VCC 2.1 V; other pins
at VCC or GND; IO = 0 A;
VCC = 4.5 V to 5.5 V
CI
input
capacitance
VI = VCC or GND
-
-
3
4
10
-
-
-
10
-
-
-
10
-
pF
pF
CO
output
capacitance
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.
Symbol Parameter Conditions
74AHC30
25 C
Min Typ[1] Max
40 C to +85 C 40 C to +125 C Unit
Min
Max
Min
Max
tpd
propagation A, B, C, D, E, F, G, H to Y; see Figure 7 and 8 [2]
delay
VCC = 3.0 V to 3.6 V
CL = 15 pF
CL = 50 pF
-
-
5.0
6.7
9.5
1.0
1.0
11.0
14.5
1.0
1.0
12.0
15.5
ns
ns
12.0
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
-
3.6
4.9
10
6.5
8.0
-
1.0
1.0
-
7.5
9.5
-
1.0
1.0
-
8.0
10.5
-
ns
ns
pF
CL = 50 pF
[3]
CPD
power
fi = 1 MHz;
dissipation
capacitance
VI = GND to VCC
74AHC_AHCT30
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 4 — 22 July 2015
7 of 17
74AHC30; 74AHCT30
NXP Semiconductors
8-input NAND gate
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.
Symbol Parameter Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ[1] Max
Min
Max
Min
Max
74AHCT30; VCC = 4.5 V to 5.5 V
tpd
propagation A, B, C, D, E, F, G, H to Y; see Figure 7 and 8 [2]
delay
CL = 15 pF
CL = 50 pF
-
-
-
3.3
4.7
12
6.5
8.5
-
1.0
1.0
-
7.5
9.5
-
1.0
1.0
-
8.0
10.5
-
ns
ns
pF
[3]
CPD
power
fi = 1 MHz;
dissipation
capacitance
VI = GND to VCC
[1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
[2] tpd is the same as tPLH and tPHL
.
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of the outputs.
12. Waveforms
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Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Input to output propagation delays
Table 9.
Type
Measurement points
Input
VM
Output
VM
74AHC30
0.5 VCC
1.5 V
0.5 VCC
0.5 VCC
74AHCT30
74AHC_AHCT30
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 4 — 22 July 2015
8 of 17
74AHC30; 74AHCT30
NXP Semiconductors
8-input NAND gate
W
:
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Test data is given in Table 10.
Definitions for test circuit:
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
CL = load capacitance including jig and probe capacitance.
Fig 8. Test circuit for measuring switching times
Table 10. Test data
Type
Input
VI
Load
Test
tr, tf
CL
74AHC30
VCC
3.0 V
3.0 ns
3.0 ns
15 pF, 50 pF
15 pF, 50 pF
tPLH, tPHL
tPLH, tPHL
74AHCT30
74AHC_AHCT30
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 4 — 22 July 2015
9 of 17
74AHC30; 74AHCT30
NXP Semiconductors
8-input NAND gate
13. Package outline
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74AHC_AHCT30
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 4 — 22 July 2015
10 of 17
74AHC30; 74AHCT30
NXP Semiconductors
8-input NAND gate
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74AHC_AHCT30
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 4 — 22 July 2015
11 of 17
74AHC30; 74AHCT30
NXP Semiconductors
8-input NAND gate
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74AHC_AHCT30
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 4 — 22 July 2015
12 of 17
74AHC30; 74AHCT30
NXP Semiconductors
8-input NAND gate
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74AHC_AHCT30
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 4 — 22 July 2015
13 of 17
74AHC30; 74AHCT30
NXP Semiconductors
8-input NAND gate
14. Abbreviations
Table 11. Abbreviations
Acronym
CDM
Description
Charged Device Model
CMOS
DUT
Complementary Metal-Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
LSTTL
MM
Low-power Schottky Transistor-Transistor Logic
Machine Model
15. Revision history
Table 12. Revision history
Document ID
Release date
20150722
Data sheet status
Change notice
Supersedes
74AHC_AHCT30 v.4
Modifications:
Product data sheet
-
74AHC_AHCT30 v.3
• Added type number 74AHC30GU12.
20090626 Product data sheet
• Section 3: DHVQFN14 package added.
74AHC_AHCT30 v.3
Modifications:
-
74AHC_AHCT30 v.2
• Section 8: derating values added for DHVQFN14 package.
• Section 13: outline drawing added for DHVQFN14 package.
74AHC_AHCT30 v.2
74AHC_AHCT30 v.1
20080530
Product data sheet
-
74AHC_AHCT30 v.1
-
19991130
Product specification
-
74AHC_AHCT30
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 4 — 22 July 2015
14 of 17
74AHC30; 74AHCT30
NXP Semiconductors
8-input NAND gate
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
16.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
74AHC_AHCT30
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 4 — 22 July 2015
15 of 17
74AHC30; 74AHCT30
NXP Semiconductors
8-input NAND gate
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74AHC_AHCT30
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 4 — 22 July 2015
16 of 17
74AHC30; 74AHCT30
NXP Semiconductors
8-input NAND gate
18. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14
8
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 16
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2015.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 22 July 2015
Document identifier: 74AHC_AHCT30
相关型号：
74AHC30PW-T
IC AHC/VHC/H/U/V SERIES, 8-INPUT NAND GATE, PDSO14, 4.40 MM, PLASTIC, MO-153, SOT402-1, TSSOP-14, Gate
NXP
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