74AHC2G32GD [NXP]
Dual 2-input OR gate; 双路2输入或门
| 型号： | 74AHC2G32GD |
| 厂家： | 
NXP |
| 描述： | Dual 2-input OR gate |
| 文件： | 总13页 (文件大小：83K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AHC2G32; 74AHCT2G32
Dual 2-input OR gate
Rev. 02 — 20 January 2009
Product data sheet
1. General description
The 74AHC2G32; 74AHCT2G32 is a high-speed Si-gate CMOS device.
The 74AHC2G32; 74AHCT2G32 provides two 2-input OR gates.
2. Features
I Symmetrical output impedance
I High noise immunity
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101C exceeds 1000 V
I Low power dissipation
I Balanced propagation delays
I Multiple package options
I Specified from −40 °C to +85 °C and from −40 °C to +125 °C
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74AHC2G32DP
74AHCT2G32DP
74AHC2G32DC
74AHCT2G32DC
74AHC2G32GD
74AHCT2G32GD
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
TSSOP8
plastic thin shrink small outline package; 8 leads; body SOT505-2
width 3 mm; lead length 0.5 mm
VSSOP8
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
XSON8U plastic extremely thin small outline package; no leads; SOT996-2
8 terminals; UTLP based; body 3 × 2 × 0.5 mm
74AHC2G32; 74AHCT2G32
NXP Semiconductors
Dual 2-input OR gate
4. Marking
Table 2.
Marking
Type number
Marking code
74AHC2G32DP
74AHCT2G32DP
74AHC2G32DC
74AHCT2G32DC
74AHC2G32GD
74AHCT2G32GD
A32
C32
A32
C32
A32
C32
5. Functional diagram
1
2
≥ 1
≥ 1
7
3
1
2
1A
1B
1Y
2Y
7
3
B
A
5
6
2A
2B
5
6
Y
mna166
mna733
mna734
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Logic diagram (one gate)
6. Pinning information
6.1 Pinning
74AHC2G32
74AHCT2G32
1A
1B
1
2
3
4
8
7
6
5
V
CC
74AHC2G32
74AHCT2G32
1Y
2B
2A
1
2
3
4
8
7
6
5
1A
1B
V
CC
2Y
1Y
2B
2A
GND
2Y
GND
001aaj505
Transparent top view
001aaj504
Fig 4. Pin configuration SOT505-2 (TSSOP8) and
SOT765-1 (VSSOP8)
Fig 5. Pin configuration SOT996-2 (XSON8U)
74AHC_AHCT2G32_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 20 January 2009
2 of 13
74AHC2G32; 74AHCT2G32
NXP Semiconductors
Dual 2-input OR gate
6.2 Pin description
Table 3.
Symbol
1A, 2A
1B, 2B
GND
Pin description
Pin
1, 5
2, 6
4
Description
data input
data input
ground (0 V)
data output
supply voltage
1Y, 2Y
VCC
7, 3
8
7. Functional description
Table 4.
Function table[1]
Input
nA
L
Output
nB
L
nY
L
L
H
L
H
H
H
H
H
H
[1] H = HIGH voltage level; L = LOW voltage level.
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
VI
Parameter
Conditions
Min
−0.5
−0.5
−20
-
Max
+7.0
+7.0
-
Unit
V
supply voltage
input voltage
V
[1]
[1]
IIK
input clamping current
output clamping current
output current
VI < −0.5 V
mA
mA
mA
mA
mA
°C
IOK
VO < −0.5 V or VO > VCC + 0.5 V
−0.5 V < VO < VCC + 0.5 V
±20
±25
75
IO
-
ICC
supply current
-
IGND
Tstg
Ptot
ground current
−75
−65
-
-
storage temperature
total power dissipation
+150
250
[2]
Tamb = −40 °C to +125 °C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP8 package: above 55 °C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110 °C the value of Ptot derates linearly with 8 mW/K.
For XSON8U package: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.
74AHC_AHCT2G32_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 20 January 2009
3 of 13
74AHC2G32; 74AHCT2G32
NXP Semiconductors
Dual 2-input OR gate
9. Recommended operating conditions
Table 6.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
74AHC2G32
74AHCT2G32
Unit
Min
2.0
0
Typ
Max
5.5
Min
4.5
0
Typ
Max
VCC
VI
supply voltage
input voltage
5.0
5.0
5.5
5.5
V
V
V
-
5.5
-
VO
output voltage
ambient temperature
0
-
VCC
+125
100
20
0
-
VCC
Tamb
∆t/∆V
−40
-
+25
−40
-
+25
+125 °C
input transition rise
and fall rate
VCC = 3.3 V ± 0.3 V
VCC = 5.0 V ± 0.5 V
-
-
-
-
-
ns/V
ns/V
-
-
20
10. Static characteristics
Table 7.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
74AHC2G32
VIH
HIGH-level
input voltage
VCC = 2.0 V
1.5
-
-
-
-
-
-
-
-
1.5
-
-
1.5
-
-
V
V
V
V
V
V
VCC = 3.0 V
2.1
2.1
2.1
VCC = 5.5 V
3.85
-
3.85
-
3.85
-
VIL
LOW-level
input voltage
VCC = 2.0 V
-
-
-
0.5
0.9
1.65
-
-
-
0.5
0.9
1.65
-
-
-
0.5
0.9
1.65
VCC = 3.0 V
VCC = 5.5 V
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = −50 µA; VCC = 2.0 V
IO = −50 µA; VCC = 3.0 V
IO = −50 µA; VCC = 4.5 V
IO = −4.0 mA; VCC = 3.0 V
IO = −8.0 mA; VCC = 4.5 V
VI = VIH or VIL
1.9
2.9
2.0
3.0
4.5
-
-
-
-
-
-
1.9
2.9
-
-
-
-
-
1.9
2.9
-
-
-
-
-
V
V
V
V
V
4.4
4.4
4.4
2.58
3.94
2.48
3.8
2.40
3.70
-
VOL
LOW-level
output voltage
IO = 50 µA; VCC = 2.0 V
IO = 50 µA; VCC = 3.0 V
IO = 50 µA; VCC = 4.5 V
IO = 4.0 mA; VCC = 3.0 V
IO = 8.0 mA; VCC = 4.5 V
-
-
-
-
-
-
0
0
0
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
V
V
0.1
0.1
0.1
V
0.36
0.36
0.1
0.44
0.44
1.0
0.55
0.55
2.0
V
-
V
II
input leakage VI = 5.5 V or GND;
current CC = 0 V to 5.5 V
-
µA
V
ICC
CI
supply current VI = VCC or GND; IO = 0 A;
CC = 5.5 V
-
-
-
1.0
10
-
-
10
10
-
-
40
10
µA
V
input
1.5
pF
capacitance
74AHC_AHCT2G32_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 20 January 2009
4 of 13
74AHC2G32; 74AHCT2G32
NXP Semiconductors
Dual 2-input OR gate
Table 7.
Static characteristics …continued
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
74AHCT2G32
VIH
VIL
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
-
-
-
2.0
-
-
2.0
-
-
V
V
LOW-level
0.8
0.8
0.8
input voltage
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = −50 µA
4.4
4.5
-
-
-
4.4
3.8
-
-
4.4
-
-
V
V
IO = −8.0 mA
3.94
3.70
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 50 µA
-
-
-
0
-
0.1
0.36
0.1
-
-
-
0.1
0.44
1.0
-
-
-
0.1
0.55
2.0
V
IO = 8.0 mA
V
II
input leakage VI = 5.5 V or GND;
current CC = 0 V to 5.5 V
-
µA
V
ICC
∆ICC
supply current VI = VCC or GND; IO = 0 A;
CC = 5.5 V
-
-
-
-
1.0
-
-
10
-
-
40
µA
V
additional
per input pin; VI = 3.4 V;
1.35
1.5
1.5
mA
supply current other inputs at VCC or GND;
IO = 0 A; VCC = 5.5 V
CI
input
-
1.5
10
-
10
-
10
pF
capacitance
11. Dynamic characteristics
Table 8.
Dynamic characteristics
GND = 0 V; for test circuit see Figure 7.
Symbol Parameter Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
74AHC2G32
[1]
[2]
tpd
propagation nA, nB to nY; see Figure 6
delay
VCC = 3.0 V to 3.6 V
CL = 15 pF
-
-
4.4
7.9
1.0
1.0
9.5
1.0
1.0
10.0
14.5
ns
ns
CL = 50 pF
6.3 11.4
13.0
[3]
[4]
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
-
3.2
4.6
16
5.5
7.5
-
1.0
1.0
-
6.5
8.5
-
1.0
1.0
-
7.0
9.5
-
ns
ns
pF
CL = 50 pF
CPD
power
per buffer;
dissipation
CL = 50 pF; fi = 1 MHz;
capacitance VI = GND to VCC
74AHC_AHCT2G32_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 20 January 2009
5 of 13
74AHC2G32; 74AHCT2G32
NXP Semiconductors
Dual 2-input OR gate
Table 8.
Dynamic characteristics …continued
GND = 0 V; for test circuit see Figure 7.
Symbol Parameter Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
74AHCT2G32
[1]
[3]
tpd
propagation nA, nB to nY; see Figure 6
delay
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
-
3.3
4.8
17
6.9
7.9
-
1.0
1.0
-
8.0
9.0
-
1.0
1.0
-
9.0
10.0
-
ns
ns
pF
CL = 50 pF
[4]
CPD
power
per buffer;
dissipation
CL = 50 pF; fi = 1 MHz;
capacitance VI = GND to VCC
[1] tpd is the same as tPLH and tPHL
.
[2] Typical values are measured at VCC = 3.3 V.
[3] Typical values are measured at VCC = 5.0 V.
[4] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
12. Waveforms
V
I
V
nA, nB input
GND
M
t
t
PLH
PHL
V
OH
nY output
V
M
V
OL
mna224
Fig 6. The input (nA and nB) to output (nY) propagation delays.
Table 9.
Type
Measurement points
Input
VM
Output
VM
74AHC2G32
0.5VCC
1.5 V
0.5VCC
0.5VCC
74AHCT2G32
74AHC_AHCT2G32_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 20 January 2009
6 of 13
74AHC2G32; 74AHCT2G32
NXP Semiconductors
Dual 2-input OR gate
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
V
CC
CC
V
V
O
I
R
L
S1
G
open
DUT
R
T
C
L
001aad983
Test data is given in Table 10.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 7. Test circuit for measuring switching times
Table 10. Test data
Type
Input
VI
Load
S1 position
tPHL, tPLH
open
tr, tf
CL
RL
tPZH, tPHZ
GND
tPZL, tPLZ
VCC
74AHC2G32
VCC
3 V
≤ 3 ns
≤ 3 ns
15 pF, 50 pF
15 pF, 50 pF
1 kΩ
1 kΩ
74AHCT2G32
open
GND
VCC
74AHC_AHCT2G32_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 20 January 2009
7 of 13
74AHC2G32; 74AHCT2G32
NXP Semiconductors
Dual 2-input OR gate
13. Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
SOT505-2
D
E
A
X
c
H
v
M
y
A
E
Z
5
8
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
A
A
A
b
c
D
E
e
H
E
L
L
p
UNIT
v
w
y
Z
θ
1
2
3
p
max.
0.15
0.00
0.95
0.75
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9
4.1
3.9
0.47
0.33
0.70
0.35
8°
0°
mm
1.1
0.65
0.25
0.5
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-01-16
SOT505-2
- - -
Fig 8. Package outline SOT505-2 (TSSOP8)
74AHC_AHCT2G32_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 20 January 2009
8 of 13
74AHC2G32; 74AHCT2G32
NXP Semiconductors
Dual 2-input OR gate
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
Q
A
2
A
A
1
(A )
3
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
A
A
A
b
c
D
E
e
H
L
L
p
Q
UNIT
v
w
y
Z
θ
1
2
3
p
E
max.
0.15
0.00
0.85
0.60
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
3.2
3.0
0.40
0.15
0.21
0.19
0.4
0.1
8°
0°
mm
1
0.5
0.12
0.4
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-06-07
SOT765-1
MO-187
Fig 9. Package outline SOT765-1 (VSSOP8)
74AHC_AHCT2G32_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 20 January 2009
9 of 13
74AHC2G32; 74AHCT2G32
NXP Semiconductors
Dual 2-input OR gate
XSON8U: plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3 x 2 x 0.5 mm
SOT996-2
D
B
A
E
A
A
1
detail X
terminal 1
index area
e
1
C
M
M
v
C A
C
B
b
e
L
1
y
y
w
C
1
1
4
L
2
L
8
5
X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
1
b
D
E
e
e
1
L
L
L
v
w
y
y
1
1
2
max
0.05 0.35
0.00 0.15
2.1
1.9
3.1
2.9
0.5
0.3
0.15
0.05
0.6
0.4
mm
0.5
0.5
1.5
0.1
0.05 0.05
0.1
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
- - -
JEDEC
JEITA
07-12-18
07-12-21
SOT996-2
- - -
Fig 10. Package outline SOT996-2 (XSON8U)
74AHC_AHCT2G32_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 20 January 2009
10 of 13
74AHC2G32; 74AHCT2G32
NXP Semiconductors
Dual 2-input OR gate
14. Abbreviations
Table 11. Abbreviations
Acronym
CDM
CMOS
DUT
Description
Charged Device Model
Complementary Metal-Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
TTL
Transistor-Transistor Logic
15. Revision history
Table 12. Revision history
Document ID
Release date
20090120
Data sheet status
Change notice Supersedes
74AHC_AHCT2G32_1
74AHC_AHCT2G32_2
Modifications:
Product data sheet
-
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Added type number 74AHC2G32GD and 74AHCT2G32GD (XSON8U package).
74AHC_AHCT2G32_1
20040223
Product specification
-
-
74AHC_AHCT2G32_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 20 January 2009
11 of 13
74AHC2G32; 74AHCT2G32
NXP Semiconductors
Dual 2-input OR gate
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
16.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74AHC_AHCT2G32_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 20 January 2009
12 of 13
74AHC2G32; 74AHCT2G32
NXP Semiconductors
Dual 2-input OR gate
18. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 11
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11
8
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 12
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 12
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 20 January 2009
Document identifier: 74AHC_AHCT2G32_2
相关型号：
74AHC30BQ-Q100
IC AHC/VHC/H/U/V SERIES, 8-INPUT NAND GATE, PQCC14, 2.50 X 3 MM, 0.85 MM HEIGHT, PLASTIC, MO-241, SOT762-1, DHVQFN-14, Gate
NXP
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