74AHC259_08 [NXP]
8-bit addressable latch; 8位可寻址锁存器
| 型号： | 74AHC259_08 |
| 厂家： | 
NXP |
| 描述： | 8-bit addressable latch |
| 文件： | 总17页 (文件大小：106K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AHC259; 74AHCT259
8-bit addressable latch
Rev. 02 — 15 May 2008
Product data sheet
1. General description
The 74AHC259; 74AHCT259 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7-A.
The 74AHC259; 74AHCT259 is a high-speed 8-bit addressable latch designed for general
purpose storage applications in digital systems. It is a multifunctional device capable of
storing single-line data in eight addressable latches and providing a 3-to-8 decoder and
multiplexer function with active HIGH outputs (Q0 to Q7). It also incorporates an active
LOW common reset (MR) for resetting all latches as well as an active LOW enable input
(LE).
The 74AHC259; 74AHCT259 has four modes of operation:
• In the addressable latch mode, data on the data line (D) is written into the addressed
latch. The addressed latch will follow the data input with all non-addressed latches
remaining in their previous states.
• In the memory mode, all latches remain in their previous states and are unaffected by
the data or address inputs.
• In the 3-to-8 decoding or demultiplexing mode, the addressed output follows the state
of the data input (D) with all other outputs in the LOW state.
• In the reset mode, all outputs are LOW and unaffected by the address inputs
(A0 to A2) and data input (D).
When operating the 74AHC259; 74AHCT259 as an address latch, changing more than
one bit of the address could impose a transient-wrong address. Therefore, this should
only be done while in the memory mode.
2. Features
I Balanced propagation delays
I All inputs have Schmitt-trigger actions
I Combines demultiplexer and 8-bit latch
I Serial-to-parallel capability
I Output from each storage bit available
I Random (addressable) data entry
I Easily expandable
I Common reset input
I Useful as a 3-to-8 active HIGH decoder
I Inputs accept voltages higher than VCC
74AHC259; 74AHCT259
NXP Semiconductors
8-bit addressable latch
I Input levels:
N For 74AHC259: CMOS level
N For 74AHCT259: TTL level
I ESD protection:
N HBM EIA/JESD22-A114E exceeds 2000 V
N MM EIA/JESD22-A115-A exceeds 200 V
N CDM EIA/JESD22-C101C exceeds 1000 V
I Multiple package options
I Specified from −40 °C to +85 °C and from −40 °C to +125 °C
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74AHC259
74AHC259D
−40 °C to +125 °C
−40 °C to +125 °C
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
SOT403-1
74AHC259PW
TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
74AHCT259
74AHCT259D
−40 °C to +125 °C
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
SOT403-1
74AHCT259PW −40 °C to +125 °C
TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
4. Functional diagram
13
Z9
15
G8
14
G10
9,10D
1
DX
4
14
LE
C10
8R
0
1
2
3
0
2
5
6
4
5
0
7
Q0
1
2
3
4
5
6
7
G
13
D
Q1
Q2
Q3
Q4
Q5
Q6
Q7
6
7
7
9
1
2
3
9
A0
A1
A2
10
11
12
10
11
12
MR
15 mna573
mna572
Fig 1. Logic symbol
Fig 2. IEC logic symbol
74AHC_AHCT259_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 15 May 2008
2 of 17
74AHC259; 74AHCT259
NXP Semiconductors
8-bit addressable latch
Q0
Q1
Q2
Q3
Q4
Q5
4
5
A0
A1
A2
1
2
3
6
1-of-8
DECODER
7
8 LATCHES
9
14 LE
10
15
13
Q6 11
Q7 12
MR
D
mna571
Fig 3. Functional diagram
5. Pinning information
5.1 Pinning
74AHC259
74AHCT259
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A0
A1
A2
Q0
Q1
Q2
Q3
V
CC
MR
LE
D
Q7
Q6
Q5
Q4
GND
001aai126
Fig 4. Pin configuration
5.2 Pin description
Table 2.
Symbol
A0
Pin description
Pin
Description
address input
address input
address input
latch output
latch output
latch output
latch output
ground (0 V)
latch output
latch output
1
2
3
4
5
6
7
8
9
10
A1
A2
Q0
Q1
Q2
Q3
GND
Q4
Q5
74AHC_AHCT259_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 15 May 2008
3 of 17
74AHC259; 74AHCT259
NXP Semiconductors
8-bit addressable latch
Table 2.
Symbol
Q6
Pin description …continued
Pin
11
12
13
14
15
16
Description
latch output
Q7
latch output
D
data input
LE
latch enable input (active LOW)
MR
conditional reset input (active LOW)
supply voltage
VCC
6. Functional description
Table 3.
Function table[1]
Operating mode
Input
Output
A0 A1 A2 Q0
MR LE
D
X
d
d
d
d
d
d
d
d
X
d
d
d
d
d
d
d
H
Q1
Q2
L
Q3
L
Q4
L
Q5
L
Q6
L
Q7
L
Reset (clear)
L
L
H
L
X
L
X
L
X
L
L
L
Demultiplexer
(active HIGH 8-channel)
decoder (when D = H)
Q = d L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
q0
Q = d L
L
L
L
L
L
H
H
L
L
L
Q = d L
L
L
L
L
H
L
L
L
L
Q = d L
L
L
L
H
H
H
H
X
L
L
L
L
Q = d L
L
L
H
L
L
L
L
L
L
Q = d L
L
H
H
X
L
L
L
L
L
L
Q = d L
H
X
L
L
L
L
L
L
L
Q = d
Memory (no action)
Addressable latch
H
H
H
L
q1
q2
q2
q3
q3
q3
q4
q4
q4
q4
q5
q5
q5
q5
q5
q6
q6
q6
q6
q6
q6
q7
q7
q7
q7
q7
q7
q7
Q = d q1
H
L
L
L
q0
q0
q0
q0
q0
q0
q0
Q = d q2
H
H
L
L
q1
q1
q1
q1
q1
q1
Q = d q3
H
L
L
q2
q2
q2
q2
q2
Q = d q4
H
H
H
H
q3
q3
q3
q3
Q = d q5
H
L
L
q4
q4
q4
Q = d q6
H
H
q5
q5
Q = d q7
q6 Q = d
H
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
d = HIGH or LOW data one set-up time prior to the LOW-to-HIGH LE transition;
q = lower case letter indicates the state of the referenced input one set-up time prior to the LOW-to-HIGH transition.
74AHC_AHCT259_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 15 May 2008
4 of 17
74AHC259; 74AHCT259
NXP Semiconductors
8-bit addressable latch
Table 4.
Operating mode select table[1]
LE
L
MR
H
Mode
addressable latch
memory
H
L
H
L
active HIGH 8-channel demultiplexer
reset
H
L
[1] H = HIGH voltage level; L = LOW voltage level.
7. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
−0.5
−0.5
−20
−20
−25
-
Max
+7.0
+7.0
-
Unit
V
VCC
VI
supply voltage
input voltage
V
[1]
[1]
IIK
input clamping current
output clamping current
output current
VI < −0.5 V
mA
mA
mA
mA
mA
°C
IOK
IO
VO < −0.5 V or VO > VCC + 0.5 V
VO = −0.5 V to (VCC + 0.5 V)
+20
+25
+75
-
ICC
IGND
Tstg
Ptot
supply current
ground current
−75
−65
-
storage temperature
total power dissipation
+150
500
[2]
Tamb = −40 °C to +125 °C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO16 packages: above 70 °C the value of Ptot derates linearly at 8 mW/K.
For TSSOP16 packages: above 60 °C the value of Ptot derates linearly at 5.5 mW/K.
8. Recommended operating conditions
Table 6.
Operating conditions
Symbol Parameter
74AHC259
Conditions
Min
Typ
Max
Unit
VCC
VI
supply voltage
2.0
5.0
5.5
V
input voltage
0
-
5.5
V
VO
output voltage
0
-
VCC
+125
100
20
V
Tamb
∆t/∆V
ambient temperature
input transition rise and fall rate
−40
+25
°C
ns/V
ns/V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
-
-
-
-
74AHCT259
VCC
VI
supply voltage
4.5
0
5.0
5.5
V
input voltage
-
5.5
V
VO
output voltage
0
-
VCC
+125
20
V
Tamb
∆t/∆V
ambient temperature
input transition rise and fall rate
−40
-
+25
-
°C
ns/V
VCC = 4.5 V to 5.5 V
74AHC_AHCT259_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 15 May 2008
5 of 17
74AHC259; 74AHCT259
NXP Semiconductors
8-bit addressable latch
9. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
74AHC259
VIH
HIGH-level
input voltage
VCC = 2.0 V
1.5
-
-
-
-
-
-
-
-
1.5
-
-
1.5
-
-
V
V
V
V
V
V
VCC = 3.0 V
2.1
2.1
2.1
VCC = 5.5 V
3.85
-
3.85
-
3.85
-
VIL
LOW-level
input voltage
VCC = 2.0 V
-
-
-
0.5
0.9
1.65
-
-
-
0.5
0.9
1.65
-
-
-
0.5
0.9
1.65
VCC = 3.0 V
VCC = 5.5 V
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = −50 µA; VCC = 2.0 V
IO = −50 µA; VCC = 3.0 V
IO = −50 µA; VCC = 4.5 V
IO = −4.0 mA; VCC = 3.0 V
IO = −8.0 mA; VCC = 4.5 V
VI = VIH or VIL
1.9
2.9
2.0
3.0
4.5
-
-
-
-
-
-
1.9
2.9
-
-
-
-
-
1.9
2.9
-
-
-
-
-
V
V
V
V
V
4.4
4.4
4.4
2.58
3.94
2.48
3.80
2.40
3.70
-
VOL
LOW-level
output voltage
IO = 50 µA; VCC = 2.0 V
IO = 50 µA; VCC = 3.0 V
IO = 50 µA; VCC = 4.5 V
IO = 4.0 mA; VCC = 3.0 V
IO = 8.0 mA; VCC = 4.5 V
-
-
-
-
-
-
0
0
0
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
V
V
0.1
0.1
0.1
V
0.36
0.36
0.1
0.44
0.44
1.0
0.55
0.55
2.0
V
-
V
II
input leakage VI = 5.5 V or GND;
current CC = 0 V to 5.5 V
-
µA
V
ICC
CI
CO
supply current VI = VCC or GND; IO = 0 A;
CC = 5.5 V
-
-
-
-
4.0
10
-
-
-
-
40
10
-
-
-
-
80
10
-
µA
pF
pF
V
input
VI = VCC or GND
3
4
capacitance
output
capacitance
74AHCT259
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
-
-
-
2.0
-
-
2.0
-
-
V
V
VIL
LOW-level
0.8
0.8
0.8
input voltage
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = −50 µA
4.4
4.5
-
-
-
4.4
-
-
4.4
-
-
V
V
IO = −8.0 mA
3.94
3.80
3.70
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 50 µA
-
-
0
-
0.1
-
-
0.1
-
-
0.1
V
V
IO = 8.0 mA
0.36
0.44
0.55
74AHC_AHCT259_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 15 May 2008
6 of 17
74AHC259; 74AHCT259
NXP Semiconductors
8-bit addressable latch
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max
Min
Max
Min
Max
II
input leakage VI = 5.5 V or GND;
current CC = 0 V to 5.5 V
-
-
-
-
-
-
0.1
-
1.0
-
2.0
µA
µA
mA
V
ICC
∆ICC
supply current VI = VCC or GND; IO = 0 A;
CC = 5.5 V
4.0
-
-
40
-
-
80
V
additional
per input pin; VI = VCC − 2.1 V;
1.35
1.5
1.5
supply current other pins at VCC or GND;
IO = 0 A; VCC = 4.5 V to 5.5 V
CI
input
capacitance
VI = VCC or GND
-
-
3
4
10
-
-
-
10
-
-
-
10
-
pF
pF
CO
output
capacitance
10. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11.
Symbol Parameter Conditions
74AHC259
25 °C
Min Typ[1] Max
−40 °C to +85 °C −40 °C to +125 °C Unit
Min
Max
Min
Max
[2]
[2]
[2]
tpd
propagation D to Qn; see Figure 5
delay
VCC = 3.0 V to 3.6 V
CL = 15 pF
-
-
5.8 11.5
7.3 14.5
1.0
1.0
13.5
17.0
1.0
1.0
15.0
18.5
ns
ns
CL = 50 pF
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
4.1
5.3
7.5
9.5
1.0
1.0
9.0
1.0
1.0
10.0
12.0
ns
ns
CL = 50 pF
11.0
An to Qn; see Figure 6
VCC = 3.0 V to 3.6 V
CL = 15 pF
-
-
7.5 14.5
9.1 18.0
1.0
1.0
17.0
21.0
1.0
1.0
18.5
23.0
ns
ns
CL = 50 pF
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
5.3
9.5
1.0
1.0
11.5
13.5
1.0
1.0
12.5
15.0
ns
ns
CL = 50 pF
6.5 11.5
LE to Qn; see Figure 7
VCC = 3.0 V to 3.6 V
CL = 15 pF
-
-
6.2 12.0
7.7 15.5
1.0
1.0
14.0
17.5
1.0
1.0
15.2
19.0
ns
ns
CL = 50 pF
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
4.3
8.0
1.0
1.0
9.5
1.0
1.0
10.5
12.5
ns
ns
CL = 50 pF
5.5 10.0
11.5
74AHC_AHCT259_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 15 May 2008
7 of 17
74AHC259; 74AHCT259
NXP Semiconductors
8-bit addressable latch
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11.
Symbol Parameter Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ[1] Max
Min
Max
Min
Max
[3]
tpd
propagation MR to Qn; see Figure 8
delay
VCC = 3.0 V to 3.6 V
CL = 15 pF
-
-
5.4 10.5
7.0 13.5
1.0
1.0
12.5
15.5
1.0
1.0
13.5
17.0
ns
ns
CL = 50 pF
VCC = 4.5 V to 5.5 V
CL = 15 pF
-
-
3.9
5.1
7.0
9.0
1.0
1.0
8.5
1.0
1.0
9.5
ns
ns
CL = 50 pF
10.5
11.5
tW
pulse width LE HIGH or LOW;
see Figure 7
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
MR LOW; see Figure 8
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
5.0
5.0
-
-
-
-
5.0
5.0
-
-
5.0
5.0
-
-
ns
ns
5.0
5.0
-
-
-
-
5.0
5.0
-
-
5.0
5.0
-
-
ns
ns
tsu
set-up time D, An to LE; see Figure 9
and Figure 10
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
4.0
4.0
-
-
-
-
4.0
4.0
-
-
4.0
4.0
-
-
ns
ns
th
hold time
D, An to LE; see Figure 9
and Figure 10
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
1.0
1.0
-
-
-
-
-
-
1.0
1.0
-
-
-
-
1.0
1.0
-
-
-
-
ns
ns
pF
[4]
CPD
power
fi = 1 MHz; VI = GND to VCC
13
dissipation
capacitance
74AHCT259; VCC = 4.5 V to 5.5 V
tpd propagation D to Qn; see Figure 5
[2]
[2]
[2]
[3]
delay
CL = 15 pF
CL = 50 pF
-
-
4.1
5.4
7.5
9.5
1.0
1.0
9.0
1.0
1.0
10.0
12.0
ns
ns
11.0
An to Qn; see Figure 6
CL = 15 pF
-
-
5.5
9.5
1.0
1.0
11.5
14.0
1.0
1.0
12.5
15.5
ns
ns
CL = 50 pF
6.6 12.0
LE to Qn; see Figure 7
CL = 15 pF
-
-
4.3
8.0
1.0
1.0
9.5
1.0
1.0
10.4
13.0
ns
ns
CL = 50 pF
5.5 10.0
12.0
MR to Qn; see Figure 8
CL = 15 pF
-
-
3.9
5.1
-
7.0
9.0
-
1.0
1.0
5.0
8.5
10.5
-
1.0
1.0
5.0
9.5
11.5
-
ns
ns
ns
CL = 50 pF
tW
pulse width LE HIGH or LOW;
see Figure 7
5.0
MR LOW; see Figure 8
5.0
-
-
5.0
-
5.0
-
ns
74AHC_AHCT259_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 15 May 2008
8 of 17
74AHC259; 74AHCT259
NXP Semiconductors
8-bit addressable latch
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11.
Symbol Parameter Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ[1] Max
Min
Max
Min
Max
tsu
th
set-up time D, An to LE; see Figure 9
4.0
1.0
-
-
-
-
-
4.0
-
4.0
-
ns
ns
pF
and Figure 10
hold time
D, An to LE; see Figure 9
and Figure 10
-
1.0
-
-
-
1.0
-
-
-
[4]
CPD
power
fi = 1 MHz; VI = GND to VCC
17
dissipation
capacitance
[1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
[2] tpd is the same as tPLH and tPHL
.
[3] tpd is the same as tPHL only.
[4] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
11. Waveforms
V
CC
D input
V
M
GND
t
t
PLH
PHL
V
OH
V
Qn output
M
V
OL
001aah123
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 5. Data input to output propagation delays
74AHC_AHCT259_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 15 May 2008
9 of 17
74AHC259; 74AHCT259
NXP Semiconductors
8-bit addressable latch
V
CC
V
An input
M
GND
t
t
PLH
PHL
V
OH
V
Qn output
M
V
OL
001aah122
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. Address input to output propagation delays
V
CC
D input
GND
V
CC
LE input
V
M
GND
t
W
t
t
PLH
PHL
V
OH
V
Qn output
M
V
OL
001aah121
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Enable input to output propagation delays and pulse width
V
CC
MR input
V
M
GND
t
W
t
PHL
V
OH
V
Qn output
M
V
OL
001aah124
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8. Conditional reset input to output propagation delays
74AHC_AHCT259_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 15 May 2008
10 of 17
74AHC259; 74AHCT259
NXP Semiconductors
8-bit addressable latch
V
CC
LE input
V
M
GND
t
t
su
su
t
t
h
h
V
CC
V
D input
M
GND
V
OH
V
Qn output
Q = D
Q = D
M
V
OL
001aah125
Measurement points are given in Table 9.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 9. Data input to latch enable input set-up and hold times
V
CC
An input
LE input
V
ADDRESS STABLE
M
GND
t
t
h
su
V
CC
V
M
GND
001aah126
Measurement points are given in Table 9.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 10. Address input to latch enable input set-up and hold times
Table 9.
Type
Measurement points
Input
VM
Output
VM
74AHC259
0.5 × VCC
1.5 V
0.5 × VCC
0.5 × VCC
74AHCT259
74AHC_AHCT259_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 15 May 2008
11 of 17
74AHC259; 74AHCT259
NXP Semiconductors
8-bit addressable latch
t
W
V
I
90 %
negative
pulse
V
V
V
V
M
M
10 %
GND
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
M
M
10 %
GND
t
W
V
CC
V
V
O
I
G
DUT
R
T
C
L
001aah768
Test data is given in Table 10.
Definitions test circuit:
RT = termination resistance should be equal to output impedance Zo of the pulse generator.
CL = load capacitance including jig and probe capacitance.
Fig 11. Load circuitry for measuring switching times
Table 10. Test data
Type
Input
VI
Load
Test
tr, tf
CL
74AHC259
VCC
3.0 V
≤ 3.0 ns
≤ 3.0 ns
15 pF, 50 pF
15 pF, 50 pF
tPLH, tPHL
tPLH, tPHL
74AHCT259
74AHC_AHCT259_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 15 May 2008
12 of 17
74AHC259; 74AHCT259
NXP Semiconductors
8-bit addressable latch
12. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig 12. Package outline SOT109-1 (SO16)
74AHC_AHCT259_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 15 May 2008
13 of 17
74AHC259; 74AHCT259
NXP Semiconductors
8-bit addressable latch
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig 13. Package outline SOT403-1 (TSSOP16)
74AHC_AHCT259_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 15 May 2008
14 of 17
74AHC259; 74AHCT259
NXP Semiconductors
8-bit addressable latch
13. Abbreviations
Table 11. Abbreviations
Acronym
CDM
Description
Charged Device Model
CMOS
DUT
Complementary Metal-Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
LSTTL
MM
Low-power Schottky Transistor-Transistor Logic
Machine Model
14. Revision history
Table 12. Revision history
Document ID
Release date
20080515
Data sheet status
Change notice
Supersedes
74AHC_AHCT259_2
Modifications:
Product data sheet
-
74AHC_AHCT259_1
• The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Table 6: the conditions for input leakage current have been changed.
74AHC_AHCT259_1
20000314
Product specification
-
-
74AHC_AHCT259_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 15 May 2008
15 of 17
74AHC259; 74AHCT259
NXP Semiconductors
8-bit addressable latch
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
15.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74AHC_AHCT259_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 15 May 2008
16 of 17
74AHC259; 74AHCT259
NXP Semiconductors
8-bit addressable latch
17. Contents
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 16
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 15 May 2008
Document identifier: 74AHC_AHCT259_2
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